JP2004296088A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the writing speed of one line data which are to be written into a DRAM that is used as a cache memory. <P>SOLUTION: When the sense amplifier cache function of DRAM macro is used as a secondary cache memory, necessity of conducting nondistructive writing is not required because data control is conducted in terms of a word line unit. Thus, no reading operation is conducted by a sense amplifier while conducting writing, transfer of writing data (GBLn) is started from a writing amplifier to bit lines (BL/BLB) at the same time (t0) of start of word line (WL) and data equivalent to one word line are written with a high speed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit in which a memory is integrated, and further relates to a semiconductor integrated circuit in which a large-capacity memory is integrated on one chip together with a logic circuit such as a CPU (Central Processing Unit). The present invention relates to a technology that is effective when applied to an embedded DRAM mounted on the same chip.

  Today, a semiconductor integrated circuit in which a large-capacity memory and a large-scale logic circuit are integrated on one chip is provided. In such a semiconductor integrated circuit, in order to increase the data throughput between the memory and the logic circuit, it is easy to increase the number of buses connecting the memory and the logic circuit to 128 bits. There is an advantage that power consumption for data input / output can be suppressed and high-speed data transfer can be performed as compared with the case of driving pins.

  A multi-bank DRAM (Dynamic Random Access Memory) can be used as the large-capacity memory. In a multi-bank DRAM, a sense amplifier is provided for each memory bank, and data once latched in the sense amplifier by a word line selection operation can be sequentially output at high speed only by switching a column switch. Therefore, if accessing consecutive addresses in the same page (same word line address), relatively high speed can be achieved. However, when a different page is accessed (a page miss occurs), the access is delayed due to bit line precharge or the like.

  The multi-bank DRAM can also hide page misses under certain conditions. In other words, when a read or write command is issued to a certain memory bank to operate it, if another memory bank different from this is used next, an activation command is given to the other memory bank in advance and a word is issued. A line selection operation can be preceded. To do so, the CPU must of course access in such an address order, but it is practically impossible to specify all of this in the operation program of the CPU.

  Some semiconductor integrated circuits include a cache memory in addition to the large-capacity memory and a large-scale logic circuit such as a CPU. This aims at high-speed data processing by the CPU by mitigating the difference in operation speed between the large-capacity memory and the CPU by the cache memory. That is, of the data held by the large-capacity memory, some data recently used by the CPU and data in the vicinity thereof are held in the high-speed cache memory. However, the memory access by the CPU is good as long as it hits the cache memory, but once a miss occurs, the large-capacity memory is accessed, thereby limiting the data processing speed of the CPU.

  Japanese Patent Application Laid-Open No. 10-65124 is an example of a document describing a multi-bank DRAM.

JP-A-10-65124

  As described above, even in a multi-bank DRAM, a page miss cannot always be hidden depending on the order of access addresses. Even if a cache memory is provided for a multi-bank DRAM, the situation is exactly the same if a cache miss occurs. It is. Therefore, the inventor has found a need to further improve the access speed of a memory having a multi-bank.

  A first object of the present invention is to speed up a first access of a memory having a multi-bank, that is, a read access in which a word line is different from a previous access.

  A second object of the present invention is to provide a cache memory for a memory having a multi-bank, when performing cache entry replacement and write-back due to a cache miss in the cache memory, a parallel operation is performed. An object of the present invention is to prevent the operation efficiency of a memory having an operable multi-bank from being reduced. That is, between the operation of writing the data of the cache line to be written back to the memory having the multi-bank and the operation of reading the new cache entry data to be written to the same cache line from the memory having the multi-bank, Address information corresponding to the index address in the address signal is the same. If the information of the index address is mapped to the memory bank selection address information, the data whose index addresses are arranged at the same address will be arranged at the same memory bank. Therefore, the cache line is replaced. The read operation and the write operation for write back must be performed on the same memory bank, and both operations cannot be efficiently performed using different memory banks.

  A third object of the present invention is to prevent one access from blocking the other access for a plurality of access requests in which a memory macro does not compete in a semiconductor integrated circuit in which a plurality of memory macros having a multi-bank are mounted. The purpose is to enable non-blocking multiple access.

  A fourth object of the present invention is to improve the efficiency of rewriting data in a DRAM having a multi-bank in which a cache line is a word line unit. That is, when a cache line is a unit of rewriting, a non-destructive method of applying write data after waiting for storage information read to a bit line by a word line selecting operation to be latched by a sense amplifier, similarly to a normal DRAM. The inventor has found that writing is not necessary.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

<< 1 >> Preceding issuance of next address By using a memory macro having a multi-bank configuration, the sense amplifier of each memory bank holds data, and when an access hits the held data, the data latched by the sense amplifier is output. The first access of the memory macro can be speeded up. That is, each memory bank functions as a sense amplifier cache. In order to further improve the hit rate of the sense amplifier cache (the hit rate for the data of the sense amplifier), after accessing the memory bank, the next address (the address to which a predetermined offset is added) is issued in advance. Then, the data of the preceding issue address is pre-read by the sense amplifier of another memory bank. The next address to be the target of the pre-issue is based on an empirical rule that the operation program of the CPU and a group of processing data are basically mapped to linear addresses.

  The semiconductor integrated circuit for realizing the next address advance issue has a memory macro (5Ma to 5Md) and an access control circuit (4). The memory macro has a plurality of memory banks (Bank 1 to Bank 4) to which bank addresses are respectively assigned. Each memory bank selects a word line (WL) by a row address signal (R-ADD) and is selected. A sense amplifier (53) capable of latching storage information read from a memory cell of the selected word line to a bit line (BL), selects a bit line according to a column address signal (Ys0 to Ys7), and selects the selected bit. The line is connected to the data line (GBL) of the memory macro. The access control circuit includes a command and address signal output means (44) which can be operated for each memory bank, and data already latched in the sense amplifier being sent to the data line in response to a later access request. Next to the hit determination means (43) for enabling output and the access control of the memory macro for the external access address, an access address having a predetermined offset with respect to the external access address is issued in advance, and Address preceding issuing means (42) for prefetching the data of the issued address from the memory cell of the memory macro to the sense amplifier.

  The preceding issue address must be an address of a memory bank different from the immediately preceding access target. If the memory banks are the same, the function of the sense amplifier cache cannot be used for the previous access. For this purpose, the access address having the predetermined offset with respect to the external access address is an address specifying a memory bank different from the memory bank specified by the external access address. In other words, the address signal output from the output means is such that the bank address signal (B0 to B3) is mapped on the upper side of the column address signal (C0 to C2), and the row address signal (R0) is mapped on the upper side of the bank address signal. .. R7) are mapped, and the predetermined offset is 2i from the least significant bit of the column address signal when the number of bits of the column address signal is i.

  Here, the hit determination means for the sense amplifier cache function is a comparison means (432A, 432B) for detecting a match or mismatch between an access address supplied from the outside and an access address of storage information held by the sense amplifier. Can be configured. The command and address signal output means, in response to the mismatch detection by the comparing means, instructs a memory macro designated by an external access address to select a memory bank, a word line and a bit line, and In response to the match detection by the means, the word line selection operation can be suppressed and the memory bank and bit line selection operation can be instructed to the memory macro specified by the external access address.

<< 2 >> Address Alignment Adjustment of Secondary Cache When a CPU (1) is connected to the access control circuit (4) and a set-associative primary cache memory (2) is connected to the CPU and the access control circuit, The access control circuit and the memory macro can be positioned as a secondary cache memory (6) by the sense amplifier cache function. All of them may be configured as a multi-chip data processing system. In some cases, due to a cache miss in the primary cache memory, it is necessary to replace the cache line related to the miss and to write back the cache line. At this time, the operation of writing back the cache line data related to the cache miss of the primary cache memory to the secondary cache memory and the operation of reading the cache line related to the miss and the cache entry data to be replaced from the secondary cache memory are described. In between, the index addresses for the primary cache memory are the same. If the memory bank address information of the secondary cache memory is the same as the index address information of the primary cache memory, the data of the addresses having the same index address are arranged in the same memory bank in the secondary cache memory. Therefore, a read operation for replacing a cache line and a write operation for write-back must be performed on the same memory bank, and it is difficult to efficiently perform both operations using different memory banks. Can not.

  Therefore, the access control circuit is provided with an address alignment adjusting means (41) for changing the bit arrangement of an externally supplied access address signal and outputting the changed bit arrangement to a memory macro. For example, the address alignment adjusting means assigns to the bank address of the memory bank an array different from the array of a plurality of address bits assigned to the index address of the primary cache memory among the address signals supplied from the CPU. Thus, when replacing a cache entry due to a cache miss of the primary cache memory, it is possible to prevent the operating efficiency of the memory having the multi-bank from being reduced.

  In other words, the address alignment adjusting means changes the arrangement of at least all or part of address information used as an index address of the primary cache memory in the address signal supplied from the CPU, and Is assigned to the bank address. For example, the address alignment adjusting means replaces a part of the address information used as an index address of the primary cache memory and a part of the address information used as a tag address in the address signal supplied from the CPU, and Assign to the bank address of the memory bank.

  As another example of the address alignment by the address alignment adjusting means, at least the lower two bits of the tag address of the primary cache memory in the address signal supplied from the CPU are used to specify the memory bank address and the memory macro address. , Or one of them. Alternatively, of the address signals supplied from the CPU, at least the lower two bits of the index address of the primary cache memory are allocated to an address specifying the memory bank and / or an address specifying the memory macro. Can be. Further, at least the lower two bits of the index address of the primary cache memory among the address signals supplied from the CPU can be assigned to the column address signal.

  The address alignment adjusting means includes a switch circuit (411) for changing the arrangement of the address information variable, and a control register (410) capable of latching control information for determining a switch state of the switch circuit. The control register may be configured to be accessible by the CPU. The difference in the address alignment appears as a difference in the frequency at which the same memory bank is designated for consecutive addresses. If the same memory bank is frequently selected at index addresses that are close to each other in the replacement of a cache line, the hit rate due to the sense amplifier cache function decreases as the information is accessed at the closest address, and conversely. If the frequency of selecting different memory banks at index addresses which are close to each other in replacing a cache line is high, the hit rate by the sense amplifier cache function is increased as the information is accessed at addresses closest to each other. Which one is more advantageous depends on the address mapping of data and instructions, and can be selected according to the application system.

  If the simplification of the configuration is first, a wiring in which address alignment is fixed by a metal option can be adopted as the address alignment adjusting means.

<< 3 >> Destructive writing of secondary cache memory composed of DRAM macro In normal DRAM, when writing data, data is temporarily read from a memory cell to a sense amplifier and then a part of the data is rewritten. That is, non-destructive writing is performed. When the sense amplifier cache function of the DRAM macro is used as a secondary cache memory, since data management is performed in word line units, there is no need to perform non-destructive writing. Therefore, at the time of writing, the transfer of write data from the write amplifier to the bit line is started at the same time as or immediately after the rise of the word line without performing the read operation by the sense amplifier, and the data for one word line is transferred at high speed. Write.

  The cache memory that realizes the destructive writing has a DRAM macro (5Ma to 5Md) and an access control circuit (4). The DRAM macro has a plurality of memory banks (Bank 1 to Bank 4) each assigned a bank address, and each memory bank selects a word line (WL) by a row address signal (R-ADD) and is selected. A sense amplifier (53) capable of latching storage information read out from a memory cell of a word line to a bit line, selecting a bit line (BL) according to a column address signal (C-ADD), and selecting the selected bit. The line is connected to the data line (GBL) of the DRAM macro. The access control circuit includes a command and address signal output means (44) which can be operated for each memory bank, and data already latched in the sense amplifier being sent to the data line in response to a later access request. There is a hit determination means (43) for enabling output. The memory bank includes a first operation mode in which a sense amplifier is activated at a first timing from a word line selection, and a second operation mode in which a sense amplifier is activated at a second timing later than the first timing from a word line selection. Operating mode. The first operation mode is a destructive write, and the second operation mode is a refresh mode. The cache memory is a secondary cache memory, and a data processing system can be configured using the primary cache memory and the CPU for the secondary cache memory.

<< 4 >> Parallel access of non-conflicting memory macros In a semiconductor integrated circuit in which a plurality of memory macros having multiple banks are mounted, one access does not block the other access for a plurality of access requests in which the memory macros do not compete. Non-blocking multi-access. A memory (6) for realizing this is provided with an access control circuit (4) having a first access port (PT1) and a second access port (PT2) and a data line (9DBa-9DBd) connected to the access control circuit. It has a plurality of memory macros (5Ma to 5Md) connected to each other. The memory macro has a plurality of memory banks (Bank 1 to Bank 4) to which bank addresses are respectively assigned. Each memory bank selects a word line (WL) by a row address signal (R-ADD) and is selected. Has a sense amplifier (53) capable of latching storage information read from a memory cell of the selected word line to a bit line (BL), selects a bit line according to a column address signal (C-ADD), and selects the selected bit. A line is connected to the data line (GBL) of the memory macro. A selector (450R, 451R, 452W, 453W) capable of selecting a memory macro accessed through a first access port and a memory macro accessed through a second access port; Priority access determination means (40) for permitting parallel access from both access ports when access through the second access port and access through the second access port use different memory macros, and a memory for the memory macro to be accessed Command and address signal output means (44) operable for each bank; hit determination means (43) for outputting data latched in the sense amplifier to a data line in response to a subsequent access request ).

  For the priority control of the competing memory macro, the priority access determining means determines a predetermined priority when the access via the first access port and the access via the second access port are accesses using the same memory macro. The operation of the access port with the higher degree can be prioritized.

  Further, one or both of the first access port and the second access port can have an SRAM interface function. Latency from address input to data output varies depending on the access situation. In order to cope with this, an SRAM interface capable of outputting a wait signal or the like from an address input to a data output is adopted as the first access port and the second access port as compared with an interface having a fixed latency. Is easy.

  The data processing system using the memory (6) includes: a memory (6); a first address bus (6AB) and a first data bus (10DB) connected to a first access port of the memory; A second address bus (11AB) and a second data bus (11DB) connected to the second access port, a CPU (1) connected to the first address bus and the first data bus, and the second address bus. A bus interface circuit (3) connected to the bus and the second data bus.

  Further, the data processing system using the memory includes: the memory (6); a first address bus (6AB) and a first data bus (10D) connected to a first access port of the memory; A second address bus (11AB) and a second data bus (11DB) connected to the second access port, and a CPU (1) and a primary cache memory (2) connected to the first address bus and the first data bus. ) And a bus master (7) connected to the second address bus and the second data bus, wherein the memory is a secondary cache memory with respect to the primary cache memory.

  The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.

  That is, the hit ratio of the sense amplifier cache due to the next address advance issue can be improved.

  When replacing a cache entry due to a cache miss in the set associative primary cache memory, it is possible to prevent the operating efficiency of the multi-bank DRAM from being reduced.

  It is possible to speed up the first access of a memory having a multi-bank.

  Non-blocking multiple access in which one access does not block the other access for a plurality of access requests that do not conflict with the access request for the memory macro from the CPU and the outside can be enabled.

  Data can be efficiently rewritten to a DRAM having a multi-bank in which a cache line is a word line unit.

《System LSI》
FIG. 1 shows a CPU / DRAM mixed LSI (also referred to as a system LSI) as an example of a semiconductor integrated circuit to which the present invention is applied. The system LSI shown in FIG. 1 is not particularly limited, but includes a CPU 1, an example of a large-scale logic circuit, a primary cache memory 2, an external bus interface circuit 3, an access optimizer 4, In addition, a plurality of DRAM macros (multi-bank DRAMs) 5Ma to 5Md as an example of a large-capacity memory are integrated by a CMOS (Complementary Metal Oxide Semiconductor) manufacturing technique. Each of the DRAM macros 5Ma to 5Md is constituted by a multi-bank DRAM having a plurality of DRAM banks (memory banks) sharing a global bit line. Each DRAM bank has a sense amplifier cache function using a sense amplifier as a cache. However, for an access that hits the data of the sense amplifier, the data can be output at high speed without performing the word line selecting operation. The access optimizer 4 performs hit determination of the sense amplifier cache and controls the DRAM macros 5Ma to 5Md.

  Although not particularly limited, the CPU 1 is a so-called 32-bit CPU, and the unit of data processing is 32 bits in principle. Although not particularly limited, the CPU 1 can manage a 4-gigabyte address space with a 32-bit address signal.

  The CPU 1 and the primary cache memory 2 are connected by a 32-bit internal data bus 6DB and an internal address bus 6AB, respectively. The primary cache memory 2 and the external bus interface circuit 3 are connected to a 32-bit internal data bus 7DB and an internal address, respectively. It is connected by a bus 7AB. The external bus interface circuit 3 is interfaced with the outside via a 32-bit external data bus 8DB and an external address bus 8AB, respectively. Each control signal bus is not shown.

  The DRAM macros 5Ma to 5Md are mapped in the address space of the CPU 1, but are used as secondary cache memories by their sense amplifier cache function. The DRAM macros 5Ma to 5Md input and output data to and from the access optimizer 4 via 128-bit memory data buses 9DBa to 9DBd, respectively, and are supplied with address signals and commands from the access optimizer 4 via a bus 9ACB.

  The access optimizer 4 is interfaced with the CPU 1 and the primary cache memory 2 via the first access port PT1. Further, the access optimizer 4 has a second access port PT2 which is interfaced with the outside of the system LSI via the external bus interface circuit 3. The first access port PT1 receives an address signal from the CPU 1 via the address bus 6A, and inputs / outputs data to / from the primary cache memory 2 via a 128-bit data bus 10DB. The second access port PT2 is connected to the external bus interface circuit 3 via a 32-bit address bus 11AB and a data bus 11DB.

  In the system LSI, when the CPU 1 outputs an address signal to the address bus 6AB to perform read access, the primary cache memory 2 starts a cache memory operation such as a hit determination in response thereto. In parallel with this, the access optimizer 4 also starts hit determination of the sense amplifier cache. The primary cache memory 2 is a small-capacity high-speed memory composed of an SRAM (Static Random Access Memory), and the DRAM macros 5Ma to 5Md are memories having a low access speed even if they have a large capacity. Therefore, the primary cache memory 2 always precedes the determination of a cache hit. If the primary cache memory 2 is a cache hit, the output of read data from the DRAM macros 5Ma to 5Md by the access optimizer 4 is suppressed, and necessary data is sent from the primary cache memory 2 to the CPU 1 via the data bus 6DB. Given. When the primary cache memory 2 has a cache miss, necessary data is provided from the DRAM macros 5Ma to 5Md to the CPU 1 via the data bus 10DB and the primary cache memory 2. At this time, the data provided from the DRAM macros 5Ma to 5Md to the primary cache memory 2 is 128 bits, and the primary cache memory 2 cuts out 32 bits using the lower side of the address signal, and supplies this to the CPU 1. At the same time, the primary cache memory 2 writes the 128-bit data to the cache line in order to fill the cache line related to the miss. At this time, if the cache line has valid data to be written back, the data of the cache line is written back to the corresponding address of the DRAM macros 5Ma to 5Md prior to the cache fill.

  In the case of write access by the CPU 1, the sense amplifier cache function of the DRAM macros 5Ma to 5Md is not used. If the primary cache memory 2 is a cache hit, writing is performed on the cache memory 2; if a cache miss occurs, writing is performed on the corresponding addresses of the DRAM macros 5Ma to 5Md. Writing to the DRAM macros 5Ma to 5Md is performed collectively in units of 128 bits via the bus 10DB.

  Data transfer between the DRAM macros 5Ma to 5Md embedded in the system LSI and the outside of the LSI is performed via the external bus interface circuit 3 and the buses 11DB and 11AB. The access control at this time can be performed by a DMAC (Direct Memory Access Controller) (not shown) arranged outside the LSI.

  In the above system LSI, the cache memory 2 is arranged between the CPU 1 which is a large-scale logic circuit and the DRAM macros 5Ma to 5Md which are large-capacity memories, and the difference in operation speed between the large-capacity memories 5Ma to 5Md and the CPU 1 is cached. High-speed data processing by the CPU 1 is realized by mitigation by the memory 2. Further, in order to increase the data throughput between the DRAM macros 5Ma to 5Md and the primary cache memory 2, the data bus 10DB connecting them is increased to 128 bits to realize high-speed data transfer.

<< DRAM macro >>
FIG. 2 shows an example of the DRAM macro 5Ma. In FIG. 2, one DRAM macro 5Ma has, for example, four DRAM banks Bank1 to Bank4. Each of the DRAM banks Bank1 to Bank4 includes a memory cell array 50, a row / column decoder 51, a column selection circuit 52, a sense amplifier array 53, and a timing generator 54. The memory cell array 50 has a large number of dynamic memory cells arranged in a matrix. The selection terminals of the memory cells are connected to word lines WL, and the data input / output terminals of the memory cells are connected to local bit lines BL. Each local bit line BL has 1024 bits in total. A sense amplifier is provided for each bit of the local bit line BL. These sense amplifiers are collectively referred to as a sense amplifier array 53. The column switch circuit 52 selects a local bit line BL of 128 bits from a local bit line BL of 1024 bits according to a column address signal. The 128-bit local bit line selected by the column switch circuit 52 is conducted to the 128-bit global bit line GBL. The word line selection signal and the selection signal of the column switch circuit are generated by the row / column decoder 51. The 128-bit global bit line GBL is connected to the data bus 9DBa via a main amplifier provided for each bit. These main amplifiers are collectively referred to as a main amplifier array 55.

  To each of the DRAM banks Bank1 to Bank4, a bank selection signal B-ADD, a row address signal R-ADD, a column address signal C-ADD, a column command CC, a row command CR are supplied from the access optimizer 4 via an address / command bus 9ACB. , And a write enable signal WE are supplied.

  Although not particularly limited, signals other than the bank selection signal B-ADD are supplied to each of the DRAM banks Bank1 to Bank4 via a common signal line. The bank selection signal B-ADD is a decode signal of a 2-bit bank address signal, and is a selection signal unique to each of the DRAM banks Bank12 to Bank4. Therefore, one DRAM bank is selected for a 2-bit bank address signal. The DRAM banks Bank12 to Bank4 are enabled by being selected by a corresponding bank selection signal. In the enabled DRAM bank, the other input signals R-ADD, C-ADD, CC, RC, WE, etc. are made significant.

  The timing generator 54 can receive a row command CR and a column command CC by being selected by the bank selection signal B-ADD. The row command CR has the same function as the RAS (row address strobe) signal of a general-purpose DRAM. When it is enabled, it takes in a row address signal R-ADD, decodes it, and performs word line selection operation. Then, the data of the memory cell for one word line read to the bit line is latched by the sense amplifier of the sense amplifier array 53. The column command CC has a function similar to that of a CAS (column address strobe) signal of a general-purpose DRAM. When the column command CC is enabled, the column command CC takes in a column address signal C-ADD, decodes it, and decodes the column address signal C-ADD. The bit line selecting operation by 52 is performed, and the 128-bit local bit line BL selected by this is conducted to the global bit line GBL. Although not particularly limited, the timing generator 54 captures the write enable signal WE together with the capture of the row address signal by the row command CR, and thereby determines the internal sequence of the read operation and the write operation.

  In the DRAM macro 5Ma, when a column access operation is being performed in a certain DRAM bank, another DRAM bank can be selected and a row command can be issued to perform the row access operation in parallel. As a result, when the previous column access is completed, the column access can be immediately performed in the DRAM bank to which the row access is being performed in parallel, and the page miss can be apparently hidden.

  The other DRAM macros 5Mb to 5Md are configured similarly to the DRAM macro 5Ma.

  FIG. 3 shows an example of a connection configuration between a DRAM bank and a global bit line. M1 and M2 are typically column switch MOS transistors, M3 and M4 are precharge MOS transistors, and M5 is an equalize MOS transistor for a pair of complementary bit lines BL <0,0> and BL <0,0>. It is. A static latch type circuit composed of MOS transistors M6 to M9 is a sense amplifier, and a high-potential-side operation power supply φP such as a power supply voltage is supplied to a common source of p-channel MOS transistors M7 and M9. A low-potential-side operation power supply φN such as a circuit ground voltage is supplied to the common sources of the transistors M6 and M8. The memory cell is a one-transistor type configured from a series circuit of an n-channel selection MOS transistor M10 and a capacitor Cs. The word line WL is connected to the gate of the selection MOS transistor M10. HVC is a precharge potential, for example, an intermediate voltage between the power supply voltage and the ground voltage of the circuit. φPC is a precharge signal, and when set to a high level, equalizes a complementary bit line and supplies a precharge voltage HVP to the complementary bit line.

  Although not shown, the configuration of the other complementary bit lines is basically the same as the above-described configuration regarding the complementary bit lines BL <0,0> and BLB <0,0>. Although not particularly limited, the column address signal is 3 bits, and eight column selection signals Ys0 to Ys7 are decoded. Eight pairs of complementary bit lines BL <0,0>, BL are supplied to a pair of global bit lines GLB0, GBLB0 via eight pairs of column switch MOS transistors M1, M2 which are switch-controlled by column selection signals Ys0 to Ys7. <0,0> to BL <0,7> and BL <0,7> are connected. In this way, a total of 1024 (128 × 8) complementary bit lines BL <0,0>, BL <0,0> to BL <127,7>, BL <127,7> are sequentially arranged in units of 8 pairs. It is connected to 128 pairs of global bit lines GBL0, GBLB0 to GBL127, GBLB127. Therefore, in accordance with the decoding result of the column address signal C-ADD, the column selection signal is set to a high level in which any one of the signals Ys0 to Ys7 is at the selection level. Conduction is performed to a pair of global bit lines GBL0, GBLB0 to GBL127, GBLB127.

《Access Optimizer》
FIG. 4 shows an example of the access optimizer. The access optimizer 4 includes a priority access determination circuit 40, an address alignment adjustment circuit 41, an address advance issue circuit 42, a hit determination circuit 43, an address / command issue circuit 44, a data buffer 45, and a control circuit 46.

  The data buffer circuit 45, together with the data buffer, can individually select to which of the data buses 9DBa to 9DBd the data bus 10DB is connected and to which of the data buses 9DBa to 9DBd the data bus 11DB is connected. It has a selector and the like.

  When the access via the first access port PT1 and the access via the second access port PT2 are accesses using different DRAM macros, the priority access determination circuit 40 allows parallel access from both access ports. When the access via the one access port PT1 and the access via the second access port PT2 are accesses using the same DRAM macro, control is performed to give priority to the operation of the access port of the predetermined higher priority.

  The address / command issuing circuit 44 outputs a command and an address signal that can be operated for each DRAM bank to the address command bus 9ACB. That is, it outputs the bank selection signal B-ADD, row address signal R-ADD, column address signal C-ADD, row command CR, column command CC, write enable signal WE, and the like.

  The address alignment adjusting circuit 41 changes the bit arrangement of an access address signal supplied from outside the access optimizer 4 and subjected to the priority access determination, and supplies the changed bit arrangement to the DRAM macros 5Ma to 5Md via the address / command issuing circuit 44. It is a circuit that makes it possible.

  The address pre-issue circuit 42 pre-issues an access address having a predetermined offset with respect to the external access address after the access control of the DRAM macro with respect to the external access address. The data at the previously issued address can be read from the memory cell of the DRAM macro to the sense amplifier via 44.

  The hit determination circuit 43 is a circuit for determining whether or not a subsequent access request has hit data already latched in the sense amplifier array 53. In other words, it is a hit judging means for realizing the sense amplifier cache, and holds the immediately preceding access address, which is related to the same word line as the current access address, or the previously issued address is Is determined to be related to the same word line as the access address. The result of the determination as to the same word line is a hit state of the sense amplifier cache. In this case, the address / command issuing circuit 44 is inhibited from issuing the row command CR and immediately issues the column command CC. Makes it possible to read data already latched in the sense amplifier array. The control circuit 46 controls the entire access optimizer 4.

  When the access optimizer 4 performs (1) improvement of the hit ratio of the sense amplifier cache by issuing the next address first, and (2) replacement of the cache entry due to a cache miss of the primary cache memory of the set associative form, (3) Non-blocking multi-access in which one access does not block the other access for a plurality of access requests that do not conflict with the access request for the DRAM macro from the CPU and the outside from the CPU. Realize what is possible. Further, the DRAM banks Bank1 to Bank4 perform (4) destructive writing in order to efficiently rewrite data in a DRAM macro using a sense amplifier cache using a memory cell group for each word line as a cache line. The contents of (1) to (4) will be described in detail below.

<< Improve the hit rate of the sense amplifier cache by issuing the next address in advance >>
FIG. 5 shows an example of a basic configuration of the primary cache memory 2. Although not particularly limited, the primary cache memory 2 is of a set associative type and has four ways WAY0 to WAY3. Each of the ways WAY0 to WAY3 includes, but is not limited to, a memory cell array for configuring a maximum of 256 cache lines, and this memory cell array includes an address array 20 and a data array 21. One cache line includes a cache tag CTAG having an address tag ATAG such as a physical page number, a valid bit V, a dirty bit not shown, and 16-byte data LW0 to LW3 corresponding thereto. The cache tag CTAG, the valid bit V and the dirty bit are stored in the address array 20, and the data LW0 to LW3 are stored in the data array 21. The valid bit V indicates whether valid data is included in the cache line. The logical value “1” means valid, and the logical value “0” means invalid. The dirty bit is used when the cache memory 2 is used in the write-back mode, and is set to a logical value "1" when writing occurs in the write-back mode. The dirty bit makes it possible to know a mismatch between the data of the corresponding entry and the data of the external memory (5Ma to 5Md). This dirty bit is initialized to a logical value "0" by a power-on reset.

  The address signal output by the CPU 1 (the address signal is a physical address signal when the CPU 1 supports a virtual address, and a logical address signal otherwise) is a 32-bit A0 to A31 as described above. Yes, it is a byte address. Although not particularly limited, A21 to A31 are regarded as address tags ATAG. The eight bits A4 to A11 are regarded as an index address Index for selecting a cache line from each way. Although the address decoders of the address array 20 and the data array 21 are not shown in FIG. 5, an index address Index is supplied to both address decoders, and a corresponding cache line is selected.

  The cache tag CTAG of the cache line of each of the ways WAT0 to WAY3 selected (indexed) by the index address Index is compared by the comparators (CMP) 22 to 25 with the address tag ATAG included in the access address at that time. You. When the cache tag CTAG and the address tag ATAG such as the physical page number match and the valid bit V has the logical value "1", the signals output from the corresponding comparators 22 to 25 are set to the logical value "1". . The signals output from the comparators 22 to 25 are supplied to the corresponding data array 21. When the signal is a logical value "1", the 32-byte cache line data indexed by the data array 21 is selected. The selected cache line data is selected by the selector 26 by two bits A2 and A3. The logical sum signal of the signals output from the comparators 22 to 25 is used as the hit / miss signal Hit of the cache memory 2.

  FIG. 6 shows the logical configuration of the sense amplifier cache function of the four DRAM macros 5Ma to 5Md so as to be comparable with the primary cache memory 2. The four least significant bits of the address signal supplied to the DRAM macros 5Ma to 5Md have no substantial meaning. This is because the data to be column-selected is 128 bits, which is a data size of 4 bits in a byte address. The three bits C0 to C2 are used as a column selection signal C-ADD. The upper two bits MS0 and MS1 are used as macro address signals for selecting the DRAM macros 5Ma to 5Md. Further, the upper four bits are used as a bank address signal for selecting a DRAM bank. Here, it is assumed that there are 16 DRAM banks. The upper 8 bits R0 to R7 are used as a row address signal R-ADD. Needless to say, the address comparison of the sense amplifier cache is different from that of the set associative cache memory, and the hit access circuit 43 holds the immediately preceding access address for each DRAM bank. FIG. 6 shows the row address in the immediately preceding access address thus held as SATAG. The hit judging circuit 43 compares the row address signal of the current access address with the row address SATAG in the immediately preceding access address. If the row address signal matches the row address signal, the hit state is entered. Is selected by the column address signal.

  As is clear from the above, the multi-bank DRAM macros 5Ma to 5Md are used to hold the data in the sense amplifiers of the respective DRAM banks, and when the access hits the held data, the data latched by the sense amplifier is output. By doing so, the speed of the first access of the DRAM macro can be increased. That is, each memory bank can function as a sense amplifier cache.

  In order to further improve the hit rate of the sense amplifier cache (the hit rate for the data of the sense amplifier), the address pre-issue circuit 42 supplies the next address (the address to which the predetermined offset is added) after the external access. ) Is pre-issued, and the data at the pre-issued address is pre-read by the sense amplifier of another memory bank. The reason why the pre-issue is set to the next address is based on an empirical rule that the operation program of the CPU 1 and a group of processing data are basically mapped to a linear address. This is to make the amplifier cache easy to hit.

  The preceding issue address must be an address of a memory bank different from the immediately preceding access target. If the memory banks are the same, the function of the sense amplifier cache cannot be used for the previous access. For this purpose, the access address having the predetermined offset with respect to the external access address is an address specifying a memory bank different from the memory bank specified by the external access address.

  Here, the bit arrangement of the address signal of FIG. 6 supplied to the DRAM macros 5Ma to 5Md with respect to the address signal output by the CPU 1 is the same at least from the lowest order to MS1. Therefore, when the address signal output by the CPU 1 is sequentially incremented, the DRAM macro is always switched when the word line selection state is switched. Thus, when the number of bits of the column address signal is i (= 3), the predetermined offset by the address advance issuing circuit 42 is 2i (= 8) from the least significant bit of the column address signal.

  FIG. 7 shows an example of a timing chart of the address advance issue operation. It is assumed that the access address by the CPU 1 is ADD1. In response, a new word line selection operation is performed. For example, after six cycles, data D1 corresponding to access address ADD1 is read. During this time, the address advance issuing circuit 42 internally generates an address ADD2 obtained by adding +8 to the address ADD1, instructs the address / command issuing circuit 44 to perform a row-related operation, and outputs a DRAM corresponding to the previously issued address signal. A word line selecting operation is performed by instructing the macro DRAM bank, and the data of the selected word line is latched by the sense amplifier. As described above, when the access address signal is +8, the access address ADD2 always moves to another DRAM macro, so that the operation of the memory bank operated by the access address ADD1 is not disturbed. Therefore, if the next access address by the CPU 1 is ADD2, the address / command issuing circuit 44 does not perform the word line selecting operation by the address ADD2, and directly selects the latch information of the sense amplifier by the column address signal included therein. To output the data D2 to the outside.

  FIG. 8 shows an example of the hit determination circuit 43 in consideration of the preceding address issuance. The hit determination circuit 43 has an address decoder 430, a register circuit 431, and comparison circuits 432A and 432B. The register circuit 431 has a unique address storage area for each DRAM bank of the DRAM macros 5Mas to 5Md. This address storage area holds the immediately preceding access address signal in the corresponding memory bank. The address decoder 430 receives an address signal supplied from the address alignment adjustment circuit 41 and an address signal supplied from the address advance issuing circuit 42, and outputs a 2-bit macro address signal and a 4-bit address signal included in the respective input address signals. Is decoded. Using the decode signal, an address storage area corresponding to the DRAM bank of the accessed DRAM macro is selected. The selected address storage area first outputs the already held address information, and then updates the already held address information to the current access address information. When the already held address information is output, the comparison circuit 432A compares the address signal supplied from the register circuit 431 with the address signal supplied from the address alignment adjustment circuit 41. The address signal supplied from the circuit 431 is compared with the address signal supplied from the preceding address issuing circuit 42. As a result of the comparison, if the address information higher than the column address signal matches, the sense amplifier cache hit information 433A, 433B is enabled and given to the address / command issuing circuit 44.

  The address / command issuing circuit 44 determines whether to issue a row command CR for the access address at that time according to the state of the sense amplifier cache hit information 433A and 433B. That is, the address / command issuing circuit 44 instructs the DRAM macro specified by the access address to select a memory bank, a word line and a bit line in response to the mismatch detection by the signals 433A and 433B. , 433B, the word line selection operation is suppressed and the memory bank and bit line selection operation is instructed to the DRAM macro designated by the access address.

<< Adjustment of secondary cache address alignment >>
FIG. 9 shows an address signal (output address signal of the CPU 1) supplied to the primary cache memory 2 and an address signal supplied to the DRAM macros 5Ma to 5Md in a state where address alignment is not performed by the address alignment adjusting circuit 41. The output address signal of the access optimizer) is shown.

  The access optimizer 4 and the DRAM macros 5Ma to 5Md can be positioned as the secondary cache memory 6 by the sense amplifier cache function.

  When a cache read miss occurs in the primary cache memory 2, the cache data of the cache line may need to be written back together with replacement of the cache line. At this time, both the write-back destination address and the read address of the cache data to be replaced have the same index address information. This is apparent from the index operation in the set associative cache memory. The part of the address tag will be different.

  At this time, as is apparent from the address alignment of FIG. 9, the CPU addresses having the same index address Index have the same A4 to A11, except for the most significant bit B3 of the bank address signal. Column address signals C0 to C2, macro address signals MS0 and MS1, and part of bank selection signals B0 to B2 are allocated. If the most significant A12 of the address tag information ATAG of the write back destination address and the most significant A12 of the address tag information ATAG of the read address of the cache data to be replaced match each other, write access to the DRAM macro for write back is performed. The read access from the DRAM macro for replacement is performed on the same DRAM bank of the same DRAM macro. The probability that one bit of A12 matches each other is relatively high. When this happens. In a DRAM macro, both operations cannot be performed efficiently using different memory banks. Unless one access operation is completed in one DRAM bank, another access operation cannot be performed. If the DRAM banks to be operated are different, when a read operation is performed on one DRAM bank, it is possible to supply at least a row command CR to the other DRAM bank to perform the word line selection operation in parallel. it can.

  Therefore, the address alignment adjusting circuit 41 is provided. The address alignment adjusting circuit 41 changes the bit arrangement of an externally supplied access address signal to enable supply to the DRAM macros 5Ma to 5Md.

  FIG. 10 shows a first example of a correspondence relationship between the output address signal of the access optimizer 4 and the output address signal of the CPU 1 obtained by the address alignment by the address alignment adjusting circuit 41. In the example of FIG. 10, A12 to A15 are bank address signals B0 to B3, and A9 to A11 are part of row address signals R0 to R2. Other arrangements are the same as in FIG. FIG. 11 shows a second example of the address alignment. In the example of FIG. 11, A12 to A14 are part of the bank address signal B1 to B3, and A10 and A11 are part of the row address signal R0 and R1. Other arrangements are the same as in FIG. 10 and 11, in the address signals supplied from the CPU 1, part of the address information used as the index address Index of the primary cache memory 2 and part of the address information used as the tag address ATAG Is assigned to the bank address of the memory bank.

  Thus, when replacing and writing back a cache entry due to a cache miss in the primary cache memory 2, both memory operations can be performed in different DRAM banks. For a different DRAM bank included in one DRAM macro, when a column operation is being performed on one DRAM bank, a row command CR is supplied to another DRAM bank in parallel with this operation to supply a word line. The selection and the latch operation of the sense amplifier can be advanced. Therefore, when a column access operation is performed in one DRAM bank to perform a write operation for write back, a row command CR is supplied to another DRAM bank to select and sense a word line in a read operation for replacement. It is possible to precede the amplifier latch operation. Therefore, following the write operation for write-back, the column selection and output operation of the read operation for replacement can be performed immediately. Thereby, the penalty operation due to a cache miss of the primary cache memory 2 can be speeded up.

  FIG. 12 shows an example of the address alignment adjustment circuit 41. The address alignment adjustment circuit 41 has a switch circuit 411 capable of changing the arrangement of input address signals and outputting the same, and a control register 410 capable of latching control information for determining a switch state of the switch circuit 411, The control register 410 is configured to be accessible by the CPU 1. Thereby, the address alignment illustrated in FIGS. 10 and 11 can be arbitrarily selected.

  The difference in the address alignment appears as a difference in the frequency at which the same memory bank is designated for consecutive addresses. FIGS. 13 to 15 show the order of the DRAM banks in which the word line selecting operation is performed when the address space of the CPU 1 is sequentially accessed. Each of the four DRAM macros 5Ma to 5Md has 16 DRAM banks. In the case of FIG. 13 corresponding to FIG. 9 in which the address alignment adjustment is not performed, all 64 DRAM banks are sequentially switched, and the selection of the word line is sequentially switched. In the case of FIG. 14 corresponding to FIG. 10 in which the address alignment of the first adjustment example is performed, the selection of the word line is switched while the four DRAM banks are cyclically switched. In the case of FIG. 15 corresponding to FIG. 11 in which the address alignment of the adjustment example 2 is performed, the selection of the word line is switched while the eight DRAM banks are switched cyclically.

  If the same memory bank is frequently selected at index addresses that are close to each other in the replacement of a cache line, the hit rate due to the sense amplifier cache function decreases as the information is accessed at the closest address, and conversely. If the frequency of selecting different memory banks at index addresses which are close to each other in replacing a cache line is high, the hit rate by the sense amplifier cache function is increased as the information is accessed at addresses closest to each other. Which one is more advantageous depends on the address mapping of data and instructions, and can be selected according to the application system.

  As the address alignment adjustment circuit 41, a wiring in which address alignment is fixed by a metal option can be employed. Although the address alignment can be selected only at the manufacturing process stage or the design stage, the circuit configuration for adjusting the address alignment can be simplified.

<< Parallel access of non-competitive DRAM macros >>
FIG. 16 shows an example of the data buffer circuit 45. The data buffer circuit 45 includes a read data buffer 454R and a write data buffer 454W connected to the data bus 10DB of the first port PT1, and a read data buffer 455R and a write data buffer 455W connected to the data bus 11DB of the second port PT2. And selectors 450R, 451R, 452W, and 453W. The selector 450R selects one of the DRAM macros 5Ma to 5Md and connects it to the read data buffer 454R. The selector 451R selects one of the DRAM macros 5Ma to 5Md and connects it to the read data buffer 455R. The selector 452W selects one of the DRAM macros 5Ma to 5Md and connects it to the write data buffer 454W. The selector 453W selects one of the DRAM macros 5Ma to 5Md and connects it to the write data buffer 455W. The control circuit 46 outputs the selection signals of the selectors 450R, 451R, 452W, and 453W.

  The input and output of the read data buffer 454R and the write data buffer 454W are both 128 bits. On the other hand, the read data buffer 455R and the write data buffer 455W have a built-in data aligner, and the interface on the bus 11DB side is 32 bits, and the interface on the selectors 451R and 453W is 128 bits.

When the access via the first access port PT1 and the access via the second access port PT2 are accesses using different DRAM macros, the priority access determination circuit 40 allows parallel access from both access ports.
Such non-contention access of the DRAM macro is determined by comparing the macro address signal included in the address signal supplied from the bus 6AB with the macro address signal included in the address signal supplied from the bus 11AB. The determination result is given to the control circuit 46, and the control circuit 46 performs selection control of the selectors 450R, 451R, 452W, and 453W according to the macro address signals from both.

  Further, when the access via the first access port PT1 and the access via the second access port PT2 are accesses using the same DRAM macro, the priority access determination circuit 40 determines which one of the predetermined priority is higher. Priority is given to the operation of the access port.

  FIG. 17 shows an example of a priority access determination when an access conflict occurs using the same DRAM macro and an access control procedure based on the priority access determination.

  The port whose access is prioritized is specified in the priority access setting register. In response to the address input, it is determined whether or not the input source is a priority port (S1). If the access is from a priority port, it is checked whether there is a priority access during a wait (S2). Wait until it finishes first (S3). Thereafter, the hit determination circuit 43 makes a hit determination of the sense amplifier cache (S4). If a cache miss occurs, word line selection and row access of the sense amplifier latch, which are row address operations, are performed (S5). A column access such as a column selection operation is performed (S6), and data is output (S7). If a cache miss occurs in step S4, the row access (S5) is skipped and the process proceeds to the column access (S6) and the data output operation (S7). If it is not a priority access in the step S1, it is determined whether or not there is a conflict with the priority access (S8). If there is a conflict, it is waited for the priority access related to the conflict to end (S9). Proceed to step S4.

  FIG. 18 illustrates some of the operation timings of the DRAM macro according to the priority access determination result. For example, consider a state in which address signals aA0 and aA1 are supplied from the CPU 1 via the bus 6AB and address signals aB0 to aB3 are supplied from the outside via the bus 11AB as shown in [A].

  [B] is a case where the access target DRAM macros do not compete. In this case, both DRAM macros to be accessed are independently operated in parallel. [C] is a case where the access target DRAM macros are in conflict and a case where the address input aB is set as the priority access. The first access request conflicts with the addresses aA0 and aB0, and the access of the address aA conflicts with another priority access from the beginning, so that the access with respect to the address aA is in a wait state until all operations on the address aB are completed. Is done. [D] shows a case in which the access target DRAM macros compete, in which the address input aA is given priority access. At this time, the first access aA0 is a cache miss, and during the replacement of the cache entry or the cache fill for the cache miss, the access of the addresses aB0 and aB1 does not compete with the access of the address aA, and the preceding data dB0 and dB1 are read. It is. The access to the data dA0 and the subsequent access to the data dA1 related to the cache hit take precedence over the access to the addresses aB2 and aB3, and the access to the data dB2 and dB3 is waited until this is completed.

  As described above, in a system LSI in which a plurality of DRAM macros are mounted, non-blocking multi-access can be performed so that one access does not block the other access for a plurality of access requests in which the DRAM macros do not compete. For example, when an external access is performed under the control of a DMAC (not shown), the access of the DRAM macro by the CPU 1 is permitted without stopping the operation of the CPU 1 without interrupting the operation of the CPU 1 and the data processing. This can contribute to improvement in efficiency.

  From the viewpoint of non-blocking multi-access of the non-conflicting DRAM macro, the system LSI can be configured as shown in FIG. The DMAC 7 is connected to the second port PT2. The data input / output of the first port PT1 is 32 bits. The primary cache memory 2 is not a unified cache memory, but is divided into an instruction cache memory 2I and a data cache memory 2D. FIG. 19 shows only the data path, but the address path can be easily inferred from FIG.

  Note that it is also possible to configure the configuration of FIG. 19 as an LSI for each functional block and configure a multi-chip data processing system. Further, in such an access method, the latency from the address input to the data output of the access optimizer may not be constant depending on each access situation. In such a case, if an SRAM interface is adopted as an interface of the access ports PT1 and PT2, connection can be easily made even when used in combination with an existing system. For this purpose, the access optimizer 4 may output a WAIT (wait) signal during a period from address input to data output.

<< Destructive writing of secondary cache memory composed of DRAM macro >>
Next, destructive writing of a DRAM bank in a DRAM macro specialized as a secondary cache memory in a system LSI will be described. In general, when writing data in a DRAM, data is temporarily read from a memory cell to a sense amplifier and then a part of the data is rewritten. That is, non-destructive writing is performed. When the sense amplifier cache function of the DRAM macro is used as a secondary cache memory, since data management is performed in word line units, there is no need to perform non-destructive writing. Therefore, in writing, without performing the data read operation to the sense amplifier, the write data is transferred from the main amplifier to the bit line at the same time as or immediately after the rise of the word line, and the data for one word line is transferred at high speed. Write.

  Regarding the data write operation mode, the timing generator 54 of the DRAM bank for realizing the destructive write includes a first operation mode (destructive write mode) in which the sense amplifier is activated at the first timing from the word line selection, and a timing operation from the word line selection. There is a second operation mode (refresh mode) in which the sense amplifier is activated at a second timing later than the first timing. Although the first operation mode is not particularly limited, the first operation mode is set by asserting the write enable signal WE and the row command CR, and immediately thereafter asserting the column command CC, and the column address signal is supplied together with the column command CC. become. Although not particularly limited, the second command is set by negating the write enable signal WE and asserting the row command CR, and a refresh address (row address) is supplied together with the row command CR. No column access is required in the refresh operation.

  FIG. 20 shows an example of an operation timing chart of the direct burst write mode which is an example of the destructive write mode. When the word line WL is selected at time t0, immediately after that, the power supplies φN and φP of the sense amplifier are turned on, and the sense amplifier is activated. Further, the first 128-bit write data D0 is input from the global bit line GBL to the 128-bit local bit line BL via the column switch circuit 52 by the column selection signal Ys0. The input 128-bit write data D0 is latched by the 128 corresponding sense amplifiers, and the potential state of the corresponding local bit line BL is determined according to the latched data. Thereafter, a similar write operation is continued from time t1 to time t127, and finally, data is written to a 1024-bit memory cell for one word line.

  FIG. 21 shows an example of an operation timing chart in the refresh mode. In the refresh operation, the non-destructive writing must be performed due to the nature of the operation of refreshing the stored information. Therefore, the precharge operation is completed at time t00, and the word line selection operation is performed at time t01. After the difference voltage due to the charge information supplied to the local bit line BL increases to some extent, the sense amplifier is activated at time t02. The sense amplifier latches the information stored in the memory cell at time t1. Thereby, the local bit line BL is driven, and the information stored in the memory cell is refreshed by the charge information. In this operation, a timing margin is taken in a period from time t00 to time t1.

  If a write operation for a part of the memory cells for one word line is supported in addition to the data write for one word line, nondestructive write is necessary as in the refresh operation. This is because even if a word line is selected, data in a memory cell that is not to be written must not be destroyed. If non-destructive writing is also performed for writing for one word line, a timing margin similar to the refresh operation is added to the access time as illustrated in FIG. 22, and the writing time is made longer than in FIG. You.

  Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it goes without saying that the invention can be variously modified without departing from the gist thereof.

  For example, the number of DRAM macros and the number of DRAM banks held by each DRAM macro are not limited to the above example, and can be changed as appropriate. Further, the type and number of circuit modules or functional modules built in a semiconductor integrated circuit represented by a system LSI are not limited to the above examples. It is also possible to include an address conversion buffer or to mount a DSP. In the above description, a DRAM macro and a DRAM bank are taken as an example of a large-capacity memory. However, the memory macro and the memory bank are not limited to the DRAM format except for the invention relating to destructive writing. For example, an SRAM (Static Random Access Memory) or the like is used. There may be. In addition, the invention relating to address pre-issuance and non-blocking multi-access is not limited to a use form in which a memory macro is specialized as a secondary cache in which data is managed in units of word lines. It goes without saying that it is applicable.

1 is a block diagram of a CPU / DRAM mixed LSI (system LSI) as an example of a semiconductor integrated circuit to which the present invention is applied. FIG. 2 is a block diagram illustrating an example of a DRAM macro of FIG. 1. FIG. 4 is a circuit diagram showing an example of a connection configuration between a DRAM bank and a global bit line. It is a block diagram showing an example of an access optimizer. FIG. 2 is a block diagram illustrating an example of a basic configuration of a primary cache memory. FIG. 3 is a block diagram showing a logical configuration of a sense amplifier cache function using a plurality of DRAM macros so as to be comparable with a primary cache memory. 9 is a timing chart illustrating an example of an address advance issue operation. FIG. 9 is a block diagram illustrating an example of a hit determination circuit when address advance issuance is considered. FIG. 4 is an explanatory diagram showing an example of a correspondence relationship between an output address signal of a CPU supplied to a primary cache memory and an output address signal of an access optimizer supplied to a DRAM macro in a state where address alignment is not performed by an address alignment adjustment circuit; . FIG. 4 is an explanatory diagram showing a first example of a correspondence between an output address signal of a CPU obtained by address alignment by an address alignment adjustment circuit and an output address signal of an access optimizer. FIG. 9 is an explanatory diagram showing a second example of the correspondence between the CPU output address signal obtained by the address alignment by the address alignment adjustment circuit and the output address signal of the access optimizer. FIG. 3 is a block diagram illustrating an example of an address alignment adjustment circuit. FIG. 10 is an explanatory diagram showing the order of the DRAM banks in which the word line selection operation is performed when the address space of the CPU is accessed sequentially when the address alignment is not adjusted as in FIG. FIG. 11 is an explanatory diagram showing the order of DRAM banks in which a word line selecting operation is performed when the address space of the CPU is sequentially accessed when the address alignment is adjusted as shown in FIG. FIG. 12 is an explanatory diagram showing the order of the DRAM banks in which the word line selection operation is performed when the address space of the CPU is sequentially accessed when the address alignment is adjusted as in FIG. 11. FIG. 3 is a block diagram illustrating an example of a data buffer circuit. 9 is a flowchart illustrating an example of priority access determination when an access conflict using the same DRAM macro occurs and an access operation control procedure based on the priority access determination. 6 is a timing chart illustrating some operation timings of a DRAM macro according to a priority access determination result. FIG. 9 is a block diagram schematically showing another example of a system LSI from the viewpoint of non-blocking multi-access of a non-conflicting DRAM macro. 6 is a timing chart illustrating an operation example of a direct burst write mode which is an example of a destructive write mode. 5 is a timing chart illustrating an operation example of a refresh mode. 9 is a timing chart showing a comparative example of operation timing when nondestructive writing is assumed to be performed for writing for one word line.

Explanation of reference numerals

1 CPU
2 Primary cache memory ATAG Address tag Index Index address CTAG Cache tag WAY0-WAY3 way 3 External bus interface circuit 4 Access optimizer PT1 First access port PT2 Second access port 40 Priority access determination circuit 41 Address alignment adjustment circuit 410 Control register 411 Switch circuit 42 Address advance issue circuit 43 Hit determination circuit 430 Address decoder 431 Register circuit 432A, 432B Comparison circuit 44 Address / command issue circuit 45 Data buffer circuit 5Ma to 5Md DRAM macro 53 Sense amplifier array B-ADD Bank selection signal R-ADD Row address signal C-ADD Column address signal CR Row command CC Column command W Write enable signals GBL global bit line BL local bit lines WL the word line 6 secondary cache memory

Claims (10)

A semiconductor memory having a memory cell array having a plurality of memory cells and a sense amplifier,
The memory cell is connected to a word line and a local bit line for inputting and outputting data,
The semiconductor memory, wherein the sense amplifier is connected to the local bit line, and writes data after the word line is selected without waiting for the activation of the sense amplifier.   2. The semiconductor memory according to claim 1, wherein data writing is performed simultaneously with said word line selecting operation.   2. The semiconductor memory according to claim 1, wherein said memory cells are dynamic memory cells. A semiconductor memory having a memory cell array having a plurality of memory cells, a column switch, and a sense amplifier,
The memory cell is connected to a word line and a local bit line that inputs and outputs data,
The local bit line is connected to a global bit line via the column switch,
The column switch selectively connects to the global bit line from a plurality of the local bit lines,
The semiconductor memory, wherein the sense amplifier is connected to the local bit line, and performs a selecting operation of the column switch after the word line is selected without waiting for the activation of the sense amplifier.   5. The semiconductor memory according to claim 4, further comprising a row / column decoder for performing the word line selecting operation and the column switch selecting operation.   5. The semiconductor memory according to claim 4, wherein said memory cells are dynamic memory cells. A semiconductor memory having a DRAM macro,
The DRAM macro includes a plurality of memory banks each having a plurality of memory cells,
The memory bank includes a word line selected based on a row address signal, and a bit line connected to a data line of the DRAM macro by being selected based on a column address signal,
Each of the plurality of memory cells is connected to a word line and a local bit line for inputting and outputting data,
The semiconductor memory according to claim 1, wherein each of the plurality of memory banks has a first operation mode in which the sense amplifier is activated at a first timing for selecting the word line.   8. The memory bank according to claim 7, wherein each of the memory banks has a second operation mode for activating the sense amplifier at a second timing after the first timing for selecting the word line. Semiconductor memory.   9. The semiconductor memory according to claim 8, wherein the first operation mode is a data write operation, and the second operation mode is a refresh operation.   A semiconductor memory capable of efficiently accessing a plurality of memory banks.

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