JP2004289008A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce wiring resistance and improve the characteristics of a wiring such as SM resistance and EM resistance of the wiring. <P>SOLUTION: A wiring groove 25 (L1-L4) with a different wiring width is formed in insulation films (22 and 23) on a plug P2, and a barrier layer 26 is formed thereon, and then a copper alloy layer 27a with low coverage is stacked thereon. Thus the covering property of the bottom, the side wall and the upper part of the side wall of the wiring groove with a smaller width is made lower, and a copper film 27b is stacked in an appropriate covering condition, and a copper film 27c is precipitated on its upper side by the field plating method. After annealing is applied to change the copper film to an alloy, a copper alloy film or the like outside the wiring groove 25 is removed to form a second layer wiring. As a result, the rate of changing of the copper film into alloy is made higher as the wiring width becomes larger, and the movement of copper atoms is suppressed by changing into alloy in a part having a larger wiring width that is significantly influenced by the movement of the copper atoms, while an increase of wiring resistance can be suppressed in a part having a smaller wiring width because the changing rate of copper into alloy is low. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a technology effective when applied to metal wiring.
[0002]
[Prior art]
In recent years, with the miniaturization and multilayering of wiring in a semiconductor integrated circuit device, a so-called damascene technique has been adopted in which a wiring groove is formed in an insulating film and then a wiring is formed by embedding a conductive film in the groove. I have.
[0003]
Further, as a conductive film to be embedded, a copper film having a small resistance has been studied.
[0004]
Further, in order to improve the electromigration resistance of the wiring made of the copper film, a method of including another metal in the copper film is adopted (for example, see Patent Documents 1 to 5 below).
[0005]
Patent Literature 1 relates to formation of wiring of pure copper and alloy copper in different wiring layers, and Patent Literature 2 relates to formation of a Cu film by orientation of Al.
[0006]
Patent Literature 3 diffuses Sn and Mg into Cu, Patent Literature 4 diffuses Al into the grain boundaries of Cu, and Patent Literature 5 diffuses Ag into Cu. Things.
[0007]
[Patent Document 1]
JP-A-9-289214
[0008]
[Patent Document 2]
JP-A-2002-26015
[0009]
[Patent Document 3]
JP 2000-150522 A
[0010]
[Patent Document 4]
JP 2000-49164 A
[0011]
[Patent Document 5]
JP-A-11-204524
[0012]
[Problems to be solved by the invention]
The present inventors are engaged in research and development of semiconductor integrated circuit devices, and employ Cu wiring using damascene technology.
[0013]
The stress migration (SM) characteristic of the Cu wiring depends on the wiring width, and the SM resistance deteriorates as the wiring width increases.
[0014]
Therefore, a method has been studied in which an impurity metal (for example, Ni, Mg, Al, or the like) is added to Cu and a wiring is made of a Cu alloy, thereby suppressing the movement of Cu and improving the SM resistance.
[0015]
However, according to the above method, although the SM resistance of the wiring is improved, the wiring resistance is increased by the impurity metal, and the advantage of using low-resistance Cu is diminished.
[0016]
An object of the present invention is to improve wiring characteristics such as lowering wiring resistance and improving SM resistance of wiring.
[0017]
Another object of the present invention is to improve the reliability of a semiconductor integrated circuit device.
[0018]
The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0019]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.
[0020]
A semiconductor integrated circuit device according to the present invention includes: (a) an insulating film formed on a semiconductor substrate; (b) a first groove formed in the insulating film; and a second groove wider than the first groove. A semiconductor integrated circuit device having: a first groove formed in the first and second grooves, and (c) first and second wirings each having a first metal as a main component and a second metal formed therein. (D) The second wiring has a higher content of the second metal than the first wiring.
[0021]
According to the method of manufacturing a semiconductor integrated circuit device of the present invention, (a) an insulating film is formed on a semiconductor substrate, and the insulating film is selectively etched to be wider than the first groove and the first groove. Forming a second groove; and (b) depositing a first metal film on the insulating film including the inside of the first groove and the inside of the second groove, wherein Depositing a first metal film under conditions in which the bottom, side walls, and upper portions of the second trench have better coverage than the bottom, sidewalls, and upper portions of the trenches; And (d) performing a heat treatment after the step (c) after depositing a second metal film on the insulating film including the inside of the first groove and the second groove. Diffusing the metal in the first metal film into the second metal film. Note that a step of forming a barrier layer may be provided between the steps (a) and (b).
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0023]
(Embodiment 1)
Hereinafter, a semiconductor integrated circuit device according to a first embodiment of the present invention will be described according to a method of manufacturing the same. 1 to 11 are cross-sectional views of main parts of a substrate showing a method for manufacturing a semiconductor integrated circuit device according to the first embodiment of the present invention.
[0024]
First, as shown in FIG. 1, a semiconductor substrate 1 on which a semiconductor element such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed is prepared.
[0025]
The process of forming the MISFET will be briefly described.
[0026]
First, a semiconductor substrate (hereinafter simply referred to as “substrate”) 1 made of, for example, p-type single crystal silicon is prepared, and a groove is formed by etching the substrate 1, and then a silicon oxide film is embedded in the groove. An element isolation 2 is formed.
[0027]
Next, a p-type impurity and an n-type impurity are ion-implanted into the substrate 1 and then heat-treated to diffuse the impurities, thereby forming the p-type well 3 and the n-type well 4.
[0028]
Next, a clean gate oxide film 5 is formed on the surface of the substrate 1 by thermal oxidation. Next, a gate electrode 7 is formed by forming a polycrystalline silicon film on the substrate 1 and etching it. Next, an n-type impurity is ion-implanted into the substrate 1 on both sides of the gate electrode 7 on the p-type well 3, and a p-type impurity is ion-implanted into the substrate 1 on both sides of the gate electrode 7 on the n-type well 4. , N ⁻ Semiconductor region 8 and p ⁻ A type semiconductor region 9 is formed.
[0029]
Next, after depositing a silicon nitride film on the substrate 1 by, for example, a CVD (Chemical Vapor Deposition) method, the sidewall 10 is formed on the sidewall of the gate electrode 7 by anisotropically etching.
[0030]
Then, using the gate electrode 7 and the side wall 10 as a mask, an n-type impurity is ion-implanted into the p-type well 3 and a p-type impurity is ion-implanted into the n-type well 4 and thermally diffused. ⁺ Semiconductor region 11 (source, drain) and p ⁺ A type semiconductor region 12 (source, drain) is formed.
[0031]
Through the steps so far, an n-channel MISFET Qn and a p-channel MISFET Qp each having a source and a drain having an LDD (Lightly Doped Drain) structure are formed.
[0032]
Next, a refractory metal film such as titanium is formed on the entire surface of the semiconductor substrate 1, and the substrate 1 is subjected to a heat treatment to form a silicide layer 16. After that, the unreacted high melting point metal film is removed.
[0033]
Next, as shown in FIG. 2, an interlayer insulating film 18 is formed by depositing, for example, a silicon oxide film by a CVD method, and the surface thereof is planarized by CMP (Chemical Mechanical Polishing).
[0034]
Then, n ⁺ Type semiconductor region 11 or p ⁺ The contact hole C1 is formed by appropriately removing the interlayer insulating film 18 on the mold semiconductor region 12 by etching.
[0035]
Next, after a titanium nitride film (not shown) is formed as a barrier film by a sputtering method on the interlayer insulating film 18 including the inside of the contact hole C1, for example, a tungsten (W) film is formed as a conductive film by a CVD method. Form. Next, the titanium nitride film (TiN) and the W film other than the contact hole C1 are removed by CMP to form a plug P1.
[0036]
Next, as shown in FIG. 3, a first layer wiring M1 is formed by sequentially depositing a TiN film (not shown) and a W film on the interlayer insulating film 18 and the plug P1, and etching the film into a desired shape. I do.
[0037]
Next, a contact hole C2 is formed by depositing, for example, a silicon oxide film as the interlayer insulating film 19 on the first layer wiring M1 and removing the interlayer insulating film 19 on the first layer wiring M1 by appropriate etching. A plug P2 is formed in the same manner as P1.
[0038]
Next, a second layer wiring M2 is formed on the plug P2. The step of forming the second layer wiring M2 will be described in detail with reference to FIGS. 4 to 11, layers below the plug P2 are omitted.
[0039]
As shown in FIG. 4, a silicon nitride film 22 is formed on the interlayer insulating film 19 and the plug P2, and then a silicon oxide film 23 is deposited by a CVD method. These laminated films are insulating films for wiring grooves in which wiring grooves are formed.
[0040]
Next, the silicon oxide film 23 on the region where the second layer wiring is to be formed is removed by etching, and the silicon nitride film 22 exposed by this etching is etched to form a wiring groove 25. This silicon nitride film 22 is used as an etching stopper. As shown in FIG. 4, there are various types of widths of the wiring groove 25. For example, the widths L1 to L4 have a relationship of L1 <L2 <L3 <L4.
[0041]
Next, as shown in FIG. 5, for example, a TiN film is deposited as a barrier layer 26 on the silicon oxide film 23 including the inside of the wiring groove 25 by, for example, a sputtering method.
[0042]
The barrier layer 26 is a single-layer film mainly composed of a Ta (tantalum), TaN (tantalum nitride) film, Ti (titanium), W, WN, titanium nitride silicide, tungsten nitride silicide, or the like, in addition to the TiN film. Alternatively, a stacked film of these films may be used. In forming the barrier layer 26, a film forming method with good coverage (coverability) is used. Good coverage (high coverage) refers to a state in which a film is deposited so as to cover the bottom, side walls, and upper corners of the wiring groove 25, and the film thickness has little variation.
[0043]
For example, in a sputtering method, an ionized metal bias sputter (IMBS) method has better coverage than a normal DC magnetron sputtering method. Further, not only the sputtering method but also a CVD method may be used. In this case, the coatability can be improved by adjusting the pressure, the film formation temperature, and the like.
[0044]
Next, as shown in FIG. 6, a copper alloy layer (copper + impurity metal) 27a is deposited on the barrier layer 26. At this time, the copper alloy layer 27a is deposited under conditions of poor coverage (low coverage).
[0045]
The condition of poor coverage refers to a condition in which a film is difficult to be formed on a side portion or a bottom portion of a narrower wiring groove. In other words, for example, the condition is such that the bottom, side walls, and upper portions of the side walls of the wiring groove having the width L2 are better covered than the wiring groove having the width L1. Similarly, a condition in which the wiring groove having the width L3 has better coverage than the wiring groove having the width L2. When the width of the wiring groove exceeds a certain width, its covering property does not change.
[0046]
The copper alloy layer 27a is a supply source of impurity metals (alloys and metals other than copper) of the copper alloy wiring formed in the wiring groove 25. Therefore, it is only necessary to contain at least the impurity metal to be diffused, and it is not necessary to contain copper. For example, only Au (gold) to be diffused may be formed.
[0047]
Examples of the metal contained in copper include magnesium (Mg), Ag (silver), Au, Pd (palladium), Ti, Ta (tantalum), aluminum (Al), Nb (niobium), and Zr (zirconium). ), Zn (zinc), W, Ru (ruthenium), nickel (Ni), chromium (Cr) and the like. These metals may be contained singly or in various kinds.
[0048]
Further, the metal contained in copper may be an alloy. For example, an Ag alloy, an Au alloy, an Al alloy, a W alloy, or the like may be used. In this case, in addition to Nb, Ti, Cu, etc., Si (silicon) or the like may be contained alone or in various kinds in the main metal (Ag, etc.) as an alloy.
[0049]
Among them, it is preferable to use Mg, Ni, Al, Cr, or the like as the metal contained in copper.
[0050]
Examples of the deposition method include a sputtering method and a CVD method. In addition, when the ordinary DC magnetron sputtering method is used, the coverage is deteriorated as compared with, for example, the case where the IMBS method is used.
[0051]
FIG. 12 shows an ordinary DC magnetron sputtering apparatus. FIG. 13 shows an IMBS device.
[0052]
As shown in FIG. 12, a susceptor 32 on which a substrate (semiconductor wafer) 1 is mounted is installed in a chamber (processing chamber) 31 of a general sputtering apparatus. Is arranged. On the back surface of the target, for example, a magnet 34 is provided. A high electric field (DC) is applied to the target. The pressure in the chamber 31 is reduced by a pump 35.
[0053]
For example, an argon (Ar) gas or the like is injected into the chamber, Ar ions are accelerated by an electric field, and the target atoms collide with the target and fly out by the recoil, thereby being deposited on the substrate.
[0054]
In the IMBS device of FIG. 13, a potential (RF) is also applied to the substrate. As described above, by applying a potential to the substrate, the target atoms easily adhere to the substrate. As a result, coverage can be improved.
[0055]
In FIG. 13, the distance (TS) between the substrate and the target is 200 mm or more, and the TS in FIG. 12 is less than 200 mm. The target atoms are repelled in various directions. However, if the distance between the substrate and the target is increased, the vertical component of the target atoms reaching the substrate can be increased. That is, the target atoms reach the bottoms of the grooves and holes, and the coverage can be improved. In addition, a grid-like shield (collimator) may be provided between the substrate and the target to selectively pass target atoms having a large vertical component, thereby improving the coverage.
[0056]
Note that the barrier layer 26 and the copper alloy layer 27a described above may be formed using an apparatus (a multi-chamber) having a chamber shown in FIGS. Further, a copper film described later may be formed. By using such a multi-chamber, contact with air (oxygen) can be reduced, and oxidation of the film surface can be reduced. In addition, the adhesion rate of foreign substances can be reduced.
[0057]
Next, as shown in FIG. 7, a thin copper film 27b is formed on the copper alloy layer 27a by a sputtering method. This copper film 27b becomes a seed layer at the time of electrolytic plating. Therefore, other conductive films (eg, copper alloy films) may be used, but in order to easily adjust the content (content, alloy concentration, alloy ratio) of other metals in the copper film, It is preferable to use a copper film. Further, this copper film 27b is deposited under conditions of good coverage. For example, it is deposited using the IMBS method.
[0058]
Next, as shown in FIG. 8, the substrate (wafer) 1 is immersed in a plating solution, and a potential is applied (electric field plating) to the seed layer (copper film 27b) to form a copper film 27c on the substrate 1. Precipitate and perform annealing (heat treatment).
[0059]
As a result, metals other than copper in the copper alloy layer 27a diffuse into the copper films 27b and 27c and are alloyed (FIG. 9). In FIG. 9, a portion where copper is alloyed is designated as 28a, and a portion of pure copper (concentration of impurities is extremely low) is designated as 28b. As described above, alloying may proceed inside the groove, and the upper portion of the copper film 27c may not be alloyed. The annealing need not be performed at the above timing, and may be performed, for example, after a later-described CMP process or the like. Further, the impurity metal may be diffused by using a subsequent step of applying heat.
[0060]
At this time, in a wiring groove having a small wiring width, for example, in a wiring groove having a width of L1 or L2, the copper alloy layer (27a) formed on the side wall or the bottom is thin or not formed, so that other metal in the copper film is not formed. The content (alloy concentration) is low or pure copper. In other words, it is close to pure copper or pure copper.
[0061]
Further, as the wiring width increases, for example, from L1 to L4, the degree of the impurity metal contained in the copper alloy film 28a (alloy concentration) increases. Note that L1 to L4 are in the range of 0.14 μm to several μm.
[0062]
Next, as shown in FIG. 10, the second layer wiring M2 is formed by removing the copper alloy film 28a and the like outside the wiring groove 25 by CMP. For example, the wiring formed in the wiring groove 25 having the width L1 is made of pure copper.
[0063]
As described above, in the present embodiment, the alloy supply source is deposited under the condition that the coverage becomes worse as the width of the wiring groove becomes smaller (the coverage becomes better as the wiring width becomes larger). Since the film was formed and alloyed, the content (alloy concentration) of other metals in the copper film increased as the wiring width increased.
[0064]
As a result, SM resistance is improved in a wiring having a large wiring width.
[0065]
That is, when the plug P2 is disposed below the wiring, in a wiring having a large wiring width, stress is applied when copper is condensed, and peeling occurs between the wiring having a low stress and the plug P2. When such peeling occurs, the SM resistance deteriorates, which causes a failure or a failure.
[0066]
On the other hand, in the present embodiment, in the case of the wiring having a large wiring width, alloying is performed, so that the movement of copper atoms can be suppressed and the condensation of copper can be suppressed. As a result, peeling between the wiring and the plug P2 can be reduced.
[0067]
In addition, when alloyed, an increase in wiring resistance poses a problem, but in this case, since the wiring width is large, a problem due to an increase in wiring resistance does not appear remarkably.
[0068]
On the other hand, in a wiring having a small wiring width, an increase in wiring resistance can be suppressed because the copper alloying ratio is small. Further, in a wiring having a small wiring width, even if the plug P2 is formed in the lower layer of the wiring, the effect of stress due to copper condensation is small even if the alloying ratio of copper is small because the volume of the wiring is small with respect to the diameter of the plug P2. Is small.
[0069]
As described above, the resistance of the wiring can be reduced and the SM resistance can be improved even at a part where the wiring width is large and a part where the wiring width is small.
[0070]
Further, according to the present embodiment, the electromigration (EM) resistance can be improved.
[0071]
That is, when the wiring width is small, the bamboo rate is high and the EM resistance is improved. The bamboo rate is a rate at which crystal grain boundaries exist in the direction of the wiring width. For example, when the grain (crystal grain) diameter is equal to the wiring width, the boundary of the grain (crystal grain boundary) crosses the wiring in the short side direction, and the EM path decreases (FIG. 23A). reference). As a result, EM resistance is improved.
[0072]
On the other hand, when the wiring width is large, a large number of grains are arranged along the short side of the wiring, and the number of EM paths along the direction in which current (electrons) flows (the long side direction of the wiring) increases ( FIG. 23 (b)). As a result, the EM resistance deteriorates. FIGS. 23A and 23B are schematic views (plan views) showing the relationship between the wiring width and the grain boundaries.
[0073]
However, in the present embodiment, the copper alloying rate increases as the wiring width increases, so that the movement of copper atoms by EM can be suppressed, and the EM resistance can be improved.
[0074]
Also, in this embodiment, the alloy supply source is formed using a film formation method with poor coverage (low coverage), so that a large number of alloy supply sources are provided in a wide wiring groove in a self-aligned manner. In addition, a small number of alloy supply sources can be formed in the narrow wiring groove.
[0075]
Thereafter, as shown in FIG. 11, a silicon nitride film 29 is formed as a barrier layer serving to prevent diffusion of copper and the like. Thereafter, by repeating the formation of the interlayer insulating film, the plug and the wiring, a further multilayer wiring can be formed. The illustration and description thereof are omitted. At this time, it is also possible to form a wiring above the second-layer wiring in the same manner as the second-layer wiring. Further, the first layer wiring can be formed in the same manner as the second layer wiring. Further, the plug in the layer above the second-layer wiring may be formed using a W film or the like as in the case of the plug P1, or may be formed using another metal, for example, copper. In addition, as a barrier layer that plays a role of preventing diffusion of copper or the like, an insulating barrier film such as silicon carbonitride (SiCN) or silicon carbide (SiC) may be used in addition to a silicon nitride film. Further, a conductive barrier film such as W or CoWB (cobalt tungsten containing boron) or CoWP (cobalt tungsten containing phosphorus) may be formed only on the second layer wiring M2.
[0076]
Further, a protective film is formed on the uppermost wiring, and a part (pad portion) of the uppermost wiring is exposed by removing the protective film. Next, the semiconductor integrated circuit device is connected by connecting the pad portion on the chip and the external terminal of the mounting board via a wire or a bump electrode, and sealing the periphery of the chip with a resin or the like as necessary. Complete. These illustrations are also omitted.
[0077]
(Embodiment 2)
In the first embodiment, a so-called single damascene method in which a wiring and a plug are formed in separate steps has been described as an example. However, a wiring and a plug portion may be formed by a dual damascene method. Note that the steps up to the step of forming the first layer wiring M1 are the same as those of the first embodiment, and a description thereof will be omitted. 14 to 22 are cross-sectional views of main parts of a substrate showing a method for manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention. In these drawings, layers below the plug P2 are omitted.
[0078]
For example, as shown in FIG. 14, a stacked film of, for example, a silicon nitride film and a silicon oxide film is deposited as an interlayer insulating film 219 on the first layer wiring. A contact hole is formed in the laminated film. Next, a silicon nitride film 22 is formed on the interlayer insulating film 219, and then a silicon oxide film 23 is deposited by a CVD method. These laminated films (22, 23) are insulating films for wiring grooves in which wiring grooves are formed.
[0079]
Next, a contact hole C2 is formed by etching the interlayer insulating film 219, the silicon nitride film 22, and the silicon oxide film 23 on the region where the plug is to be formed.
[0080]
Next, as shown in FIG. 15, the silicon oxide film 23 on the region where the second layer wiring is to be formed is removed by etching, and the silicon nitride film 22 exposed by this etching is etched to form a wiring groove 25. . This silicon nitride film 22 is used as an etching stopper. After forming the wiring groove 25, the contact hole C2 may be formed.
[0081]
As shown in FIG. 15, there are various types of widths of the wiring groove 25. For example, the widths L1 to L4 have a relationship of L1 <L2 <L3 <L4.
[0082]
Next, as shown in FIG. 16, for example, a TiN film is deposited as a barrier layer 26 on the silicon oxide film 23 including the inside of the contact hole C2 and the wiring groove 25 by, for example, a sputtering method as in the first embodiment.
[0083]
Next, as shown in FIG. 17, a copper alloy layer 27a is deposited on the barrier layer 26 in the same manner as in the first embodiment. That is, the copper alloy layer 27a is deposited under conditions of poor coverage (low coverage).
[0084]
As described in the first embodiment, the condition of poor coverage refers to a condition in which a film is hardly formed on a side portion or a bottom portion of a narrower wiring groove. In other words, it means that the bottom, side walls, and upper portions of the side walls of the wiring groove having the width L2 are better covered than the wiring groove having the width L1, for example.
[0085]
The copper alloy layer 27a is a source of an alloy (metal other than copper) of the copper alloy wiring formed in the wiring groove 25. Therefore, it is only necessary to contain at least the impurity metal to be diffused, and it is not necessary to contain copper.
[0086]
The metal contained in copper is as described in the first embodiment. Examples of the deposition method include a sputtering method and a CVD method. Further, as described in the first embodiment, when the ordinary DC magnetron sputtering method is used, the coverage is deteriorated as compared with, for example, the case where the IMBS method is used.
[0087]
Next, as shown in FIG. 18, a thin copper film 27b is formed on the copper alloy layer 27a by a sputtering method. This copper film 27b becomes a seed layer at the time of electrolytic plating. Therefore, other conductive films (eg, copper alloy films) may be used, but in order to easily adjust the content (content, alloy concentration, alloy ratio) of other metals in the copper film, It is preferable to use a copper film. Further, this copper film 27b is deposited under conditions of good coverage. For example, it is deposited using the IMBS method.
[0088]
Next, as shown in FIG. 19, the substrate (wafer) 1 is immersed in a plating solution, and a potential is applied (electric field plating) to the seed layer (copper film 27b) to form a copper film 27c on the substrate 1. Precipitate and perform annealing (heat treatment).
[0089]
As a result, metals other than copper in the copper alloy layer 27a diffuse into the copper films 27b and 27c and are alloyed (FIG. 20). In FIG. 20, a portion where copper is alloyed is referred to as 28a, and a portion of pure copper (the concentration of impurities is extremely low) is referred to as 28b. As described above, alloying may proceed inside the groove, and the upper portion of the copper film 27c may not be alloyed. The annealing need not be performed at the above timing, and may be performed, for example, after a later-described CMP process or the like. Further, the impurity metal may be diffused by using a subsequent step of applying heat.
[0090]
At this time, in a wiring groove having a small wiring width, for example, in a wiring groove having a width of L1 or L2, the copper alloy layer (27a) formed on the side wall or the bottom is thin or not formed, so that other metal in the copper film is not formed. The content (alloy concentration) is low or pure copper. In other words, it is close to pure copper or pure copper.
[0091]
Further, as the wiring width increases, for example, from L1 to L4, the degree of the impurity metal contained in the copper alloy film 28a (alloy concentration) increases. Note that L1 to L4 are in the range of 0.14 μm to several μm.
[0092]
Next, as shown in FIG. 21, the copper alloy film 28a and the like outside the wiring groove 25 are removed by CMP to form a second layer wiring M2 and a plug P2. For example, the wiring formed in the wiring groove 25 having the width L1 is made of pure copper.
[0093]
As described above, in the present embodiment, similarly to the first embodiment, the alloy supply source under the condition that the coverage becomes worse as the width of the wiring groove becomes smaller (the coverage becomes better as the wiring width becomes larger). Is deposited, and a copper film is formed thereon and alloyed. As the wiring width increases, the content of other metals in the copper film (alloy concentration) increases. As a result, the effects described in detail in the first embodiment, such as improvement in SM resistance and EM resistance, can be achieved.
[0094]
Further, in the present embodiment, since no barrier film exists between the wiring portion and the plug portion, the alloy in the copper alloy film deposited at the bottom of the wide wiring groove or the like may be used as the copper film in the contact hole C2. The diffusion into the plugs 27b and 27c also makes it possible to alloy the plug P2.
[0095]
As a result, the copper atoms of the plug P2 are less likely to move, and the SM resistance and the EM resistance at the boundary between the plug P2 and the second layer wiring M2 can be improved.
[0096]
Thereafter, as in the first embodiment, for example, a silicon nitride film 29 is formed as a barrier layer (FIG. 22). Thereafter, a multilayer wiring is further formed, and a part (pad portion) of the uppermost layer wiring is exposed by removing a protective film on the uppermost layer wiring, and thereafter, mounting is performed.
[0097]
As described above, the present invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0098]
In particular, in the above-described embodiment, the present invention is applied to the wiring formed on the MISFET and the like, but the present invention is widely applicable to a semiconductor integrated circuit device using a multilayer wiring.
[0099]
【The invention's effect】
The effects obtained by the typical inventions among the inventions disclosed in the present application will be briefly described as follows.
[0100]
A first groove formed in an insulating film and a first groove formed in a second groove wider than the first groove, the first and second grooves each containing a second metal as a main component. Since the content of the second metal in the second wiring is higher than that in the first wiring of the two wirings, the wiring resistance can be reduced and the SM resistance of the wiring can be improved. In addition, EM resistance can be improved. Further, the characteristics of the wiring can be improved. Further, the reliability of the semiconductor integrated circuit device can be improved.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 3 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 5 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 6 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 1 of the present invention;
FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 10 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 1 of the present invention;
FIG. 11 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 12 is a sectional view showing a normal DC magnetron sputtering apparatus used for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 13 is a sectional view showing a sputtering apparatus (IMBS apparatus) used for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 14 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 15 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 16 is a fragmentary cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;
FIG. 17 is a fragmentary cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 18 is a fragmentary cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;
FIG. 19 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 20 is an essential part cross sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 21 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 22 is an essential part cross sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 23 is a schematic diagram (plan view) showing a relationship between a wiring width and a grain boundary of a grain.
[Explanation of symbols]
1 semiconductor substrate (substrate)
2 Element separation
3 p-type well
4 n-type well
5 Gate oxide film
7 Gate electrode
8 n ⁻ Type semiconductor region
9 p ⁻ Type semiconductor region
10 Sidewall
11 n ⁺ Type semiconductor region
12 p ⁺ Type semiconductor region
16 Silicide layer
18 interlayer insulating film
19 Interlayer insulation film
22 Silicon nitride film
23 Silicon oxide film
25 Wiring groove
26 Barrier layer
27a Copper alloy layer
27b Copper film
27c copper film
28a Copper alloy film
28b pure copper
29 Silicon nitride film
31 chambers
32 susceptor
33 Target
34 magnet
35 pump
219 Interlayer insulating film
C1 contact hole
C2 contact hole
DC electric field
L1 to L4 Wiring groove width
M1 First layer wiring
M2 Second layer wiring
P1 plug
P2 plug
Qn n-channel type MISFET
Qp p-channel type MISFET
RF electric field
Distance between TS substrate and target

Claims (5)

(A) an insulating film formed on a semiconductor substrate;
(B) a first groove formed in the insulating film and a second groove wider than the first groove;
(C) first and second wirings each containing a first metal as a main component and a second metal formed inside the first and second grooves, respectively;
A semiconductor integrated circuit device having
(D) The semiconductor integrated circuit device, wherein the second wiring has a higher content of the second metal than the first wiring. (A) an insulating film formed on a semiconductor substrate;
(B) a first groove formed in the insulating film and a second groove wider than the first groove;
(C) first and second wirings mainly containing copper formed inside the first and second trenches and containing a metal other than copper,
A semiconductor integrated circuit device having
(D) The semiconductor integrated circuit device, wherein the second wiring has a higher content of a metal other than the copper than the first wiring. (A) forming an insulating film on a semiconductor substrate, and selectively etching the insulating film to form a first groove and a second groove wider than the first groove;
(B) depositing a first metal film on the insulating film including the insides of the first groove and the second groove, wherein a bottom portion, a side wall, and an upper portion of the side wall of the first groove are covered; Depositing the first metal film under conditions in which the bottom, side walls, and upper portions of the side walls of the second groove have better coverage than the first groove;
(C) after the step (b), depositing a second metal film on the insulating film including the inside of the first groove and the second groove;
(D) after the step (c), performing a heat treatment to diffuse the metal in the first metal film into the second metal film;
A method for manufacturing a semiconductor integrated circuit device, comprising: 4. The method according to claim 3, wherein in the step (b), the first metal film is formed by an ionized metal bias sputtering method. (A) forming an insulating film on a semiconductor substrate, and selectively etching the insulating film to form a first groove and a second groove wider than the first groove;
(B) depositing a metal other than copper on the insulating film including the inside of the first groove and the second groove, and covering a bottom, a side wall, and an upper part of the side wall of the first groove; Depositing a metal other than copper under conditions that the bottom, side walls, and the upper part of the side walls of the second groove have good coatability due to their properties;
(C) after the step (b), depositing copper on the insulating film including the insides of the first groove and the second groove;
(D) a step of diffusing a metal other than the copper into the copper by performing a heat treatment after the step (c);
A method for manufacturing a semiconductor integrated circuit device, comprising:

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