JP2004282063A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to peel off an element formation layer including a semiconductor element over a substrate or an element formation layer including an integrated circuit over a substrate from a substrate and then attaching the element formation layer to another substrate. Provided are a method for manufacturing a semiconductor device including a transfer step in which adhesion to a layer can be controlled, and a semiconductor device manufactured using the method.
According to the present invention, an adhesive body made of a material having high adhesion is formed between a substrate and a semiconductor element formed over the substrate (also referred to as a first substrate). Alternatively, an adhesive body made of a material having high adhesiveness is formed between the substrate and an integrated circuit formed by a plurality of semiconductor elements formed over the substrate. This prevents the semiconductor element or the integrated circuit from peeling off from the substrate during the manufacture of the semiconductor element or the integrated circuit, and removes the adhesive after forming the semiconductor element or the integrated circuit, thereby removing the semiconductor element from the substrate. Alternatively, peeling of the integrated circuit can be facilitated.
[Selection diagram] Fig. 1

Description

  The present invention relates to a method for manufacturing a semiconductor device including a step of transferring a semiconductor element such as a thin film transistor (TFT) formed on a substrate to another substrate, and a semiconductor device manufactured by the method.

The present invention also provides a method for manufacturing a semiconductor device including a step of transferring an integrated circuit including a plurality of semiconductor elements (including thin film transistors (TFTs)) formed on a substrate to another substrate, and a method for manufacturing the semiconductor device. The present invention relates to a semiconductor device to be manufactured.

  2. Description of the Related Art In recent years, various technologies have been developed for a semiconductor element represented by a thin film transistor (TFT) formed using a semiconductor thin film (having a thickness of several to several hundred nm) formed on the same substrate.

  In order to ensure the characteristics of the semiconductor element, a certain high temperature is required in the manufacturing process. At present, the introduction of laser crystallization as part of the fabrication process has resulted in a significant reduction in process temperature, and as a result, the fabrication of semiconductor devices on glass substrates, which has been impossible with high-temperature processes, has been realized. It is possible.

  However, in the case of forming a semiconductor element on a flexible substrate such as a plastic, for example, further lowering the temperature is required, which is extremely difficult from the viewpoint of the heat resistance of the substrate.

  On the other hand, a method of forming a semiconductor element on a glass substrate and then transferring the semiconductor element to a flexible substrate such as plastic is an effective method because a thermal inhibition factor for the substrate can be essentially eliminated. Has been shown.

As a method for separating a semiconductor element formed on a substrate from a substrate, several methods have been proposed. 1) After a semiconductor element is formed on a glass substrate, the glass substrate is dissolved by an etching method. After isolating the element, a method of attaching the element on a plastic substrate (for example, see Patent Document 1), or 2) peeling off the semiconductor element formed on the substrate from the substrate, followed by a flexible substrate such as plastic There is known a method of pasting on the top (for example, see Patent Document 2).
JP 2002-184959 A JP-A-10-125931

  In the case of the method 1), after the semiconductor element is formed on the substrate, the substrate and the semiconductor element can be surely separated from each other, but the process time is long and the material cost of the etching agent and the glass substrate is large. is there.

  In the case of the method 2), control of adhesion and film stress is extremely important. That is, if the adhesion is reduced and the film stress is increased, the separation becomes easier, but there is a problem that the separation occurs during the manufacture of the semiconductor element. Further, if the adhesion is increased, peeling does not occur during the manufacture of the semiconductor element, but there is a problem that it is difficult to peel off the semiconductor element after forming the semiconductor element.

  In the present invention, when the element formation layer including the semiconductor element formed on the substrate is peeled off from the substrate as in 2) and then attached to another substrate, the adhesion between the substrate and the element formation layer is reduced. It is an object to provide a method for manufacturing a semiconductor device including a controllable transfer step.

  Therefore, in order to solve the above problem, according to the present invention, when fabricating the element formation layer, while improving the adhesion between the substrate and the semiconductor element, after forming the element formation layer, the adhesion between the substrate and the element formation layer is improved. It is characterized by lowering the performance.

  Specifically, by forming an adhesive body between a semiconductor element formed over a substrate (also referred to as a first substrate) and the substrate, peeling of the semiconductor element from the substrate during manufacturing of the semiconductor element is prevented. In other words, the adhesive is removed after the semiconductor element is formed, thereby facilitating the peeling of the semiconductor element from the substrate.

  Note that the adhesive in the present invention is made of a material having high adhesion to a metal layer formed in advance on a substrate in order to easily separate the semiconductor element from the substrate. A material which can form a metal compound (including silicide) or an alloy by being formed in contact with and reacting with a metal in the metal layer can be used.

  The reaction between the metal in the metal layer and the adhesive can be intentionally subjected to a heat treatment, but can be promoted by a heat treatment or the like in the production of an element formation layer (including a TFT) in a later step.

  A metal layer is provided over a substrate, an adhesive is formed, an oxide layer is formed to cover the metal layer and the adhesive, and the adhesion between the metal layer and the oxide layer on the substrate is increased by the adhesive. Further, an element formation layer including a semiconductor element is formed over the oxide layer.

  Note that as a method for removing the adhesive body after the element formation layer is formed, an etching method can be used, and the adhesive can be removed by etching together with part of the element formation layer that has been formed. As an etching method, a wet etching method or a dry etching method can be used.

  Note that the opening formed in a part of the element formation layer by etching may be left as it is, but may be made of the same insulating material as the material removed by etching after removing the adhesive, or another insulating material. It may be filled using.

  Then, by applying a physical force, the substrate and the element formation layer can be separated. This is because a metal layer and an oxide layer which are formed in advance on a substrate are likely to peel off at the lamination interface due to a process of forming a semiconductor element on the oxide layer, etc. Is formed to increase the adhesion, but the adhesion at the interface is reduced again by removing the adhesive. Then, the transferred element formation layer is completed by attaching the separated element formation layer to another substrate.

  Note that, in the structure of the present invention, a metal layer is formed over a first substrate, an adhesive is formed over part of the metal layer, and an oxide layer is formed to cover the metal layer and the adhesive. Forming a semiconductor element on the oxide layer, and removing the adhesive. In this case, by including a heat treatment step at 400 ° C. or more, preferably 600 ° C. or more in the formation of the semiconductor element, the adhesion between the metal layer and the adhesive can be further improved. By applying a heat treatment of 400 ° C. or more, the interface between the metal layer and the adhesive can be stabilized, and by applying a heat treatment of 600 ° C. or more, the metal layer reacts with the adhesive. Can be done.

  Note that in the above structure, the semiconductor element (such as a TFT) is included in the element formation layer. As a method for removing the adhesive, it is preferable to simultaneously remove a part of the element formation layer by etching.

  Note that in the above structure, the interface between the metal layer and the oxide layer is subjected to heat treatment in a step of forming an element formation layer, whereby the adhesion at the interface is reduced. When heat treatment is applied in the step of manufacturing the element formation layer, the element reacts with the metal material contained in the metal layer, so that the adhesion is increased. Thus, the element formation layer can be formed without the element formation layer being separated from the substrate.

  After the element formation layer is formed, the adhesive is removed by etching together with a part of the element formation layer, so that the adhesion between the first substrate and the element formation layer can be reduced.

  Note that, in the above configuration, after the adhesive is removed, attaching the second substrate to the element formation layer via the first adhesive can easily remove the element formation layer from the first substrate. It is more preferable because it can be peeled off.

  Further, in the above configuration, the element formation layer was formed by attaching the second substrate and the element formation layer separated from the first substrate to a third substrate via a second adhesive. The element formation layer can be transferred to a third substrate different from the first substrate. After the transfer, the second substrate may be removed from the element formation layer.

  Further, according to the present invention, when an element formation layer including an integrated circuit formed of a plurality of semiconductor elements formed on a substrate is peeled off from the substrate as in 2) and then attached to another substrate, An object of the present invention is to provide a method for manufacturing a semiconductor device including a transfer step capable of controlling the adhesion between a substrate and an element formation layer.

  Therefore, in order to solve the above problem, according to the present invention, when fabricating the element formation layer, while improving the adhesion between the substrate and the semiconductor element, after forming the element formation layer, the adhesion between the substrate and the element formation layer is improved. It is characterized by lowering the performance.

  Specifically, by forming an adhesive body made of a material with high adhesion between an integrated circuit including a plurality of semiconductor elements formed over a substrate (also referred to as a first substrate) and the substrate, The semiconductor device is prevented from peeling off from the substrate during fabrication of the integrated circuit, and the adhesive is removed after the integrated circuit is formed, thereby facilitating the peeling of the integrated circuit from the substrate. Note that the integrated circuit includes circuits such as a CPU (Central Processing Unit), an MPU (Micro Processor Unit), a memory, a microcomputer, and an image processor.

  Note that the adhesive in the present invention is made of a material having high adhesion to a metal layer formed in advance on a substrate in order to easily separate an integrated circuit from the substrate. A material which can form a metal compound (including silicide) or an alloy by being formed in contact with and reacting with a metal in the metal layer can be used.

  In addition, the reaction between the metal in the metal layer and the adhesive can be intentionally subjected to heat treatment, but can be accelerated in a later step by heat treatment or the like in manufacturing an element formation layer (including an integrated circuit). .

  In this manner, an element forming layer including an integrated circuit including a plurality of semiconductor elements is formed on the oxide layer after the adhesion between the metal layer and the oxide layer on the substrate is increased by the adhesive.

  Note that as a method for removing the adhesive body after the element formation layer is formed, an etching method can be used, and the adhesive can be removed by etching together with part of the element formation layer that has been formed. As an etching method, a wet etching method or a dry etching method can be used.

  Note that the opening formed in a part of the element formation layer by etching may be left as it is, but may be made of the same insulating material as the material removed by etching after removing the adhesive, or another insulating material. It may be filled using.

  Then, by applying a physical force, the substrate and the element formation layer can be separated. This is because a metal layer and an oxide layer that are formed in advance on a substrate are likely to peel off at the lamination interface due to a process of forming an integrated circuit (a plurality of TFTs) on the oxide layer. Although the adhesion was increased by forming an adhesive at the interface, the adhesion at the interface was reduced again by removing the adhesive. Then, the transferred element formation layer is completed by attaching the separated element formation layer to another substrate.

  Note that, in the structure of the present invention, a metal layer is formed over a first substrate, an adhesive is formed over part of the metal layer, and an oxide layer is formed to cover the metal layer and the adhesive. Forming an integrated circuit including a plurality of semiconductor elements on the oxide layer and removing the adhesive. In this case, by including a heat treatment step at 400 ° C. or more, preferably 600 ° C. or more in the formation of the semiconductor element, the adhesion between the metal layer and the adhesive can be further improved. By applying a heat treatment of 400 ° C. or more, the interface between the metal layer and the adhesive can be stabilized, and by applying a heat treatment of 600 ° C. or more, the metal layer reacts with the adhesive. Can be done.

  Note that in the above structure, an integrated circuit including a plurality of semiconductor elements (such as TFTs) is included in an element formation layer. As a method for removing the adhesive, it is preferable to simultaneously remove a part of the element formation layer by etching.

  Note that in the above structure, the interface between the metal layer and the oxide layer is subjected to heat treatment in the step of forming the element formation layer, so that the adhesion at the interface is reduced. When heat treatment is applied in the step of manufacturing the element formation layer, the element reacts with the metal material contained in the metal layer, so that the adhesion is increased. Thus, the element formation layer can be formed without the element formation layer being separated from the substrate.

  After the element formation layer is formed, the adhesive is removed by etching together with a part of the element formation layer, so that the adhesion between the first substrate and the element formation layer can be reduced.

  Note that, in the above configuration, after the adhesive is removed, attaching the second substrate to the element formation layer via the first adhesive can easily remove the element formation layer from the first substrate. It is more preferable because it can be peeled off.

Further, in the above configuration, the element formation layer was formed by attaching the second substrate and the element formation layer separated from the first substrate to a third substrate via a second adhesive. The element formation layer can be transferred to a third substrate different from the first substrate. After the transfer, the second substrate may be removed from the element formation layer.

One aspect of the present invention includes an adhesive layer on a substrate, a first insulating film on the adhesive layer, and the first insulating film is bonded to the substrate via at least the adhesive layer. Has at least one thin film transistor on the first insulating film, has a second insulating film covering the thin film transistor, the first insulating film and the second insulating film are removed, and the adhesive layer is formed. A semiconductor device having an opening to be exposed, a third insulating film filling the opening, and further covering a second insulating film.

One aspect of the present invention includes an adhesive layer on a substrate, a first insulating film on the adhesive layer, and the first insulating film is bonded to the substrate via at least the adhesive layer. And an integrated circuit including a plurality of thin film transistors on the first insulating film, a second insulating film covering the integrated circuit, and the first insulating film and the second insulating film are removed. And a third insulating film that has an opening for exposing the adhesive layer, fills the opening, and further covers the second insulating film.

Note that in the above structure, a flexible substrate such as a plastic substrate can be used.

Further, the adhesive layer can be formed by using an adhesive such as a photo-curable adhesive such as a reactive curable type, a thermosetting type, or an ultraviolet curable type, or various curable adhesives such as an anaerobic type adhesive.

Further, the insulating film is made of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, acrylic (including photosensitive acrylic), polyacryl (including photosensitive polyacryl), polyimide, polyamide, or BCB (benzocyclobutene). ) Can be used.

  According to the present invention, by forming an adhesive body on a substrate in advance, it is possible to increase the adhesion to a substrate at the time of manufacturing an element formation layer including a semiconductor element (such as a TFT). Of the element forming layer can be prevented. On the other hand, since the adhesive can be removed after the element formation layer is formed, peeling can be easily performed by reducing the adhesion between the substrate and the element formation layer. That is, the adhesion between the substrate and the element formation layer in manufacturing a semiconductor device can be controlled.

  Further, according to the present invention, by forming an adhesive body on a substrate in advance, it is possible to increase the adhesion to the substrate at the time of manufacturing an element formation layer including an integrated circuit. Peeling of the formation layer can be prevented. On the other hand, since the adhesive can be removed after the element formation layer is formed, separation from the substrate can be easily performed by reducing the adhesion between the substrate and the element formation layer. That is, the adhesion between the substrate and the element formation layer in manufacturing a semiconductor device can be controlled.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG.

  FIG. 1A shows a top view of a substrate on which the adhesive body of the present invention is formed, and FIG. 1B shows a cross-sectional view taken along a broken line AA ′ in FIG. . That is, the adhesive body 103 is formed in an island shape in contact with the metal layer 102 formed over the substrate 101 as shown in FIG. Note that the adhesive formed here is formed between the metal layer 102 and the oxide layer 104 to be formed next, so that the adhesion between the metal layer 102 and the oxide layer 104 can be increased.

  As a material used for the substrate 101, a quartz substrate, a glass substrate, or the like can be used. When a device formation layer (including a TFT) formed over the substrate is separated from the substrate in a later step, its strength and the like are reduced. If is insufficient, a plurality of substrates can be bonded and used.

  Note that as a material for forming the metal layer 102, tungsten (W), molybdenum (Mo), technetium (Tc), rhenium (Re), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir) ), Palladium (Pd), platinum (Pt), silver (Ag), or gold (Au), alloys containing these elements as main components, or nitrides (eg, titanium nitride, tungsten nitride, nitride Tantalum, molybdenum nitride) can be used as a single layer or a stacked layer.

  Further, the adhesive 103 formed on the metal layer 102 is formed around the TFT formed on the oxide layer 104. That is, as shown in FIG. 1A, after the bonding body 103 is formed, a TFT is formed in a region 105 covered by a dotted line. Note that the arrangement and shape of the adhesive body 103 are not limited to those shown in FIG. 1A and can be appropriately designed.

  Note that the adhesive body 103 is made of a material having high adhesion to the metal layer 102 formed over the substrate 101 so that the element formation layer (including the TFT) can be easily separated from the substrate. A material that is formed in contact with the metal layer 102 and reacts with a metal in the metal layer 102 to form a metal compound or alloy, such as silicon, which forms silicide, germanium, carbon, boron, magnesium, aluminum, titanium, It is formed by using a metal material such as tantalum, iron, cobalt, nickel, and manganese.

  Further, the adhesive body 103 can be formed by forming a film by a film forming method such as a CVD (Chemical Vapor Deposition) method, a sputtering method, and a vapor deposition method, and then patterning the film.

For the oxide layer in the present invention, silicon oxide, silicon oxynitride (SiO _x N _y ), silicon nitride, or the like can be used, and can be formed by a sputtering method, a CVD method, or the like.

  Further, in the present invention, after the TFT 106 which is a semiconductor element is formed over the oxide layer 104, the adhesive is removed as shown in FIGS. 1C and 1D. Note that FIG. 1C shows a top view of the substrate on which the TFT 106 is formed, and FIG. 1D shows a cross-sectional view taken along a broken line BB # in FIG. 1C. As a method for removing the adhesive 103, an etching method (dry etching, wet etching) can be used, and the adhesive 103 is removed together with part of the interlayer insulating film and the oxide layer 104 in the element formation layer 107. . That is, a region a (111) in FIG. 1C shows a portion where the adhesive body 103 has been removed.

  Note that by removing the adhesive 103, the adhesion between the metal layer 102 and the oxide layer 104 on the substrate 101, which has been increased by the adhesive 103, decreases.

  Next, after an auxiliary substrate (also referred to as a second substrate) 110 is attached over the element formation layer 107 including the TFT 106 via an adhesive layer (also referred to as a first adhesive layer) 109, physical force is applied. With the addition, the element formation layer 107 and the auxiliary substrate 110 can be separated from the substrate 101. Note that in this case, separation can be performed at the interface between the metal layer 102 and the oxide layer 104 over the substrate 101. Hereinafter, the layer formed by the adhesive is referred to as an adhesive layer.

  Further, in the present invention, the opening formed when removing the adhesive 103 can be filled with an insulating material. Note that the insulating material used here may be an organic insulating material or an inorganic insulating material. Specifically, silicon oxide, silicon nitride, silicon oxynitride, and the like can be used as the inorganic insulating material, and acrylic (including photosensitive acrylic) and polyacryl (including photosensitive polyacryl) can be used as the organic insulating material. , Polyimide, polyamide, BCB (benzocyclobutene) and the like can be used.

  For the adhesive layer (first adhesive layer) 109, a material from which the auxiliary substrate (second substrate) 110 can be separated from the element formation layer 107 later is used. For example, an adhesive material whose adhesive strength is reduced by irradiation with ultraviolet light or heating is used. Further, a double-sided tape or the like can be used as the adhesive material. Further, after the auxiliary substrate (second substrate) 110 is peeled off, the element forming layer 107 and the adhesive layer (first adhesive layer) 109 are formed to facilitate removal of the remaining adhesive layer (first adhesive layer) 109. A film made of a water-soluble organic resin can be formed in between. In this case, the remainder of the adhesive layer (first adhesive layer) 109 can be removed at the same time by removing the film made of the water-soluble organic resin by washing with water.

  After the auxiliary substrate 110 is attached to the element formation layer 107, the element formation layer 107 is separated from the substrate 101 together with the auxiliary substrate 110. At this time, separation between the metal layer 102 and the oxide layer 104 over the substrate 101 can be performed. Then, an adhesive layer (also referred to as a second adhesive layer) (not illustrated here) is formed over the separated element formation layer 107 over another substrate (also referred to as a third substrate), for example, a flexible substrate such as plastic. Use and paste.

  Note that a thermoplastic or thermosetting synthetic resin can be used as the flexible substrate such as the plastic. For example, polyethylene, polypropylene, polystyrene, polyamide, polyimide, polyamideimide, polycarbonate (PC), acrylic resin, nylon, polymethyl methacrylate, acryl-styrene copolymer (AS resin), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide polyethylene, polypropylene, fluorine resin, styrene resin, polyolefin resin, melamine resin, phenol resin, norbornene resin and the like can be used.

  The adhesive layer (second adhesive layer) includes various curable adhesives such as a reaction curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive. And the like, but an ultraviolet curable adhesive is preferable from the viewpoint of work efficiency.

  Finally, the transfer of the present invention is completed by removing the auxiliary substrate 110. Specifically, the adhesive strength of the adhesive layer (first adhesive layer) 109 is reduced by irradiating or heating with ultraviolet light, and the element formation layer attached to the substrate (third substrate). The auxiliary substrate 110 is separated from 107. Further, in the case where a film made of a water-soluble organic resin is formed between the element forming layer 107 and the adhesive layer (first adhesive layer) 109, the film made of the water-soluble organic resin is washed with water. , And the remainder of the adhesive layer (first adhesive layer) 109 can be removed.

[Embodiment 2]
An embodiment of the present invention will be described with reference to FIG.

  FIG. 14A is a top view of a substrate on which the adhesive body of the present invention is formed, and FIG. 14B is a cross-sectional view taken along a broken line AA ′ in FIG. . That is, the adhesive 3103 is formed in an island shape in contact with the metal layer 3102 formed over the substrate 3101 as shown in FIG. Note that the adhesive formed here is formed between the oxide layer 3104 and the oxide layer 3104 to be formed next, so that the adhesion between the metal layer 3102 and the oxide layer 3104 can be increased.

  As a material used for the substrate 3101, a quartz substrate, a glass substrate, or the like can be used. In a later step, when an element formation layer (including a plurality of integrated circuits) formed over the substrate is separated from the substrate, When the strength or the like is insufficient, a plurality of substrates can be bonded and used.

  Note that as a material for forming the metal layer 3102, tungsten (W), molybdenum (Mo), technetium (Tc), rhenium (Re), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir) ), Palladium (Pd), platinum (Pt), silver (Ag), or gold (Au), alloys containing these elements as main components, or nitrides (eg, titanium nitride, tungsten nitride, nitride Tantalum, molybdenum nitride) can be used as a single layer or a stacked layer.

  In addition, the adhesive 3103 formed over the metal layer 3102 is formed around an integrated circuit including a plurality of TFTs formed over the oxide layer 3104. That is, as shown in FIG. 14A, after the adhesive 3103 is formed, an integrated circuit including a plurality of TFTs is formed in a region 3105 covered by a dotted line. Note that the arrangement and shape of the adhesive 3103 are not limited to those shown in FIG. 14A, and can be appropriately designed.

  Note that the adhesive 3103 is a material having high adhesion to the metal layer 3102 formed over the substrate 3101 so that the element formation layer (including a plurality of integrated circuits including a plurality of TFTs) can be easily separated from the substrate. Specifically, a material that is formed in contact with the metal layer 3102 to react with a metal in the metal layer 3102 to form a metal compound or alloy, for example, silicon that forms silicide, germanium, It is formed by using a metal material such as carbon, boron, magnesium, aluminum, titanium, tantalum, iron, cobalt, nickel, and manganese.

  Further, the adhesive 3103 can be formed by forming a film by a film forming method such as a CVD (Chemical Vapor Deposition) method, a sputtering method, or a vapor deposition method, and then patterning the film.

For the oxide layer in the present invention, silicon oxide, silicon oxynitride (SiO _x N _y ), silicon nitride, or the like can be used, and can be formed by a sputtering method, a CVD method, or the like.

  In addition, in the present invention, after a plurality of integrated circuits 3106 including a plurality of TFTs are formed over the oxide layer 3104, the adhesive 3103 is removed as illustrated in FIGS. 14C and 14D. . Note that FIG. 14C illustrates a top view of the substrate over which the integrated circuit 3106 is formed, and FIG. 14D illustrates a cross-sectional view taken along a dashed line BB ′ in FIG. . As a method for removing the adhesive 3103, an etching method (dry etching or wet etching) can be used, and the adhesive 3103 is removed together with part of the interlayer insulating film and the oxide layer 3104 in the element formation layer 3107. . That is, a region a (111) in FIG. 14C shows a portion where the adhesive 3103 has been removed.

  Note that by removing the adhesive 3103, the adhesion between the metal layer 3102 and the oxide layer 3104 on the substrate 3101 which has been increased by the adhesive 3103 is reduced.

  Next, an auxiliary substrate (also referred to as a second substrate) 3110 is attached over an element formation layer 3107 including the integrated circuit 3106 through an adhesive layer (also referred to as a first adhesive layer) 3109 and then physically attached. By applying force, the element formation layer 3107 and the auxiliary substrate 3110 can be separated from the substrate 3101. Note that in this case, separation can be performed at the interface between the metal layer 3102 and the oxide layer 3104 over the substrate 3101.

  Further, in the present invention, the opening formed when removing the adhesive 3103 can be filled with an insulating material. Note that the insulating material used here may be an organic insulating material or an inorganic insulating material. Specifically, silicon oxide, silicon nitride, silicon oxynitride, and the like can be used as the inorganic insulating material, and acrylic (including photosensitive acrylic) and polyacryl (including photosensitive polyacryl) can be used as the organic insulating material. , Polyimide, polyamide, BCB (benzocyclobutene) and the like can be used.

  For the adhesive layer (first adhesive layer) 3109, a material from which the auxiliary substrate (second substrate) 3110 can be peeled later from the element formation layer 3107 is used. For example, an adhesive material whose adhesive strength is reduced by irradiation with ultraviolet light or heating is used. Further, a double-sided tape or the like can be used as the adhesive material. Further, after the auxiliary substrate (second substrate) 3110 is peeled off, the element forming layer 3107 and the adhesive layer (first adhesive layer) 3109 are formed so that the remaining adhesive layer (first adhesive layer) 3109 can be easily removed. A film made of a water-soluble organic resin can be formed in between. In this case, the remaining adhesive layer (first adhesive layer) 3109 can be removed at the same time by removing the film made of the water-soluble organic resin by washing with water.

  After the auxiliary substrate 3110 is attached to the element formation layer 3107, the element formation layer 3107 is separated from the substrate 3101 together with the auxiliary substrate 3110. At this time, separation between the metal layer 3102 over the substrate 3101 and the oxide layer 3104 can be performed. Then, the separated element formation layer 3107 is provided with an adhesive layer (also referred to as a second adhesive layer) (not illustrated here) on another substrate (also referred to as a third substrate), for example, a flexible substrate such as plastic. Use and paste.

  Note that a thermoplastic or thermosetting synthetic resin can be used as the flexible substrate such as the plastic. For example, polyethylene, polypropylene, polystyrene, polyamide, polyimide, polyamideimide, polycarbonate (PC), acrylic resin, nylon, polymethyl methacrylate, acryl-styrene copolymer (AS resin), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide polyethylene, polypropylene, fluorine resin, styrene resin, polyolefin resin, melamine resin, phenol resin, norbornene resin and the like can be used.

  The adhesive layer (second adhesive layer) includes various curable adhesives such as a reaction curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive. And the like, but an ultraviolet curable adhesive is preferable from the viewpoint of work efficiency.

Finally, the transfer of the present invention is completed by removing the auxiliary substrate 3110. Specifically, the adhesive strength of the adhesive layer (first adhesive layer) 3109 is reduced by irradiating or heating with ultraviolet light, and the element formation layer attached to the substrate (third substrate). The auxiliary substrate 3110 is separated from 3107. Further, in the case where a film made of a water-soluble organic resin is formed between the element forming layer 3107 and the adhesive layer (first adhesive layer) 3109, the film made of the water-soluble organic resin is washed by water. , And the remainder of the adhesive layer (first adhesive layer) 3109 can be removed.

  Hereinafter, examples of the present invention will be described.

  Example 1 In this example, a manufacturing method including a transfer step of the present invention will be described with reference to FIGS.

  In FIG. 2A, a metal layer 202 is stacked over a first substrate 201, and a plurality of adhesive bodies 203 are formed thereover.

  In this embodiment, as the first substrate 201, a glass substrate or a quartz substrate can be used. As the glass substrate, a glass substrate made of barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, or the like can be used. Typically, a 1737 glass substrate manufactured by Corning Incorporated (with a strain point of 667 ° C.) ), AN100 (strain point 670 ° C.) manufactured by Asahi Glass Co., Ltd. can be applied. In this embodiment, the AN 100 is used.

  The metal layer 202 includes tungsten (W), molybdenum (Mo), technetium (Tc), rhenium (Re), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), palladium ( Pd), an element selected from platinum (Pt), silver (Ag), or gold (Au), an alloy containing the element as a main component, or a nitride (for example, titanium nitride, tungsten nitride, tantalum nitride, molybdenum nitride) ) Can be used as a single layer or stacked, but in this embodiment, a metal layer 202 containing W (tungsten) as a main component is used. Note that the thickness of the metal layer 202 may be 10 nm to 200 nm, preferably 50 nm to 75 nm.

  The metal layer 202 can be formed by a sputtering method, a CVD method, or an evaporation method. In this embodiment, the metal layer 202 is formed by a sputtering method. In the case where the metal layer 202 is formed by a sputtering method, the first substrate 201 is fixed, so that the film thickness in the vicinity of the peripheral portion of the first substrate 201 tends to be uneven. Therefore, it is preferable to remove only the peripheral portion by dry etching.

  The adhesive body 203 formed on the metal layer 202 is formed by forming an amorphous silicon film and then patterning the amorphous silicon film.

  Next, an oxide layer 204 is formed (FIG. 2B). In this embodiment, a film made of silicon oxide is formed with a thickness of 150 nm to 200 nm by a sputtering method using a silicon oxide target. Note that the thickness of the oxide layer 204 is preferably twice or more the thickness of the metal layer 202.

  Next, an element formation layer 301 is formed over the oxide layer 204 (FIG. 2C). A plurality of TFTs (p-channel TFTs or n-channel TFTs) are formed in the element formation layer 301 and connected to these TFTs in addition to the wiring 211 connecting these TFTs, the insulating films (210, 212). (Light emitting element, liquid crystal element). Note that a method for manufacturing an element formation layer including a TFT is not particularly limited in the present invention, and a known manufacturing method can be used in combination with the manufacturing method described in Embodiment 5. Note that the TFT includes an impurity region 205 and a channel formation region 206 formed in part of the semiconductor film over the oxide layer 204, an insulating film 207, and a gate electrode 208.

  In this embodiment, when forming the element formation layer 301, after forming a material film containing at least hydrogen (semiconductor film or metal film), a heat treatment for diffusing hydrogen contained in the material film containing hydrogen is performed. Do. This heat treatment may be performed at a temperature of 420 ° C. or higher, and may be performed separately from the formation process of the element formation layer 301, or may be combined with and omitted from the process. For example, if a hydrogen-containing amorphous silicon film is formed as a hydrogen-containing material film by a CVD method and then a heat treatment at 500 ° C. or more is performed for crystallization, a polysilicon film can be formed by heating, and at the same time, hydrogen diffusion is performed. It can be carried out.

  Note that by performing this heat treatment, a layer (not illustrated) including a metal oxide having a crystal structure is formed between the metal layer 202 and the oxide layer 204. Note that when the adhesive body 203 is formed over the metal layer 202 and the oxide layer 204 is stacked thereover, an amorphous state which is formed to a thickness of about 2 to 5 nm between the metal layer 202 and the oxide layer 204 is formed. A metal oxide layer (a tungsten oxide film in this embodiment) also forms a crystal structure by this heat treatment, and forms a layer (not shown) made of a metal oxide.

  Note that a layer (not shown) made of the metal oxide is formed at the interface between the metal layer 202 and the oxide layer 204, so that the substrate and the element formation layer can be easily separated in a later step. . In this embodiment, the case where a layer made of a metal oxide is formed in the heat treatment during the formation of the element formation layer 301 has been described. However, the present invention is not limited to this method. After the formation of the adhesive 203, a metal oxide layer may be formed and the oxide layer 204 may be formed.

On the other hand, the heat treatment during the formation of the element formation layer 301 can increase the adhesion between the adhesive body 203 and the metal layer 202. That is, in this embodiment, the adhesive body 203 formed of an amorphous silicon film reacts with tungsten (W) in the previously formed metal layer 202 by performing a heat treatment, thereby forming a silicide (tungsten silicide). : WSi ₂ ) is formed. Therefore, the adhesion between the adhesive 203 and the metal layer 202 is improved. Note that, in the present invention, the method is not limited to the method in which the metal in the metal layer reacts with the adhesive by heat treatment during the formation of the element formation layer 301. The heat treatment for reacting the metal with the adhesive may be performed separately from the formation of the element formation layer 301.

  When the element formation layer 301 is completed, the adhesive 203 is removed. Specifically, the opening 213 is formed by etching the insulating film (207, 209, 210, 212) and part of the oxide layer 204 and the adhesive 203 by a dry etching method (FIG. 2D). .

For example, in the case where the insulating films (207, 209, 210, 212) and the oxide layer 204 are etched, and these are formed of silicon oxide, the main component is fluorine carbide (CF ₄ ). Dry etching using an etching gas to be performed and etching the adhesive body 203, wherein the adhesive body 203 is formed of silicon, and a part of the adhesive body 203 is formed despite the reaction with the metal layer (for example, W). If a portion containing silicon as a main component remains, the portion can be etched using an etching gas containing hydrogen bromide (HBr) and chlorine (Cl ₂ ) as a main component. Further, when the adhesive body 203 is formed of silicon and a part thereof forms silicide (WSi) by a reaction with the metal layer (W), this is converted to sulfur fluoride (SF ₆ ) and odor. Etching can be performed using an etching gas containing hydrogen chloride (HBr) as a main component.

  Next, an organic resin layer 214 is formed over the element formation layer 301. As a material used for the organic resin layer 214, an organic material that is soluble in water or alcohols is used, and is formed by applying and curing the entire surface. The composition of the organic material may be, for example, any of epoxy-based, acrylate-based, and silicon-based. Specifically, a water-soluble resin (VL-WSHL10, manufactured by Toagosei Co., Ltd.) (thickness: 30 μm) is applied by spin coating, and is exposed for 2 minutes to temporarily cure, and then UV light is applied from the back surface to the surface for 2 minutes. The organic resin layer 214 is formed by performing exposure for 0.5 minutes and exposure for 10 minutes from the surface, for a total of 12.5 minutes, and performing full curing (FIG. 2E).

  Note that in order to facilitate subsequent peeling, a treatment for partially reducing adhesion at an interface (a layer containing a metal oxide) between the metal layer 202 and the oxide layer 204 is performed. The treatment for partially reducing the adhesion is performed by partially irradiating the metal layer 202 or the oxide layer 204 with laser light along the periphery of the region to be separated, or at the periphery of the region to be separated. This is a process in which pressure is applied locally from the outside to damage the inside of the oxide layer 204 or a part of the interface. Specifically, a hard needle may be pressed vertically with a diamond pen or the like and moved with a load. Preferably, a scriber device is used, the pressing amount is set to 0.1 mm to 2 mm, and the pressing may be performed by applying pressure. As described above, it is important to create a portion where the peeling phenomenon is likely to occur before performing the peeling, that is, to create a trigger, and by performing a pretreatment for selectively (partially) reducing the adhesion, the peeling is performed. Defects are eliminated, and the yield is further improved.

  Next, by forming the first adhesive layer 215, a second substrate 216 serving as an auxiliary substrate can be attached to the organic resin layer 214 through the first adhesive layer 215 (see FIG. 2E )). Note that as a material for forming the first adhesive layer 215, a known material whose adhesiveness is reduced by performing a predetermined process in a later step can be used. The case where a photosensitive double-sided tape whose adhesive strength is reduced by light irradiation will be described.

  Next, the first substrate 201 is separated from the element formation layer 301 to which the auxiliary substrate is attached by physical means. In the case of this embodiment, a relatively small force (for example, a human hand, the wind pressure of gas blown from a nozzle, (E.g., ultrasonic waves). Specifically, separation and separation can be performed in the tungsten oxide film, at the interface between the tungsten oxide film and the silicon oxide film, or at the interface between the tungsten oxide film and the tungsten film. Thus, the element formation layer 301 formed over the oxide layer 204 can be separated from the first substrate 201. The state at the time of peeling is shown in FIG.

  In addition, a part of the layer containing the metal oxide remains on the surface exposed by the separation, and this causes a decrease in adhesion when the exposed surface is bonded to a substrate or the like in a later step. For this reason, it is preferable to perform a treatment for removing part of the layer containing the metal oxide remaining on the exposed surface. In order to remove these, an alkaline aqueous solution such as an aqueous ammonia solution or an acidic aqueous solution can be used.

  Next, a second bonding layer 217 is formed, and the third substrate 218 and the oxide layer 204 (and the element formation layer 301) are bonded to each other through the second bonding layer 217 (FIG. 3B). . Note that the adhesion between the second substrate 216 and the organic resin layer 214 bonded by the first bonding layer 215 and the oxide layer 204 (and the element formation layer 301) bonded by the second bonding layer 217 are smaller than the adhesion between the organic resin layer 214 and the second substrate 216. It is important that the adhesion between the first substrate and the third substrate 218 is higher.

  As the third substrate 218, a flexible substrate (plastic substrate) is preferably used. In this embodiment, ARTON (manufactured by JSR) made of norbornene resin having a polar group is used.

  As the material used for the second adhesive layer 217, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a light curable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive. Is mentioned. More preferably, it is more preferable to provide high thermal conductivity by including a powder or a filler made of silver, nickel, aluminum, or aluminum nitride.

  Next, by irradiating ultraviolet rays from the second substrate 216 side, the adhesive strength of the double-sided tape used for the first adhesive layer 215 is reduced, and the second substrate 216 is separated from the element formation layer 301 ( (FIG. 3 (C)). Further, in this embodiment, the first adhesive layer 215 and the organic resin layer 214 can be dissolved and removed by washing the exposed surface with water, so that the structure shown in FIG. 3D can be obtained.

  As described above, the TFT formed over the first substrate 201 can be separated and transferred to another substrate (the third substrate 218).

  In this embodiment, a manufacturing method including the transfer step of the present invention, which is partially different from that in Embodiment 1, will be described with reference to FIGS.

  In FIG. 4A, a metal layer 402 is stacked over a first substrate 401, and a plurality of adhesive bodies 403 are formed thereover.

  In this embodiment, a glass substrate (AN100) similar to that of the first embodiment is used as the first substrate 401. Also, as in the first embodiment, a metal layer mainly containing W (tungsten) is used for the metal layer 402. Note that the metal layer 402 is formed by a sputtering method and has a thickness of 10 nm to 200 nm, preferably 50 nm to 75 nm.

  The adhesive body 403 formed on the metal layer 402 is formed by forming an amorphous silicon film and then patterning the same.

  Next, an oxide layer 404 is formed (FIG. 4B). In this embodiment, a film made of silicon oxide is formed with a thickness of 150 nm to 200 nm by a sputtering method using a silicon oxide target. Note that the thickness of the oxide layer 404 is preferably twice or more the thickness of the metal layer 402.

  Next, an element formation layer 501 is formed over the oxide layer 404 (FIG. 4C). A plurality of TFTs (p-channel TFTs or n-channel TFTs) are formed in the element formation layer 501, and a wiring 411 connecting these TFTs, an insulating film 410, and an element (light emitting element) connected to these TFTs Element, liquid crystal element). Note that a method for manufacturing an element formation layer including a TFT is not particularly limited in the present invention, and a known manufacturing method can be used in combination with the manufacturing method described in Embodiment 5. Note that the TFT includes an impurity region 405 and a channel formation region 406 formed in part of the semiconductor film over the oxide layer 404, an insulating film 407, and a gate electrode 408.

  In this embodiment, when forming the element formation layer 501 in the same manner as in Embodiment 1, after forming at least a material film containing hydrogen (semiconductor film or metal film), hydrogen contained in the material film containing hydrogen is used. Is performed for diffusing the heat. Note that by performing this heat treatment, a layer (not illustrated) including a metal oxide having a crystal structure is formed between the metal layer 402 and the oxide layer 404.

  Note that when a layer (not shown) made of this metal oxide is formed at the interface between the metal layer 402 and the oxide layer 404, separation between the substrate and the element formation layer in a later step is facilitated. .

  On the other hand, the heat treatment during the formation of the element formation layer 501 can increase the adhesion between the bonding body 403 and the metal layer 402.

  In this embodiment, when the wiring 411 included in the element formation layer 501 is formed, the adhesive 403 is removed. Specifically, part of the insulating film 410 and the adhesive body 403 are etched by a dry etching method, so that an opening 412 is formed (FIG. 4D).

For example, in the case where the insulating films (407, 409, 410) and the oxide layer 404 are etched, and these are formed of silicon oxide, the etching mainly includes fluorine carbide (CF ₄ ). In the case where dry etching is performed using a gas and the adhesive 403 is etched, the adhesive 403 is formed of silicon, and silicon is partially applied to the metal layer (for example, W) despite the reaction with the metal layer (for example, W). When a portion mainly composed of γ is left, it can be etched using an etching gas mainly composed of hydrogen bromide (HBr) and chlorine (Cl ₂ ). Further, when the adhesive body 403 is formed of silicon and a part thereof forms silicide (WSi) by a reaction with the metal layer (W), this is converted to sulfur fluoride (SF ₆ ) and odor. Etching can be performed using an etching gas containing hydrogen chloride (HBr) as a main component.

  Next, an insulating film 413 is formed to fill the opening 412 and planarize the surface of the element formation layer 501 (FIG. 4E). Note that in this embodiment, a silicon nitride oxide film having a thickness of 1 to 3 μm formed by a plasma CVD method is used. Of course, this insulating film is not limited to a silicon nitride oxide film, but may be a single-layer structure made of an insulating material such as silicon nitride or silicon oxide, an organic insulating material such as acryl, polyimide, or polyamide, or a combination thereof. It is good also as a structure.

  Note that, after the surface of the element formation layer 501 is flattened by the insulating film 413, (1) an organic resin layer is formed on the element formation layer 501, and an auxiliary resin layer is formed on the organic resin layer via a first adhesive layer. A step of attaching a second substrate, which is a substrate, (2) peeling the first substrate 401 from the element formation layer 501 from the element formation layer 501 to which the auxiliary substrate (the second substrate) is attached by physical means (3) forming a second adhesive layer, bonding the third substrate and the oxide layer (and the element forming layer) via the second adhesive layer, and (4) starting from the element forming layer. The step of separating the second substrate can be formed using a material similar to that described in Embodiment 1 and by a similar method, and thus description thereof is omitted.

  As described above, the structure illustrated in FIG. 5A in which the element formation layer 501 is transferred to the third substrate 418 through the second adhesive layer 417 can be obtained.

  In this embodiment, the structure shown in FIG. 5B may be formed by forming the opening 412 in FIG. 4D and then forming the insulating film 419.

  As described above, the TFT formed over the first substrate 401 can be peeled and transferred to another substrate (the third substrate 418).

  In this embodiment, a manufacturing method including the transfer step of the present invention, which is partially different from Embodiments 1 and 2, will be described with reference to FIGS.

  In FIG. 6A, a metal layer 602 is stacked over a first substrate 601, and an oxide layer 603 is formed thereover.

  In this embodiment, a glass substrate (AN100) similar to that in Embodiment 1 is used as the first substrate 601. Further, as in the first embodiment, the metal layer 602 mainly containing W (tungsten) is used as the metal layer 602. Note that the metal layer 402 is formed by a sputtering method and has a thickness of 10 nm to 200 nm, preferably 50 nm to 75 nm.

  The oxide layer 603 formed over the metal layer 602 is formed using a silicon oxide target with a thickness of 150 nm to 200 nm by a sputtering method using a silicon oxide target. Note that the thickness of the oxide layer 603 is preferably twice or more the thickness of the metal layer 602. In this embodiment, the oxide layer 603 is separated and formed into a plurality of islands by patterning.

  Next, a semiconductor film 604 is formed to cover the oxide layer 603. In this embodiment, an amorphous silicon film is formed by a plasma CVD method (FIG. 6A). Then, by patterning the semiconductor film 604, a semiconductor a (605) formed on the oxide layer 603 and a semiconductor b (606) formed between the two separated oxide layers 603 are obtained. Can be The semiconductor a (605) formed here becomes an impurity region and a channel formation region of a TFT to be formed later, and the semiconductor b (606) becomes an adhesive in the present invention.

  That is, the present invention is characterized in that the semiconductor a (605) forming a part of the TFT and the semiconductor b (606) forming the adhesive are formed at the same time.

  Next, an element formation layer 701 partially including the semiconductor a (605) is formed (FIG. 6C). A plurality of TFTs (p-channel TFTs or n-channel TFTs) are formed in the element formation layer 701, and a wiring 613 connecting these TFTs, an insulating film 612, and an element connected to these TFTs (light-emitting TFT). Element, liquid crystal element). Note that a method for manufacturing an element formation layer including a TFT is not particularly limited in the present invention, and a known manufacturing method can be used in combination with the manufacturing method described in Embodiment 5. Note that the TFT includes an impurity region 607 and a channel formation region 608 formed in part of the semiconductor a (605) over the oxide layer 603, a gate insulating film 609, and a gate electrode 610.

  In this embodiment, when forming the element formation layer 701 in the same manner as in Embodiment 1, after forming a material film containing at least hydrogen (semiconductor film or metal film), hydrogen contained in the material film containing hydrogen is used. Is performed for diffusing the heat. Note that by performing the heat treatment, a layer (not illustrated) including a metal oxide having a crystal structure is formed between the metal layer 602 and the oxide layer 603.

  Note that a layer (not shown) made of this metal oxide is formed at the interface between the metal layer 602 and the oxide layer 603, so that the first substrate 601 and the element formation layer 701 in a later step are separated. Separation is facilitated.

  On the other hand, by the heat treatment during the formation of the element formation layer 701, the adhesiveness between the semiconductor b (606) serving as an adhesive and the metal layer 602 can be increased.

  In this embodiment, after the wiring 613 included in the element formation layer 701 is formed, the semiconductor b (606) is removed (FIG. 6D). Specifically, the opening 614 is formed by etching a part of the insulating film 612 and the semiconductor b (606) by a dry etching method.

For example, in the case where the insulating films (609, 611, 612) and the oxide layer 603 are etched, and these are formed of silicon oxide, the etching mainly includes fluorine carbide (CF ₄ ). In the case where dry etching is performed using a gas and the semiconductor b (606) as an adhesive body is etched, the semiconductor b (606) is formed of silicon and reacts with a metal layer (for example, W). Nevertheless, if a portion containing silicon as a main component remains in a part thereof, it can be etched using an etching gas containing hydrogen bromide (HBr) and chlorine (Cl ₂ ) as a main component. it can. Further, when the semiconductor b (606) is formed of silicon and a part thereof forms silicide (WSi) by a reaction with the metal layer (W), this is converted to sulfur fluoride (SF ₆ ). And an etching gas containing hydrogen bromide (HBr) as a main component.

  Next, an insulating film 615 is formed to fill the opening 614 and planarize the surface of the element formation layer 701 (FIG. 6E). Note that in this embodiment, a silicon nitride oxide film having a thickness of 1 to 3 μm formed by a plasma CVD method is used. Of course, this insulating film is not limited to a silicon nitride oxide film, but may be an insulating material such as silicon nitride, silicon nitride, or silicon oxide, or a single-layer structure made of an organic insulating material such as acryl, polyimide, or polyamide. A stacked structure may be used in combination.

  Note that this is a step after the surface of the element formation layer 701 is flattened by the insulating film 615. (1) An organic resin layer is formed on the element formation layer 701 and an auxiliary resin layer is formed thereon via a first adhesive layer. A step of attaching a second substrate, which is a substrate, (2) peeling off the first substrate 601 from the element formation layer 701 by physical means from the element formation layer 701 to which the auxiliary substrate (second substrate) is attached (3) forming a second adhesive layer, bonding the third substrate and the oxide layer (and the element forming layer) via the second adhesive layer, and (4) starting from the element forming layer. The step of separating the second substrate can be formed using a material similar to that described in Embodiment 1 and by a similar method, and thus description thereof is omitted.

  As described above, the structure illustrated in FIG. 7A in which the element formation layer 701 is transferred to the third substrate 618 through the second adhesive layer 617 can be obtained.

  In this embodiment, the structure illustrated in FIG. 7B may be formed by forming the opening 614 in FIG. 6D and then forming the insulating film 800.

  As described above, the TFT formed over the first substrate 601 can be separated and transferred to another substrate (a third base 618 plate).

  In this embodiment, the arrangement and the shape of the adhesive in the present invention will be described with reference to FIGS.

  In the present invention, as shown in FIG. 8A, transfer is performed by peeling the element formation layer 802 formed on the substrate 801 by physical means and attaching the element formation layer 802 to another substrate. Note that in the case of FIG. 8A, the element formation layer 802 is separated in the direction of the arrow.

  Therefore, regarding the arrangement and shape of the adhesive formed in the element formation layer 802, the adhesive formed in the region 803 which is a part of the element formation layer 802 during the production of the element formation layer 802 and removed immediately before peeling is formed. An example of the arrangement and the shape is shown in FIGS.

  FIG. 8B illustrates a case where a rectangular adhesive body 805 is formed between the TFTs 804 arranged in the peeling direction XX ′ in a region 803 where a plurality of TFTs 804 are formed. In this case, it is more preferable that the quadrangular adhesive 805 has a rectangular shape and the rectangular long sides are arranged in parallel to the peeling direction AA '. By forming the bonding body 805 in a square shape in this manner, the element formation layer 802 can be easily peeled from the substrate 801 after the bonding body 805 is removed.

  FIG. 8C illustrates a case where a triangular adhesive 807 is formed between the TFTs 806 arranged in the peeling direction AA ′ in a region 803 where a plurality of TFTs 806 are formed. Note that, in this case, it is more preferable that the bottom side of the triangular adhesive body 807 is disposed so as to be perpendicular to the peeling direction XX '. Even when the bonding body 807 has a triangular shape, the element formation layer 802 can be easily separated from the substrate 801 after the bonding body 807 is removed.

  FIG. 8D illustrates a case where a line-shaped adhesive body 809 is formed between a plurality of rows of TFTs 808 arranged in the peeling direction XX 'in a region 803 where a plurality of TFTs 808 are formed. Note that, in this case, the linear adhesive body 809 may be formed to have the same length as the plurality of TFTs 808 arranged in the peeling direction XX ′, or may be formed to have a length corresponding to one TFT 808. . Even when the bonding body 809 is formed in a line as described above, the element formation layer 802 can be easily peeled off from the substrate 801 after the bonding body 807 is removed.

  It should be noted that the arrangement and shape of the adhesive shown in this example are merely preferred examples of the present invention, and do not limit the shape of the adhesive of the present invention at all.

  In this embodiment, a method for simultaneously manufacturing an n-channel TFT and a p-channel TFT on the same substrate will be described with reference to FIGS.

  A metal layer 902 is formed on a substrate 901, and an adhesive 903 is formed thereon.

  In this embodiment, a glass substrate (# 1737) is used as the substrate 901, and a metal material mainly containing tungsten (W) is used for the metal layer 902 as in the first embodiment. Note that the adhesive 903 is patterned and formed into a desired shape so as to be disposed between TFTs to be formed later.

Next, an oxide layer 904 which also functions as a base insulating film is formed over the metal layer 902 and the adhesive 903. In this embodiment, a film formation temperature 300 ° C. by a plasma CVD method, a raw material gas SiH _4, N ₂ O silicon oxynitride made from film (composition ratio Si = 32%, O = 59 %, N = 7%, H = 2%) to a thickness of 100 nm, whereby an oxide layer 904 is formed.

Furthermore, a semiconductor layer having an amorphous structure (here, an amorphous silicon layer) is formed to a thickness of 54 nm by a plasma CVD method continuously at a film forming temperature of 300 ° C. and a film forming gas of SiH ₄ without opening to the atmosphere. . This amorphous silicon layer contains hydrogen, and hydrogen can be diffused by a heat treatment performed later, and can be separated in the oxide layer or at the interface by physical means.

  Next, a nickel acetate salt solution containing 10 ppm by weight of nickel is applied by a spinner. Instead of coating, a method of spraying a nickel element over the entire surface by a sputtering method may be used. Next, a semiconductor film (here, a polysilicon layer) having a crystal structure is formed by heat treatment and crystallization. Here, after a heat treatment for dehydrogenation (500 ° C., 1 hour), a heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a silicon film having a crystal structure. The heat treatment for dehydrogenation (at 500 ° C. for one hour) also serves as a heat treatment for diffusing hydrogen contained in the amorphous silicon film to the interface between the metal layer 902 and the oxide layer 904. Although a crystallization technique using nickel as a metal element for promoting crystallization of silicon is used here, other known crystallization techniques, for example, a solid phase growth method or a laser crystallization method may be used.

Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, a laser beam (XeCl: wavelength 308 nm) for increasing the crystallization rate and repairing defects remaining in the crystal grains is used. Irradiation is performed in the air or in an oxygen atmosphere. Excimer laser light having a wavelength of 400 nm or less, or the second and third harmonics of a YAG laser is used as the laser light. Here, a pulse laser beam having a repetition frequency of about 10 to 1000 Hz is used, and the laser beam is condensed to 100 to 500 mJ / cm ² by an optical system and irradiated with an overlap ratio of 90 to 95%, and the silicon film surface is irradiated. May be scanned. Here, laser light irradiation is performed in the atmosphere at a repetition frequency of 30 Hz and an energy density of 470 mJ / cm ² .

Note that an oxide film is formed on the surface by laser light irradiation because the irradiation is performed in the air or in an oxygen atmosphere. Although an example using a pulse laser is described here, a continuous wave laser may be used. In crystallizing an amorphous semiconductor film, continuous oscillation is possible in order to obtain a crystal with a large grain size. It is preferable to use a solid-state laser and apply the second to fourth harmonics of the fundamental wave. Typically, Nd: YVO ₄ may be applied laser (fundamental wave 1064 nm) second harmonic (532 nm) or the third harmonic (355 nm). When a continuous wave laser is used, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a nonlinear optical element. There is also a method in which a YVO ₄ crystal and a nonlinear optical element are put in a resonator to emit a harmonic. Then, the laser beam is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the laser beam is irradiated on the object. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relatively to the laser beam at a speed of about 10 to 2000 cm / s.

  Next, in addition to the oxide film formed by the laser light irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total of 1 to 5 nm. In this embodiment mode, the barrier layer is formed using ozone water. A method of oxidizing the surface of the semiconductor film having a crystal structure by irradiation with ultraviolet light in an oxygen atmosphere or the surface of the semiconductor film having a crystal structure by oxygen plasma treatment A barrier layer may be formed by depositing an oxide film of about 1 to 10 nm by a method of oxidizing, a plasma CVD method, a sputtering method, an evaporation method, or the like. Further, before forming the barrier layer, an oxide film formed by laser light irradiation may be removed.

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed to a thickness of 10 nm to 400 nm, here, 100 nm over the barrier layer by a sputtering method. In this embodiment, the amorphous silicon film containing an argon element is formed in an atmosphere containing argon using a silicon target. When an amorphous silicon film containing an argon element is formed by a plasma CVD method, the film forming conditions are as follows: a flow rate ratio of monosilane to argon (SiH ₄ : Ar) is 1:99, and a film forming pressure is 6.665 Pa. (0.05 Torr), the RF power density is 0.087 W / cm ² , and the film formation temperature is 350 ° C.

  After that, heat treatment is performed in a furnace heated to 650 ° C. for 3 minutes to perform gettering to reduce the nickel concentration in the semiconductor film having a crystal structure. A lamp annealing device may be used instead of the furnace.

  Next, after the amorphous silicon film containing an argon element, which is a gettering site, is selectively removed using the barrier layer as an etching stopper, the barrier layer is selectively removed with dilute hydrofluoric acid. Note that at the time of gettering, since nickel tends to move to a region having a high oxygen concentration, it is desirable to remove the barrier layer made of an oxide film after gettering.

  Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also called a polysilicon film), a mask made of a resist is formed, and an etching process is performed into a desired shape to form an island shape. Semiconductor layers 905 and 906 are formed. After forming the semiconductor layers 905 and 906, the resist mask is removed (FIG. 9A).

  Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film (semiconductor layers 905 and 906) is washed. Then, an insulating film containing silicon as a main component to be a gate insulating film 907 is formed. In this embodiment, a silicon oxide film is formed with a thickness of 115 nm by a plasma CVD method (FIG. 9B).

  Further, a first conductive film 908 having a thickness of 20 to 100 nm and a second conductive film 909 having a thickness of 100 to 400 nm are formed over the gate insulating film 907. In this embodiment, a 50-nm-thick tantalum nitride film serving as the first conductive film 908 and a 370-nm-thick tungsten film serving as the second conductive film 909 are sequentially stacked over the gate insulating film 907.

  Note that a conductive material for forming the first conductive film 908 and the second conductive film 909 is an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material containing the above element as a main component. Alternatively, a compound material can be used. Further, as the first conductive film 908 and the second conductive film 909, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used. The structure is not limited to a two-layer structure. For example, a three-layer structure in which a 50-nm-thick tungsten film, a 500-nm-thick aluminum-silicon alloy (Al-Si) film, and a 30-nm-thick titanium nitride film are sequentially stacked. Is also good. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum may be used instead of an aluminum-silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al-Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Further, it may have a single-layer structure.

Next, as shown in FIG. 9C, masks 910 and 911 made of resist are formed by a light exposure process, and a first etching process for forming a gate electrode and a wiring is performed. The first etching process is performed under the first and second etching conditions. It is preferable to use an ICP (Inductively Coupled Plasma) etching method for the etching. The film is formed into a desired tapered shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) using the ICP etching method. Can be etched. As the etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ , NF ₃ , or the like, or O ₂ is appropriately used. Can be used.

In this embodiment, RF (13.56 MHz) power of 150 W is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, a quartz disk provided with a coil) is a disk having a diameter of 25 cm. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered. Under the first etching conditions, the etching rate for W is 200.39 nm / min, the etching rate for TaN is 80.32 nm / min, and the selectivity ratio of W to TaN is about 2.5. Further, the taper angle of W becomes about 26 ° under the first etching condition. After that, the masks 910 and 911 made of resist are changed to the second etching condition without being removed, CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30/30 (sccm). A 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching was performed for about 30 seconds. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%.

  In the first etching process, the shape of the resist mask is made appropriate, so that the edges of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of the tapered portion may be 15 to 45 degrees.

  In this manner, the first shape conductive layers 912 and 913 (the first conductive layers 912a and 913a and the second conductive layers 912b and 913b) including the first conductive layer and the second conductive layer by the first etching process. To form The insulating film 907 serving as a gate insulating film is etched by about 10 to 20 nm, and becomes a gate insulating film 907 in which a region which is not covered with the first shape conductive layers 912 and 913 is thinned.

Next, as shown in FIG. 9D, second-shaped conductive layers 914 and 915 are formed by a second etching process without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, the respective gas flow rates are set to 24/12/24 (sccm), and 700 W RF ( (13.56 MHz) Power is supplied to generate plasma, and etching is performed for 25 seconds. A 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate for W is 227.3 nm / min, the etching rate for TaN is 32.1 nm / min, the selectivity ratio of W to TaN is 7.1, and the gate insulating film 911 is formed. The etching rate for SiON is 33.7 nm / min, and the selectivity ratio of W to SiON is 6.83. As described above, when SF ₆ is used as the etching gas, the selectivity to the gate insulating film 911 is high, so that the film loss can be suppressed. The reduction in the thickness of the gate insulating film 907 in this embodiment is about 8 nm.

  The taper angle of W can be set to 70 ° by the second etching process. By this second etching process, second conductive layers 914b and 915b are formed. At this time, the first conductive layer is hardly etched and becomes first conductive layers 914a and 915a. Note that the first conductive layers 914a and 915a have substantially the same size as the first conductive layers 912a and 913a. Actually, the width of the first conductive layer may be set back by about 0.3 μm as compared with before the second etching treatment, that is, about 0.6 μm in the entire line width, but there is almost no change in size.

Further, instead of the two-layer structure, a three-layer structure in which a 50-nm-thick tungsten film, a 500-nm-thick aluminum-silicon alloy (Al-Si) film, and a 30-nm-thick titanium nitride film are sequentially stacked, As the first etching conditions in the first etching process, BCl ₃ , Cl _2, and O ₂ are used as source gases, the respective gas flow ratios are set to 65/10/5 (sccm), and the substrate side (sample stage) is used. ) Is supplied with 300 W RF (13.56 MHz) power, and 450 W RF (13.56 MHz) power is supplied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma and perform etching for 117 seconds. Ebayoku, as the second etching conditions of the first etching treatment, CF ₄ and using a Cl ₂ and O _2, a ratio of respective gas flow rates is 25/25/10 (scc ), 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and 500 W RF (13.56 MHz) power is applied to the coil type electrode at a pressure of 1 Pa to generate plasma. The etching may be performed for about 30 seconds. As the second etching process, BCl ₃ and Cl ₂ are used, each gas flow ratio is set to 20/60 (sccm), and 100 W is applied to the substrate side (sample stage). RF (13.56 MHz) power is supplied, and 600 W RF (13.56 MHz) power is supplied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma and perform etching.

  Next, after removing the resist masks 910 and 911, a resist mask 918 is formed as shown in FIG. 10A, and a first doping process is performed. The doping treatment may be performed by an ion doping method or an ion implantation method. Note that the mask 918 is a mask that protects a semiconductor film forming a p-channel TFT and a peripheral region thereof.

The condition of the ion doping method in the first doping treatment is to dope phosphorus (P) with a dose amount of 1.5 × 10 ¹⁵ atoms / cm ² and an acceleration voltage of 60 to 100 keV. Note that typically, phosphorus (P) or arsenic (As) can be used as the impurity element imparting n-type. Here, an impurity region is formed in each semiconductor layer in a self-aligned manner using the second conductive layers 914b and 915b as a mask. Of course, it is not added to the area covered with the mask 918. Thus, a first impurity region 919 and a second impurity region 920 are formed. The first impurity region 919 is doped with an impurity element imparting n-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Here, a region having the same concentration range as the first impurity region is also called an n ⁺ region.

Further, the second impurity region 920 is formed at a lower concentration than the first impurity region 919 by the first conductive layer 915a, and has an n-type in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ^3. Is added. Note that the second impurity region 920 has a concentration gradient in which the impurity concentration increases toward the end of the tapered portion because doping is performed by passing the second conductive region 920 through a portion of the first conductive layer 915a having a tapered shape. ing. Here, a region in the same concentration range as second impurity region 920 is also referred to as an n ⁻ region.

  Next, after removing the resist mask 918, a new resist mask 921 is formed and a second doping process is performed as shown in FIG. The doping may be performed by ion doping or ion implantation. Note that the mask 921 is a mask that protects a semiconductor film forming an n-channel TFT and a peripheral region thereof.

The condition of ion doping in the second doping process is to dope boron (B) at a dose of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ atoms / cm ² and an acceleration voltage of 50 to 100 keV. Here, an impurity region is formed in each semiconductor layer in a self-aligned manner using the second conductive layers 914b and 915b as a mask. Of course, boron is not added to the region covered with the mask 921. By the second doping treatment, a third impurity region 922 and a fourth impurity region 923 in which an impurity element imparting p-type conductivity is added to a semiconductor layer forming a p-channel TFT are formed.

Further, an impurity element imparting p-type conductivity is added to the third impurity region 922 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

Further, the fourth impurity region 923 is formed in a region overlapping with the tapered portion of the first conductive layer 914a, and is provided with a p-type in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. The impurity element is added. Note that the fourth impurity region 923 has a concentration gradient in which the impurity concentration increases toward the end of the tapered portion because the fourth impurity region 923 is doped by transmitting the portion of the first conductive layer 914a having a tapered shape. Here, a region having the same concentration range as fourth impurity region 923 is also referred to as ap ⁻ region.

  Through the above steps, an impurity region having n-type or p-type conductivity is formed in each semiconductor layer. The second shape conductive layers 914 and 915 serve as gate electrodes of the TFT.

  Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination of any of these methods. Done by the method

  Next, a first insulating film 924 is formed. Note that in this embodiment, a 50-nm-thick silicon nitride oxide film formed by a plasma CVD method is used. Needless to say, this insulating film is not limited to a silicon nitride oxide film, and an insulating film such as silicon nitride or silicon oxide may be used as a single layer or a stacked structure.

  Next, a second insulating film 925 is formed over the first insulating film 924. As the second insulating film 925 formed here, an insulating film such as silicon nitride, silicon nitride oxide, or silicon oxide can be used. In this embodiment, a 50-nm-thick insulating film formed by a plasma CVD method is used. A silicon nitride film is used.

  Next, after forming a second insulating film 925 made of a silicon nitride film, heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) is performed to hydrogenate the semiconductor layer (FIG. 10C )). In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the second insulating film 925. As other means of hydrogenation, heat treatment at about 350 ° C. in a hydrogen atmosphere or plasma hydrogenation (using hydrogen excited by plasma) can be performed.

  Next, a third insulating film 926 made of an organic insulating material is formed over the second insulating film 925. Here, an acrylic resin film having a thickness of 1.6 μm is formed. Next, a contact hole 927 reaching each impurity region is formed.

  Since the acrylic resin used in this embodiment is photosensitive acrylic, a desired position can be opened by exposure and development. In addition, a part of the first insulating film 924 and the second insulating film 925 is etched by a dry etching method, and the second insulating film 925 is etched using the first insulating film 924 as an etching stopper. Then, the first insulating film 924 is etched. As a result, a contact hole 927 is obtained.

  In this embodiment, the case where the contact hole is formed after the third insulating film 926 formed of the organic resin film is formed has been described. However, the second hole is formed before the third insulating film 926 is formed. The insulating film 925 and the first insulating film 924 can be dry-etched. Note that in this case, it is preferable that the substrate be subjected to heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) after the etching treatment and before the third insulating film 926 is formed.

  Then, as shown in FIG. 10D, by forming a wiring 928 using Al, Ti, Mo, W, or the like, the n-channel TFT 1001 and the p-channel TFT 1002 can be formed over the same substrate.

  Example 1 In this example, a light-emitting device having a light-emitting element in a pixel portion of a panel among semiconductor devices manufactured according to the present invention will be described with reference to FIGS. Note that FIG. 11A illustrates a cross-sectional structure of the light-emitting element, and FIGS. 11B and 11C illustrate an element structure of the light-emitting element. Note that the light-emitting element described here includes a first electrode electrically connected to the current control TFT and a second electrode formed with an electroluminescent layer interposed therebetween.

  In FIG. 11A, an adhesive layer 1110 and an oxide layer 1109 are formed over a substrate 1101, and a thin film transistor (TFT) is formed thereover. Note that here, a current controlling TFT 1122 which is electrically connected to the first electrode 1111 of the light emitting element 1115 and has a function of controlling a current supplied to the light emitting element 1115 and a gate electrode of the current controlling TFT 1122 are provided. 1 shows a switching TFT 1121 for controlling a video signal to be supplied.

  As the substrate 1101, a silicon substrate having a light-blocking property is used; however, a glass substrate, a quartz substrate, a resin substrate, or a flexible substrate material (plastic) may be used. The active layer of each TFT includes at least a channel formation region 1102, a source region 1103, and a drain region 1104.

  The active layer of each TFT is covered with a gate insulating film 1105, and a gate electrode 1106 overlapping with the channel formation region 1102 with the gate insulating film 1105 interposed therebetween is formed. Further, an interlayer insulating film 1108 is provided to cover the gate electrode 1106. Note that as a material for forming the interlayer insulating film 1108, in addition to an insulating film containing silicon such as silicon oxide, silicon nitride, and silicon nitride oxide, polyimide, polyamide, acrylic (including photosensitive acrylic), and BCB (benzocyclobutene) ) Can be used.

  Next, an opening is formed in the interlayer insulating film 1108, a wiring 1107 electrically connected to the source region 1103 of the current controlling TFT 1122 is formed, and a first electrode electrically connected to the drain region 1104 is formed. 1111 is formed. Note that when the first electrode 1111 is an anode, the current control TFT 1122 is preferably formed in a p-channel type, and when the first electrode 1111 is a cathode, the current control TFT 1122 is preferably formed in a p-channel type.

Since the above can be formed using another embodiment of the present invention, the description is omitted. Note that the opening formed in the process of separation and transfer is filled by forming an interlayer insulating film 1112. Further, after cueing of the wiring 1107 by etch back, the first electrode 1111 is formed so as to be connected to the wiring 1107. An insulating layer 1112 is formed to cover an end portion of the first electrode 1111, the wiring 1107, and the like. Next, an electroluminescent layer 1113 is formed over the first electrode 1111 and a second electrode 1114 is formed thereover, whereby a light-emitting element 1115 can be completed.

  Note that in this embodiment, the material of the first electrode 1111 and the material of the second electrode 1114 can be appropriately selected. However, in the case where an electrode functioning as an anode is formed, a conductive material having a large work function is generally used. It is preferable to use a material (for example, a work function of 4.0 eV or more). In the case of forming an electrode functioning as a cathode, a conductive material having a small work function (for example, a work function of 3.5 eV or less) is generally used. ) Is preferably used. In the case where an electrode that transmits light generated in the electroluminescent layer is formed, the electrode needs to be formed using a light-transmitting material. Note that in this case, only one of the electrodes may be formed of a light-transmitting material and the other may be formed of a light-blocking material. Accordingly, a light emitting element that can emit light from both electrodes can be formed.

  In the light-emitting element illustrated in FIG. 11A, holes are injected into the electroluminescent layer 1113 from an electrode serving as an anode, and electrons are injected into the electroluminescent layer 1113 from an electrode serving as a cathode. Then, light is obtained by recombination of holes and electrons in the electroluminescent layer 1113.

  The electroluminescent layer 1113 includes at least a light-emitting layer, and includes one or more of layers having different functions with respect to carriers, such as a hole injection layer, a hole transport layer, a blocking layer, an electron transport layer, and an electron injection layer. Are formed by stacking in combination.

  In addition, as a material for forming the electroluminescent layer 1113, a known low molecular weight, high molecular weight, or medium molecular weight organic compound can be used. Here, the medium molecular organic compound refers to a material having no sublimability and having a molecular number of 20 or less, or a chain molecule having a length of 10 μm or less.

  Note that as a material for forming the electroluminescent layer 1113, specifically, the following materials can be used.

As the hole injecting material for forming the hole injecting layer, a porphyrin-based compound is effective as long as it is an organic compound, and phthalocyanine (hereinafter, referred to as H ₂ -Pc) and copper phthalocyanine (hereinafter, referred to as Cu-Pc). )and so on. There is also a material obtained by subjecting a conductive polymer compound to chemical doping, such as polyethylene dioxythiophene (hereinafter, referred to as PEDOT) doped with polystyrene sulfonic acid (hereinafter, referred to as PSS), polyaniline, and polyvinyl carbazole (hereinafter, referred to as PVK). Shown).

  As the hole transporting material forming the hole transporting layer, an aromatic amine-based compound (that is, a compound having a benzene ring-nitrogen bond) is suitable. As a widely used material, for example, in addition to the above-mentioned TPD, a derivative thereof, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (hereinafter, “α -NPD "), 4,4 ', 4" -tris (N, N-diphenyl-amino) -triphenylamine (hereinafter referred to as "TDATA"), 4,4', 4 ''- Starburst type aromatic amine compounds such as tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (hereinafter referred to as “MTDATA”).

As the light emitting material forming the light-emitting layer, specifically, tris (8-quinolinolato) aluminum (hereinafter, referred to as Alq _3), tris (4-methyl-8-quinolinolato) aluminum (hereinafter, referred to as Almq ₃₎ , bis (10-hydroxybenzo [h] - quinolinato) beryllium (hereinafter, referred to as BeBq _2), bis (2-methyl-8-quinolinolato) - (4-hydroxy - biphenylyl) - aluminum (hereinafter, referred to as BAlq) , Bis [2- (2-hydroxyphenyl) -benzoxazolat] zinc (hereinafter referred to as Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (hereinafter Zn (BTZ) In addition to metal complexes such as ₂ ), various fluorescent dyes are effective. Further, a triplet light-emitting material is also possible, and a complex containing platinum or iridium as a central metal is mainly used. Examples of the triplet light emitting material include tris (2-phenylpyridine) iridium (hereinafter referred to as Ir (ppy) ₃ ), 2,3,7,8,12,13,17,18-octaethyl-21H, 23H-porphyrin. -Platinum (hereinafter referred to as PtOEP) and the like are known.

As the electron transporting material forming the electron transporting layer, a metal complex is often used, and a metal complex having a quinoline skeleton or a benzoquinoline skeleton such as Alq ₃ , Almq ₃ , or BeBq ₂ described above, or a mixed ligand complex BAlq is suitable. Further, there are metal complexes having an oxazole-based or thiazole-based ligand such as Zn (BOX) ₂ and Zn (BTZ) ₂ . Further, in addition to the metal complex, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (hereinafter, referred to as PBD), 1,3-bis [ Oxadiazole derivatives such as 5- (p-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (hereinafter referred to as OXD-7), 3- (4-tert-butyl Phenyl) -4-phenyl-5- (4-biphenylyl) -1,2,4-triazole (hereinafter referred to as TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl)- Triazole derivatives such as 5- (4-biphenylyl) -1,2,4-triazole (hereinafter referred to as p-EtTAZ), bathophenanthroline (hereinafter referred to as BPhen), bathocuproine (hereinafter referred to as BCP), and the like; Enantororin derivative has an electron transporting property.

  In addition, when a blocking layer is included in the electroluminescent layer, the above-mentioned BAlq, OXD-7, TAZ, p-EtTAZ, BPhen, BCP, etc. are used as the hole blocking material for forming the blocking layer. Is effective because it is high.

FIG. 11B illustrates a structure in which the first electrode 1131 is an anode formed using a light-transmitting material and the second electrode 1133 is a cathode formed using a light-blocking material. In this case, the first electrode 1131 is made of an indium tin oxide (ITO) film, a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide, IZO, and In ₂ O _3. The second electrode 1133 can be formed using Al, Ti, W, or the like. Here, ITO is used for the first electrode 1131. The case where Al is used for the second electrode 1133 is shown. Then, light generated in the electroluminescent layer 1132 is emitted from the first electrode 1131 side. Note that in this structure, as a material for forming the electroluminescent layer 1132, any of the materials described above can be appropriately selected and used.

  Note that the present invention is not limited to the above structure, and the first electrode 1131 may be formed using a light-blocking anode, and the second electrode 1133 may be formed as a light-transmitting cathode. In this case, light is emitted from the second electrode 1133 side.

In FIG. 11C, both the first electrode 1141 and the second electrode 1143 are formed using a light-transmitting material, the first electrode 1141 is an anode, and the second electrode 1143 is a cathode. The configuration in the case of is shown. In this case, the first electrode 1141 is made of an indium tin oxide (ITO) film as in the case shown in FIG. 11B, and 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide. And a transparent conductive film such as IZO and In ₂ O ₃ —ZnO. The second electrode 1143 is made of a material having a small work function, such as Mg: Ag (an alloy of magnesium and silver). ) And ITO. In this case, light generated in the electroluminescent layer 1142 is emitted from both the first electrode 1141 and the second electrode 1143. Note that also in this structure, as a material for forming the electroluminescent layer 1142, any of the materials described above can be appropriately selected and used.

Note that in a semiconductor device manufactured according to the present invention, the structure of a light-emitting device having a light-emitting element in a pixel portion of a panel is not limited thereto. For example, a structure as shown in FIG. 26 can be adopted.

First, an adhesive layer 4502 and an oxide layer 4503 are formed over a substrate 4501. A current control TFT 4509 including a channel formation region 4504, a source region 4505, a drain region 4506, a gate insulating film 4507, and a gate electrode 4508 and a switching TFT 4510 are formed thereover. The active layer of each TFT is covered with a gate insulating film 4507, and a gate electrode 4508 overlapping with the channel formation region 4504 is formed with the gate insulating film 4507 interposed therebetween. Further, an interlayer insulating film 4511 is provided to cover the gate electrode 4508.

The current controlling TFT 4509 is electrically connected to the first electrode 4515 of the light-emitting element 4519 and has a function of controlling current supplied to the light-emitting element 4515. The switching TFT 4510 controls a video signal applied to the gate electrode of the current control TFT 4509.

  Although a silicon substrate having a light-blocking property is used here as the substrate 4501, a glass substrate, a quartz substrate, a resin substrate, or a flexible substrate material (plastic) may be used. The active layer of each TFT includes at least a channel formation region 4504, a source region 4505, and a drain region 4506.

  Next, an opening is formed in the interlayer insulating film 4511, and a wiring 4512 which is electrically connected to the source region 4505 of the current controlling TFT 4509 is formed. Further, an insulating film 4513 is formed. A contact hole is formed in the insulating film 4513, and a wiring 4514 electrically connected to the wiring 4512 is formed. After that, a first electrode 4515 electrically connected to the wiring 4514 is formed. As a result, the source region 4505 of the current controlling TFT 4509 and the first electrode 4515 are connected. Note that when the first electrode 4515 is an anode, the current control TFT 4509 is preferably formed of a p-channel type, and when the first electrode 4515 is a cathode, the current control TFT 4509 is preferably formed of a p-channel type.

  In addition, an insulating layer 4516 is formed to cover an end portion of the first electrode 4515, the wiring 4514, and the like. Next, an electroluminescent layer 4517 is formed over the first electrode 4515, and a second electrode 4518 is formed thereover, whereby a light-emitting element 4519 can be completed.

  Note that as a material for manufacturing the semiconductor device illustrated in FIG. 26, any of the materials described above can be appropriately selected and used.

  Embodiment 2 In this embodiment, a case of a liquid crystal device having a liquid crystal element in a pixel portion of a panel among semiconductor devices manufactured according to the present invention will be described with reference to FIGS.

As shown in FIG. 12, an adhesive layer and an oxide layer 1214 are formed over a substrate 1201, and a TFT 1202 is formed thereover. After an opening is formed in the interlayer insulating film 1203, the TFT 1202 is electrically connected to a first electrode 1205 to be a pixel electrode through a wiring 1204. Further, an alignment film 1206 is formed over the first electrode 1205, and a rubbing treatment is performed. In addition, a columnar spacer 1207 made of an organic resin for maintaining a distance between the substrates is provided. Note that the order of forming the spacer 1207 and the alignment film 1206 may be reversed.

Since the above can be formed using another embodiment of the present invention, the description is omitted. Note that the opening formed in the process of separation and transfer is filled by forming the insulating film 1216. Further, after cueing of the wiring 1204 by etch back, the first electrode 1205 is formed so as to be connected to the wiring 1204.

  On the other hand, the counter substrate 1213 has a coloring layer 1208, a planarizing film 1209, a counter electrode 1210 made of a transparent conductive film, and an alignment film 1211 on the substrate. Note that as the coloring layer 1208, a red coloring layer, a blue coloring layer, and a green coloring layer may be formed.

  The substrate 1201 on which the element is formed and the counter substrate 1213 are attached to each other with a sealant (not illustrated). In addition, a filler is mixed in the sealant, and the two substrates are bonded together while maintaining a uniform interval (preferably 2.0 to 3.0 μm) by the filler and the spacer. In addition, a liquid crystal 1212 is injected between the two substrates, and is completely sealed by a sealing agent. Note that a known liquid crystal material can be used for the liquid crystal 1212.

  Note that in the case of the structure illustrated in FIG. 12, light enters from the counter substrate 1213 side, is modulated by the liquid crystal 1212, and exits from the substrate 1201 side where the element is formed.

In the present invention, the first electrode can be formed using a reflective metal film (specifically, an aluminum (alloy) film or the like). In this case, light enters from the counter substrate 1213 side, is modulated by the liquid crystal 1212, and is emitted again from the counter substrate 1213 side. Note that in such a structure, since light does not transmit below the first electrode, a memory element, a resistor, or the like can be provided.

Note that, in the semiconductor device manufactured according to the present invention, the structure of the liquid crystal device having a liquid crystal element in a pixel portion of a panel is not limited to this, and another structure can be used.

  Embodiment 1 In this embodiment, various electronic devices which are completed by incorporating a semiconductor element manufactured according to the present invention into a part thereof will be described.

  These electronic devices include video cameras, digital cameras, head mounted displays, (goggle type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, portable game machines or electronic And a device provided with a semiconductor device capable of reproducing a recording medium such as a book) and displaying an image thereof. FIG. 13 shows specific examples of these electronic devices.

  FIG. 13A illustrates a display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. Note that the display portion 2003 includes the light-emitting elements described in Embodiment 6 and the liquid crystal elements described in Embodiment 7. The display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

  FIG. 13B illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. Note that the display portion 2203 includes the light-emitting element described in Embodiment 6 and the liquid crystal element described in Embodiment 7.

  FIG. 13C illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. Note that the display portion 2302 includes the light-emitting elements described in Embodiment 6 and the liquid crystal elements described in Embodiment 7.

  FIG. 13D illustrates a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), which includes a main body 2401, a housing 2402, a display A 2403, a display b2404, a recording medium reading unit 2405, and operation keys 2406. , A speaker unit 2407 and the like. Note that the display portion A 2403 and the display portion B 2404 include the light-emitting elements described in Embodiment 6 and the liquid crystal elements described in Embodiment 7. This player uses a DVD (Digital Versatile Disc), a CD, or the like as a recording medium, and can enjoy music, movies, games, and the Internet.

  FIG. 13E illustrates a portable book (electronic book), which includes a main body 2501, a display portion 2502, a storage medium 2503, operation switches 2504, an antenna 2505, and the like. Note that the display portion 2502 includes the light-emitting elements described in Embodiment 6 and the liquid crystal elements described in Embodiment 7.

  FIG. 13F illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, a voice input portion 2608, operation keys 2609, and an eyepiece. Unit 2610 and the like. Note that the display portion 2602 includes the light-emitting element described in Embodiment 6 and the liquid crystal element described in Embodiment 7.

  Here, FIG. 13G illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a sound input portion 2704, a sound output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. Note that the display portion 2703 includes the light-emitting element described in Embodiment 6 and the liquid crystal element described in Embodiment 7.

  As described above, the applicable range of the semiconductor element manufactured according to the present invention is extremely wide, and the semiconductor element can be applied to electronic devices in all fields.

  Example 1 In this example, a manufacturing method including a transfer step of the present invention will be described with reference to FIGS.

  In FIG. 15A, a metal layer 3202 is stacked over a first substrate 3201, and a plurality of adhesive bodies 3203 are formed thereover.

  Note that in this embodiment, a glass substrate or a quartz substrate can be used as the first substrate 3201. As the glass substrate, a glass substrate made of barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, or the like can be used. Typically, a 1737 glass substrate manufactured by Corning Incorporated (with a strain point of 667 ° C.) ), AN100 (strain point 670 ° C.) manufactured by Asahi Glass Co., Ltd. can be applied. In this embodiment, the AN 100 is used.

  The metal layer 3202 includes tungsten (W), molybdenum (Mo), technetium (Tc), rhenium (Re), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), and palladium ( Pd), an element selected from platinum (Pt), silver (Ag), or gold (Au), an alloy containing the element as a main component, or a nitride (for example, titanium nitride, tungsten nitride, tantalum nitride, molybdenum nitride) ) Can be used as a single layer or a stacked layer. In this embodiment, a metal layer 3202 containing W (tungsten) as a main component is used. Note that the metal layer 3202 has a thickness of 10 nm to 200 nm, preferably 50 nm to 75 nm.

  The metal layer 3202 can be formed by a sputtering method, a CVD method, or an evaporation method. In this embodiment, the metal layer is formed by a sputtering method. In the case where the metal layer 3202 is formed by a sputtering method, the first substrate 3201 is fixed, so that the thickness of the first substrate 3201 in the vicinity of the peripheral portion tends to be uneven. Therefore, it is preferable to remove only the peripheral portion by dry etching.

  The adhesive 3203 formed on the metal layer 3202 is formed by forming an amorphous silicon film and then patterning the amorphous silicon film.

  Next, an oxide layer 3204 is formed (FIG. 15B). In this embodiment, a film made of silicon oxide is formed with a thickness of 150 nm to 200 nm by a sputtering method using a silicon oxide target. Note that the thickness of the oxide layer 3204 is preferably twice or more the thickness of the metal layer 3202.

  Next, an element formation layer 3301 is formed over the oxide layer 3204 (FIG. 15C). The element formation layer 3301 includes a plurality of TFTs (p-channel TFTs or n-channel TFTs) included in an integrated circuit, and includes a wiring 3211 connecting these TFTs, insulating films (3210, 3212), and the like. Shall be. Note that a method for manufacturing such an element formation layer is not particularly limited in the present invention, and a known manufacturing method can be used in combination with the manufacturing method described in Example 13. Note that the TFT includes an impurity region 3205 and a channel formation region 3206 formed in part of the semiconductor film over the oxide layer 3204, an insulating film 3207, and a gate electrode 3208.

  In this embodiment, at the time of forming the element formation layer 3301, at least a material film containing hydrogen (semiconductor film or metal film) is formed, and then heat treatment for diffusing hydrogen contained in the material film containing hydrogen is performed. Do. This heat treatment may be performed at a temperature of 420 ° C. or higher, and may be performed separately from the formation process of the element formation layer 301, or may be combined with and omitted from the process. For example, if a hydrogen-containing amorphous silicon film is formed as a hydrogen-containing material film by a CVD method and then a heat treatment at 500 ° C. or more is performed for crystallization, a polysilicon film can be formed by heating, and at the same time, hydrogen diffusion is performed. It can be carried out.

  Note that by performing this heat treatment, a layer (not illustrated) including a metal oxide having a crystal structure is formed between the metal layer 3202 and the oxide layer 3204. Note that when the adhesive body 3203 is formed over the metal layer 3202 and the oxide layer 3204 is stacked thereover, an amorphous state formed between the metal layer 3202 and the oxide layer 3204 in a thickness of about 2 nm to 5 nm is used. The metal oxide layer (tungsten oxide film) also forms a crystal structure by this heat treatment, and forms a layer (not shown) made of metal oxide.

  Note that when a layer (not shown) made of the metal oxide is formed at the interface between the metal layer 3202 and the oxide layer 3204, separation between the substrate and the element formation layer in a later step is facilitated. . Note that in this embodiment, the case where a layer made of a metal oxide is formed in the heat treatment during the formation of the element formation layer 3301 is described; however, the present invention is not limited to this method. After the formation of the bonding body 3203, a method in which a metal oxide layer is formed and the oxide layer 3204 is formed can also be employed.

On the other hand, the heat treatment in the course of forming the element formation layer 3301 can increase the adhesion between the bonding body 3203 and the metal layer 3202. That is, in this embodiment, the adhesive 3203 formed of an amorphous silicon film reacts with tungsten (W) in the previously formed metal layer 3202 by applying a heat treatment, thereby forming a silicide (tungsten silicide). : WSi ₂ ) is formed. Therefore, the adhesion between the adhesive body 3203 and the metal layer 3202 is improved. Note that, in the present invention, the method is not limited to a method in which the metal in the metal layer reacts with the adhesive by heat treatment during the formation of the element formation layer 3301. The heat treatment for reacting the metal with the adhesive may be performed separately from the formation of the element formation layer 301.

  When the element formation layer 3301 is completed, the adhesive 3203 is removed. Specifically, an opening 3213 is formed by etching part of the insulating film (3210, 3212) and the adhesive body 3203 by a dry etching method (FIG. 15D).

For example, in the case where the insulating films (3207, 3209, 3210, 3212) and the oxide layer 3204 are etched, and when these are formed using silicon oxide, fluorine carbide (CF ₄ ) is mainly used. Dry etching using an etching gas to be performed and etching the adhesive body 3203, wherein the adhesive body 3203 is formed of silicon, and a part of the adhesive body 3203 is formed despite the reaction with the metal layer (for example, W). If a portion containing silicon as a main component remains, the portion can be etched using an etching gas containing hydrogen bromide (HBr) and chlorine (Cl ₂ ) as a main component. Further, in the case where the adhesive body 3203 is formed of silicon and a part thereof forms silicide (WSi) by reaction with the metal layer (W), this is converted to sulfur fluoride (SF ₆ ) and odor. Etching can be performed using an etching gas containing hydrogen chloride (HBr) as a main component.

  Next, an organic resin layer 3214 is formed over the element formation layer 3301. As a material used for the organic resin layer 3214, an organic material soluble in water or alcohols is used, and is formed by applying and curing the entire surface. The composition of the organic material may be, for example, any of epoxy-based, acrylate-based, and silicon-based. Specifically, a water-soluble resin (VL-WSHL10, manufactured by Toagosei Co., Ltd.) (thickness: 30 μm) is applied by spin coating, and is exposed for 2 minutes to temporarily cure, and then UV light is applied from the back surface to the surface for 2 minutes. The organic resin layer 3214 is formed by performing exposure for 0.5 minutes and exposure from the surface for 10 minutes, that is, for a total of 12.5 minutes, and performing full curing (FIG. 15E).

  Note that a treatment for partially reducing the adhesion at the interface (a layer containing a metal oxide) between the metal layer 3202 and the oxide layer 3204 is performed so that subsequent separation can be easily performed. The treatment for partially reducing the adhesion may be performed by partially irradiating the metal layer 3202 or the oxide layer 3204 with laser light along the periphery of the region to be separated, or by applying a laser beam to the periphery of the region to be separated. This is a process in which pressure is applied locally from the outside to damage the inside of the oxide layer 3204 or a part of the interface. Specifically, a hard needle may be pressed vertically with a diamond pen or the like and moved with a load. Preferably, a scriber device is used, the pressing amount is set to 0.1 mm to 2 mm, and the pressing may be performed by applying pressure. As described above, it is important to create a portion where the peeling phenomenon is likely to occur before performing the peeling, that is, to create a trigger, and by performing a pretreatment for selectively (partially) reducing the adhesion, the peeling is performed. Defects are eliminated, and the yield is further improved.

  Next, by forming the first adhesive layer 3215, a second substrate 3216 which is an auxiliary substrate can be attached to the organic resin layer 3214 through the first adhesive layer 3215 (see FIG. 15E )). Note that as a material for forming the first adhesive layer 3215, a known material whose adhesiveness is reduced by performing a predetermined process in a later step can be used. The case where a photosensitive double-sided tape whose adhesive strength is reduced by light irradiation will be described.

  Next, the first substrate 3201 is separated from the element formation layer 301 to which the auxiliary substrate is attached by physical means. In the case of this embodiment, a relatively small force (for example, a human hand, a wind pressure of gas blown from a nozzle, or the like) is provided at an interface (a layer containing a metal oxide) between the metal layer 3202 and the oxide layer 3204. (E.g., ultrasonic waves). Specifically, separation and separation can be performed in the tungsten oxide film, at the interface between the tungsten oxide film and the silicon oxide film, or at the interface between the tungsten oxide film and the tungsten film. Thus, the element formation layer 3301 formed over the oxide layer 3204 can be separated from the first substrate 3201. FIG. 16A shows a state at the time of peeling.

  In addition, a part of the layer containing the metal oxide remains on the surface exposed by the separation, and this causes a decrease in adhesion when the exposed surface is bonded to a substrate or the like in a later step. For this reason, it is preferable to perform a treatment for removing part of the layer containing the metal oxide remaining on the exposed surface. In order to remove these, an alkaline aqueous solution such as an aqueous ammonia solution or an acidic aqueous solution can be used. In addition, the subsequent steps may be performed at a temperature (430 ° C.) or lower at which a part of the layer containing the metal oxide is easily separated.

  Next, a second adhesive layer 3217 is formed, and the third substrate 3218 and the oxide layer 3204 (and the element formation layer 3301) are bonded to each other through the second adhesive layer 3217 (FIG. 16B). . Note that the adhesion between the second substrate 3216 and the organic resin layer 3214 bonded by the first bonding layer 3215 and the oxide layer 3204 (and the element formation layer 3301) bonded by the second bonding layer 3217 are smaller than the adhesiveness between the organic resin layer 3214 and the second substrate 3216. It is important that the adhesion between the third substrate 3218 and the third substrate 3218 is higher.

  As the third substrate 3218, a flexible substrate (plastic substrate) is preferably used, and in this embodiment, ARTON (manufactured by JSR) made of norbornene resin having a polar group is used.

  As the material used for the second adhesive layer 3217, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a light curable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive. Is mentioned. More preferably, it is more preferable to provide high thermal conductivity by including a powder or a filler made of silver, nickel, aluminum, or aluminum nitride.

  Next, by irradiating ultraviolet light from the second substrate 3216 side, the adhesive strength of the double-sided tape used for the first adhesive layer 3215 is reduced, and the second substrate 3216 is separated from the element formation layer 3301 ( FIG. 16 (C)). Further, in this embodiment, the first adhesive layer 3215 and the organic resin layer 3214 can be dissolved and removed by washing the exposed surface with water, so that the structure shown in FIG. 16D can be obtained.

  As described above, an integrated circuit formed over the first substrate 3201 and including a plurality of TFTs can be manufactured over another substrate (the third substrate 3218).

  In this embodiment, a manufacturing method including the transfer step of the present invention, which is partially different from that in Embodiment 9, will be described with reference to FIGS.

  In FIG. 17A, a metal layer 3402 is stacked over a first substrate 3401, and a plurality of adhesive bodies 3403 are formed thereover.

  Note that in this embodiment, a glass substrate (AN100) similar to that in Embodiment 9 is used as the first substrate 3401. Also, as in the ninth embodiment, a metal layer 3402 containing W (tungsten) as a main component is used for the metal layer 3402. Note that the metal layer 3402 is formed by a sputtering method and has a thickness of 10 nm to 200 nm, preferably 50 nm to 75 nm.

  The adhesive 3403 formed over the metal layer 3402 is formed by forming an amorphous silicon film and then patterning the amorphous silicon film.

  Next, an oxide layer 3404 is formed (FIG. 17B). In this embodiment, a film made of silicon oxide is formed with a thickness of 150 nm to 200 nm by a sputtering method using a silicon oxide target. Note that the thickness of the oxide layer 3404 is preferably greater than or equal to twice the thickness of the metal layer 3402.

  Next, an element formation layer 3501 is formed over the oxide layer 3404 (FIG. 17C). The element formation layer 3501 includes a plurality of TFTs (p-channel TFTs or n-channel TFTs) included in an integrated circuit, and includes a wiring 3411 connecting these TFTs, an insulating film 3410, and the like. Note that a method for manufacturing such an element formation layer is not particularly limited in the present invention, and a known manufacturing method can be used in combination with the manufacturing method described in Example 13. Note that the TFT includes an impurity region 3405 and a channel formation region 3406 formed in part of the semiconductor film over the oxide layer 3404, an insulating film 3407, and a gate electrode 3408.

  In this embodiment, as in Embodiment 9, when forming the element formation layer 3501, at least a material film containing hydrogen (semiconductor film or metal film) is formed, and then hydrogen contained in the material film containing hydrogen is formed. Is performed for diffusing the heat. Note that by performing this heat treatment, a layer (not illustrated) including a metal oxide having a crystal structure is formed between the metal layer 3402 and the oxide layer 3404.

  Note that when a layer (not shown) made of this metal oxide is formed at the interface between the metal layer 3402 and the oxide layer 3404, the substrate and the element formation layer can be easily separated in a later step. .

  On the other hand, the heat treatment in the course of forming the element formation layer 3501 can increase the adhesion between the bonding body 3403 and the metal layer 3402.

  In this embodiment, after the wiring 3411 included in the element formation layer 3501 is formed, the adhesive 3403 is removed. Specifically, part of the insulating film 3410 and the adhesive 3403 are etched by a dry etching method, so that an opening 3412 is formed (FIG. 17D).

For example, in the case where the insulating film (3407, 3409, 3410) and the oxide layer 3404 are etched, and these are formed using silicon oxide, the etching mainly includes fluorine carbide (CF ₄ ). In the case where dry etching is performed using a gas and the adhesive 3403 is etched, the adhesive 3403 is formed of silicon, and a part of the adhesive is formed despite the reaction with the metal layer (for example, W). When a portion mainly composed of γ is left, it can be etched using an etching gas mainly composed of hydrogen bromide (HBr) and chlorine (Cl ₂ ). Further, in the case where the adhesive body 3403 is formed of silicon and a part thereof forms silicide (WSi) by a reaction with the metal layer (W), this is converted to sulfur fluoride (SF ₆ ) and odor. Etching can be performed using an etching gas containing hydrogen chloride (HBr) as a main component.

  Next, an insulating film 3413 is formed to fill the opening 3412 and planarize the surface of the element formation layer 3501 (FIG. 17E). Note that in this embodiment, a silicon nitride oxide film having a thickness of 1 to 3 μm formed by a plasma CVD method is used. Of course, this insulating film is not limited to a silicon nitride oxide film, but may be an insulating material such as silicon nitride, silicon nitride, or silicon oxide, or a single-layer structure made of an organic insulating material such as acryl, polyimide, or polyamide. A stacked structure may be used in combination.

  Note that this is a step after the surface of the element formation layer 3501 is flattened by the insulating film 3413. (1) An organic resin layer is formed on the element formation layer 3501 and an auxiliary resin layer is provided thereon via a first adhesive layer. A step of attaching a second substrate, which is a substrate, (2) peeling off the first substrate 3401 from the element formation layer 501 from the element formation layer 3501 to which the auxiliary substrate (the second substrate) is attached by physical means (3) forming a second adhesive layer, bonding the third substrate and the oxide layer (and the element forming layer) via the second adhesive layer, and (4) starting from the element forming layer. The step of separating the second substrate can be formed using a material similar to that described in Embodiment 9 and by a similar method, and a description thereof will not be repeated.

  As described above, the structure illustrated in FIG. 18A in which the element formation layer 3501 is transferred to the third substrate 3418 through the second adhesive layer 3417 can be obtained.

  In this embodiment, the structure illustrated in FIG. 18B may be formed by forming the opening 3412 in FIG. 17D and then forming the insulating film 3419.

  As described above, an integrated circuit formed over the first substrate 3401 and including a plurality of TFTs can be manufactured over another substrate (the third substrate 3418).

  In this embodiment, a manufacturing method including the transfer step of the present invention, which is partially different from Embodiments 9 and 10, will be described with reference to FIGS.

  In FIG. 19A, a metal layer 3602 is stacked over a first substrate 3601, and an oxide layer 3603 is formed thereover.

  In this embodiment, a glass substrate (AN100) similar to that in Embodiment 9 is used as the first substrate 3601. Also, as in the ninth embodiment, a metal layer 3602 containing W (tungsten) as a main component is used for the metal layer 3602. Note that the metal layer 3602 is formed by a sputtering method and has a thickness of 10 nm to 200 nm, preferably 50 nm to 75 nm.

  The oxide layer 3603 formed over the metal layer 3602 is formed using a silicon oxide target with a thickness of 150 nm to 200 nm by a sputtering method using a silicon oxide target. Note that the thickness of the oxide layer 3603 is preferably twice or more the thickness of the metal layer 3602. In this embodiment, the oxide layer 3603 is formed in a plurality of islands by patterning.

  Next, a semiconductor film 3604 is formed to cover the oxide layer 3603. In this embodiment, an amorphous silicon film is formed by a plasma CVD method (FIG. 19A). Then, by patterning the semiconductor film 3604, a semiconductor a (3605) formed over the oxide layer 3603 and a semiconductor b (3606) formed between two separated oxide layers 3603 are obtained. Can be Note that the semiconductor a (3605) formed here becomes an impurity region and a channel formation region of a TFT to be formed later, and the semiconductor b (3606) becomes an adhesive in the present invention.

  That is, the present invention is characterized in that the semiconductor a (3605) forming a part of the TFT and the semiconductor b (3606) forming the adhesive are formed at the same time.

  Next, an element formation layer 3701 partially including the semiconductor a (3605) is formed (FIG. 19C). The element formation layer 3701 is formed with a plurality of TFTs (p-channel TFTs or n-channel TFTs) included in an integrated circuit, and includes a wiring 3613 connecting these TFTs, an insulating film 3612, and the like. Note that a method for manufacturing an element formation layer including a TFT is not particularly limited in the present invention, and a known manufacturing method can be used in combination with the manufacturing method described in Embodiment 13. Note that the TFT includes an impurity region 3607 and a channel formation region 3608 formed in part of the semiconductor a (3605) over the oxide layer 3603, a gate insulating film 3609, and a gate electrode 3610.

  In this embodiment, as in Embodiment 9, when forming the element formation layer 3701, after forming at least a material film containing hydrogen (semiconductor film or metal film), hydrogen contained in the material film containing hydrogen is used. Is performed for diffusing the heat. Note that by performing this heat treatment, a layer (not illustrated) including a metal oxide having a crystal structure is formed between the metal layer 3602 and the oxide layer 3603.

  Note that a layer (not shown) made of the metal oxide is formed at the interface between the metal layer 3602 and the oxide layer 3603, so that the first substrate 3601 and the element formation layer 3701 in a later step are separated. Separation is facilitated.

  On the other hand, by the heat treatment in the course of forming the element formation layer 3701, the adhesiveness between the semiconductor b (3606) as an adhesive and the metal layer 3602 can be increased.

  In this embodiment, after the wiring 3613 included in the element formation layer 3701 is formed, the semiconductor b (3606) is removed (FIG. 19D). Specifically, an opening 3614 is formed by etching part of the insulating film 3612 and the semiconductor b (3606) by a dry etching method.

For example, in the case where the insulating films (3609, 3611, 3612) and the oxide layer 3603 are etched, and these are formed using silicon oxide, the etching mainly includes fluorine carbide (CF ₄ ). In the case where dry etching is performed using a gas and the semiconductor b (3606) as an adhesive is etched, the semiconductor b (3606) is formed of silicon, and the semiconductor b (3606) reacts with a metal layer (for example, W). Nevertheless, if a portion containing silicon as a main component remains in a part thereof, it can be etched using an etching gas containing hydrogen bromide (HBr) and chlorine (Cl ₂ ) as a main component. it can. Further, when the semiconductor b (3606) is formed of silicon and a part thereof forms silicide (WSi) by a reaction with the metal layer (W), the semiconductor b (3606) is converted to sulfur fluoride (SF ₆ ). And an etching gas containing hydrogen bromide (HBr) as a main component.

  Next, an insulating film 3615 is formed to fill the opening 3614 and planarize the surface of the element formation layer 3701 (FIG. 19E). Note that in this embodiment, a silicon nitride oxide film having a thickness of 1 to 3 μm formed by a plasma CVD method is used. Of course, this insulating film is not limited to a silicon nitride oxide film, but may be an insulating material such as silicon nitride, silicon nitride, or silicon oxide, or a single-layer structure made of an organic insulating material such as acryl, polyimide, or polyamide. A stacked structure may be used in combination.

  Note that this is a step after the surface of the element formation layer 3701 is planarized by the insulating film 3615. (1) An organic resin layer is formed on the element formation layer 3701, and an auxiliary resin layer is provided thereon via a first adhesive layer. A step of attaching a second substrate, which is a substrate, (2) peeling the first substrate 3601 from the element formation layer 3701 from the element formation layer 3701 to which the auxiliary substrate (the second substrate) is attached by physical means (3) forming a second adhesive layer, bonding the third substrate and the oxide layer (and the element forming layer) via the second adhesive layer, and (4) starting from the element forming layer. The step of separating the second substrate can be formed using a material similar to that described in Embodiment 9 and by a similar method, and a description thereof will not be repeated.

  As described above, a structure illustrated in FIG. 20A in which the element formation layer 3701 is transferred to the third substrate 3618 through the second adhesive layer 3617 can be obtained.

  In this embodiment, the structure illustrated in FIG. 20B may be formed by forming the opening 3614 in FIG. 19D and then forming the insulating film 3800.

  As described above, an integrated circuit formed over the first substrate 3601 and including a plurality of TFTs can be manufactured over another substrate (a third base 3618 plate).

  In this embodiment, the arrangement and the shape of the adhesive in the present invention will be described with reference to FIGS.

  In the present invention, as shown in FIG. 21A, transfer is performed by separating an element formation layer 3802 formed over a substrate 3801 by physical means and attaching the element formation layer 3802 to another substrate. Note that in the case of FIG. 21A, the element formation layer 3802 is separated in the direction of the arrow.

  Therefore, regarding the arrangement and shape of the adhesive formed in the element formation layer 3802, the adhesive formed in the region 3803 which is a part of the element formation layer 3802 during the production of the element formation layer 3802 and removed immediately before peeling is used. Examples of the arrangement and the shape are shown in FIGS.

  FIG. 21B illustrates a case where a quadrangular adhesive 3805 is formed between integrated circuits 3804 arranged in the peeling direction XX 'in a region 3803 where a plurality of integrated circuits 3804 are formed. In this case, it is more preferable that the quadrangular adhesive 3805 has a rectangular shape and the rectangular long sides are arranged in parallel with the peeling direction AA '. By forming the bonding body 3805 in a square shape in this manner, the element formation layer 3802 can be easily separated from the substrate 3801 after the bonding body 3805 is removed.

  FIG. 21C illustrates a case where a triangular adhesive 3807 is formed between the integrated circuits 3806 arranged in the separation direction AA 'in a region 3803 where a plurality of integrated circuits 3806 are formed. Note that, in this case, it is more preferable that the bottom side of the triangular adhesive body 3807 is arranged so as to be perpendicular to the peeling direction XX '. Even when the bonding body 3807 has a triangular shape in this manner, the element formation layer 3802 can be easily separated from the substrate 3801 after the bonding body 3807 is removed.

  In FIG. 21D, in a region 3803 where a plurality of integrated circuits 3808 are formed, a line-shaped adhesive body 3809 is formed between rows of the integrated circuits 3808 which are arranged in a separation direction XX ′. It shows about. Note that in this case, the linear adhesive body 3809 may be formed in the same length as the plurality of integrated circuits 3808 are arranged in the peeling direction XX ′, but is formed in a length corresponding to one integrated circuit 38081. You may. In this manner, even when the adhesive 3809 is formed in a line shape, the element formation layer 3802 can be easily separated from the substrate 3801 after the adhesive 3807 is removed.

  It should be noted that the arrangement and shape of the adhesive shown in this example are merely preferred examples of the present invention, and do not limit the shape of the adhesive of the present invention at all.

  In this embodiment, a method for simultaneously manufacturing an n-channel TFT and a p-channel TFT on the same substrate will be described with reference to FIGS.

  A metal layer 3902 is formed over a substrate 3901, and an adhesive 3903 is formed thereon.

  In this embodiment, a glass substrate (# 1737) is used as the substrate 3901, and a metal material mainly containing tungsten (W) is used for the metal layer 3902 as in the ninth embodiment. Note that the adhesive 3903 is patterned and formed into a desired shape so as to be disposed between integrated circuits (including a plurality of TFTs) to be formed later.

Next, an oxide layer 3904 which also functions as a base insulating film is formed over the metal layer 3902 and the adhesive 3903. In this embodiment, a film formation temperature 300 ° C. by a plasma CVD method, a raw material gas SiH _4, N ₂ O silicon oxynitride made from film (composition ratio Si = 32%, O = 59 %, N = 7%, H = 2%) to a thickness of 100 nm, so that an oxide layer 3904 is formed.

Furthermore, a semiconductor layer having an amorphous structure (here, an amorphous silicon layer) is formed to a thickness of 54 nm by a plasma CVD method continuously at a film forming temperature of 300 ° C. and a film forming gas of SiH ₄ without opening to the atmosphere. . This amorphous silicon layer contains hydrogen, and hydrogen can be diffused by a heat treatment performed later, and can be separated in the oxide layer or at the interface by physical means.

  Next, a nickel acetate salt solution containing 10 ppm by weight of nickel is applied by a spinner. Instead of coating, a method of spraying a nickel element over the entire surface by a sputtering method may be used. Next, a semiconductor film (here, a polysilicon layer) having a crystal structure is formed by heat treatment and crystallization. Here, after a heat treatment for dehydrogenation (500 ° C., 1 hour), a heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a silicon film having a crystal structure. The heat treatment for dehydrogenation (at 500 ° C. for one hour) also serves as a heat treatment for diffusing hydrogen contained in the amorphous silicon film to the interface between the metal layer 3902 and the oxide layer 3904. Although a crystallization technique using nickel as a metal element for promoting crystallization of silicon is used here, other known crystallization techniques, for example, a solid phase growth method or a laser crystallization method may be used.

Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, a laser beam (XeCl: wavelength 308 nm) for increasing the crystallization rate and repairing defects remaining in the crystal grains is used. Irradiation is performed in the air or in an oxygen atmosphere. Excimer laser light having a wavelength of 400 nm or less, or the second and third harmonics of a YAG laser is used as the laser light. Here, a pulse laser beam having a repetition frequency of about 10 to 1000 Hz is used, and the laser beam is condensed to 100 to 500 mJ / cm ² by an optical system and irradiated with an overlap ratio of 90 to 95%, and the silicon film surface is irradiated. May be scanned. Here, laser light irradiation is performed in the atmosphere at a repetition frequency of 30 Hz and an energy density of 470 mJ / cm ² .

Note that an oxide film is formed on the surface by laser light irradiation because the irradiation is performed in the air or in an oxygen atmosphere. Although an example using a pulse laser is described here, a continuous wave laser may be used. In crystallizing an amorphous semiconductor film, continuous oscillation is possible in order to obtain a crystal with a large grain size. It is preferable to use a solid-state laser and apply the second to fourth harmonics of the fundamental wave. Typically, Nd: YVO ₄ may be applied laser (fundamental wave 1064 nm) second harmonic (532 nm) or the third harmonic (355 nm). When a continuous wave laser is used, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a nonlinear optical element. There is also a method in which a YVO ₄ crystal and a nonlinear optical element are put in a resonator to emit a harmonic. Then, the laser beam is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the laser beam is irradiated on the object. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relatively to the laser beam at a speed of about 10 to 2000 cm / s.

  Next, in addition to the oxide film formed by the laser light irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total of 1 to 5 nm. In this embodiment mode, the barrier layer is formed using ozone water. A method of oxidizing the surface of the semiconductor film having a crystal structure by irradiation with ultraviolet light in an oxygen atmosphere or the surface of the semiconductor film having a crystal structure by oxygen plasma treatment A barrier layer may be formed by depositing an oxide film of about 1 to 10 nm by a method of oxidizing, a plasma CVD method, a sputtering method, an evaporation method, or the like. Further, before forming the barrier layer, an oxide film formed by laser light irradiation may be removed.

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed to a thickness of 10 nm to 400 nm, here, 100 nm over the barrier layer by a sputtering method. In this embodiment, the amorphous silicon film containing an argon element is formed in an atmosphere containing argon using a silicon target. When an amorphous silicon film containing an argon element is formed by a plasma CVD method, the film forming conditions are as follows: a flow rate ratio of monosilane to argon (SiH ₄ : Ar) is 1:99, and a film forming pressure is 6.665 Pa. (0.05 Torr), the RF power density is 0.087 W / cm ² , and the film formation temperature is 350 ° C.

  After that, heat treatment is performed in a furnace heated to 650 ° C. for 3 minutes to perform gettering to reduce the nickel concentration in the semiconductor film having a crystal structure. A lamp annealing device may be used instead of the furnace.

  Next, after the amorphous silicon film containing an argon element, which is a gettering site, is selectively removed using the barrier layer as an etching stopper, the barrier layer is selectively removed with dilute hydrofluoric acid. Note that at the time of gettering, since nickel tends to move to a region having a high oxygen concentration, it is desirable to remove the barrier layer made of an oxide film after gettering.

  Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also called a polysilicon film), a mask made of a resist is formed, and an etching process is performed into a desired shape to form an island. To form separated semiconductor layers 3905 and 3906. After the formation of the semiconductor layers 3905 and 3906, the resist mask is removed (FIG. 22A).

  Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film (semiconductor layers 3905 and 3906) is washed. Then, an insulating film containing silicon as a main component which is to be a gate insulating film 3907 is formed. In this embodiment, a silicon oxide film is formed with a thickness of 115 nm by a plasma CVD method (FIG. 22B).

  Further, a first conductive film 3908 having a thickness of 20 to 100 nm and a second conductive film 3909 having a thickness of 100 to 400 nm are formed over the gate insulating film 3907. In this embodiment, a 50-nm-thick tantalum nitride film to be the first conductive film 3908 and a 370-nm-thick tungsten film to be the second conductive film 3909 are sequentially stacked over the gate insulating film 3907.

  Note that a conductive material for forming the first conductive film 3908 and the second conductive film 3909 is an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material containing the above element as a main component. Alternatively, a compound material can be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or an AgPdCu alloy may be used for the first conductive film 3908 and the second conductive film 3909. The structure is not limited to a two-layer structure. For example, a three-layer structure in which a 50-nm-thick tungsten film, a 500-nm-thick aluminum-silicon alloy (Al-Si) film, and a 30-nm-thick titanium nitride film are sequentially stacked. Is also good. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum may be used instead of an aluminum-silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al-Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Further, it may have a single-layer structure.

Next, as shown in FIG. 22C, masks 3910 and 3911 made of resist are formed by a light exposure process, and a first etching process for forming a gate electrode and a wiring is performed. The first etching process is performed under the first and second etching conditions. It is preferable to use an ICP (Inductively Coupled Plasma) etching method for the etching. The film is formed into a desired tapered shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) using the ICP etching method. Can be etched. As the etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ , NF ₃ , or the like, or O ₂ is appropriately used. Can be used.

In this embodiment, RF (13.56 MHz) power of 150 W is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, a quartz disk provided with a coil) is a disk having a diameter of 25 cm. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered. Under the first etching conditions, the etching rate for W is 200.39 nm / min, the etching rate for TaN is 80.32 nm / min, and the selectivity ratio of W to TaN is about 2.5. Further, the taper angle of W becomes about 26 ° under the first etching condition. Thereafter, the masks 3910 and 3911 made of resist are changed to the second etching condition without being removed, and CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow rates are set to 30/30 (sccm). A 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching was performed for about 30 seconds. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%.

  In the first etching process, the shape of the resist mask is made appropriate, so that the edges of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of the tapered portion may be 15 to 45 degrees.

  Thus, the first shape conductive layers 3912 and 3913 composed of the first conductive layer and the second conductive layer by the first etching process (the first conductive layers 3912a and 3913a and the second conductive layers 3912b and 3913b). To form The insulating film 3907 serving as a gate insulating film is etched by about 10 to 20 nm, and becomes a gate insulating film 3907 in which a region which is not covered with the first shape conductive layers 3912 and 3913 is thinned.

Next, a second etching process is performed without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, the respective gas flow rates are set to 24/12/24 (sccm), and 700 W RF ( (13.56 MHz) Power is supplied to generate plasma, and etching is performed for 25 seconds. A 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. The etching rate for W in the second etching process is 227.3 nm / min, the etching rate for TaN is 32.1 nm / min, the selectivity ratio of W to TaN is 7.1, and the gate insulating film 3911 is formed. The etching rate for SiON is 33.7 nm / min, and the selectivity ratio of W to SiON is 6.83. As described above, when SF ₆ is used as the etching gas, the selectivity to the gate insulating film 3911 is high, so that the film loss can be suppressed. The reduction in the thickness of the gate insulating film 3907 in this embodiment is about 8 nm.

  The taper angle of W can be set to 70 ° by the second etching process. By this second etching process, second conductive layers 3914b and 3915b are formed. At this time, the first conductive layer is hardly etched and becomes first conductive layers 3914a and 3915a. Note that the first conductive layers 3914a and 3915a have substantially the same size as the first conductive layers 3912a and 3913a. Actually, the width of the first conductive layer may be set back by about 0.3 μm as compared with before the second etching treatment, that is, about 0.6 μm in the entire line width, but there is almost no change in size.

Further, instead of the two-layer structure, a three-layer structure in which a 50-nm-thick tungsten film, a 500-nm-thick aluminum-silicon alloy (Al-Si) film, and a 30-nm-thick titanium nitride film are sequentially stacked, As the first etching conditions in the first etching process, BCl ₃ , Cl _2, and O ₂ are used as source gases, the respective gas flow ratios are set to 65/10/5 (sccm), and the substrate side (sample stage) is used. ) Is supplied with 300 W RF (13.56 MHz) power, and 450 W RF (13.56 MHz) power is supplied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma and perform etching for 117 seconds. Ebayoku, as the second etching conditions of the first etching treatment, CF ₄ and using a Cl ₂ and O _2, a ratio of respective gas flow rates is 25/25/10 (scc ), 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and 500 W RF (13.56 MHz) power is applied to the coil type electrode at a pressure of 1 Pa to generate plasma. The etching may be performed for about 30 seconds. As the second etching process, BCl ₃ and Cl ₂ are used, each gas flow ratio is set to 20/60 (sccm), and 100 W is applied to the substrate side (sample stage). RF (13.56 MHz) power is supplied, and 600 W RF (13.56 MHz) power is supplied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma and perform etching.

  Next, after removing the mask 3910 made of resist, next, as shown in FIG. 23A, a mask 3918 made of resist is formed and first doping treatment is performed. The doping treatment may be performed by an ion doping method or an ion implantation method. Note that a mask 3918 is a mask for protecting a semiconductor film forming a p-channel TFT and a peripheral region thereof.

The condition of the ion doping method in the first doping treatment is to dope phosphorus (P) with a dose amount of 1.5 × 10 ¹⁵ atoms / cm ² and an acceleration voltage of 60 to 100 keV. Note that typically, phosphorus (P) or arsenic (As) can be used as the impurity element imparting n-type. Here, an impurity region is formed in each semiconductor layer in a self-aligned manner using the second conductive layers 3914b and 3915b as a mask. Of course, it is not added to the area covered with the mask 3918. Thus, a first impurity region 3919 and a second impurity region 3920 are formed. The first impurity region 3919 is doped with an impurity element imparting n-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Here, a region having the same concentration range as the first impurity region is also called an n ⁺ region.

In addition, the second impurity region 3920 is formed at a lower concentration than the first impurity region 3919 by the first conductive layer 3915a, and is given n-type in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ^3. Is added. Note that the second impurity region 920 has a concentration gradient in which the impurity concentration increases toward the end of the tapered portion because doping is performed by passing the second conductive region 920 through a portion of the first conductive layer 3915a having a tapered shape. ing. Here, a region having the same concentration range as second impurity region 3920 is also referred to as an n ⁻ region.

  Next, after removing the mask 3918 made of resist, a new mask 3921 made of resist is formed, and a second doping process is performed as shown in FIG. The doping treatment may be performed by an ion doping method or an ion implantation method. Note that the mask 3921 is a mask for protecting a semiconductor film forming an n-channel TFT and a peripheral region thereof.

The condition of the ion doping method in the second doping treatment is to dope boron (B) at a dose of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ atoms / cm ² and an acceleration voltage of 50 to 100 keV. Here, an impurity region is formed in each semiconductor layer in a self-aligned manner using the second conductive layers 3914b and 3915b as a mask. Of course, boron is not added to the region covered with the mask 3921. By the second doping treatment, a third impurity region 3922 and a fourth impurity region 3923 in which an impurity element imparting p-type conductivity is added to a semiconductor layer forming a p-channel TFT are formed.

Further, an impurity element imparting p-type conductivity is added to the third impurity region 3922 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

The fourth impurity region 3923 is formed in a region overlapping with the tapered portion of the first conductive layer 3914a, and has a p-type concentration in a range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. The impurity element is added. Note that the fourth impurity region 3923 performs doping by transmitting a portion of the first conductive layer 3914a having a tapered shape. Therefore, the fourth impurity region 3923 has a concentration gradient in which the impurity concentration increases toward the end of the tapered portion. I have. Here, a region having the same concentration range as fourth impurity region 3923 is also referred to as ap ⁻ region.

  Through the above steps, an impurity region having n-type or p-type conductivity is formed in each semiconductor layer. The first shape conductive layers 3914 and 3915 serve as TFT gate electrodes.

  Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination of any of these methods. Done by the method

  Next, a first insulating film 3924 is formed. Note that in this embodiment, a 50-nm-thick silicon nitride oxide film formed by a plasma CVD method is used. Needless to say, this insulating film is not limited to a silicon nitride oxide film, and an insulating film such as silicon nitride, silicon nitride, or silicon oxide may be used as a single layer or a stacked structure.

  Next, a second insulating film 3925 is formed over the first insulating film 3924. As the second insulating film 3925 formed here, an insulating film such as silicon nitride, silicon nitride oxide, or silicon oxide can be used. In this embodiment, a 50 nm-thick film formed by a plasma CVD method is used. A silicon nitride film is used.

  Next, after forming a second insulating film 3925 formed of a silicon nitride film, heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) is performed to perform a step of hydrogenating the semiconductor layer (FIG. 23C )). In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the second insulating film 3925. As other means of hydrogenation, heat treatment at about 350 ° C. in a hydrogen atmosphere or plasma hydrogenation (using hydrogen excited by plasma) can be performed.

  Next, a third insulating film 3926 made of an organic insulating material is formed over the second insulating film 3925. Here, an acrylic resin film having a thickness of 1.6 μm is formed. Next, a contact hole 3927 reaching each impurity region is formed.

  Since the acrylic resin used in this embodiment is photosensitive acrylic, a desired position can be opened by exposure and development. Further, the first insulating film 3924 and the second insulating film 3925 are partially etched by a dry etching method, and the second insulating film 3925 is etched using the first insulating film 3924 as an etching stopper. Then, the first insulating film 3924 is etched. Thus, a contact hole 3927 is obtained.

  In this embodiment, the case where the contact hole is formed after the third insulating film 3926 formed of the organic resin film is formed has been described. However, the second insulating film 3926 is formed before the third insulating film 3926 is formed. The insulating film 3925 and the first insulating film 3924 can be dry-etched. Note that in this case, it is preferable that the substrate be heat-treated (heat treatment at 300 to 550 ° C. for 1 to 12 hours) after the etching treatment and before the third insulating film 3926 is formed.

  Then, by forming a wiring 3928 using Al, Ti, Mo, W, or the like as shown in FIG. 23D, an n-channel TFT 3931 and a p-channel TFT 3932 can be formed over the same substrate.

  In this embodiment, functions and configurations in a case where an integrated circuit formed by the present invention is a CPU will be described with reference to FIGS.

  First, when an operation code is input to the interface 4001, the code is decoded in the analysis circuit 4003 (also referred to as Instruction Decoder), and a signal is input to the control signal generation circuit 4004 (CPU Timing Control). When a signal is input, a control signal is output from control signal generation circuit 4004 to arithmetic circuit 4009 (hereinafter, referred to as ALU) and storage circuit 4010 (hereinafter, referred to as Register).

  The control signal generation circuit 4004 includes an ALU controller 4005 (hereinafter, referred to as ACON) for controlling the ALU 4009, a circuit 4006 (hereinafter, referred to as RCON) for controlling the Register 4010, a timing controller 4007 (hereinafter, TCON) for controlling timing. And an interrupt controller 4008 (hereinafter, referred to as ICON) for controlling interrupts.

  On the other hand, when an operand is input to the interface 4001, it is output to the ALU 4009 and the Register 4010. Then, processing (for example, a memory read cycle, a memory write cycle, an I / O read cycle, an I / O write cycle, and the like) based on the control signal input from the control signal generation circuit 4004 is performed.

  The Register 4010 includes a general-purpose register, a stack pointer (SP), a program counter (PC), and the like.

  An address controller 4011 (hereinafter, referred to as ADRC) outputs a 16-bit address.

  Note that the structure of the CPU described in this embodiment is an example of a CPU formed using the manufacturing method of the present invention, and does not limit the structure of the present invention. Therefore, a known CPU configuration other than the configuration shown in this embodiment can be used.

  In this embodiment, the manner in which the integrated circuit of the present invention is incorporated in a module and is actually incorporated in an electronic device will be described with reference to FIGS.

  In a mobile phone module illustrated in FIG. 25, a printed wiring board 4406 includes a controller 4401, a CPU 4402, a memory 4411, a power supply circuit 4403, an audio processing circuit 4429, a transmission / reception circuit 4404, and other elements such as a resistor, a buffer, and a capacitor. Has been implemented. Note that the integrated circuit manufactured according to the present invention can be used for the controller 4401, the CPU 4402, the memory 4411, the power supply circuit 4403, the audio processing circuit 4429, and the like. Although not shown here, the panel is mounted on the printed wiring board 4406 by FPC.

  A power supply voltage to the printed wiring board 4406 and various signals input from a keyboard or the like are supplied via a printed wiring board interface (I / F) unit 4409 provided with a plurality of input terminals. An antenna port 4410 for transmitting and receiving signals to and from an antenna is provided on the printed wiring board 4406.

  Note that the memory 4411 includes a VRAM, a DRAM, a flash memory, and the like. The VRAM stores image data to be displayed on the panel, the DRAM stores image data or audio data, and the flash memory stores various programs.

  In the power supply circuit 4403, a power supply voltage for the controller 4401, the CPU 4402, the audio processing circuit 4429, the memory 4411, and the transmission / reception circuit 4404 is generated. Depending on the specifications of the panel, the power supply circuit 4403 may include a current source.

  Although the configuration of the CPU 4402 has been described in the fourteenth embodiment and is omitted, a signal including various instructions is transmitted to the memory 4411, the transmission / reception circuit 4404, the audio processing circuit 4429, the controller 4401, and the like based on the input signal.

  The memory 4411, the transmission / reception circuit 4431, the audio processing circuit 4429, and the controller 4401 operate according to the received instructions. The operation will be briefly described below.

  A signal input from the keyboard is sent to the CPU 4402 mounted on the printed wiring board 4406 via the interface 4409. The CPU 4402 converts the image data stored in the VRAM into a predetermined format according to the signal sent from the keyboard, and sends the converted data to the controller 4401.

  The controller 4401 performs data processing on a signal including image data sent from the CPU 4402 according to the specifications of the panel, and supplies the processed signal to the panel. The controller 4401 generates an Hsync signal, a Vsync signal, a clock signal CLK, and an AC voltage (AC Cont) based on a power supply voltage input from the power supply voltage 4403 and various signals input from the CPU, and supplies the generated signals to the panel. I do.

  In the transmission / reception circuit 4404, signals transmitted and received as radio waves by the antenna are processed. Specifically, high frequency circuits such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun are used. Contains. A signal including audio information among signals transmitted and received by the transmission / reception circuit 4404 is sent to the audio processing circuit 4429 according to a command from the CPU 4402.

  A signal including audio information transmitted in accordance with an instruction from the CPU 4402 is demodulated into an audio signal in an audio processing circuit 4429 and sent to a speaker. The audio signal sent from the microphone is modulated in the audio processing circuit 4429 and sent to the transmission / reception circuit 4404 according to a command from the CPU 4402.

  The integrated circuit formed according to the present invention is not limited to the above-described circuits, except for high frequency circuits such as isolators, bandpass filters, VCOs (Voltage Controlled Oscillator), LPFs (Low Pass Filters), couplers, and baluns. It can be applied to any circuit.

  Various modules as shown in Embodiment 15 can be completed using an integrated circuit formed by using the manufacturing method of the present invention. Therefore, various electronic devices can be completed by incorporating these modules.

  These electronic devices include video cameras, digital cameras, head mounted displays, (goggle type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, portable game machines or electronic And a device having a display device capable of reproducing a recording medium such as a book) and displaying the image. FIG. 13 shows specific examples of these electronic devices.

  FIG. 13A illustrates a display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The integrated circuit formed by the present invention can be used for a circuit portion or the like for displaying on a display device. The display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

  FIG. 13B illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The integrated circuit formed by the present invention can be used for a circuit portion or the like for driving a notebook personal computer.

  FIG. 13C illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The integrated circuit formed by the present invention can be used for a circuit portion or the like for driving a mobile computer.

  FIG. 13D illustrates a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), which includes a main body 2401, a housing 2402, a display A 2403, a display b2404, a recording medium reading unit 2405, and operation keys 2406. , A speaker unit 2407 and the like. Note that the display portion A 2403 and the display portion B 2404 include the light-emitting elements described in Embodiment 6 and the liquid crystal elements described in Embodiment 7. This player uses a DVD (Digital Versatile Disc), a CD, or the like as a recording medium, and can enjoy music, movies, games, and the Internet.

  FIG. 13E illustrates a portable book (electronic book), which includes a main body 2501, a display portion 2502, a storage medium 2503, operation switches 2504, an antenna 2505, and the like. The integrated circuit formed by the present invention can be used for a circuit portion or the like for making a portable book function.

  FIG. 13F illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 5606, a battery 5607, a voice input portion 5608, operation keys 5609, and an eyepiece. Section 5610 and the like. The integrated circuit formed by the present invention can be used for a circuit portion or the like for making a video camera function.

  Here, FIG. 13G illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a sound input portion 2704, a sound output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The integrated circuit formed by the present invention can be used for a circuit portion or the like for making a mobile phone function.

  As described above, the application range of the integrated circuit manufactured according to the present invention is extremely wide, and the integrated circuit can be applied to products in various fields.

FIG. 2 illustrates a configuration of the present invention. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. The figure explaining the shape of an adhesion body. 7A to 7C illustrate a method for manufacturing a TFT. 7A to 7C illustrate a method for manufacturing a TFT. FIG. 4 illustrates a structure of a light-emitting element formed in a pixel portion. FIG. 4 illustrates a structure of a liquid crystal element formed in a pixel portion. FIG. 13 illustrates an electronic device formed using the present invention. FIG. 2 illustrates a configuration of the present invention. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. FIG. 4 illustrates a method for manufacturing a semiconductor device including a transfer step. The figure explaining the shape of an adhesion body. 7A to 7C illustrate a method for manufacturing a TFT. 7A to 7C illustrate a method for manufacturing a TFT. FIG. 4 illustrates a CPU formed by the present invention. FIG. 2 illustrates a module in which an integrated circuit formed by the present invention is incorporated. FIG. 4 illustrates a structure of a light-emitting element formed in a pixel portion.

Claims (25)

Forming a metal layer on the first substrate;
Forming an adhesive on a part of the metal layer,
Forming an oxide layer over the metal layer and the adhesive;
Forming a semiconductor element on the oxide layer,
A method for manufacturing a semiconductor device, comprising: removing the adhesive. Forming a metal layer on the first substrate;
Forming an adhesive on a part of the metal layer,
Forming an oxide layer over the metal layer and the adhesive;
Forming an element formation layer including a semiconductor element on the oxide layer;
A method for manufacturing a semiconductor device, wherein the adhesive is removed by etching a part of the element formation layer. Forming a metal layer on the first substrate;
Forming an adhesive on a part of the metal layer,
Forming an oxide layer over the metal layer and the adhesive;
Forming an element formation layer including a semiconductor element on the oxide layer;
The adhesive is removed by etching a part of the element forming layer,
A second substrate is attached to the element formation layer via a first adhesive,
A method for manufacturing a semiconductor device, wherein the second substrate and the element formation layer are separated from the first substrate by physical means. Forming a metal layer on the first substrate;
Forming an adhesive on a part of the metal layer,
Forming an oxide layer over the metal layer and the adhesive;
Forming an element formation layer including a semiconductor element on the oxide layer;
The adhesive is removed by etching a part of the element forming layer,
A second substrate is attached to the element formation layer via a first adhesive,
Separating the second substrate and the element formation layer from the first substrate by physical means;
Affixing the second substrate and the element formation layer on a third substrate via a second adhesive;
A method for manufacturing a semiconductor device, comprising removing the second substrate from the element formation layer. In any one of claims 1 to 4,
A method for manufacturing a semiconductor device, comprising using any one of tungsten, molybdenum, technetium, rhenium, ruthenium, osmium, rhodium, iridium, palladium, platinum, silver, and gold as the metal layer. In any one of claims 1 to 5,
The method for manufacturing a semiconductor device, wherein the element formation layer includes a heat treatment step at 400 ° C. or higher, preferably 600 ° C. or higher as part of the manufacturing process. In any one of claims 1 to 6,
The method for manufacturing a semiconductor device, wherein the semiconductor element is formed at a position that does not overlap with the adhesive. In any one of claims 1 to 7,
A method for manufacturing a semiconductor device, wherein a material that chemically reacts with a metal included in the metal layer is used as the adhesive. In any one of claims 1 to 8,
A method for manufacturing a semiconductor device, wherein any one of silicon, germanium, carbon, boron, magnesium, aluminum, titanium, tantalum, iron, cobalt, nickel, and manganese is used as the adhesive. 10. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is made of plastic. Forming a metal layer on the first substrate;
Forming an adhesive on a part of the metal layer,
Forming an oxide layer over the metal layer and the adhesive;
Forming an integrated circuit composed of a plurality of semiconductor elements on the oxide layer,
A method for manufacturing a semiconductor device, comprising: removing the adhesive. Forming a metal layer on the first substrate;
Forming an adhesive on a part of the metal layer,
Forming an oxide layer over the metal layer and the adhesive;
Forming an element formation layer including an integrated circuit composed of a plurality of semiconductor elements on the oxide layer,
A method for manufacturing a semiconductor device, wherein the adhesive is removed by etching a part of the element formation layer. Forming a metal layer on the first substrate;
Forming an adhesive on a part of the metal layer,
Forming an oxide layer over the metal layer and the adhesive;
Forming an element formation layer including an integrated circuit composed of a plurality of semiconductor elements on the oxide layer,
The adhesive is removed by etching a part of the element forming layer,
A second substrate is attached to the element formation layer via a first adhesive,
A method for manufacturing a semiconductor device, wherein the second substrate and the element formation layer are separated from the first substrate by physical means. Forming a metal layer on the first substrate;
Forming an adhesive on a part of the metal layer,
Forming an oxide layer over the metal layer and the adhesive;
Forming an element formation layer including an integrated circuit composed of a plurality of semiconductor elements on the oxide layer,
The adhesive is removed by etching a part of the element forming layer,
A second substrate is attached to the element formation layer via a first adhesive,
Separating the second substrate and the element formation layer from the first substrate by physical means;
Affixing the second substrate and the element formation layer on a third substrate via a second adhesive;
A method for manufacturing a semiconductor device, comprising removing the second substrate from the element formation layer. In any one of claims 11 to 14,
A method for manufacturing a semiconductor device, comprising using any one of tungsten, molybdenum, technetium, rhenium, ruthenium, osmium, rhodium, iridium, palladium, platinum, silver, and gold as the metal layer. In any one of claims 11 to 15,
The method for manufacturing a semiconductor device, wherein the element formation layer includes a heat treatment step at 400 ° C. or higher, preferably 600 ° C. or higher as part of the manufacturing process. In any one of claims 11 to 16,
The method for manufacturing a semiconductor device, wherein the integrated circuit is formed at a position that does not overlap with the adhesive. In any one of claims 11 to 17,
A method for manufacturing a semiconductor device, wherein a material that chemically reacts with a metal included in the metal layer is used as the adhesive. In any one of claims 11 to 18,
A method for manufacturing a semiconductor device, wherein any one of silicon, germanium, carbon, boron, magnesium, aluminum, titanium, tantalum, iron, cobalt, nickel, and manganese is used as the adhesive. 20. The method for manufacturing a semiconductor device according to claim 11, wherein the substrate is made of plastic. Having an adhesive layer on the substrate,
A first insulating film on the adhesive layer,
The first insulating film is bonded to the substrate via at least the bonding layer,
At least one thin film transistor is on the first insulating film;
A second insulating film is on the thin film transistor,
The first insulating film and the second insulating film are removed, and an opening for exposing the adhesive layer is provided;
A semiconductor device having a third insulating film which covers a second insulating film and fills the opening. Having an adhesive layer on the substrate,
A first insulating film on the adhesive layer,
The first insulating film is bonded to the substrate via at least an adhesive layer,
An integrated circuit including at least a plurality of thin film transistors is on the first insulating film;
A second insulating film is on the integrated circuit;
The first insulating film and the second insulating film are removed, and an opening for exposing the adhesive layer is provided;
A semiconductor device having a third insulating film which covers a second insulating film and fills the opening. 23. The semiconductor device according to claim 21, wherein the substrate is made of plastic. 24. The semiconductor device according to claim 21, wherein the adhesive layer is a photo-setting type or a thermo-setting type. 25. The semiconductor device according to claim 21, wherein the third insulating film uses any one of silicon oxide, nitrogen oxide, acrylic, polyimide, and polyamide.

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