JP2004282049A - Compound semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an HBT having a large current amplification factor and a small Ic drift dependency.
SOLUTION: A V / III ratio is set in a range of 3.3 to 40, and a p-type GaAs layer is subjected to MOCVD vapor deposition using C as a dopant to form an HBT base layer 43 having good thermal stability. As a result, there is no bonding mode C2-H between C and H. Thereafter, H taken in the base layer 43 by the heat treatment is removed, thereby obtaining an HBT having a large current amplification factor β and a small Ic drift dependence.
[Selection] Fig. 6

Description

  The present invention relates to a heterojunction bipolar transistor (HBT) device, a compound semiconductor device for an HBT, and a method for manufacturing the same.

  The HBT is a bipolar transistor in which the emitter-base junction is a heterojunction using a substance having a larger band gap than the base layer for the emitter layer in order to increase the emitter injection efficiency.

For example, in the case of a GaAs-based HBT, an n ⁺ -GaAs layer (sub-collector layer) and an n-GaAs layer (collector layer) are generally formed on a semi-insulating GaAs substrate by using a metalorganic pyrolysis method (MOCVD method). , A p-GaAs layer (base layer), an n-InGaP layer (emitter layer), and an n-GaAs layer (sub-emitter layer) are successively crystal-grown to form a heterojunction pn junction as an emitter-base junction. The thin film crystal wafer having the above-described layer structure is formed, and the HBT is manufactured using the thin film crystal wafer.

FIG. 7 is a diagram schematically showing the structure of a conventional general GaAs-based HBT. The HBT 100 includes a sub-collector layer 102 composed of an n ⁺ -GaAs layer, a collector layer 103 composed of an n-GaAs layer, a base layer 104 composed of a p-GaAs layer, and an n-InGaP layer on a semi-insulating GaAs substrate 101. An emitter layer 105, a sub-emitter layer 106 composed of an n ⁺ -GaAs layer, and an emitter contact layer 107 composed of an n ⁺ -InGaAs layer are formed in this order as a semiconductor thin-film crystal layer using an appropriate vapor deposition method such as MOCVD. The collector electrode 108 is formed on the sub-collector layer 102, the base electrode 109 is formed on the base layer 104, and the emitter electrode 110 is formed on the emitter contact layer 107.

  In the HBT thus configured, the current amplification factor β is represented by β = Ic / Ib = (In−Ir) / (Ip + Is + Ir). Here, In is an electron injection current from the emitter to the base, Ip is a hole injection current from the base to the emitter, Is is an emitter / base interface recombination current, and Ir is a recombination current in the base.

Therefore, from the above equation, the magnitude of the current amplification factor β is affected by the recombination current Ir in the base, but the recombination current in the base is sensitive to the crystallinity of the base layer, and In order to obtain excellent transistor characteristics, it is necessary to improve the crystallinity of the base layer.
JP-A-3-110829

By the way, when a semiconductor wafer for manufacturing an HBT having a layer structure as shown in FIG. 7 is manufactured, when a p-GaAs thin film layer serving as a base layer is vapor-phase grown by MOCVD, trimethylgallium as a gallium source is used. It is common practice to use carbon (C) contained in (TMG) as a p-type dopant. For example, when the V / III ratio is about 20 to 150, the incorporation of C into the thin film layer is unsatisfactory. Therefore, there is known a method of carrying out at a V / III ratio of 2.5 or less at which the incorporation of C rapidly increases. (Patent Document 1). When the p-GaAs thin film crystal layer is grown in a gas phase in a MOCVD reactor in this manner, C used as a dopant is combined with hydrogen (H) contained in the raw material, resulting in 1-2 × 10 ¹⁹ cm ^{− Since three} kinds of H are taken into the crystal, the carriers in the base layer are inactivated, which causes a problem that the current amplification characteristics of the HBT are affected.

  That is, if a large amount of C as a P-type dopant is contained in the base layer in a state of being combined with H, the current amplification factor drifts due to the collector current during operation as an HBT element. It has been pointed out that the above-mentioned initial fluctuation of the transistor characteristics occurs or a problem occurs in long-term reliability.

  In order to solve these problems, it is considered that a heat treatment is performed after the growth of the p-GaAs layer, thereby breaking the bond between C and H and reducing the H concentration in the p-GaAs layer. When applied to the above-mentioned known method, there arises a problem that the current amplification factor is also lowered at the same time.

  An object of the present invention is to provide a compound semiconductor device and a method for manufacturing the same, which can solve the above-mentioned problems in the prior art.

  In order to solve the above problem, in the present invention, when a p-GaAs layer constituting a base layer of an HBT is vapor-phase grown, a V / III ratio, which is a growth condition thereof, is in a range of 3.3 to 40, and The p-GaAs layer is grown in vapor phase by supplying C as a dopant as halogenated methane. Further, the compound semiconductor wafer thus obtained has a feature that almost no peak of the bonding mode C2-H of H and C is detected in the infrared absorption measurement at room temperature.

  Here, the V / III ratio is a supply ratio of the group 5 raw material and the group 3 raw material during the growth of the group 3-5 compound semiconductor crystal. Generally, in the metal organic chemical vapor deposition method, a raw material is supplied in a gas state from a gas cylinder or a bubbler. The amount of gas supplied from the gas cylinder is controlled by a flow rate control device such as a mass flow controller installed in the supply line, and the (gas concentration in the cylinder) × (gas flow rate) is the actual flow rate of the raw material. The amount of gas supplied from the bubbler is controlled by a flow control device such as a mass flow controller installed in the carrier gas supply line that flows through the bubbler. (Carrier gas flow rate) x (vapor pressure of raw material in bubbler) / (pressure of internal bubbler) Is the actual flow rate. The actual flow rate of the raw material supplied by these methods, which is the ratio of the supply amount of the Group 5 raw material to the Group 3 raw material, is generally called the V / III ratio. The term V / III ratio is also used herein according to the above definition.

  As described above, when the p-GaAs layer is vapor-phase grown with the V / III ratio in the range of 3.3 to 40 and under the supply of halogenated methane, the thermal stability of the p-GaAs layer is improved. be able to. That is, when the p-GaAs layer is vapor-phase grown as described above, after the growth, the P-GaAs layer is subjected to a heat treatment to cut C-H bonds existing in the crystal, thereby reducing the H concentration in the crystal. Even if this is done, it is possible to suppress a decrease in the current amplification factor due to this. The V / III ratio is preferably between 5 and 35, more preferably between 10 and 30, even more preferably between 10 and 25.

  According to the first aspect of the present invention, there is provided a compound semiconductor including a heterojunction bipolar transistor in which a subcollector layer, a collector layer, a base layer, and an emitter layer are formed on a compound semiconductor substrate in this order as a thin film crystal layer by vapor phase growth. In the device, the front base layer is a p-type compound semiconductor thin film containing C as a dopant, and a peak of a bonding mode C2-H between H and C is not detected in infrared absorption measurement at room temperature. A device is proposed.

  According to a second aspect of the present invention, there is provided the compound semiconductor device according to the first aspect, wherein the base layer includes at least one of Ga, Al, and In and includes As as a group V element.

  According to a third aspect of the present invention, there is provided the compound semiconductor device according to the first aspect, wherein the vapor phase growth is a vapor phase growth by MOCVD.

  According to the invention, a compound semiconductor wafer including a heterojunction bipolar transistor structure in which a subcollector layer, a collector layer, a base layer, and an emitter layer are formed on a compound semiconductor substrate in this order as a thin-film crystal layer. A method of manufacturing a compound semiconductor wafer, characterized in that the front base layer has a V / III ratio in the range of 3.3 to 40 and is vapor grown by MOCVD under the supply of halogenated methane. Is done.

  According to a fifth aspect of the present invention, there is provided a method of manufacturing a compound semiconductor wafer according to the fourth aspect, wherein the base layer includes at least one of Ga, Al, and In and includes As as a group V element. You.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a compound semiconductor wafer according to the fourth or fifth aspect, wherein the halogenated methane is CBrCl ₃ .

  According to the seventh aspect of the present invention, the compound according to the fourth, fifth or sixth aspect, further comprising, after growing the base layer, a heat treatment at a temperature of 600 to 700 ° C. and in an atmosphere containing no arsine. A method for manufacturing a semiconductor wafer is proposed.

  According to the invention of claim 8, a p-type compound semiconductor thin film grown by the MOCVD method so as to contain at least one of Ga, Al, and In, contain As as a group V element, and contain C as a dopant. There is proposed a compound semiconductor thin film characterized in that no peak of the bonding mode C2-H between H and C is detected in infrared absorption measurement at room temperature.

  According to the ninth aspect of the present invention, there is provided a hetero-bipolar transistor element including the compound semiconductor thin film of the eighth aspect as a base layer.

  According to the tenth aspect of the present invention, there is provided a method for confirming the quality of a compound semiconductor wafer having a compound semiconductor layer containing C as a dopant on a compound semiconductor substrate, wherein a bonding mode C2-H between H and C in the wafer is determined. There has been proposed a method for confirming the quality of a compound semiconductor wafer characterized by confirming the quality by measuring by infrared absorption.

  According to the eleventh aspect of the present invention, after a compound semiconductor wafer having a compound semiconductor layer containing C as a dopant on a compound semiconductor substrate is manufactured by a vapor phase growth method, a bonding mode of H and C in the wafer is C2- There is proposed a method for manufacturing a compound semiconductor wafer, comprising a step of measuring H by infrared absorption and confirming the quality.

  According to the invention of claim 12, in the invention of claim 10 or 11, the compound semiconductor wafer has a sub-collector layer, a collector layer, a base layer containing C as a dopant and an emitter layer on the compound semiconductor substrate. A method is proposed that includes a hetero-coupled bipolar transistor structure formed in sequence.

  According to the invention of claim 13, in the invention of claim 10, 11, or 12, the compound semiconductor layer containing C as a dopant contains at least one of Ga, Al, and In, and contains As as a group V element. A method is proposed.

  According to the present invention, in a p-type compound semiconductor thin film using C as a dopant, thermal stability is obtained by preventing C2-H from being generated in a bonding configuration between C and H. Can be. As a result, the amount of H in the crystal can be easily reduced by the heat treatment.

  Therefore, by using this p-type compound semiconductor thin film as the base layer of the HBT, it is possible to reduce the dependence of the current gain β on the Ic drift amount while maintaining the current gain, thereby realizing a high-performance HBT element. it can.

  In addition, when manufacturing a compound semiconductor wafer having an HBT structure, the V / III ratio, which is one of the growth conditions, is set within a required range in a growth step of a compound semiconductor thin film layer serving as a base layer, so that high performance can be easily achieved. Since a compound semiconductor wafer suitable for HBT production can be manufactured, a low-cost, high-performance HBT element can be realized.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a layer structure diagram schematically showing an example of a thin film crystal wafer for HBT manufactured by the method of the present invention. This thin-film crystal wafer is a compound semiconductor wafer used for manufacturing a GaAs-based HBT. An example of an embodiment in which the semiconductor wafer having the layer structure shown in FIG. 1 is manufactured by the method of the present invention will be described. Therefore, it is not intended that the method of the present invention be limited only to the manufacture of the compound semiconductor wafer having the structure shown in FIG.

  The structure of the semiconductor wafer 1 shown in FIG. 1 is as follows. The semiconductor wafer 1 has a structure in which a plurality of semiconductor thin film crystal growth layers are successively stacked on a GaAs substrate 2 which is a semi-insulating GaAs compound semiconductor crystal by MOCVD. The GaAs substrate 2 is composed of a semi-insulating GaAs (001) layer, and a buffer layer 3 composed of an i-GaAs layer is formed on the GaAs substrate 2.

Next, the configuration of the HBT functional layer 4 formed on the buffer layer 3 will be described. In the HBT functional layer 4, an n ⁺ -GaAs layer serving as a sub-collector layer 41 and an n ⁻ -GaAs layer serving as a collector layer 42 are sequentially formed to a predetermined thickness as a semiconductor epitaxial growth crystal layer on the buffer layer 3. ing. A p ⁺ -GaAs layer serving as a base layer 43 is also formed as a semiconductor epitaxial growth crystal layer on the collector layer 42, and an n-InGaP layer serving as an emitter layer 44 is formed on the base layer 43. I have. On the emitter layer 44, an n ^-- GaAs layer is formed as a sub-emitter layer 45, and n ⁺ -GaAs layers and n ⁺ -InGaAs layers are formed as emitter contact layers 46 and 47.

  Here, the base layer 43 is formed as a compound semiconductor thin film layer containing at least one of Ga, Al, and In, containing As as a group V element, and containing carbon (C) as a raw material of a p-type dopant. . As a raw material of the p-type dopant, for example, halogenated methane described below is usually used.

  A method for forming each of the above-described layers as an epitaxially grown semiconductor thin film crystal layer by MOCVD will be described in detail.

  FIG. 2 schematically shows a main part of a vapor growth semiconductor manufacturing apparatus 10 used for manufacturing the semiconductor wafer 1 shown in FIG. 1 by the MOCVD method. The vapor phase growth semiconductor manufacturing apparatus 10 includes a reactor 12 to which a raw material gas from a raw material supply system (not shown) is supplied via a raw material supply line 11, and the GaAs substrate 2 is placed in the reactor 12 and heated. Susceptor 13 is provided.

  In the present embodiment, the susceptor 13 is a polygonal column, and a plurality of GaAs substrates 2 are attached to the surface of the susceptor 13. The susceptor 13 has a known configuration that can be rotated by the rotating device 14. Reference numeral 15 denotes a coil for high-frequency induction heating of the susceptor 13. The GaAs substrate 2 can be heated to a required growth temperature by supplying a heating current from the heating power supply 16 to the coil 15. By this heating, the source gas supplied into the buffer layer 3 via the source supply line 11 is thermally decomposed on the GaAs substrate 2 so that a desired semiconductor thin film crystal can be grown on the GaAs substrate 2 in vapor phase. It has become. The used gas is discharged to the outside from the exhaust port 12A and sent to the exhaust gas treatment device.

  After the GaAs substrate 2 is mounted on the susceptor 13 in the reactor 12, hydrogen is used as a carrier gas, arsine and trimethylgallium (TMG) are used as raw materials, and GaAs is grown to about 500 nm as a buffer layer 3 at 650 ° C. Thereafter, the sub-collector layer 41 and the collector layer 42 are grown on the buffer layer 3 at a growth temperature of 620 ° C.

Then, on the collector layer 42, trimethylgallium (TMG) is used as a Group ₃ source material, arsine (AsH ₃ ) is used as a Group 5 source material, CBrCl ₃ is used as a p-type dopant source material, and 620 ° C. The base layer 43 is grown at a growth temperature. By controlling the flow rate of CBrCl ₃ during the growth of the base layer 43, the carrier concentration of the base layer 43 can be adjusted. For this carrier concentration adjustment, another halogenated methane material may be used.

  Here, in order to improve the thermal stability of the base layer 43, the V / III ratio is set in the range of 3.3 to 40, and the base layer 43 is set to a range of 3.3 to 40. Grow.

  The reason is as follows. There are two types of bonding between C and H generated in the p-GaAs layer, namely, C-H and C2-H, and the p-GaAs layer has a V / III ratio of 3.3 to 40. Is grown, the bond of C—H becomes dominant, and the heat treatment after the growth facilitates the breaking of the bond between C and H, resulting in a property having excellent thermal stability. On the other hand, when the V / III ratio is less than 3.3, the bond form of C2-H increases as compared to the bond form of CH, and the base on which two types of CH bond and C2-H bond are formed. It will be present in the crystals of layer 43. As a result, even if a heat treatment is performed after the p-GaAs layer is grown as the base layer 43, the bond of C2-H is not easily broken, resulting in impairing the thermal stability.

  After the base layer 43 is thus grown, the emitter layer 44 and the sub-emitter layer 45 are grown at a growth temperature of 620 ° C. on the base layer 43, and the emitter contact layer 46 and the sub-emitter layer 45 are grown on the sub-emitter layer 45. 47 is formed.

  In the semiconductor wafer 1, when the base layer 43 constituting the HBT is vapor-phase grown by MOCVD, as described above, the V / III ratio is set in the range of 3.3 to 40, and halogenated methane is supplied. Because of the growth, the thermal stability of the base layer 43 becomes extremely good. Therefore, if heat treatment is performed as described later, the bond between C and H is easily cut, and the H concentration in the base layer 43 decreases, thereby reducing the current amplification factor β of the HBT. The Ic drift of the current amplification factor β of the HBT can be reduced as compared with the conventional case, and a highly stable HBT can be obtained.

  In the above embodiment, TMG, that is, Ga is used as the group 3 raw material, but Al and In can also be used. Although Ga, Al, and In may be used alone, some of them may be used in combination. In addition, the base layer 43 may be grown by using an appropriate group V material including As as well as As group V material.

Since CBrCl ₃ is used as a dopant material and carbon (C) is doped to make the base layer 43 p-type, the flow rate of CBrCl ₃ during the growth of the base layer 43 is appropriately adjusted so that the carbon (C ), The carrier concentration of the base layer 43 can be adjusted independently of the growth conditions.

When the V / III ratio is increased during the growth of the base layer 43, the amount of C taken into the crystal from C-containing TMG generally decreases, so that the carrier concentration decreases. For this reason, it is necessary to supply a C dopant from the outside. However, when a CBrCl ₃ raw material is used, a carrier concentration of about 4 × 10 ¹⁹ cm ⁻³ can be sufficiently controlled due to a high vapor pressure.

The control of the carrier concentration in the base layer 43 can be performed in the same manner by adjusting the flow rate of CBrCl _{3 or} by flowing halogenated methane during growth and controlling the flow rate. As the halogenated methane, other than the above, for example, CBr ₄ , CBr ₃ Cl, CBr ₂ Cl ₂ , CCl _{4 and the} like can be used.

  In this manner, if the semiconductor wafer 1 having the layer configuration shown in FIG. 1 is manufactured and an HBT is manufactured using the semiconductor wafer 1, the thermal stability of the base layer 43 is improved. After that, even if heat treatment is performed on the base layer 43 at a temperature of 600 ° C. to 700 ° C. to easily cut the bond between C and H and reduce the H concentration in the base layer 43, the current is reduced. It does not lower the amplification rate. As a result, the Ic drift characteristic of the current gain β can be significantly improved without lowering the current gain. Note that this heat treatment is preferably performed in an atmosphere containing no arsine.

A semiconductor thin film having a structure in which a 1 μm-thick p-GaAs layer was sandwiched between AlGaAs layers was manufactured. The p-GaAs layer is formed on the AlGaAs layer by vapor phase growth using MOCVD under a growth condition of a V / III ratio of 25, using trimethylgallium (TMG) as a Group 3 raw material, and using arsine (AsH ₃ ) as a Group 5 raw material. CBrCl ₃ was used as a p-type dopant and grown at a growth temperature of 620 ° C. After growing the sample thus manufactured, it was heat-treated at 500 ° C. to 670 ° C. for 5 minutes, and the sample was subjected to PL measurement at room temperature.

(Comparative Example 1)
Also, as Comparative Example 1, a sample was grown under the same growth conditions as described above except that the p-GaAs layer was grown under the V / III ratio of 0.7, and this comparative sample was grown. Thereafter, annealing was performed at a temperature of 500 ° C., 550 ° C., 600 ° C., 650 ° C., 670 ° C., or the like. The PL intensity of the comparative sample thus obtained was also measured.

The results of these measurements were as follows.
Example 1
(V / III ratio = 25)
Annealing temperature (° C) PL strength (AU)
Asglone 100
550 ° C 107
600 ° C 112
650 ° C 102
670 ° C 89
Comparative Example 1
(V / III ratio = 0.7)
Annealing temperature (° C) PL strength (AU)
Asglone 100
500 ° C 102
550 ° C 98
600 ° C 46
650 ° C 15
670 ℃ 9

  FIG. 3 is a graph showing these measurement results. Comparing the case where the V / III ratio is 25 and the case where the V / III ratio is 0.7, when the V / III ratio is 25, the PL strength does not change even after the heat treatment, and the crystallinity does not deteriorate, that is, the thermal stability is good. You can see that. It can be seen that when the V / III ratio is 0.7, the PL strength is reduced by heat treatment at 600 ° C. or higher, and the crystallinity is deteriorated.

  In addition, room temperature infrared absorption measurement was performed on the samples of Example 1 and Comparative Example 1 described above. This measurement was performed on each of an as-grown sample and a sample subjected to a heat treatment at 600 ° C. for 5 minutes. The measurement results are shown in FIG. 4 and FIG. The following can be seen from these measurement results.

  Focusing on the bond between C and H in the as-grown sample, when the V / III ratio is 25, only the CH bond is detected, and the C2-H bond is not detected. On the other hand, when the V / III ratio was 0.7, a C2-H bond was observed in addition to the C-H bond.

  When each sample is heat-treated at 600 ° C. for 5 minutes, the peak intensity due to the C—H bond decreases in both cases of the V / III ratio of 25 and 0.7, but the V / III ratio is reduced to 0.1. In the case of 7, the peak intensity of the C2-H bond does not decrease even by the heat treatment. From this, it was found that the C2-H bond was difficult to be cut even by heat treatment. From the above, when the V / III ratio is 0.7, H tends to remain in the crystal even when the as-grown sample is heat-treated. Therefore, regarding the thermal stability, the V / III ratio is set to 25 and p-GaAs is used. It can be said that when the layer is grown, the thermal stability is better than when the V / III ratio is 0.7.

A compound semiconductor wafer having the layer structure shown in FIG. 1 was manufactured under the conditions described in the embodiment, and an HBT element was manufactured as follows using the semiconductor wafer obtained thereby. The emitter size is 100 μm × 100 μm. Here, the collector current / base current when the collector current is 1 kA / cm ² is defined as a current amplification factor β. The base layer 43 was subjected to MOCVD vapor-phase growth at a V / III ratio of 25, followed by heat treatment at 670 ° C. for 0 to 10 minutes.

  The HBT manufactured in this manner was measured to examine the relationship between the Ic drift (%) and the current amplification factor β.

  FIG. 6 is a graph showing the measurement results. FIG. 6 shows the dependence of the fluctuation rate Δβ of the current amplification rate β on the Ic drift amount. Δβ is standardized by β when no annealing is performed, and the Ic drift amount is defined by Ic drift = (Icf−Ici) / Ic × 100 (Ici: initial collector voltage, Icf: collector Current saturation value). It is known that this characteristic has a correlation with the amount of H in the base layer, and an Ic drift amount within 10% is desired in device operation. According to the graph shown in FIG. 6, in the case of Example 2 manufactured with the V / III ratio set to 25, the dependence of the current amplification factor β on the Ic drift amount is extremely small.

(Comparative Example 2)
An HBT was manufactured and measured in the same manner as in Example 2 except that the base layer was formed under the growth condition of a V / III ratio of 0.7. In Comparative Example 2, the heat treatment was performed at 670 ° C. and 620 ° C.

  The results of these measurements are shown graphically in FIG. From FIG. 6, in the case of Comparative Example 2 (V / III ratio = 0.7), the dependence of the current amplification factor β on the Ic drift amount is extremely large, and the characteristic is such that the current amplification factor β is reduced by as much as 50%. It can be seen that the transistor characteristics are extremely excellent.

FIG. 1 is a layer structure diagram schematically showing an example of a thin film crystal wafer for HBT manufactured by the method of the present invention. FIG. 2 is a diagram schematically showing a main part of a vapor growth semiconductor manufacturing apparatus used for manufacturing the semiconductor wafer shown in FIG. 1. 7 is a graph showing the measurement results of PL intensity for Example 1 and Comparative Example 1. 6 is a graph showing measurement results obtained by performing a room-temperature infrared absorption measurement on the sample of Example 1. 9 is a graph showing measurement results obtained by performing a room-temperature infrared absorption measurement on the sample of Comparative Example 1. 9 is a graph showing the Ic drift amount dependence of the current amplification factor β for Example 2 and Comparative Example 2. The figure which shows typically the layer structure of the conventional general GaAs type HBT.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 GaAs substrate 3 Buffer layer 4 HBT functional layer 10 Vapor growth semiconductor manufacturing apparatus 41 Subcollector layer 42 Collector layer 43 Base layer 44 Emitter layer 45 Subemitter layer 46, 47 Emitter contact layer

Claims (13)

In a compound semiconductor device including a heterojunction bipolar transistor in which a subcollector layer, a collector layer, a base layer, and an emitter layer are formed on a compound semiconductor substrate as a thin-film crystal layer by vapor-phase growth in this order,
A compound semiconductor device, wherein the front base layer is a p-type compound semiconductor thin film containing C as a dopant, and a peak of a bonding mode C2-H between H and C is not detected in infrared absorption measurement at room temperature.   2. The compound semiconductor device according to claim 1, wherein the base layer contains at least one of Ga, Al, and In, and contains As as a group V element.   2. The compound semiconductor device according to claim 1, wherein said vapor phase growth is vapor phase growth by MOCVD.   In a method of manufacturing a compound semiconductor wafer including a heterojunction bipolar transistor structure in which a subcollector layer, a collector layer, a base layer, and an emitter layer are formed on a compound semiconductor substrate in this order as a thin-film crystal layer, A method for producing a compound semiconductor wafer, wherein the compound has a III ratio in the range of 3.3 to 40 and is grown by MOCVD under the supply of halogenated methane.   The method of manufacturing a compound semiconductor wafer according to claim 4, wherein the base layer contains at least one of Ga, Al, and In and contains As as a Group 5 element. The method according to claim 4, wherein the halogenated methane is CBrCl ₃ .   7. The method of manufacturing a compound semiconductor wafer according to claim 4, further comprising a step of performing a heat treatment at a temperature of 600 to 700 [deg.] C. and in an atmosphere containing no arsine after growing the base layer.   A p-type compound semiconductor thin film containing at least one of Ga, Al, and In, containing As as a group V element, and containing C as a dopant by vapor phase growth using a MOCVD method. 3. The compound semiconductor thin film according to claim 1, wherein a peak of a bonding mode C2-H between H and C is not detected.   A hetero-bipolar transistor element comprising the compound semiconductor thin film according to claim 8 as a base layer.   A method for confirming the quality of a compound semiconductor wafer having a compound semiconductor layer containing C as a dopant on a compound semiconductor substrate, wherein a bonding mode C2-H between H and C in the wafer is measured by infrared absorption, and the quality is measured. A method for confirming the quality of a compound semiconductor wafer, comprising:   After manufacturing a compound semiconductor wafer having a compound semiconductor layer containing C as a dopant on a compound semiconductor substrate by a vapor phase growth method, a bonding mode C2-H between H and C in the wafer is measured by infrared absorption, A method for manufacturing a compound semiconductor wafer, comprising a step of checking the quality.   12. The compound semiconductor wafer includes a hetero-coupled bipolar transistor structure in which a sub-collector layer, a collector layer, a base layer containing C as a dopant, and an emitter layer are formed in this order on the compound semiconductor substrate. The described method.   13. The method according to claim 10, wherein the compound semiconductor layer containing C as a dopant contains at least one of Ga, Al, and In, and contains As as a Group 5 element.

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