JP2004281988A - Solid state inductor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a size smaller in a state of a large inductance value and to perform easy tuning by varying the inductance value by an IC circuit. <P>SOLUTION: A method comprises processes for: forming a bottom electrode 102; forming a colossal magnetoresistance (CMR) thin film 104 overlying the bottom electrode 102; forming a top electrode 106 overlying the CMR thin film 104; applying electrical field treatment to the CMR thin film 104 in a range of 0.4 to 1 megavolts per centimeter (MV/cm) with a pulse width in a range of 100 nanoseconds (ns) to 1 millisecond (ms); converting the CMR thin film 104 into a CMR thin film inductor in response to the electrical field treatment; applying a bias voltage between the top electrode 106 and bottom electrode 102; and creating inductance between the top electrode 106 and the bottom electrode 102 in response to the applied bias voltage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid state inductor and a method for manufacturing the same, and more specifically, to an inductor such as a solid state inductor for an analog integrated circuit (IC) and a method for manufacturing the same.
[0002]
[Prior art]
Conventional solid-state inductors (IC-integrated solid-state inductors are referred to as IC-integrated inductors) are formed from metal lines, are designed in a spiral shape, and are stacked on a thick layer of insulator on a silicon substrate. Since the inductance value of the inductor thus formed is very low, the silicon area required for forming the actual inductor is large. The large size inductor not only uses very large amounts of expensive IC area, but also has parasitic reactances and unintended interaction with elements adjacent to, overlaid on, or below the inductor. It generates inductance.
[0003]
Further, the IC integrated inductor is a passive element. That is, once formed in an IC, the conventional inductor cannot change its inductance value. Therefore, inductors cannot be used for frequency tuning. Inductors for frequency tuning are desired in the manufacture of various circuits such as filters, antennas, and oscillators.
[0004]
[Problems to be solved by the invention]
In the above-mentioned conventional IC integrated inductor, it is difficult to have a larger inductance value and to reduce the size. Also, by changing the inductance value of the IC integrated inductor, the inductor cannot be used for frequency tuning.
[0005]
An object of the present invention is to solve the above-mentioned conventional problems and to provide a solid-state inductor that can be reduced in size with a large inductance value and a method of manufacturing the same.
[0006]
Another object of the present invention is to solve the above-mentioned conventional problems and to provide a solid-state inductor that can be easily tuned by changing an inductance value in an IC circuit, and a method of manufacturing the same.
[0007]
[Means for Solving the Problems]
The method for manufacturing a solid state inductor according to the present invention includes a step of forming a bottom electrode, a step of forming a super giant magnetoresistive (CMR) thin film on the bottom electrode, Forming an upper electrode by superimposing on the substrate, and performing an electric field treatment on the giant magnetoresistive (CMR) thin film. And a step of converting to a thin film inductor, whereby the above object is achieved.
[0008]
Preferably, in the method for manufacturing a solid state inductor of the present invention, a bias voltage is applied between the upper electrode and the bottom electrode, and an inductance is created between the upper electrode and the bottom electrode according to the applied bias voltage. Further comprising the step of:
[0009]
Still preferably, in a method for manufacturing a solid-state inductor according to the present invention, the method further includes a step of varying the applied bias voltage, and a step of varying the inductance in accordance with the variation of the applied bias voltage.
[0010]
Further, preferably, in the method of manufacturing a solid state inductor of the present invention, the step of forming a giant magnetoresistive (CMR) thin film overlying the bottom electrode includes: _0.3 Ca _0.7 MnO ₃ (PCMO), La _0.7 Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ (YCMO) and using a material selected from the group comprising high temperature superconductor (HTSC) materials.
[0011]
Further, preferably, in the method of manufacturing a solid state inductor of the present invention, the step of forming a super giant magnetoresistive (CMR) thin film overlying the bottom electrode includes forming a super giant magnetoresistive (CMR) thin film having a thickness of about 2000 mm. And b) forming a thin film.
[0012]
More preferably, in the method of manufacturing a solid state inductor of the present invention, the step of forming a giant magnetoresistive (CMR) thin film overlying the bottom electrode comprises spinning the first layer having a thickness of about 670 °. Coating, annealing the first layer at about 650 degrees Celsius for about 30 minutes, and spin coating a second layer of about 670 degrees thick over the first layer. Annealing the second layer at about 550 degrees Celsius for about 30 minutes; spin-coating a third layer of about 670 degrees thick over the second layer; Annealing the third layer at about 550 degrees Celsius for about 30 minutes.
[0013]
More preferably, in the method for manufacturing a solid state inductor of the present invention, the step of forming the bottom electrode includes Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and another noble metal. Forming the bottom electrode from a material selected from the group.
[0014]
More preferably, in the method for manufacturing a solid state inductor of the present invention, the step of forming the upper electrode includes Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and another noble metal. Forming the upper electrode from a material selected from the group.
[0015]
More preferably, in the method for manufacturing a solid-state inductor of the present invention, the step of performing an electric field treatment on the giant magnetoresistive (CMR) thin film includes a pulse width of 100 nanoseconds (ns) to 1 millisecond (ms). ) And applying an electric field in the range of 0.4 to 1 megavolt per centimeter (MV / cm).
[0016]
Still preferably, in a method for manufacturing a solid state inductor according to the present invention, a step of applying a bias voltage between the top electrode and the bottom electrode includes the step of: applying a bias voltage in a range of 0.5 to 5 volts DC. DC -0.5 to -5 volts.
[0017]
Still preferably, in a method of manufacturing a solid state inductor according to the present invention, the step of forming an inductance between the top electrode and the bottom electrode includes an inductance in a range from a value greater than 0.01 microhenry (μH) to a value less than 1 μH. Including the step of creating
[0018]
Further preferably, in the method for manufacturing a solid state inductor of the present invention, the step of changing the inductance between the top electrode and the bottom electrode in accordance with the change in the applied bias voltage includes changing DC + 1 volt and DC-1 volt. Creating a maximum inductance with a bias voltage selected from the group including.
[0019]
More preferably, in the method for manufacturing a solid state inductor of the present invention, the step of performing an electric field treatment on the giant magnetoresistive (CMR) thin film includes simultaneously applying an electric field while annealing the giant magnetoresistive (CMR) thin film. Including the step of applying.
[0020]
Still preferably, in a method for manufacturing a solid-state inductor according to the present invention, a step of forming a bottom electrode, a step of forming a giant magnetoresistive (CMR) thin film overlying the bottom electrode, Forming an upper electrode overlying the resistive (CMR) thin film, and a pulse width of 100 nanoseconds (ns) to 1 millisecond (ms) for the giant magnetoresistive (CMR) thin film. And performs an electric field treatment in the range of 0.4 to 1 megavolt per centimeter (MV / cm), and converts the giant magnetoresistive (CMR) thin film to a giant magnetoresistive (CMR) thin film inductor according to the electric field treatment. And applying a bias voltage between the top electrode and the bottom electrode, and creating an inductance between the top electrode and the bottom electrode according to the applied bias voltage. Indicia varying the pressure bias voltage, which comprises the step of varying the inductance in accordance with a variation in the bias voltage, the object can be achieved.
[0021]
The solid state inductor of the present invention comprises a bottom electrode, an electric field treated giant magnetoresistive (CMR) thin film overlaid on the bottom electrode, and a top electrode overlaid on the electric field treated giant magnetoresistive (CMR) thin film. And an electrode, whereby the above object is achieved.
[0022]
Preferably, the solid-state inductor according to the present invention further includes a voltage applying means for applying a bias voltage between the upper electrode and the lower electrode, wherein the upper electrode and the lower electrode correspond to the applied bias voltage. An inductance is created between the electrodes.
[0023]
Still preferably, in a solid state inductor according to the present invention, the voltage application unit varies the applied bias voltage, and varies the inductance between the upper electrode and the bottom electrode according to the variation of the applied bias voltage.
[0024]
Further, preferably, the giant magnetoresistive (CMR) thin film in the solid state inductor of the present invention is Pr Pr _0.3 Ca _0.7 MnO ₃ (PCMO), La _0.7 Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ (YCMO) and / or high temperature superconductor (HTSC) material.
[0025]
More preferably, the thickness of the giant magnetoresistive (CMR) thin film in the solid state inductor of the present invention is about 2000 °.
[0026]
More preferably, the bottom electrode in the solid state inductor of the present invention comprises a material selected from the group comprising Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals.
[0027]
More preferably, the upper electrode in the solid state inductor of the present invention is formed from a material selected from the group including Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. ing.
[0028]
Further, preferably, the electric field treated giant magnetoresistance (CMR) thin film in the solid state inductor of the present invention has a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms) and 0.4 to 1 MV /. It was exposed to an electric field in the range of cm.
[0029]
Still preferably, in a solid state inductor according to the present invention, the voltage applying means applies a bias voltage between the top electrode and the bottom electrode, and the bias voltage is a voltage in a range of 0.5 to 5 VDC and a DC voltage. And a voltage in the range of -0.5 to -5 volts.
[0030]
More preferably, the inductance value between the top electrode and the bottom electrode in the solid state inductor of the present invention is a value within a range from a value greater than 0.01 microhenry (μH) to a value less than 1 μH.
[0031]
Further, preferably, the inductance between the top electrode and the bottom electrode in the solid state inductor of the present invention is a maximum value corresponding to an applied bias voltage selected from a group including DC + 1 volt and DC-1 volt.
[0032]
With the above configuration, a relatively large inductance value, a very small chip area is required, and a conventional integrated circuit (a CMOS circuit manufactured on silicon or a compound semiconductor substrate or a bipolar circuit) Solid state inductor suitable for integration into a solid state inductor and a method for manufacturing the same. In addition, since the inductance value can be changed in the IC circuit, tuning can be easily performed.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a solid state inductor (hereinafter, simply referred to as an inductor) and a method of manufacturing the same according to the present invention will be described with reference to the drawings.
[0034]
FIG. 1 is a diagram schematically showing a schematic configuration of the inductor of the present invention.
[0035]
In FIG. 1, an inductor 100 has a bottom electrode 102, an electric field treated giant magnetoresistive (CMR) thin film 104 overlaid on the bottom electrode 102, and an upper electrode 106 overlaid on the CMR thin film 104. are doing.
[0036]
The CMR thin film 104 is made of Pr _0.3 Ca _0.7 MnO ₃ (PCMO), La _0.7 Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ (YCMO) or high temperature superconductor (HTSC) materials. Note that other equivalent materials may be used according to requirements. The thickness t1 of the CMR thin film 104 is about 2000 °.
[0037]
More specifically, the CMR thin film 104 has a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms) and a pulse width of 0.4 to 1 megavolt (MV / cm) per centimeter. Exposure to a range of electric fields. This is only an exemplary process. Other processing means may also be used, depending on the CMR material, the intervening material and the desired inductance value.
[0038]
The bottom electrode 102 of the inductor 100 is made of a material selected from a group of materials such as Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi or other noble metals. Note that other conductive materials well known in the IC manufacturing field may be used. Similarly, the upper electrode 106 is also typically made of a material selected from a group of materials including Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi or other noble metals. Is done.
[0039]
Further, a voltage applying means 112 for applying a bias voltage between the upper electrode 106 and the bottom electrode 102 of the inductor 100 is provided. Typically, the inductor 100 has part of a larger and more complex circuit, and the bias voltage from the voltage application means 112 and the ground zero potential relative to the bias voltage are shown in FIG. Not connected, for example, via a transistor circuit. The inductance of the inductor 100 or the inductance value L (114) is formed on the CMR thin film 104 between the upper electrode 106 and the bottom electrode 102 according to the applied bias voltage from the voltage applying means 112.
[0040]
In some aspects, the voltage application unit 112 can vary the bias voltage applied to the inductor 100. In response to the change in the applied bias voltage, the inductance value L (114) between the top electrode 106 and the bottom electrode 102 changes. Several practical bias voltage ranges have been developed as examples. In some aspects, the voltage applying means 112 applies a voltage between the top electrode 106 and the bottom electrode 102 in any range of 0.5 to 5 volts DC or -0.5 to -5 volts DC. In a specific circuit application example, an AC voltage may be used. In addition, other DC voltage ranges may be used for different CMR materials, CMR capacitances, and electric field processing.
[0041]
By using the above bias voltage values, the inductance 114 between the top electrode 106 and the bottom electrode 102 depends on the bias voltage, the CMR material, and the geometry (capacity, diameter 108, and thickness t1) of the CMR thin film 104. Thus, it can range from a value greater than 0.01 microhenry (μH) to a value less than 1 μH. Typically, the inductance value L (114) between the top electrode 106 and the bottom electrode 102 is a maximum value depending on the applied voltage of either +1 dc volts or -1 dc volts. However, the relationship between the maximum inductance value and the bias voltage also depends on the CMR material and the CMR geometry.
[0042]
FIG. 2 is a sectional view of a device structure when two inductors 100 of the present invention are applied to an actual IC integrated circuit.
[0043]
As shown in FIG. 2, the inductor 100 of the present invention is a columnar structure having two terminals. The inductor 100 is fabricated in a single via hole with the bottom electrode 102 on a pn junction or local interconnect metal line. Also, the inductor 100 may be integrated into the IC after the beginning of the process has been completed. In the device A200, the inductor 100 is integrated with the drain junction 202. In the device B204, another inductor 100 is integrated with the gate electrode 206. These inductor (s) 100 may be deposited on a semiconductor substrate using conventional deposition methods, such as, for example, spin coating, sputtering, and CVD processes. Also, the inductor 100 has a very high inductance that can vary more than two orders (two digits) by using bias voltage control. Tuning of any LC circuit of which the inductor 100 is a part may be accomplished by adjusting the bias voltage applied to the inductor 100.
[0044]
For example, the inductor 100 of the present invention can be manufactured using a giant magnetoresistive (CMR) thin film resistor manufactured using a spin coating process. The CMR material is, for example, PCMO (Pr _0.3 Ca _0.7 MnO ₃ ). The CMR thin film is coated three times on a platinum substrate until the total thickness is about 200 nm. The CMR thin film is annealed at 650 ° C. for 30 minutes after the first coating, and annealed at 550 ° C. for 30 minutes after the second and third coatings. The upper electrode 106 is platinum, but other metals, for example, Al, Cu, W, Ir, AlSi, or other noble metals may be used. It is determined that the impedance of the CMR thin film 104 immediately after or as manufactured has a resistance R by a resistance element and a capacitance C by a capacitance element.
[0045]
FIG. 3 is a diagram illustrating reactance of an exemplary CMR thin film before electric field treatment.
[0046]
All measurements in FIG. 3 are measurements of the resistance in series with the inductance. The measurement frequency is 1 MHz. The measured inductance value is negative, so it is capacitive.
[0047]
FIG. 3 also shows that the capacitance value and the resistance value of the CMR thin film are actually independent of the bias voltage value in a certain measurement value range.
[0048]
FIG. 4 is a diagram illustrating reactance of an exemplary CMR thin film after electric field treatment.
[0049]
As shown in FIG. 4, the impedance characteristic changes significantly after an electric field of 0.4 MV / cm to 1 MV / cm is applied to the CMR thin film 104 via the upper electrode 106 and the bottom electrode 102. The resistance of the CMR thin film 104 decreases from about 275 ohms to less than 20 ohms. The CMR thin film 104 has inductive properties according to a bias voltage of -5V to -0.5V or 0.5V to 5V. At bias voltages outside these ranges, the reactance of the CMR thin film 104 is capacitance. The maximum inductance is higher than 1 μH.
[0050]
The inductance value of the PCMO solid state inductor 100 can vary more than two orders (two digits) by changing the bias voltage applied to the device. Due to the nature of the material, giant magnetoresistive (CMR) and high temperature superconducting (HTSC) materials are expected to be practical in the manufacture of electrically tunable solid state inductors 100. Electrically tunable inductor 100 is suitable as a built-in element for filters and antennas of any integrated circuit.
[0051]
FIG. 5 is a flowchart showing one embodiment of a method for manufacturing the solid state inductor 100 of the present invention.
[0052]
As shown in FIG. 5, in the method of manufacturing inductor 100, numbered steps are continuously shown for clarity of description, but unless otherwise specified, the order is inferred from these numbers. Should not be. Some of these steps may be skipped, performed in parallel, and need not be performed in a strict sequential order.
[0053]
As shown in FIG. 5, in step 500, manufacturing of the solid state inductor 100 is started.
[0054]
In step 502, a bottom electrode 102 is formed.
[0055]
Step 504 forms a giant magnetoresistive (CMR) thin film 104 overlying the bottom electrode 102.
[0056]
Step 506 forms an upper electrode overlying the CMR thin film 104.
[0057]
In step 508, electric field processing is performed on the CMR thin film 104. Alternatively, in step 508, an electric field is applied simultaneously with annealing of the CMR thin film 104.
[0058]
At step 510, the CMR thin film 104 is converted to the CMR thin film inductor 100 in response to the electric field treatment.
[0059]
Here, a method for manufacturing the inductor 100 will be described in more detail. Some aspects include additional steps. In step 512 following step 510, a bias voltage is applied between the top electrode 106 and the bottom electrode 102.
[0060]
In step 514, an inductance is created between the top electrode 106 and the bottom electrode 102 in response to the applied bias voltage.
[0061]
In another aspect, step 516 varies the applied bias voltage.
[0062]
In step 518, the inductance changes in response to the change in the applied bias voltage.
[0063]
Next, returning to step 504, the step of forming the CMR thin film 104 overlaid on the bottom electrode 102 includes Pr _0.3 Ca _0.7 MnO ₃ (PCMO), La _0.7 Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ (YCMO) or using a material such as a high-temperature superconductor (HTSC) material. In some aspects, the CMR thin film 104 is formed to a thickness of about 2000 degrees, depending on the variation.
[0064]
In some aspects, forming the CMR thin film overlying the bottom electrode 102 in Step 504 includes the sub-steps of Steps 504a through 504f.
[0065]
First, in step 504a, a first layer having a thickness of about 670 ° is spin coated.
[0066]
Next, in step 504b, the first layer is annealed at a temperature of about 650 degrees Celsius for about 30 minutes.
[0067]
Further, in step 504c, a second layer of about 670 ° thickness overlying the first layer is spin coated.
[0068]
Further, in step 504d, the second layer is annealed at a temperature of about 550 degrees Celsius for about 30 minutes.
[0069]
Further, in step 504e, a third layer of about 670 ° thickness overlying the second layer is spin coated.
[0070]
Finally, in step 504f, the third layer is annealed at a temperature of about 550 degrees Celsius for about 30 minutes.
[0071]
In some aspects of the invention, forming the bottom electrode 502 of Step 502 comprises forming the bottom electrode from a material such as Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi or other noble metal. Is formed. Similarly, forming the upper electrode 106 in step 506 includes forming the upper electrode 106 from a material such as Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi or other noble metal. Process.
[0072]
In some aspects, the step of applying an electric field to the CMR thin film 104 in step 508 includes applying an electric field in the range of 0.4-1 megavolts per centimeter (MV / cm) with a pulse width of 100 ns to 1 ms. Including the step of applying.
[0073]
Also, in some aspects, the step of applying a bias voltage between the top electrode 106 and the bottom electrode 102 in Step 512 comprises applying a DC voltage between 0.5 and 5 volts between the top electrode 106 and the bottom electrode 102. Or applying a bias voltage of any DC voltage in the range of -0.5 to -5 volts. Also, the step of creating an inductance between the top electrode 106 and the bottom electrode 102 in step 514 includes creating an inductance ranging from a value greater than 0.01 microhenry (μH) to less than 1 μH.
[0074]
Also, in some aspects, varying the inductance between the top electrode 106 and the bottom electrode 102 in response to a variation in the applied bias voltage in Step 518 includes either about +1 volts DC or about −1 volts DC. Creating a maximum inductance at the bias voltage.
[0075]
As described above, according to the embodiment of the present invention, the step of forming the bottom electrode 102, the step of forming the super giant magnetoresistive (CMR) thin film 104 on the bottom electrode 102, and the step of forming And forming a top electrode 106 and applying a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms) to the CMR thin film 104 at 0.4 to 1 megavolt per centimeter (MV). / Cm), a step of converting the CMR thin film 104 into a CMR thin film inductor according to the electric field treatment, a step of applying a bias voltage between the top electrode 106 and the bottom electrode 102, Creating an inductance between the top electrode 106 and the bottom electrode 102 in response to the bias voltage. When the applied bias voltage changes, the inductance value also changes accordingly. Therefore, the size can be reduced in a state having a larger inductance value, and tuning can be easily performed by changing the inductance value in the IC circuit.
[0076]
It should be noted that the inductor 100 according to the present invention has not only these examples but also wider applications. Similarly, while an exemplary manufacturing process is shown, the solid state inductor may be manufactured using equivalent processing and materials. One of ordinary skill in the art will appreciate other variations and embodiments of the invention.
[0077]
【The invention's effect】
As described above, according to the present invention, the size can be further reduced in a state having a larger inductance value, and tuning can be easily performed by changing the inductance value in the IC circuit.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a schematic configuration of an inductor of the present invention.
FIG. 2 is a cross-sectional view of a device structure when two inductors of the present invention are applied to an actual IC integrated circuit.
FIG. 3 shows the reactance of an exemplary CMR film before electric field treatment.
FIG. 4 illustrates reactance of an exemplary CMR thin film after electric field treatment.
FIG. 5 is a flowchart showing one embodiment of a method for manufacturing an inductor of the present invention.
[Explanation of symbols]
100 inductor
102 bottom electrode
104 Electric field treated giant magnetoresistive (CMR) thin film
106 Upper electrode
112 Voltage application means

Claims (25)

Forming a bottom electrode;
Forming a giant magnetoresistive (CMR) thin film overlying the bottom electrode;
Forming an upper electrode overlying the giant magnetoresistive (CMR) thin film;
Performing an electric field treatment on the giant magnetoresistive (CMR) thin film, and converting the giant magnetoresistive (CMR) thin film into a giant magnetoresistive (CMR) thin film inductor in response to the electric field treatment. Manufacturing method of inductor. The method of claim 1, further comprising: applying a bias voltage between the top and bottom electrodes and creating an inductance between the top and bottom electrodes in response to the applied bias voltage. Method. Varying the applied bias voltage;
3. The method of manufacturing a solid state inductor according to claim 2, further comprising: changing the inductance according to the change in the applied bias voltage. The step of forming a giant magnetoresistive (CMR) thin film on the bottom electrode is performed by using Pr _0.3 Ca _0.7 MnO ₃ (PCMO), LaO _{. 3. The} method according to claim 1, further comprising using a material selected from the group including ₇ Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ (YCMO), and a high-temperature superconductor (HTSC) material. A method for manufacturing the solid state inductor according to the above. 3. The method of claim 1 or 2, wherein forming a giant magnetoresistive (CMR) thin film overlying the bottom electrode comprises forming a giant magnetoresistive (CMR) thin film having a thickness of about 2000 degrees. Manufacturing method of solid state inductor. Forming a giant magnetoresistive (CMR) thin film overlying the bottom electrode,
Spin coating a first layer about 670 ° thick;
Annealing the first layer at about 650 degrees Celsius for about 30 minutes;
Spin coating a second layer overlying the first layer and having a thickness of about 670 °;
Annealing the second layer at about 550 degrees Celsius for about 30 minutes;
Spin coating a third layer overlying the second layer and having a thickness of about 670 °;
Annealing the third layer at about 550 degrees Celsius for about 30 minutes. Forming the bottom electrode includes forming the bottom electrode from a material selected from the group including Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. A method for manufacturing the solid state inductor according to claim 2. The step of forming the upper electrode includes a step of forming the upper electrode from a material selected from the group including Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi, and other noble metals. A method for manufacturing the solid state inductor according to claim 1. The step of performing an electric field treatment on the giant magnetoresistive (CMR) thin film is performed at a pulse width in a range of 100 nanoseconds (ns) to 1 millisecond (ms) and 0.4 to 1 megavolt per centimeter (cm). The method for manufacturing a solid state inductor according to claim 1, further comprising a step of applying an electric field in a range of MV / cm). In the step of applying a bias voltage between the top electrode and the bottom electrode, the bias voltage is:
A voltage in the range of 0.5-5 VDC,
The method of claim 3, wherein the method is selected from the group consisting of: DC-0.5 to -5 volts. 3. The solid state of claim 2, wherein creating an inductance between the top electrode and the bottom electrode includes creating an inductance in a range from greater than 0.01 microhenry (μH) to less than 1 μH. Manufacturing method of inductor. Varying the inductance between the top and bottom electrodes in response to the variation in the applied bias voltage comprises creating a maximum inductance with a bias voltage selected from the group comprising DC + 1 volts and DC-1 volts. The method for manufacturing a solid state inductor according to claim 10, comprising a step. 2. The solid state inductor according to claim 1, wherein the step of performing an electric field treatment on the giant magnetoresistive (CMR) thin film includes simultaneously applying an electric field while annealing the giant magnetoresistive (CMR) thin film. Production method. Forming a bottom electrode;
Forming a giant magnetoresistive (CMR) thin film overlying the bottom electrode;
Forming an upper electrode overlying the giant magnetoresistive (CMR) thin film;
For the giant magnetoresistive (CMR) thin film, a pulse width of 0.4-1 megavolts per centimeter (MV / cm) within a range of 100 nanoseconds (ns) to 1 millisecond (ms). Performing a range of electric field treatments and converting the giant magnetoresistive (CMR) thin film into a giant magnetoresistive (CMR) thin film inductor in response to the electric field treatment;
Applying a bias voltage between the top electrode and the bottom electrode;
Creating an inductance between the top and bottom electrodes in response to the applied bias voltage;
Fluctuating the applied bias voltage, and fluctuating the inductance in accordance with the fluctuation of the bias voltage. A bottom electrode;
An electric field treated giant magnetoresistance (CMR) thin film overlaid on the bottom electrode;
A solid state inductor comprising an upper electrode overlying the electric field treated giant magnetoresistance (CMR) thin film. A solid state inductor further comprising voltage applying means for applying a bias voltage between the top electrode and the bottom electrode,
16. The solid state inductor according to claim 15, wherein an inductance is created between the top electrode and the bottom electrode according to the applied bias voltage. 17. The solid-state inductor according to claim 16, wherein the voltage application unit varies the applied bias voltage, and varies the inductance between the top electrode and the bottom electrode according to the variation of the applied bias voltage. The colossal magnetoresistance (CMR) film _{is, Pr 0.3 Ca 0.7 MnO 3 (} PCMO), La 0.7 Ca 0.3 MnO 3 (LCMO), Y 1-x Ca x MnO 3 (YCMO) The solid-state inductor according to any one of claims 15 to 17, comprising at least one of a material selected from the group consisting of a high-temperature superconductor (HTSC) material and a high-temperature superconductor (HTSC) material. 20. The solid state inductor of claim 17, wherein the giant magnetoresistive (CMR) thin film has a thickness of about 2000 degrees. 17. The solid state inductor according to claim 15 or 16, wherein the bottom electrode comprises a material selected from the group comprising Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. 17. The solid according to claim 15, wherein the upper electrode is formed of a material selected from a group including Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi, and other noble metals. State inductor. The electric field treated giant magnetoresistive (CMR) thin film has a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms) and is exposed to an electric field in the range of 0.4 to 1 MV / cm. 17. The solid state inductor according to 15 or 16. The voltage applying unit applies a bias voltage between the top electrode and the bottom electrode, and the bias voltage is
A voltage in the range of 0.5-5 VDC,
18. The solid state inductor of claim 17, wherein the solid state inductor is selected from the group comprising: -0.5 to -5 volts DC. 18. The solid-state inductor according to claim 17, wherein an inductance value between the top electrode and the bottom electrode ranges from a value greater than 0.01 microhenry (μH) to a value less than 1 μH. 24. The solid state inductor according to claim 23, wherein the inductance between the top electrode and the bottom electrode is a maximum value according to an applied bias voltage selected from a group including DC + 1 volt and DC-1 volt.

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