JP2004281960A

JP2004281960A - Ultra-high speed interface using intersymbol interference suppression resistor

Info

Publication number: JP2004281960A
Application number: JP2003074815A
Authority: JP
Inventors: Yutaka Uematsu; 裕植松; Hideki Osaka; 英樹大坂
Original assignee: Renesas Technology Corp
Current assignee: Renesas Technology Corp
Priority date: 2003-03-19
Filing date: 2003-03-19
Publication date: 2004-10-07

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ultra-high speed interface using an intersymbol interference suppression resistor capable of forming a signal transfer system for a high speed signal by shaping a drive waveform from a rectangular wave to a pre-emphasis waveform by utilizing a reflected waveform caused by impedance mismatching. <P>SOLUTION: Between an I/O circuit of an LSI consisting of a signal transfer master/slave and a substrate such as a mother board, or the like, a wiring (shaping wiring) having a value of an impedance Za (Rx<Za<Zo) which is greater than an output impedance Rx of a driver of the LSI and is smaller than an impedance Zo of a main line 2-1 of the substrate and a resistor (intersymbol interference suppression resistor) of Ra=Zo-Za are inserted between a shaping wiring 2-2 and the main line 2-1, thereby generating the reflected waves having a reverse polarity to a signal, and a drive wave is subjected to a pre-emphasis shaping by the reflected waves. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は情報処理装置においてプロセッサやメモリ等の半導体装置間（例えばＣＭＯＳ等により構成されたデジタル回路間又はその機能ブロック間）で高速に信号を転送するための技術に関する。
【０００２】
【従来の技術】
２つの抵抗終端された半導体装置が同一の信号線に接続されたシステムの双方向転送における基本方式を図２に示す。信号転送マスタ１０−１とスレーブ１０−２間のデータ転送を行う時、送端側及び受端側で反射が起こらないように両者の入出力インピーダンスをプリント基板２−１の特性インピーダンスに整合、あるいは送受端の入出力インピーダンスを必要に応じて適宜変更してデータ転送を行う技術である。これは信号転送マスタ１０−１とスレーブ１０−２間の１対１間の転送に適しており、すなわちメモリとメインプロセッサ間のデータ信号転送に適していた。
【０００３】
ところで、通常、半導体チップを実装するための半導体チップを実装する基板（以下、中間基板）内の信号線の特性インピーダンスは、プリント基板の特性インピーダンスに比べ低い値を取るが、中間基板配線の長さはミリメートルオーダーと短いため、１Ｇｂｐｓ以下程度の信号転送ではその配線特性インピーダンスとプリント基板のインピーダンスミスマッチは無視できるものであった。
【０００４】
しかし、近年の信号の高速化に伴い、この信号転送方式により転送される信号波形は有損失の信号配線での信号転送過程での誘電損失、表皮効果等に起因する立ち上がり／立ち下がり波形なまりの影響が問題となっていた。これを図３に示す。信号転送マスタ１０−１から有損失伝送線路２−１を通過して信号転送スレーブ１０−２に信号が転送される時、その波形は例えインピーダンスの整合が完全に取られていても、信号転送マスタで出力した矩形波が信号転送スレーブに到達すると角のなまった波形となってしまう。この波形なまりは、受端側で観測されるアイパターンにおいてアイ開口率の狭小化やジッタの増大、符号間干渉（ＩｎｔｅｒＳｙｍｂｏｌＩｎｔｅｒｆｅｒｅｎｃｅ：ＩＳＩ）といった問題を生じさせ、３Ｇｂｐｓ以上のデータ転送速度に対する電圧ノイズマージン、タイミングマージンに制限を与え信号の高速化に対して問題となっていた。これを解決するための従来技術として、送端側出力波形の立ち上がり／立ち下がり部の電圧振幅を一定時間増幅させる方法があった。このようなＩＳＩ低減に効果を持つ信号波形をプリエンファシス波形と呼ぶ。
【０００５】
特許文献１では、プリエンファシス波形整形として、デジタル信号をプリエンファシス伝送経由で送信するための出力バッファ回路を用いていた。これは、制御回路によって２つのインピーダンスを持つ出力回路を制御して出力波形をプリエンファシス波形にするものである。つまり、従来は、プリエンファシス波形整形を、送端側の回路で出力電圧や出力抵抗を時間的に変化させ信号振幅を調整することで実現していた。
【０００６】
【特許文献１】
特開２０００−６８８１６
【特許文献２】
特開平６−１４０２１５号公報
【０００７】
【発明が解決しようとする課題】
しかしながら、従来の技術による信号転送方式では３Ｇｂｐｓを超えるような系では以下の点が問題となる。
（１）中間基板配線とプリント基板配線の間の特性インピーダンスミスマッチによる反射の影響による符号間干渉が大きくなり、ジッタの増大、アイ開口率の狭小化の原因となる。その結果、信号の高速化が制限される。
（２）特許文献１のプリエンファシス波形整形手段は、回路による信号振幅調整手法であるため、主に送端側ＬＳＩに複雑な回路構成を必要とする。その結果、回路の大規模化による実装面積の増大やコストアップの問題が生じる。
【０００８】
【課題を解決するための手段】
前述の課題（１）と課題（２）を解決するために、本発明では中間基板配線とプリント基板配線の間に両配線の特性インピーダンス（Ｚｐｃｂ、Ｚｐｋｇ）の差の値を持つ抵抗Ｒ＝Ｚｐｃｂ−Ｚｐｋｇを挿入する。このとき、信号転送マスタおよび信号転送スレーブのドライバの出力インピーダンスＲｏｕｔを中間基板配線インピーダンスＺｐｋｇより小さく、レシーバの入力インピーダンスＲｉｎを中間基板配線インピーダンスＺｐｋｇとほぼ等しくする。
【０００９】
この結果、
（１）プリント基板からレシーバへ信号が転送するときは、プリント基板から中間基板、レシーバまでインピーダンスプロファイルがほぼ一定となる。その結果、プリント基板−中間基板間及び中間基板レシーバ間で反射がほとんど生じない。
（２）ドライバからプリント基板へ信号が転送するときは、ドライバ、中間基板、プリント基板に至るインピーダンスプロファイルが段階的に増加する。その結果、ドライバ−中間基板間及び中間基板プリント基板間で反射が生じ、その反射波でプリント基板へと伝播する波形はプリエンファシス波形へと整形される。なお、プリエンファシスにより電圧レベルの高くなる時間領域は中間基板配線の遅延時間ｔｄａの２倍となる。
【００１０】
本発明では、中間基板への抵抗挿入という簡易な実装方法で（１）レシーバ側での反射低減による符号間干渉の抑制、（２）ドライバ側でのプリエンファシス波形整形によるアイパターン開口電圧の拡大、ジッタの低減、符号間干渉の抑制という効果を有し、３Ｇｂｐｓ以上の信号転送の高速化に大きく寄与するものである。
【００１１】
【発明の実施の形態】
本実施例では、プリント基板配線より特性インピーダンスの低い中間基板配線を利用する場合の他に、プリント基板内に敢えて、基板内の信号配線のうち主要となる配線（メインライン）よりも低インピーダンスな配線を設けることでも有効である。なぜなら、プリエンファシス波形を形成するのに、メインラインより低インピーダンスな配線が必要だからである。プリエンファシス整形を行なう配線としてパッケージの配線長が十分でない場合、これを補うためにプリント基板にパッケージ配線と同様な低インピーダンス配線を設けることが有効となり、また、パッケージをもたないチップの場合においても、プリント基板に低インピーダンス配線を設ける事が有効となるからである。これらの具体例は実施例４及び実施例５で説明する。
【００１２】
したがって、以下の説明では、中間基板配線と挿入抵抗をそれぞれ整形配線（インピーダンスＺａ（＜Ｚｏ：メインラインのインピーダンス）、遅延時間ｔｄａ）、符号間干渉抑制抵抗（Ｒａ＝Ｚｏ−Ｚａ）と呼ぶことにし、メインラインで接続された信号を出力し、信号配線を介して信号を転送させる半導体チップ（信号転送マスタ）、信号配線を介して転送された信号を入力する半導体チップ（信号転送スレーブ）を有する信号転送システムに対して整形配線と符号間干渉抑制抵抗を挿入すると言う概念で考えを進める。
【００１３】
本発明の第１の実施例における半導体装置に含まれる信号出力回路（ドライバ）からプリント基板配線へ信号伝送する際のプリエンファシス効果について説明する。
【００１４】
図７はｐｏｉｎｔ−ｔｏ−ｐｏｉｎｔの単方向伝送において、反射波を利用してプリエンファシス波形を生成し伝送するための配線方式であり、その基本原理を示したものである。図中右方向が信号転送方向である。
【００１５】
１０−１、１０−２はＬＳＩ等から構成される半導体装置であり、それぞれ信号転送マスタ、信号転送スレーブと呼ぶことにする。簡単のためデータ信号線を一本のみ抽出して記述している。入出力信号の数に応じて信号線等が増えることは言うまでもない。
【００１６】
信号転送マスタ１０−１は信号転送スレーブ１０−２に対し信号転送を行う。この信号転送のための配線が２−１〜２−２であり、この中で特に配線２−１をメインラインと呼ぶことにする。
図３に代表される従来のシステムとの違いは信号転送マスタ１０−１とメインライン２−１の間にメインラインのインピーダンスＺｏより小さい或る値のインピーダンスＺａを持つ整形配線２−２、及び抵抗値Ｒａの符号間干渉抑制抵抗４−１を有することにある。
【００１７】
従来では図２で示すようなシステムにおいて信号転送マスタ１０−１から矩形波を出力し信号伝送を行う。この時、図２のシステム上部及びシステム下部に描写した信号波形の概略図のように、高速信号ではドライバ側から出力した矩形波はメインライン２−１を通過する際に誘電損失や表皮効果によりその波形先端部になまりが生じていた。このため、信号の高速化に伴い信号の周期が短くなると、この先端部のなまりが次のデータと干渉するようになり、シンボル間干渉（ＩＳＩ）の問題が生じ、この結果、アイパターンのジッタの増大やアイ開口電圧の低下が起こり、タイミングマージンやノイズマージが減少し、高速化を制限していた。
【００１８】
さて、この高速化を制限する波形先端部なまりをなくすための方法の一つは、ドライブ波をプリエンファシス波に整形することである。図１０に従来の矩形波伝送とプリエンファシス伝送における受端側アイパターンを示す。（ａ）はプリエンファシス波形、（ｂ）は矩形波形がそれぞれ受端側に到達した時の立ち上がり波形であり、（ｃ）はプリエンファシス波形の受端側アイパターン、（ｄ）は矩形波形のランダムパターンによる受端側アイパターンである。（ｃ）、（ｄ）を比べると、プリエンファシスを用いた（ｃ）ではアイ開口電圧Ｖａ１が矩形波のそれよりも大きく、ジッタＴｊ１が矩形波のそれよりも小さくなり、高速信号に対するノイズ・タイミングマージンがより大きく取れていることを表す。
【００１９】
このプリエンファシス波形生成を複雑な回路構成ではなく、配線や抵抗の追加のみで実現可能であることを図８、図９を用いてＬｏｗｔｏＨｉｇｈ信号（立ち上がり）の場合を例に説明する。
【００２０】
図８に示すように、ドライバ側から振幅Ｖｏ、立ち上がり時間ｔｒの矩形波を出力すると、この信号波は出力抵抗Ｒｘｄ、波形整形配線２−２、符号間干渉抑制抵抗４−１、メインライン２−１、受端入力抵抗Ｒｙｒに伝播する。メインライン２−１の配線インピーダンスはＺｏで遅延時間はｔｄｏ、整形配線２−２のインピーダンスはＺａ（＜Ｚｏ）で、配線遅延時間ｔｄａを持つ。ドライバの出力抵抗ＲｘｄはＲｘｄ＜Ｚａ（＜Ｚｏ）に設定し、レシーバの入力抵抗はＲｙｒ≒Ｚｂに整合する。符号間干渉抑制抵抗Ｒａの値はこの方式では任意の値でよい。ここでの符号間干渉抑制抵抗の役割は、図８中点Ｂでの反射率を大きくすることにある。反射率の大きさは、隣接する配線のインピーダンスの差が大きいほどその絶対値は大きくなる。
【００２１】
一方で、プリント基板で配線のインピーダンスを設計する時は配線の幅と厚さ、誘電体の誘電率から決定されるが、同一基板でこれらパラメータを大きく振ることは難しくインピーダンスの差をつけにくい。そこで、集中定数素子の抵抗を挿入することで、見かけ上大きいインピーダンス差を作り出すことが可能となる。すなわち、ＢＣ間に抵抗Ｒａを挿入しない時のインピーダンス差はＺｏ−Ｚａであるのに対し、挿入後は（Ｒａ＋Ｚｏ）−Ｚａとなりその差は大きくなる。
【００２２】
図８の点Ａにおける右行波の電圧振幅はドライバ側波形整形配線２−２と出力抵抗Ｒｘｄの分圧電力で
Ｖ１＝Ｖｏ×Ｚａ／（Ｚａ＋Ｒｘｄ）・・・（１）
となり、また点Ａにおける点Ｂから点Ａ方向への信号に対する反射率Γ１は、
Γ１＝（Ｒｘｄ−Ｚａ）／（Ｒｘｄ＋Ｚａ）・・・（２）
点Ｂにおける点Ａから点Ｂ方向への信号に対する反射率Γ２は、集中定数の抵抗ＲａとメインラインのインピーダンスＺｏが点Ｂより右側において同時に見えるため、
Γ２＝（［Ｚｏ＋Ｒａ］−Ｚａ）／（［Ｚｏ＋Ｒａ］＋Ｚａ）・・・（３）
点Ｂにおける点Ｃへの透過率Ｔ２は
Ｔ２＝１＋Γ２・・・（４）
となる。ここでＲｘｄ、Ｚａ、Ｚｏの大小関係をＲｘｄ＜Ｚａ＜Ｚｏとしているので、（２）〜（４）よりΓ１＜０、Γ２＞０、Ｔ２＞１となる。
【００２３】
図７にこの系における信号及び反射波の伝播の様子を示す。図中（ａ）はドライバより伝搬した振幅Ｖ１の矩形パルスが点Ｂに到達し、点Ｃに時刻ｔ０でドライブパルスの立ち上がりが開始したと考える。この時、点Ｃより点Ｄ方向へ伝播していくドライブパルスの信号振幅は
Ｖ２＝Ｖ１×Ｔ２・・・（５）
となる。一方この時、点Ｂにおいて、点Ａへと向かう反射波の振幅はＶ３＝Ｖ１×Γ２となり、Γ２＞０よりこれは常に正の振幅を持つ波である（ｂ）。これよりｔｄａ後（時刻ｔ１）にて反射波は点Ａに到達し、点Ａで点Ｂ方向へＶ４＝Ｖ３×Γ１の反射波を生成する。Γ１＜０より、生成される反射波は負のパルスである（ｃ）。これよりｔｄａ後（時刻ｔ２）において、反射波Ｖ４が点Ｂに到達する。時刻ｔ２において点Ｂでは点Ａ方向への反射波Ｖ６（＝Ｖ４×Γ２）の生成と同時に点Ｃから点Ｄへの透過波Ｔ２×Ｖ４＝Ｖ５を生成する（ｄ）。ここでＴ２＞１よりＶ４より振幅が増加した負のパルスがドライブパルスに重畳することとなり、図５（ｅ）に示すように時刻ｔ２（＝２ｔｄａ後）で低い電圧レベルにシフトした形になる。なお、この時のレベルシフト前後の電圧Ｖ１、Ｖ２はそれぞれ
Ｖ１＝Ｖｏ×Ｔ２・・・（５）
Ｖ２＝Ｖ１−Ｖ５・・・（６）
と書け、Ｒｘｄ、Ｚａ、Ｒａ、Ｚｏの値で調整できることがわかる。この結果２ｔｄａ後に電位が低くなるようなプリエンファシス波が生成される。この後さらなる点Ａ、点Ｂ間の多重反射により時刻ｔ２より２ｔｄ後（＝４ｔｄ後）にもわずかにリングバックが生じるが、このリングバックの振幅は｜Γ１Γ２｜＜１であるから、そのリングバック波の振幅は最初のリンギングに比べて小さいものとなるため、影響はほとんど無視できる。以上のように反対極性の反射波がメインラインに到達する時刻がプリエンファシス部の時間幅を決めるため、その時間幅は整形配線の伝搬遅延時間ｔｄａの２倍となる。一般的なプリエンファシス回路では、利用する信号の立ち上がり時間ｔｒ以上、信号周期Ｔ以下がプリエンファシス部の時間幅となるようにプリエンファシス波に整形する。したがって、ｔｒ＜２ｔｄａ＜Ｔとなるように、整形配線の長さを調整するのが適当である。
【００２４】
なお、上記の効果はＨｉｇｈｔｏＬｏｗ信号（立ち下がり）時にもインピーダンスミスマッチの反射のため同様に得られる。
次に整形配線・符号間干渉抑制抵抗追加によるプリエンファシス整形双方向信号転送システムの原理について説明する。
【００２５】
図１はｐｏｉｎｔ−ｔｏ−ｐｏｉｎｔの双方向（ｂｉ−ｄｉｒｅｃｔｉｏｎａｌ）信号転送において、反射波を利用してプリエンファシス波形を相互に伝送するための基本原理を示したものである。
１０−１、１０−２はそれぞれ信号転送マスタ、信号転送スレーブである。
【００２６】
信号転送マスタ１０−１は信号転送スレーブ１０−２に対しデータの読み書き（リード・ライト）の動作を行う。この読み書きのためのデータ配線が２−１〜２−３であり、この中で特に中央に位置する配線２−１をメインラインと呼ぶことにする。
先ほどの例と同様にメインライン２−１と信号転送マスタ１０−１間には整形配線２−２と符号間干渉抑制抵抗４−１が配置され、メインラインを中心として対称に信号転送スレーブ１０−２とメインライン２−１間にも整形配線２−３と符号間干渉抑制抵抗４−２が配置される。
【００２７】
メインライン２−１のインピーダンスＺｏ、配線遅延時間ｔｄｏに対し、整形配線２−２、２−３のインピーダンスはそれぞれＺａ（＜Ｚｏ）、Ｚｂ（＜Ｚｏ）、配線遅延時間はｔｄａ、ｔｄｂであり、符号間干渉抑制抵抗４−１、４−２の抵抗値はそれぞれＲａ≒Ｚｏ−Ｚａ、Ｒｂ≒Ｚｏ−Ｚｂとする。
【００２８】
まず、図１において信号転送マスタから右方向に信号を転送する場合を考える。
【００２９】
先ほどの例にて示したとおり、図１の信号伝送システムにおいて１０−１より出力された矩形波は点Ａ、点Ｂ、点Ｃを通過してメインライン上ではプリエンファシス波形として整形される。
【００３０】
メインライン２−１上を伝搬するプリエンファシス波形はメインライン２−１の伝搬遅延時間後に点Ｄに到達する。点Ｄから進行方向の配線インピーダンスを見ると、符号間干渉抑制抵抗Ｒｂが集中定数の抵抗として見えるため、点Ｄより進行方向の特性インピーダンスはメインラインからはＲｂ＋Ｚｂに見える。ここで、Ｒｂ≒Ｚｏ−Ｚｂに設計しているため、Ｒｂ＋Ｚｂ≒Ｚｏである。すなわち、点Ｄから進行方向を見た特性インピーダンスの大きさはメインラインのそれとほぼ等しい。すなわち、点Ｄ、点Ｅでは反射はほとんど生じない。
【００３１】
整形配線を中間基板配線と見立てても同じことが言える。プリント基板のメインラインよりも低い特性インピーダンスを持つ中間基板配線に対して符号間干渉抑制抵抗を挿入することで、レシーバ、中間基板、メインライン間のインピーダンスプロファイルがほぼ平坦なものとなり、反射がほとんど生じないことになる。
【００３２】
反射無しに整形配線２−３上を伝搬するプリエンファシス波形は点Ｆに到達し、信号転送スレーブ１０−２のレシーバへと伝搬する。ここで、レシーバの入力抵抗ＲｙｒはＺｙｒ＝Ｚｂであるためここでも反射波が生じない。このようにして、信号転送マスタ１０−１のドライバで出力した矩形波はインピーダンスミスマッチの反射波によりプリエンファシス波形に調整されてレシーバに到達する。
【００３３】
次に逆方向の信号伝送を考える。１０−２⇒１０−１方向、すなわち左行波の伝送を考えると、１０−２がドライバ、１０−１がレシーバとして働く。このとき、ドライバ抵抗はＲｙｄ（＜Ｚｂ）、Ｒｘｒ＝Ｚａとなっている。これは、Ｒｘｄ⇔Ｒｙｄ、Ｒｘｒ⇔Ｒｙｒ、Ｒａ⇔Ｒｂ、Ｚａ⇔Ｚｂの対応関係が成立しており、前述の伝送系と全く同じ原理で点Ｆから発進した矩形波は点Ｄでプリエンファシス波に整形されメインライン２−１を伝送し、反射波無く点Ｃ、点Ｂを通過し点Ａに到達することになる。
【００３４】
なお、ドライバとレシーバの構成例は図４と図５の通りである。図４のドライバ構成例はＣＭＯＳ回路による構成例である。電源供給系から信号出力パッドに至るインピーダンスを所望のＲｘｄになるように設計する。一方図５のレシーバ構成例はテブナン終端回路による構成例である。電源／グランドに対して所望の入力インピーダンスの２倍の抵抗値を持つ抵抗でテブナン終端を構成し、入力回路へと信号を送るものである。本発明ではドライバとレシーバで異なる入出力インピーダンスを持つ必要がある。図６にその入出力回路の実現例を示す。この回路では信号出力のインピーダンスは出力バッファのＭＯＳのインピーダンスＲｘｄで決定され、その前段に所望の入力インピーダンスの２倍の値を有するＮＭＯＳとＰＭＯＳをテブナン終端型で配置する。さらに出力バッファと前段のテブナン終端の間に配線抵抗より十分大きい抵抗（ただし、Ｒｘｄよりは十分小さい）を配置する。テブナン終端のＭＯＳの入力信号には／ＷＥ（Ｌｏｗ入力時に書き込み可能）信号を用い、信号の書き込み命令が来た時にこれら入力段のＭＯＳはＯＮとなる。そして、テブナン終端と出力バッファの前の抵抗の間に入出力回路への配線を設ける。
【００３５】
以上の構成により、出力時にはテブナン終端のＭＯＳをＯＦＦとすることから出力インピーダンスはほぼＲｘｄとなり、入力時にはテブナン終端のＭＯＳをＯＮとすることで入力インピーダンスをＲｙｒとすることができる。なお入力回路の入力インピーダンスは出力時にはＨｉｇｈ−Ｚ、入力時はＬｏｗ−Ｚ（＜＜Ｒｘｒ）となるようにする。なお、この入出力回路は構成の一例であり、これ以外の構成でも入力インピーダンス、出力インピーダンスを所定の値にできる構成ならば何ら問題はない。
【００３６】
以上まとめると、この原理に基づきｐｏｉｎｔ−ｔｏ−ｐｏｉｎｔの双方向信号伝送モードにおいて、半導体チップを搭載した基板又は半導体装置の中間基板内に、メインラインより低いインピーダンスの配線とメインラインと前記挿入配線との差の抵抗値の抵抗を付加することにより、ドライブ波をプリエンファシス波へと変換し、その波形をメインラインより先ではほとんど反射無しにレシーバへと伝達できることを示した。
【００３７】
この信号転送形態の有用性を示すために、従来の信号転送システム（図１１）及び本実施例の信号転送システム（図１２）についてＳＰＩＣＥによるシミュレーションを行い、アイパターンの比較を行なった。
【００３８】
図１１の信号転送形態は、既存の送受端整合終端信号転送システムである。図１１での回路パラメータは以下の通りである。
信号振幅Ｖｏ＝１．４Ｖ、信号立ち上がり時間ｔｒ＝１００ｐｓ、信号周期Ｔ＝３００ｐｓ
ドライバ側出力抵抗Ｒｘｄ＝５０Ω
ドライバ・レシーバ側整形配線インピーダンスＺａ＝Ｚｂ＝４２Ω
ドライバ・レシーバ側入出力容量Ｃａ＝Ｃｂ＝３ｐＦ
レシーバ側入力抵抗Ｒｙｒ＝５０Ω
メインラインＷは有損失配線（ＨＳＰＩＣＥのＷ−ｅｌｅｍｅｎｔ）であり、この配線のＳＰＩＣＥ用回路パラメータは以下の通りである。

なお、配線長は２１．５ｃｍを採用した。
【００３９】
また、図１２の信号転送形態は本発明のプリエンファシス整形双方向信号転送システムである。図１２での回路パラメータは以下の通りである。

ドライバ・レシーバ側整形配線インピーダンスＺａ＝Ｚｂ＝４２Ω
ドライバ・レシーバ側整形配線遅延時間ｔｄａ＝ｔｄｂ＝７０ｐｓ
ドライバ・レシーバ側符号間干渉抑制抵抗Ｒａ＝Ｒｂ＝８Ω
配線Ｗのパラメータについては図１１と全く同じである。
【００４０】
なお図１１と図１２のバス形態では入出力抵抗等の値が異なるため、レシーバ側で観測される信号振幅をそろえるために、図１１の場合は１．４Ｖ、図１２では１Ｖの信号振幅を用いた。
【００４１】
この条件下で図１１の点ａ及び図１２の点ｂで観測した波形のアイパターンを図１３、図１４に示す。図１３からわかるようにドライバからの出力電圧Ｖｏが図１２のバスの方が小さいにも関わらず、アイパターンは図１２の信号転送形態の方が開口したものとなっている。
【００４２】
図１１のシステムと図１２のシステムのアイパターンパラメータを比較すると、図１２のバスのパラメータはジッタではＴｊ＿ａ＝７１ｐｓに対してＴｊ＿ｂ＝２０ｐｓと３０％程度であり、またアイ開口電圧ではＶａ＿ａ＝１９７ｍＶに対しＶａ＿ｂ＝３４０ｍＶと１．７倍程度であった。
【００４３】
すなわち、低ジッタ、高開口電圧が実現しており、高速信号に対するタイミングマージン、ノイズマージンが従来の信号転送システムより大きくなっていることが分かる。
【００４４】
次に、第１の実施例の実装形態を示すことにする。
【００４５】
なお、以下の実施例では単方向転送システムのドライバ側の実装方式のみを例示するが、原理でも示した通り双方向転送システムは単方向転送システムの対称形であるため、以後の実施例の組み合わせで実現可能であることが容易に類推できるため省略する。
【００４６】
第１の実施例の実装形態例を図１５・図１６を用いて説明する。
この実施例の目的は、中間基板のみの特殊な配線設計によりプリエンファシス整形高速伝送信号転送システムを実現するものである。
【００４７】
図１５に原理的な等価回路、図１６に具体的な実装方法の例を示す。
【００４８】
図１５に示すように符号間干渉抑制抵抗までをチップと半導体チップを実装する基板側で実現し、プリント基板側では特殊な設計は何も施していない。
【００４９】
図１５の１００−１がＬＳＩチップを表し、このチップのデータ入出力パッド１００−３より信号が出力される。この信号はＢＧＡ基板のような中間基板１００−２内の配線を通過してプリント基板３−１へと伝送される。この中間基板までの経路としては１００−７で示した中間基板内整形配線や１００−８の高抵抗配線、１００−６のＶｉａ、１００−９の中間基板内メインライン、１００−４の中間基板の入出力パッド、１００−５のはんだボール等があり、このうち１００−４￣６の部品は集中定数回路でショート部品（時には誘導的であったり容量的であったりするが）として取り扱える部分である。なお、この実施例の図では中間基板の最上層に信号配線１００−７、最下層に高抵抗配線１００−８を配しているが、配線の構成はこれに限られるものでないことは言うまでもない。また、中間基板内には電源層やグランド層が通常あるが、ここではその描画を省略している。
【００５０】
図１６で示す整形配線１００−７は通常Ｚａ＜Ｚｏなるインピーダンスを持ち、配線長をプリエンファシスに必要な配線遅延時間に合わせて設計する。また、整形配線１００−７からＶｉａを介して集中定数として取り扱える長さの高抵抗配線１００−８に接続している。この高抵抗配線は基板のメインライン３−３と整形配線１００−７の特性インピーダンスの差の抵抗値を持つものである。すなわち図１５における４−１に相当するものである。高抵抗配線は金属で実現するのは難しいため半導体材料や酸化物で実現されるものである。
【００５１】
高抵抗配線の実現例としては、特許文献２に記載の製造方法がある。この方法のプロセスフロー図を図１７に示す。この方法はクロム（Ｃｒ）、シリコン（Ｓｉ）、酸素（Ｏ）を主成分とした薄膜を抵抗層とした薄膜抵抗を製造するものである。図１７を元にプロセスを説明する。最初の製造過程で１４０℃〜３００℃の加熱処理を施すことで抵抗値のばらつきが抑えられ、その後の抵抗層・電極層をフォトエッチング手法で抵抗層と電極層の積層膜を囲うし、抵抗層の素子分離と不要領域の抵抗層除去を行い、電極層のパターンをフォトエッチングで形成する。次にポリイミド膜やシリコン酸化膜などの絶縁層を形成し、フォトエッチング手法などによりスルーホール等のパターンを設けることで保護層パターンを形成する。その後の熱処理安定化によって、デバイス動作温度での薄膜抵抗体の抵抗値変動を抑制する。これらプロセスで、体積低効率１００μΩ／ｍ程度の抵抗膜が形成され、膜厚やパッド面積から抵抗値を決定できる。
【００５２】
この高抵抗薄膜で高抵抗配線を作る以外にも、中間基板の基板側入出力パッド部をこのような高抵抗膜で形成しても良いし、１００−６で示したＶｉａを高抵抗Ｖｉａを形成しそれに代替してもよい。また、ＢＧＡボール１００−５の材料を高抵抗部品で置き換えることでも実現は可能である。
【００５３】
以上で図１６の半導体装置内の配線が実現される。
【００５４】
一方で、プリント基板３−１ではＶｉａ３−２を介してプリント基板内のメインライン３−３に接続する。すなわち従来のプリント基板と何ら変化はない。これにより図１５中のプリント基板内の配線が実現される。
【００５５】
この実施例の効果は、中間基板の特殊な配線設計のみでプリエンファシス高速信号転送システムを実現できることにある。チップ側ではドライバの出力抵抗Ｒｘｄを小さく、レシーバの入力抵抗ＲｘｒをＺａに合わせて設計するだけで良く、プリント基板では特殊な実装は何も必要としない。ただし、中間基板では高抵抗配線や配線長などを適切に設計する必要がある。
【００５６】
次に、第２の実施例として、第１の実施例との相違する特徴部分を説明する。
【００５７】
第２の実施例の実装形態を図１８・図１９を用いて説明する。
この実施例の目的は、プリエンファシスで必要とする整形配線の長さに対して、チップの入出力パッドと中間基板の基板側入出力パッドの間隔が長い場合に、本方式を実現することである。
【００５８】
図１８に原理的な等価回路、図１９に具体的な実装方法の例を示す。
【００５９】
図１８の１００−１がＬＳＩチップを表し、このチップのデータ入出力パッド１００−３より信号が出力される。この信号はＢＧＡ基板のような中間基板１００−２内の配線を通過してプリント基板３−１へと転送される。この中間基板までの経路としては１００−７で示した中間基板内整形配線や１００−８の高抵抗配線、１００−６のＶｉａ、１００−９の中間基板内メインライン、１００−４の中間基板の入出力パッド、１００−５のはんだボール等があり、このうち１００−４￣６の部品は集中定数回路でショート部品（時には誘導的であったり容量的であったりするが）として取り扱える部分である。なお、この実施例の図では中間基板の最上層と最下層に信号配線１００−７を配しているが、この配線のある層が最上層・最下層に限られるものでないことは言うまでもない。また、中間基板内には電源層やグランド層が通常あるが、ここではその描画を省略している。
【００６０】
第１の実施例とほとんど同じであるが、違う点は中間基板内にプリント基板のメインラインの特性インピーダンスとほぼ等しい特性インピーダンスを持つ配線を有する点である。
【００６１】
図１９で示す整形配線１００−７は配線長をプリエンファシスに必要な配線遅延時間に合わせて設計する。また、整形配線１００−７の先に集中定数として取り扱える長さの高抵抗配線１００−８を配し、その先にＶｉａを介して１００−９の中間基板内メインラインに接続している。１００−９配線の特性インピーダンス値は基板側のメインラインの特性インピーダンスに合わせ、配線の長さは任意で良く、一方１００−８の高抵抗配線は１００−９と１００−７の特性インピーダンスの差の抵抗値を持つものである。すなわち図１９における４−１に相当するものである。高抵抗配線の実現は第１の実施例と同様にすればよい。
【００６２】
以上で図１８の半導体装置内の配線が実現される。
【００６３】
一方で、プリント基板３−１ではＶｉａ３−２を介してプリント基板内のメインライン３−３に接続する。すなわち従来のプリント基板と何ら変化はない。これにより図１８中のプリント基板内の配線が実現される。
【００６４】
以上、図１８のような実装方式でプリエンファシス信号転送システムが実現されることを示したが、配線やチップ抵抗の実装位置は必ずしも図中で示した通りである必要はない。
【００６５】
この発明の効果は、中間基板サイズが大きい、あるいは信号周波数が高くプリエンファシス時間が非常に短い必要がある場合に、中間基板の特殊な配線設計のみでプリエンファシス信号転送システムを実現できることにある。チップ側ではドライバの出力抵抗Ｒｘｄを小さく、レシーバの入力抵抗ＲｙｒをＺａに合わせて設計するだけで良く、プリント基板では特殊な実装は何も必要としない。ただし、中間基板では高抵抗配線や２種類の特性インピーダンス配線（Ｚａ、Ｚｏ）を設計する必要がある。
次に、第３の実施例として、第１、第２の実施例との相違する特徴部分を説明する。
【００６６】
第３の実施例の実装形態を図２０・図２１を用いて説明する。
【００６７】
この実施例の目的は、中間基板の配線をそのまま整形配線として利用し、中間基板側に符号間干渉抑制抵抗を設けず、符号間干渉抑制抵抗はプリント基板側に搭載することでプリエンファシス整形バスを実現するものである。
【００６８】
図２０に原理的な等価回路、図２１に具体的な実装方法の例を示す。
【００６９】
図２０に示すように整形配線までをチップと中間基板側で実現し、その後の符号間干渉抑制抵抗から先をプリント基板側で実現するものである。
【００７０】
図２１の１００−１がＬＳＩチップを表し、このチップのデータ入出力パッド１００−３より信号が出力される。この信号はＢＧＡ基板のような中間基板１００−２内の配線を通過してプリント基板３−１へと伝送される。この中間基板の基板までの経路としては１００−７で示した中間基板内配線や１００−６のＶｉａ、１００−４の中間基板の入出力パッド、１００−５のはんだボール等があり、このうち１００−４￣６の部品は集中定数回路でショート部品（時には誘導的であったり容量的であったりするが）として取り扱える部分である。なお、この実施例の図では中間基板の最上層と最下層に信号配線１００−７を配しているが、この配線のある層が最上層・最下層に限られるものでないことは言うまでもない。また、中間基板内には電源層やグランド層が通常あるが、ここではその描画を省略している。
【００７１】
図２１で示す配線１００−７は特性インピーダンスの制御が可能であるため、この配線のインピーダンスをＺａ（＜Ｚｏ）、配線長をプリエンファシスに必要な配線遅延時間に合わせて設計することで図２０の半導体装置内の配線が実現される。
【００７２】
一方で、プリント基板３−１ではＶｉａ３−２を介して中間基板のチップが実装している背面に実装してあるチップ抵抗６−１の片端に接続し、さらにチップ抵抗の他端からＶｉａを介してプリント基板内のメインライン３−３に接続する。ここで、チップ抵抗Ｒａは双方向信号転送システムではプリント基板の配線３−３の特性インピーダンスと中間基板内配線１００−７の特性インピーダンスの差となるような抵抗値のものを選ぶ。これにより図２０中のプリント基板内の配線が実現される。
【００７３】
以上、図２１のような実装方式でプリエンファシス信号転送システムが実現されることを示したが、配線やチップ抵抗の実装位置は必ずしも図中で示した通りである必要はない。Ｖｉａの数を低減するためにチップ抵抗をプリント基板内に埋め込んだり、あるいは信号配線をチップ抵抗のある表面層に配線したりしてももちろん良い。
【００７４】
この実施例の効果は、従来ある技術をそのまま用いることでプリエンファシス信号転送システムを実現できることにある。チップ側ではドライバの出力抵抗ＲｘｄをＺａより小さく、レシーバの入力抵抗をＺａに合わせて設計するだけで良く、中間基板では中間基板内配線の特性インピーダンスをプリント基板の配線特性インピーダンスよりも小さく、そして配線長を必要なプリエンファシス時間に合わせて設計するだけで良い。プリント基板では基板配線と中間基板配線の特性インピーダンス差の値のチップ抵抗を中間基板の入出力部と基板内メインラインの間に実装するだけで良い。この方式を用いるには、基板設計側で搭載する中間基板の配線の特性インピーダンスを知っている必要がある。
次に、第４の実施例として、第１、第２、第３の実施例との相違する特徴部分を説明する。
【００７５】
第４の実施例の実装形態を図２２・図２３を用いて説明する。
【００７６】
この実施例の目的は、整形用の配線長が中間基板内の配線のみでは不足する場合や、中間基板での設計を単純化してプリント基板側での特殊な配線設計に重点を置く場合にプリエンファシス信号転送システムを実現するものである。
【００７７】
図２２に原理的な等価回路、図２３に具体的な実装方法の例を示す。
【００７８】
図２２に示すよう整形配線の一部までをチップと中間基板側で実現し、それ以降をプリント基板側では実現するものである。
【００７９】
図２３の１００−１がＬＳＩチップを表し、このチップのデータ入出力パッド１００−３より信号が出力される。この信号はＢＧＡ基板のような中間基板１００−２内の配線を通過してプリント基板３−１へと伝送される。この中間基板の基板までの経路としては１００−７で示した中間基板内整形配線や１００−６のＶｉａ、１００−４の中間基板の入出力パッド、１００−５のはんだボール等があり、このうち１００−４￣６の部品は集中定数回路でショート部品（時には誘導的であったり容量的であったりするが）として取り扱える部分である。なお、この実施例の図では中間基板の最上層と最下層に信号配線１００−７を配しているが、この配線のある層が最上層・最下層に限られるものでないことは言うまでもない。また、中間基板内には電源層やグランド層が通常あるが、ここではその描画を省略している。
【００８０】
図２３で示す整形配線１００−７はインピーダンスの制御が可能であるため、この配線の特性インピーダンスをＺａ（＜Ｚｏ）、配線長をプリエンファシスに必要な配線遅延時間に合わせて設計する。以上で図２４の半導体装置内の配線が実現される。
【００８１】
一方で、プリント基板３−１ではＶｉａ３−２を介してプリント基板内の整形配線３−４に接続し、その先には符号間干渉抑制抵抗用チップ抵抗６−１、さらにＶｉａを介してメインライン３−３に接続する。これにより図２２中のプリント基板内の配線が実現される。
【００８２】
以上、図２３のような実装方式でプリエンファシス信号転送システムが実現されることを示したが、配線やチップ抵抗の実装位置は必ずしも図中で示した通りである必要はない。
【００８３】
この実施例の効果は、整形配線の長さが中間基板サイズと比べ長い場合や基板側の特殊実装のみでプリエンファシス信号転送システムを実現できることにある。チップ側ではドライバの出力抵抗Ｒｘｄを小さく、レシーバの入力抵抗ＲｙｒをＺａに合わせて設計するだけで良く、中間基板では中間基板内配線をプリント基板の配線より小さくするのみで良く、特殊な実装は何も必要としない。ただし、プリント基板側では符号間干渉抑制抵抗としてのチップ抵抗や２種類の特性インピーダンス配線（Ｚａ、Ｚｏ）を設計する必要がある。整形配線は、符号間干渉抑制抵抗を表面実装する場合が多いことから、表面層に配線するのがＶｉａを余計に打つ必要が減るため効果的である。なぜなら、抵抗素子は基本的に基板の表面層に実装されるため、基板内層に配線すると、そこから表面層に信号を伝えるために、１つ余計なＶｉａを打つことになる。しかし、表面層に配線しておけば、直接抵抗素子に配線接続できるので、Ｖｉａを一つ打たずに済むため、基板コストや配線レイアウトの容易性の面で利点がある。
次に、第５の実施例として、第１、第２、第３、第４の実施例との相違する特徴部分を説明する。
【００８４】
第５の実施例の実装形態を図２４・図２５を用いて説明する。
この実施例の目的は、ＬＳＩを中間基板無しにプリント基板に実装する場合（ＳｙｓｔｅｍＯｎＣｈｉｐ：ＳＯＣ）に、プリント基板側での特殊な配線設計によってプリエンファシス整形バスを実現するものである。
【００８５】
図２４に原理的な等価回路、図２５に具体的な実装方法の例を示す。
【００８６】
図２４に示すよう整形配線から符号間干渉抑制抵抗に至るまでプリント基板側では実現するものである。
【００８７】
図２５の１００−１がＬＳＩチップを表し、このチップのデータ入出力パッド１００−３より信号が出力される。この信号は１００−５のはんだボールを介して直接プリント基板に伝搬する。
【００８８】
プリント基板３−１ではＶｉａ３−２を介してプリント基板内の整形配線３−４に接続し、その先には符号間干渉抑制抵抗用チップ抵抗６−１、さらにＶｉａを介してメインライン３−３に接続する。これにより図２５中のプリント基板内の配線が実現される。
【００８９】
以上、図２５のような実装方式でプリエンファシス信号転送システムが実現されることを示したが、配線やチップ抵抗の実装位置は必ずしも図２５中で示した通りである必要はない。
【００９０】
この実施例の効果は、ＳＯＣでプリエンファシス信号転送システムを実現できることにある。チップ側ではドライバの出力抵抗Ｒｘｄを小さく、レシーバの入力抵抗ＲｙｒをＺａに合わせて設計するだけで良い。ただし、プリント基板側では符号間干渉抑制抵抗としてのチップ抵抗や２種類のインピーダンス配線（Ｚａ、Ｚｏ）を設計する必要がある。整形配線は、符号間干渉抑制抵抗を表面実装する場合が多いことから、表面層に配線するのがＶｉａを余計に打つ必要が減るため効果的である。
【００９１】
以上、第１〜第５の実施例は差動信号伝送にも適用できる。
【００９２】
これの構成例を図２７に示す。図２７中の１０−３、１０−４で示される信号入出力回路は差動信号を入出力するため、ドライバ・レシーバには２本の信号線が接続され、それぞれの信号線には正負符号の異なる信号が伝送される。この場合は、信号線は差動伝送のために２本が１対となって差動信号線路を形成する。この伝送系で信号の伝送特性を特徴付けるインピーダンスは、単線の特性インピーダンスではなく差動信号線路の差動インピーダンスである。２本の信号線が十分に離れている場合は、２本ある単線の特性インピーダンスの和が差動インピーダンスとなる。２本の線が近く、お互い電磁気的に影響する場合は、その影響を考慮した値（単純和より小さい値）が差動インピーダンスとなる。この差動インピーダンス値は、信号配線の形状、寸法、間隔、材料定数で決まる。符合間干渉抑制抵抗は、図中４−３、４−４で示した通り、２つで一対を成す。これは、信号配線が２本で一組となるためである。この時の抵抗値は基板配線の差動インピーダンスＺｏと整形配線の差動インピーダンスＺａ、Ｚｂの差で決まる。すなわち、メインラインの差動インピーダンスと整形配線の差動インピーダンスの差の値を持つ符号間干渉抑制抵抗を２本のメインライン−整形配線間に挿入する。また、差動ドライバの出力インピーダンスＲｘｄ、Ｒｙｄは整形配線の差動インピーダンスより小さく、差動レシーバの入力インピーダンスＲｘｒ、Ｒｙｒは整形配線の差動インピーダンスと等しくする必要がある。以上の構成を基本にすることで、実施例１〜実施例５が差動伝送系でも実現できる。
【００９３】
図２６は、マルチチップモジュールに本方式を実装した場合の実施例（第６の実施例）である。１００−１はチップを表し、１００−２がチップモジュール、１００−３はチップのＩ／Ｏパッド、２−２はモジュール内の配線、４−１が高抵抗薄膜で作った符号間干渉抑制抵抗、１００−３が中間基板基板間のＩ／Ｏパッドとなる。なお、本図では差動線路を想定しており、対となった線路が中間基板内を等長配線され、基板のメインラインの差動インピーダンスと中間基板内差動信号線の差動インピーダンスの差を持つ抵抗を介して基板へと信号を伝えるものである。
【００９４】
情報処理機能を有するＬＳＩ間の信号伝送において、メインラインとドライバａｎｄ／ｏｒレシーバ間に適切な配線インピーダンスと適切な遅延時間を持つ整形配線と適切な抵抗値を持つ符号間干渉抑制抵抗を挿入することで、インピーダンスミスマッチにより生ずる反射波を利用してドライブ波形を矩形波からプリエンファシス波形に整形することで高速信号用信号転送システムを形成する。
【００９５】
この手法によりＬＳＩ側では複雑な回路構成を伴うことなく、プリント基板やＬＳＩ中間基板の配線や抵抗の一部を変更あるいは追加するだけでプリエンファシス波形転送を実現し、ジッタの低減、ＩＳＩの抑制、アイ開口電圧の拡大が実現され、単方向あるいは双方向ｐｏｉｎｔ−ｔｏ−ｐｏｉｎｔ信号転送システムにおける信号の高速対応性能が向上する。
【００９６】
つまり、半導体装置が同一の信号線に接続されデータ転送を行うｐｏｉｎｔ‐ｔｏ‐ｐｏｉｎｔ接続型信号転送システムにおける信号転送の高速化が可能となる。
【００９７】
また、この抵抗は中間基板配線と基板配線の間に挿入することで、基板と中間基板の配線の特性インピーダンスの差による多重反射をレシーバ側で抑制するものである。これにより多重反射によるＩＳＩの影響を軽減でき、高速対応性能が向上する。
【００９８】
【発明の効果】
本発明によれば、インピーダンスミスマッチにより生ずる反射波を利用してドライブ波形を矩形波からプリエンファシス波形に整形することで高速信号用信号転送システムを形成することが可能となる。
【図面の簡単な説明】
【図１】本発明の高速信号双方向転送方式
【図２】半導体チップを実装する基板を含めた従来の信号転送方式
【図３】従来の信号転送方式
【図４】ドライバ回路の構成例
【図５】レシーバ回路の構成例
【図６】入出力回路の構成例
【図７】本発明の高速信号単方向転送方式
【図８】本発明の高速信号単方向転送方式の回路モデル
【図９】本発明におけるプリエンファシス信号生成を説明する図
【図１０】従来方式と本発明方式の違いを説明する図
【図１１】従来方式の回路モデル
【図１２】本発明の高速信号双方向転送方式の回路モデル
【図１３】従来方式のアイパターン例
【図１４】本発明方式のアイパターン例
【図１５】第１の実施例を説明する図
【図１６】第１の実施例の具体例
【図１７】符号間干渉抑制抵抗素子の実現例
【図１８】第２の実施例を説明する図
【図１９】第２の実施例の具体例
【図２０】第３の実施例を説明する図
【図２１】第３の実施例の具体例
【図２２】第４の実施例を説明する図
【図２３】第４の実施例の具体例
【図２４】第５の実施例を説明する図
【図２５】第５の実施例の具体例
【図２６】第６の実施例の具体例
【図２７】差動伝送システムでの基本構成
【符号の説明】
２−１、２−４・・・・メインライン
２−２〜２−３・・・・整形配線
２−１０〜２−１２・・・・差動信号線
３−１・・・・プリント基板
３−２・・・・プリント基板内Ｖｉａ
３−３・・・・プリント基板内メインライン
３−４・・・・プリント基板内整形配線
４−１〜４−２・・・・符号間干渉抑制抵抗
４−３、４−４・・・・符号間干渉抑制抵抗対
６−１・・・・チップ抵抗（符号間干渉抑制抵抗用）
１０−１〜１０−２・・・・データ転送を行う半導体装置（メモリ、プロセッサ等）
１００−１・・・・ＬＳＩチップ
１００−２・・・・ＬＳＩチップを実装する基板
１００−３・・・・ＬＳＩチップＩ／Ｏパッド
１００−４・・・・半導体チップを実装する基板のＩ／Ｏパッド
１００−５・・・・基板接着材（ＢＧＡ−ｂａｌｌ等）
１００−６・・・・半導体チップを実装する基板内Ｖｉａ
１００−７・・・・半導体チップを実装する基板内整形配線
１００−８・・・・半導体チップを実装する基板内高抵抗配線（符号間干渉抑制抵抗配線）
１００−９・・・・半導体チップを実装する基板内メインライン
Ｒｘｄ・・・・信号転送マスタのドライバ出力抵抗
Ｒｘｒ・・・・信号転送マスタのレシーバ入力抵抗
Ｒｙｄ・・・・信号転送スレーブのドライバ出力抵抗
Ｒｙｒ・・・・信号転送スレーブのレシーバ入力抵抗
Ｒａ、Ｒｂ・・・・符号間干渉抑制抵抗
Ｚｏ・・・・メインラインの特性インピーダンス
Ｚａ、Ｚｂ・・・・整形配線の特性インピーダンス
ｔｄｏ・・・・メインラインの伝搬遅延時間
ｔｄａ、ｔｄｂ・・・・整形配線の伝搬遅延時間
Ｖｏ・・・・ドライブパルスの信号振幅
ｔｒ・・・・ドライブパルスの立ち上がり時間
Ｔｊ１、Ｔｊ２・・・・ジッタ
Ｖａ１、Ｖａ２・・・・アイパターンのアイ開口電圧[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for transferring a signal at high speed between semiconductor devices such as a processor and a memory (for example, between digital circuits constituted by CMOS or the like or between functional blocks thereof) in an information processing device.
[0002]
[Prior art]
FIG. 2 shows a basic scheme in bidirectional transfer of a system in which two semiconductor devices that are terminated with resistors are connected to the same signal line. When performing data transfer between the signal transfer master 10-1 and the slave 10-2, the input and output impedances of both sides are matched with the characteristic impedance of the printed circuit board 2-1 so that reflection does not occur at the transmitting end and the receiving end. Alternatively, this is a technique of performing data transfer by appropriately changing the input / output impedance of the transmitting / receiving end as needed. This is suitable for one-to-one transfer between the signal transfer master 10-1 and the slave 10-2, that is, suitable for data signal transfer between the memory and the main processor.
[0003]
By the way, the characteristic impedance of a signal line in a board on which a semiconductor chip is mounted (hereinafter referred to as an intermediate board) for mounting a semiconductor chip usually has a lower value than the characteristic impedance of a printed board, but the length of the wiring of the intermediate board is long. Since the length is as short as the order of millimeters, the mismatch between the wiring characteristic impedance and the impedance of the printed circuit board is negligible in the signal transfer of about 1 Gbps or less.
[0004]
However, with the recent increase in the speed of signals, the signal waveform transferred by this signal transfer method has a rounded rising / falling waveform due to a dielectric loss, a skin effect, and the like in a signal transfer process in a lossy signal wiring. The effect was a problem. This is shown in FIG. When a signal is transferred from the signal transfer master 10-1 through the lossy transmission line 2-1 to the signal transfer slave 10-2, the waveform of the signal is transferred even if the impedance is perfectly matched. When the rectangular wave output from the master reaches the signal transfer slave, the waveform becomes a rounded waveform. This waveform rounding causes problems in the eye pattern observed on the receiving end side, such as narrowing of the eye opening ratio, increase in jitter, and inter symbol interference (ISI), and a voltage for a data transfer rate of 3 Gbps or more. The noise margin and the timing margin are restricted, and this has been a problem with respect to high-speed signals. As a conventional technique for solving this, there has been a method of amplifying the voltage amplitude at the rising / falling portion of the output waveform on the sending end side for a certain period of time. Such a signal waveform having the effect of reducing the ISI is called a pre-emphasis waveform.
[0005]
In Patent Literature 1, an output buffer circuit for transmitting a digital signal via pre-emphasis transmission is used as pre-emphasis waveform shaping. In this method, an output circuit having two impedances is controlled by a control circuit to make an output waveform a pre-emphasis waveform. That is, conventionally, the pre-emphasis waveform shaping has been realized by adjusting the signal amplitude by temporally changing the output voltage or the output resistance in the circuit on the transmitting end side.
[0006]
[Patent Document 1]
JP-A-2000-68816
[Patent Document 2]
JP-A-6-140215
[0007]
[Problems to be solved by the invention]
However, the following points are problematic in a system exceeding 3 Gbps in the signal transfer system according to the conventional technology.
(1) Intersymbol interference due to the influence of reflection due to the characteristic impedance mismatch between the intermediate board wiring and the printed board wiring increases, causing an increase in jitter and a reduction in the eye opening ratio. As a result, the speeding up of the signal is limited.
(2) Since the pre-emphasis waveform shaping means of Patent Document 1 is a signal amplitude adjustment method using a circuit, a complicated circuit configuration is required mainly in the transmitting end LSI. As a result, there arises a problem of an increase in a mounting area and an increase in cost due to an increase in circuit scale.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problems (1) and (2), according to the present invention, a resistor R = Zpcb having a value of a difference between characteristic impedances (Zpcb, Zpkg) of both wirings between an intermediate wiring and a printed wiring. Insert -Zpkg. At this time, the output impedance Rout of the driver of the signal transfer master and the signal transfer slave is made smaller than the intermediate substrate wiring impedance Zpkg, and the input impedance Rin of the receiver is made substantially equal to the intermediate substrate wiring impedance Zpkg.
[0009]
As a result,
(1) When a signal is transferred from the printed board to the receiver, the impedance profile from the printed board to the intermediate board and the receiver is substantially constant. As a result, almost no reflection occurs between the printed circuit board and the intermediate substrate and between the intermediate substrate receiver.
(2) When a signal is transferred from the driver to the printed board, the impedance profile to the driver, the intermediate board, and the printed board increases stepwise. As a result, reflection occurs between the driver and the intermediate substrate and between the intermediate substrate and the printed circuit board, and the waveform of the reflected wave propagating to the printed circuit board is shaped into a pre-emphasis waveform. The time region where the voltage level becomes high due to the pre-emphasis is twice the delay time tda of the intermediate substrate wiring.
[0010]
According to the present invention, with a simple mounting method of inserting a resistor into an intermediate substrate, (1) suppression of intersymbol interference by reducing reflection at a receiver side, and (2) expansion of an eye pattern opening voltage by shaping a pre-emphasis waveform at a driver side. It has the effect of reducing jitter and suppressing intersymbol interference, and greatly contributes to speeding up signal transfer of 3 Gbps or more.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present embodiment, in addition to using the intermediate substrate wiring having a lower characteristic impedance than the printed circuit board wiring, the impedance of the signal wiring in the printed circuit board is lower than that of the main wiring (main line). Providing wiring is also effective. This is because a wiring having lower impedance than the main line is required to form the pre-emphasis waveform. If the wiring length of the package is not enough to perform pre-emphasis shaping, it is effective to provide a low-impedance wiring similar to the package wiring on the printed circuit board to compensate for this, and in the case of a chip without a package, This is because it is effective to provide low impedance wiring on the printed circuit board. These specific examples will be described in

Embodiments

4 and 5.
[0012]
Therefore, in the following description, the intermediate substrate wiring and the insertion resistance are referred to as shaped wiring (impedance Za (<Zo: impedance of main line), delay time tda), and intersymbol interference suppression resistance (Ra = Zo−Za), respectively. A semiconductor chip (signal transfer master) for outputting a signal connected via the main line and transferring the signal via the signal wiring, and a semiconductor chip (signal transfer slave) for inputting the signal transferred via the signal wiring. The concept is advanced with the concept of inserting a shaped wiring and an intersymbol interference suppression resistor into a signal transfer system having the same.
[0013]
A pre-emphasis effect when transmitting a signal from a signal output circuit (driver) included in the semiconductor device to a printed circuit board according to the first embodiment of the present invention will be described.
[0014]
FIG. 7 shows a wiring method for generating and transmitting a pre-emphasis waveform by using a reflected wave in a point-to-point unidirectional transmission, and shows a basic principle thereof. The right direction in the figure is the signal transfer direction.
[0015]
Reference numerals 10-1 and 10-2 denote semiconductor devices composed of an LSI or the like, which are respectively referred to as a signal transfer master and a signal transfer slave. For simplicity, only one data signal line is extracted and described. It goes without saying that the number of signal lines increases according to the number of input / output signals.
[0016]
The signal transfer master 10-1 performs signal transfer to the signal transfer slave 10-2. Wirings for this signal transfer are 2-1 to 2-2, and among them, the wiring 2-1 is particularly called a main line.
The difference from the conventional system represented by FIG. 3 is that the shaping wiring 2-2 having a certain value of the impedance Za smaller than the impedance Zo of the main line between the signal transfer master 10-1 and the main line 2-1, and The present invention is characterized in having an intersymbol interference suppression resistor 4-1 having a resistance value Ra.
[0017]
Conventionally, in a system as shown in FIG. 2, a rectangular wave is output from the signal transfer master 10-1 to perform signal transmission. At this time, as shown in the schematic diagrams of the signal waveforms drawn at the top and bottom of the system in FIG. 2, in the case of a high-speed signal, the rectangular wave output from the driver side is caused by dielectric loss and skin effect when passing through the main line 2-1. The waveform had a rounded end. For this reason, if the period of the signal is shortened with the increase in the speed of the signal, the bluntness of the leading end interferes with the next data, causing a problem of inter-symbol interference (ISI). And the eye opening voltage decreases, the timing margin and the noise merge decrease, and the speeding up is restricted.
[0018]
Now, one of the methods for eliminating the rounding of the waveform tip that limits the speeding up is to shape the drive wave into a pre-emphasis wave. FIG. 10 shows a receiving-side eye pattern in conventional rectangular wave transmission and pre-emphasis transmission. (A) is a pre-emphasis waveform, (b) is a rising waveform when each of the rectangular waveforms reaches the receiving end, (c) is an eye pattern on the receiving end of the pre-emphasis waveform, and (d) is a rectangular waveform. The receiving-side eye pattern is a random pattern. Comparing (c) and (d), in (c) using pre-emphasis, the eye opening voltage Va1 is larger than that of the rectangular wave, the jitter Tj1 is smaller than that of the rectangular wave, and noise and noise for high-speed signals are reduced. This indicates that the timing margin is larger.
[0019]
The fact that this pre-emphasis waveform generation can be realized only by adding a wiring and a resistor instead of a complicated circuit configuration will be described with reference to FIGS. 8 and 9 in the case of a Low to High signal (rising).
[0020]
As shown in FIG. 8, when a rectangular wave having an amplitude Vo and a rise time tr is output from the driver side, this signal wave is converted into an output resistance Rxd, a waveform shaping wiring 2-2, an intersymbol interference suppression resistance 4-1 and a main line 2. -1, propagating to the receiving end input resistance Ryr. The wiring impedance of the main line 2-1 is Zo and the delay time is tdo, and the impedance of the shaping wiring 2-2 is Za (<Zo) and has a wiring delay time tda. The output resistance Rxd of the driver is set so that Rxd <Za (<Zo), and the input resistance of the receiver matches Ryr ≒ Zb. The value of the intersymbol interference suppression resistor Ra may be any value in this system. The role of the intersymbol interference suppression resistor here is to increase the reflectance at point B in FIG. The absolute value of the reflectance increases as the difference between the impedances of adjacent wirings increases.
[0021]
On the other hand, when designing the impedance of a wiring on a printed circuit board, it is determined from the width and thickness of the wiring and the dielectric constant of the dielectric. However, it is difficult to greatly vary these parameters on the same substrate, and it is difficult to make a difference in impedance. Therefore, by inserting the resistance of the lumped constant element, an apparently large impedance difference can be created. That is, the impedance difference when the resistor Ra is not inserted between the BCs is Zo-Za, whereas after the insertion, the difference becomes (Ra + Zo) -Za, and the difference becomes large.
[0022]
The voltage amplitude of the right-hand wave at point A in FIG. 8 is the divided power of the driver-side waveform shaping wiring 2-2 and the output resistor Rxd.
V1 = Vo × Za / (Za + Rxd) (1)
And the reflectance Γ1 at point A for a signal from point B to point A is:
Γ1 = (Rxd−Za) / (Rxd + Za) (2)
The reflectivity Γ2 of the signal at the point B from the point A to the point B is such that the lumped constant resistance Ra and the impedance Zo of the main line are simultaneously visible on the right side of the point B.
Γ2 = ([Zo + Ra] -Za) / ([Zo + Ra] + Za) (3)
The transmittance T2 from point B to point C is
T2 = 1 + Γ2 (4)
It becomes. Here, since the magnitude relation between Rxd, Za, and Zo is Rxd <Za <Zo, Γ1 <0, Γ2> 0, and T2> 1 from (2) to (4).
[0023]
FIG. 7 shows how signals and reflected waves propagate in this system. In FIG. 9A, it is assumed that the rectangular pulse having the amplitude V1 propagated from the driver reaches the point B, and the drive pulse starts rising at the point C at time t0. At this time, the signal amplitude of the drive pulse propagating from point C to point D is
V2 = V1 × T2 (5)
It becomes. On the other hand, at this time, at the point B, the amplitude of the reflected wave going to the point A is V3 = V1 × Γ2, and since Γ2> 0, this is a wave always having a positive amplitude (b). After tda (time t1), the reflected wave reaches point A, and generates a reflected wave of V4 = V3 × Γ1 at point A in the direction of point B. From Γ1 <0, the generated reflected wave is a negative pulse (c). After tda (time t2), the reflected wave V4 reaches the point B. At time t2, at point B, a reflected wave V6 (= V4 × Γ2) in the direction of point A is generated, and at the same time, a transmitted wave T2 × V4 = V5 from point C to point D is generated (d). Here, a negative pulse whose amplitude has increased from V4 since T2> 1 is superimposed on the drive pulse, and the voltage is shifted to a lower voltage level at time t2 (= 2 tda) as shown in FIG. 5E. . The voltages V1 and V2 before and after the level shift at this time are respectively
V1 = Vo * T2 (5)
V2 = V1-V5 (6)
It can be seen that it can be adjusted by the values of Rxd, Za, Ra, and Zo. As a result, a pre-emphasis wave whose potential decreases after 2 tda is generated. Thereafter, due to multiple reflections between points A and B, a ringback occurs slightly after 2td (= 4td) after time t2. Since the amplitude of this ringback is | Γ1Γ2 | <1, the ringback is generated. Since the amplitude of the back wave is smaller than that of the first ringing, the effect is almost negligible. As described above, the time at which the reflected wave of the opposite polarity reaches the main line determines the time width of the pre-emphasis unit, and the time width is twice the propagation delay time tda of the shaped wiring. In a general pre-emphasis circuit, a pre-emphasis wave is shaped so that a time width of a pre-emphasis unit is equal to or longer than a rising time tr of a signal to be used and equal to or shorter than a signal period T. Therefore, it is appropriate to adjust the length of the shaped wiring so that tr <2tda <T.
[0024]
The above-described effect can be obtained in the same manner even at the time of a High to Low signal (falling) due to reflection of impedance mismatch.
Next, the principle of a pre-emphasis shaped bidirectional signal transfer system by adding a shaped wiring / intersymbol interference suppression resistor will be described.
[0025]
FIG. 1 shows a basic principle for mutually transmitting a pre-emphasis waveform using a reflected wave in a point-to-point bi-directional signal transfer.
10-1 and 10-2 are a signal transfer master and a signal transfer slave, respectively.
[0026]
The signal transfer master 10-1 performs a data read / write (read / write) operation with respect to the signal transfer slave 10-2. The data lines for reading and writing are 2-1 to 2-3, and among them, the line 2-1 located particularly at the center is called a main line.
As in the previous example, the shaping wiring 2-2 and the intersymbol interference suppression resistor 4-1 are disposed between the main line 2-1 and the signal transfer master 10-1, and the signal transfer slave 10 is symmetrical about the main line. Also, a shaping wiring 2-3 and an intersymbol interference suppression resistor 4-2 are arranged between -2 and the main line 2-1.
[0027]
With respect to the impedance Zo of the main line 2-1 and the wiring delay time tdo, the impedances of the shaped wirings 2-2 and 2-3 are Za (<Zo) and Zb (<Zo), respectively, and the wiring delay times are tda and tdb. , And the resistance values of the intersymbol interference suppression resistors 4-1 and 4-2 are respectively Ra ≒ Zo-Za and Rb ≒ Zo-Zb.
[0028]
First, consider the case where a signal is transferred from the signal transfer master in the right direction in FIG.
[0029]
As shown in the previous example, the rectangular wave output from 10-1 in the signal transmission system of FIG. 1 passes through points A, B, and C and is shaped as a pre-emphasis waveform on the main line.
[0030]
The pre-emphasis waveform propagating on the main line 2-1 reaches the point D after the propagation delay time of the main line 2-1. When looking at the wiring impedance in the traveling direction from the point D, the intersymbol interference suppression resistance Rb appears as a lumped constant resistance, so that the characteristic impedance in the traveling direction from the point D appears as Rb + Zb from the main line. Here, Rb + Zb ≒ Zo because Rb ≒ Zo−Zb. That is, the magnitude of the characteristic impedance as viewed in the traveling direction from the point D is substantially equal to that of the main line. That is, the reflection hardly occurs at the points D and E.
[0031]
The same can be said when the shaped wiring is regarded as the intermediate substrate wiring. By inserting an intersymbol interference suppression resistor to the intermediate board wiring with a lower characteristic impedance than the main line of the printed circuit board, the impedance profile between the receiver, the intermediate board, and the main line becomes almost flat, and reflection is almost eliminated. Will not occur.
[0032]
The pre-emphasis waveform propagating on the shaping wiring 2-3 without reflection reaches the point F and propagates to the receiver of the signal transfer slave 10-2. Here, since the input resistance Ryr of the receiver is Zyr = Zb, no reflected wave is generated here. In this way, the rectangular wave output by the driver of the signal transfer master 10-1 is adjusted to a pre-emphasis waveform by the reflected wave of the impedance mismatch, and reaches the receiver.
[0033]
Next, consider signal transmission in the reverse direction. Considering the direction of 10-2⇒10-1, that is, transmission of the left-hand wave, 10-2 functions as a driver and 10-1 functions as a receiver. At this time, the driver resistance is Ryd (<Zb) and Rxr = Za. This is because Rxd⇔Ryd, Rxr⇔Ryr, Ra⇔Rb, Za⇔Zb are established, and the rectangular wave started from the point F by the same principle as the above-described transmission system is a pre-emphasis wave at the point D. Is transmitted through the main line 2-1 and passes through the points C and B without reflected waves to reach the point A.
[0034]
The configuration examples of the driver and the receiver are as shown in FIGS. The driver configuration example in FIG. 4 is a configuration example using a CMOS circuit. The impedance from the power supply system to the signal output pad is designed to be a desired Rxd. On the other hand, the receiver configuration example in FIG. 5 is a configuration example using a Thevenin termination circuit. A Thevenin termination is formed by a resistor having a resistance value twice the desired input impedance with respect to the power supply / ground, and a signal is sent to the input circuit. In the present invention, it is necessary that the driver and the receiver have different input / output impedances. FIG. 6 shows an implementation example of the input / output circuit. In this circuit, the impedance of the signal output is determined by the impedance Rxd of the MOS of the output buffer, and an NMOS and a PMOS having a value twice as large as a desired input impedance are arranged in the preceding stage in a Thevenin-terminated type. Further, a resistor (which is sufficiently smaller than Rxd) sufficiently larger than the wiring resistance is arranged between the output buffer and the previous stage Thevenin termination. A / WE (writable at Low input) signal is used as the input signal of the Thevenin-terminated MOS, and the MOS of these input stages is turned on when a signal write command is received. Then, a wiring to the input / output circuit is provided between the Thevenin terminal and the resistor before the output buffer.
[0035]
With the above configuration, the output impedance is substantially Rxd because the Thevenin-terminated MOS is turned off at the time of output, and the input impedance can be Ryr by turning the Thevenin-terminated MOS on at the time of input. The input impedance of the input circuit is set to High-Z at the time of output and to Low-Z (<< Rxr) at the time of input. Note that this input / output circuit is an example of a configuration, and there is no problem with other configurations as long as the input impedance and the output impedance can be set to predetermined values.
[0036]
In summary, in the point-to-point bidirectional signal transmission mode based on this principle, a wiring having a lower impedance than the main line, the main line, and the insertion wiring are provided in the substrate on which the semiconductor chip is mounted or the intermediate substrate of the semiconductor device. It was shown that by adding a resistance having a resistance value different from the above, the drive wave could be converted into a pre-emphasis wave, and the waveform could be transmitted to the receiver with little reflection before the main line.
[0037]
In order to show the usefulness of this signal transfer mode, SPICE simulation was performed for the conventional signal transfer system (FIG. 11) and the signal transfer system of the present embodiment (FIG. 12), and eye patterns were compared.
[0038]
The signal transfer mode of FIG. 11 is an existing transmission / reception end matched termination signal transmission system. The circuit parameters in FIG. 11 are as follows.
Signal amplitude Vo = 1.4V, signal rise time tr = 100ps, signal cycle T = 300ps
Driver side output resistance Rxd = 50Ω
Driver / receiver side shaped wiring impedance Za = Zb = 42Ω
Driver / receiver side input / output capacitance Ca = Cb = 3 pF
Receiver side input resistance Ryr = 50Ω
The main line W is a lossy wiring (W-element of HSPICE), and circuit parameters for SPICE of this wiring are as follows.

The wiring length was 21.5 cm.
[0039]
The signal transfer form shown in FIG. 12 is a pre-emphasis shaped bidirectional signal transfer system of the present invention. The circuit parameters in FIG. 12 are as follows.

Driver / receiver side shaped wiring impedance Za = Zb = 42Ω
Driver / receiver side shaped wiring delay time tda = tdb = 70 ps
Driver / receiver side intersymbol interference suppression resistance Ra = Rb = 8Ω
The parameters of the wiring W are exactly the same as in FIG.
[0040]
Since the values of the input / output resistance and the like are different between the bus configurations of FIG. 11 and FIG. 12, the signal amplitude of 1.4 V in FIG. 11 and 1 V in FIG. Using.
[0041]
FIGS. 13 and 14 show the eye patterns of the waveforms observed at the point a in FIG. 11 and the point b in FIG. 12 under this condition. As can be seen from FIG. 13, although the output voltage Vo from the driver is smaller in the bus of FIG. 12, the eye pattern is open in the signal transfer mode of FIG.
[0042]
Comparing the eye pattern parameters of the system of FIG. 11 and the system of FIG. 12, the bus parameters of FIG. Va_b = 340 mV, which is about 1.7 times.
[0043]
That is, it is understood that low jitter and high aperture voltage are realized, and the timing margin and noise margin for high-speed signals are larger than those of the conventional signal transfer system.
[0044]
Next, an implementation of the first embodiment will be described.
[0045]
In the following embodiment, only the mounting method on the driver side of the one-way transfer system is illustrated. However, since the two-way transfer system is a symmetric type of the one-way transfer system as shown in the principle, a combination of the following embodiments is used. Since it can be easily inferred that it can be realized by the above, the description is omitted.
[0046]
An example of a mounting form of the first embodiment will be described with reference to FIGS.
The purpose of this embodiment is to realize a pre-emphasis-shaped high-speed transmission signal transfer system by a special wiring design of only the intermediate substrate.
[0047]
FIG. 15 shows a principle equivalent circuit, and FIG. 16 shows a specific example of a mounting method.
[0048]
As shown in FIG. 15, up to the intersymbol interference suppression resistor is realized on the board side on which the chip and the semiconductor chip are mounted, and no special design is applied on the printed board side.
[0049]
15 denotes an LSI chip, and a signal is output from a data input / output pad 100-3 of this chip. This signal is transmitted to the printed board 3-1 through a wiring in the intermediate board 100-2 such as a BGA board. The route to the intermediate substrate is as follows: shaped wiring in the intermediate substrate, high-resistance wiring 100-8, via in 100-6, main line in the intermediate substrate 100-9, intermediate substrate 100-4 Input / output pads, 100-5 solder balls, etc., of which 100-4￣6 are parts that can be treated as short parts (although sometimes inductive or capacitive) in a lumped circuit. is there. In this embodiment, the signal wiring 100-7 is provided on the uppermost layer of the intermediate substrate and the high-resistance wiring 100-8 is provided on the lowermost layer. However, it is needless to say that the wiring configuration is not limited to this. . Further, a power supply layer and a ground layer are usually provided in the intermediate substrate, but the drawing is omitted here.
[0050]
The shaped wiring 100-7 shown in FIG. 16 usually has an impedance of Za <Zo, and the wiring length is designed according to the wiring delay time required for pre-emphasis. Further, the wiring is connected to the high resistance wiring 100-8 having a length that can be handled as a lumped constant from the shaping wiring 100-7 via. This high resistance wiring has a resistance value that is the difference between the characteristic impedance of the main line 3-3 of the substrate and the characteristic impedance of the shaping wiring 100-7. That is, it corresponds to 4-1 in FIG. Since it is difficult to realize a high-resistance wiring with a metal, it is realized with a semiconductor material or an oxide.
[0051]
As a realization example of the high resistance wiring, there is a manufacturing method described in Patent Document 2. A process flow diagram for this method is shown in FIG. This method is to manufacture a thin film resistor using a thin film mainly composed of chromium (Cr), silicon (Si) and oxygen (O) as a resistance layer. The process will be described with reference to FIG. By performing a heat treatment at 140 ° C. to 300 ° C. in the first manufacturing process, the variation in resistance value is suppressed, and then the resistive layer and the electrode layer are surrounded by a photoetching method around the laminated film of the resistive layer and the electrode layer. The element isolation of the layer and the removal of the resistive layer in the unnecessary area are performed, and the pattern of the electrode layer is formed by photoetching. Next, an insulating layer such as a polyimide film or a silicon oxide film is formed, and a pattern such as a through hole is provided by a photoetching method or the like to form a protective layer pattern. By the subsequent heat treatment stabilization, the fluctuation of the resistance value of the thin film resistor at the device operating temperature is suppressed. Through these processes, a resistive film having a volume efficiency of about 100 μΩ / m is formed, and the resistance value can be determined from the film thickness and the pad area.
[0052]
In addition to forming a high-resistance wiring with this high-resistance thin film, the substrate-side input / output pad portion of the intermediate substrate may be formed of such a high-resistance film, or Via represented by 100-6 may be replaced with a high-resistance Via. It may be formed and substituted for it. Further, it can be realized by replacing the material of the BGA ball 100-5 with a high-resistance component.
[0053]
Thus, the wiring in the semiconductor device of FIG. 16 is realized.
[0054]
On the other hand, the printed board 3-1 is connected to the main line 3-3 in the printed board via the Via 3-2. That is, there is no change from the conventional printed circuit board. This realizes the wiring in the printed circuit board in FIG.
[0055]
The effect of this embodiment is that a pre-emphasis high-speed signal transfer system can be realized only by a special wiring design of the intermediate substrate. On the chip side, it is only necessary to design the output resistance Rxd of the driver to be small and the input resistance Rxr of the receiver in accordance with Za, and no special mounting is required on the printed circuit board. However, it is necessary to appropriately design the high resistance wiring and the wiring length on the intermediate substrate.
[0056]
Next, as a second embodiment, features different from those of the first embodiment will be described.
[0057]
A mounting form of the second embodiment will be described with reference to FIGS.
The purpose of this embodiment is to realize this method when the distance between the chip input / output pad and the substrate-side input / output pad of the intermediate substrate is longer than the length of the shaped wiring required for pre-emphasis. is there.
[0058]
FIG. 18 shows a principle equivalent circuit, and FIG. 19 shows a specific example of a mounting method.
[0059]
18 denotes an LSI chip, and a signal is output from a data input / output pad 100-3 of the chip. This signal is transferred to the printed board 3-1 through wiring in the intermediate board 100-2 such as a BGA board. The route to the intermediate substrate is as follows: shaped wiring in the intermediate substrate, high-resistance wiring 100-8, via in 100-6, main line in the intermediate substrate 100-9, intermediate substrate 100-4 Input / output pads, 100-5 solder balls, etc., of which 100-4￣6 are parts that can be treated as short parts (although sometimes inductive or capacitive) in a lumped circuit. is there. Although the signal wiring 100-7 is arranged on the uppermost layer and the lowermost layer of the intermediate substrate in the drawing of this embodiment, it goes without saying that the layer with this wiring is not limited to the uppermost layer and the lowermost layer. Further, a power supply layer and a ground layer are usually provided in the intermediate substrate, but the drawing is omitted here.
[0060]
The second embodiment is almost the same as the first embodiment, except that the intermediate substrate has a wiring having a characteristic impedance substantially equal to the characteristic impedance of the main line of the printed circuit board.
[0061]
The shaped wiring 100-7 shown in FIG. 19 is designed so that the wiring length is adjusted to the wiring delay time necessary for pre-emphasis. Further, a high resistance wiring 100-8 having a length that can be handled as a lumped constant is arranged at the end of the shaping wiring 100-7, and connected to the main line in the intermediate substrate 100-9 via the end of the high resistance wiring 100-8. The characteristic impedance value of the 100-9 wiring is adjusted to the characteristic impedance of the main line on the substrate side, and the length of the wiring may be arbitrarily determined. On the other hand, the high resistance wiring of 100-8 has a difference between the characteristic impedance of 100-9 and 100-7. It has a resistance value of That is, it corresponds to 4-1 in FIG. The realization of the high resistance wiring may be performed in the same manner as in the first embodiment.
[0062]
As described above, the wiring in the semiconductor device of FIG. 18 is realized.
[0063]
On the other hand, the printed board 3-1 is connected to the main line 3-3 in the printed board via the Via 3-2. That is, there is no change from the conventional printed circuit board. Thus, the wiring in the printed circuit board in FIG. 18 is realized.
[0064]
As described above, the pre-emphasis signal transfer system is realized by the mounting method as shown in FIG. 18, but the mounting positions of the wirings and the chip resistors do not necessarily have to be as shown in the drawing.
[0065]
An advantage of the present invention is that a pre-emphasis signal transfer system can be realized only by a special wiring design of the intermediate substrate when the intermediate substrate size is large or the signal frequency is high and the pre-emphasis time needs to be very short. On the chip side, it is only necessary to design the output resistance Rxd of the driver to be small and the input resistance Ryr of the receiver in accordance with Za, and no special mounting is required on the printed circuit board. However, it is necessary to design a high resistance wiring and two types of characteristic impedance wirings (Za, Zo) on the intermediate substrate.
Next, as a third embodiment, features different from those of the first and second embodiments will be described.
[0066]
A mounting form of the third embodiment will be described with reference to FIGS.
[0067]
The purpose of this embodiment is to use the wiring of the intermediate board as it is as the shaping wiring, without providing the intersymbol interference suppression resistor on the intermediate board side, and mounting the intersymbol interference suppression resistor on the printed circuit board side to achieve a pre-emphasis shaping bus Is realized.
[0068]
FIG. 20 shows an equivalent circuit in principle, and FIG. 21 shows an example of a specific mounting method.
[0069]
As shown in FIG. 20, the process up to the shaping wiring is realized on the chip and the intermediate substrate side, and the subsequent inter-symbol interference suppression resistance is realized on the printed circuit board side.
[0070]
In FIG. 21, reference numeral 100-1 denotes an LSI chip, and a signal is output from a data input / output pad 100-3 of the chip. This signal is transmitted to the printed board 3-1 through a wiring in the intermediate board 100-2 such as a BGA board. The route to the board of the intermediate board includes the wiring in the intermediate board indicated by 100-7, the via of 100-6, the input / output pad of the intermediate board of 100-4, the solder ball of 100-5, and the like. The part of 100-4￣6 is a lumped constant circuit that can be handled as a short part (although it is sometimes inductive or capacitive). Although the signal wiring 100-7 is arranged on the uppermost layer and the lowermost layer of the intermediate substrate in the drawing of this embodiment, it goes without saying that the layer with this wiring is not limited to the uppermost layer and the lowermost layer. Further, a power supply layer and a ground layer are usually provided in the intermediate substrate, but the drawing is omitted here.
[0071]
Since the characteristic impedance of the wiring 100-7 shown in FIG. 21 can be controlled, the impedance of this wiring is designed to be Za (<Zo), and the wiring length is designed in accordance with the wiring delay time required for pre-emphasis. The wiring in the semiconductor device is realized.
[0072]
On the other hand, the printed circuit board 3-1 is connected to one end of the chip resistor 6-1 mounted on the back surface of the intermediate substrate via the via 3-2, and Via is connected from the other end of the chip resistor. Through the main line 3-3 in the printed circuit board. Here, in the bidirectional signal transfer system, a chip resistor Ra having a resistance value that makes a difference between the characteristic impedance of the wiring 3-3 of the printed board and the characteristic impedance of the wiring 100-7 in the intermediate board selected. Thereby, the wiring in the printed circuit board in FIG. 20 is realized.
[0073]
As described above, the pre-emphasis signal transfer system is realized by the mounting method as shown in FIG. 21, but the mounting positions of the wirings and the chip resistors do not necessarily have to be as shown in the drawing. Of course, in order to reduce the number of vias, chip resistors may be embedded in a printed circuit board, or signal wires may be wired on a surface layer having chip resistors.
[0074]
The effect of this embodiment is that a pre-emphasis signal transfer system can be realized by using a conventional technique as it is. On the chip side, it is only necessary to design the output resistance Rxd of the driver smaller than Za and the input resistance of the receiver in accordance with Za. On the intermediate board, the characteristic impedance of the wiring in the intermediate board is smaller than the wiring characteristic impedance of the printed board, and It is only necessary to design the wiring length according to the required pre-emphasis time. In a printed circuit board, it is only necessary to mount a chip resistor having a value of a characteristic impedance difference between the board wiring and the intermediate board wiring between the input / output unit of the intermediate board and the main line in the board. To use this method, it is necessary for the board design side to know the characteristic impedance of the wiring of the intermediate board mounted.
Next, a description will be given of features of the fourth embodiment that are different from the first, second, and third embodiments.
[0075]
A mounting form of the fourth embodiment will be described with reference to FIGS.
[0076]
The purpose of this embodiment is when the wiring length for shaping is insufficient with only the wiring in the intermediate board, or when the design on the intermediate board is simplified and the emphasis is placed on the special wiring design on the printed circuit board side. This implements an emphasis signal transfer system.
[0077]
FIG. 22 shows a theoretical equivalent circuit, and FIG. 23 shows a specific example of a mounting method.
[0078]
As shown in FIG. 22, up to a part of the shaped wiring is realized on the chip and the intermediate substrate side, and the rest is realized on the printed circuit board side.
[0079]
Reference numeral 100-1 in FIG. 23 denotes an LSI chip, and a signal is output from a data input / output pad 100-3 of this chip. This signal is transmitted to the printed board 3-1 through a wiring in the intermediate board 100-2 such as a BGA board. The route to the substrate of the intermediate substrate includes a shaped wiring in the intermediate substrate indicated by 100-7, a via of 100-6, an input / output pad of the intermediate substrate of 100-4, and a solder ball of 100-5. Among them, the part of 100-4￣6 is a lumped constant circuit that can be treated as a short part (although it is sometimes inductive or capacitive). Although the signal wiring 100-7 is arranged on the uppermost layer and the lowermost layer of the intermediate substrate in the drawing of this embodiment, it goes without saying that the layer with this wiring is not limited to the uppermost layer and the lowermost layer. Further, a power supply layer and a ground layer are usually provided in the intermediate substrate, but the drawing is omitted here.
[0080]
The impedance of the shaped wiring 100-7 shown in FIG. 23 can be controlled. Therefore, the characteristic impedance of this wiring is designed to be Za (<Zo), and the wiring length is designed according to the wiring delay time required for pre-emphasis. Thus, the wiring in the semiconductor device of FIG. 24 is realized.
[0081]
On the other hand, the printed circuit board 3-1 is connected to the shaping wiring 3-4 in the printed circuit board via the via 3-2, and further to the chip resistor 6-1 for the intersymbol interference suppression resistor, and further to the main via the via 3a. Connect to line 3-3. Thus, the wiring in the printed circuit board in FIG. 22 is realized.
[0082]
As described above, although the pre-emphasis signal transfer system is realized by the mounting method as shown in FIG. 23, the mounting positions of the wirings and the chip resistors do not necessarily have to be as shown in the drawing.
[0083]
The effect of this embodiment is that the pre-emphasis signal transfer system can be realized only when the length of the shaped wiring is longer than the size of the intermediate board or only by special mounting on the board. On the chip side, it is only necessary to design the output resistance Rxd of the driver to be small and the input resistance Ryr of the receiver to match Za. On the intermediate board, it is only necessary to make the wiring in the intermediate board smaller than the wiring of the printed board. Nothing needed. However, it is necessary to design a chip resistor as an intersymbol interference suppression resistor and two types of characteristic impedance wirings (Za, Zo) on the printed circuit board side. In many cases, the shaped wiring is surface-mounted with the inter-symbol interference suppression resistor. Therefore, wiring the wiring on the surface layer is effective because it is not necessary to hit an extra Via. Because the resistive element is basically mounted on the surface layer of the substrate, if wiring is performed on the inner layer of the substrate, an extra Via is hit to transmit a signal from there to the surface layer. However, if wiring is performed on the surface layer, wiring can be directly connected to the resistance element, so that it is not necessary to hit one via, which is advantageous in terms of substrate cost and ease of wiring layout.
Next, as a fifth embodiment, features different from those of the first, second, third, and fourth embodiments will be described.
[0084]
A mounting form of the fifth embodiment will be described with reference to FIGS.
The purpose of this embodiment is to realize a pre-emphasis shaping bus by a special wiring design on the printed circuit board side when an LSI is mounted on a printed circuit board without an intermediate board (System On Chip: SOC).
[0085]
FIG. 24 shows a principle equivalent circuit, and FIG. 25 shows a specific example of a mounting method.
[0086]
As shown in FIG. 24, everything from the shaped wiring to the inter-symbol interference suppression resistance is realized on the printed circuit board side.
[0087]
Reference numeral 100-1 in FIG. 25 represents an LSI chip, and a signal is output from a data input / output pad 100-3 of this chip. This signal propagates directly to the printed circuit board via the 100-5 solder balls.
[0088]
The printed circuit board 3-1 is connected to the shaping wiring 3-4 in the printed circuit board via the via 3-2, and the chip resistor 6-1 for the inter-symbol interference suppression resistance is connected to the connection via the via 3-2. Connect to 3. Thus, the wiring in the printed circuit board in FIG. 25 is realized.
[0089]
As described above, the pre-emphasis signal transfer system is realized by the mounting method as shown in FIG. 25, but the mounting positions of the wiring and the chip resistor need not necessarily be as shown in FIG.
[0090]
The effect of this embodiment is that a pre-emphasis signal transfer system can be realized by SOC. On the chip side, it is only necessary to design the output resistance Rxd of the driver to be small and the input resistance Ryr of the receiver to match Za. However, it is necessary to design a chip resistor as an intersymbol interference suppression resistor and two types of impedance wiring (Za, Zo) on the printed circuit board side. In many cases, the shaped wiring is surface-mounted with the inter-symbol interference suppression resistor. Therefore, wiring the wiring on the surface layer is effective because it is not necessary to hit an extra Via.
[0091]
As described above, the first to fifth embodiments can also be applied to differential signal transmission.
[0092]
An example of this configuration is shown in FIG. Signal input / output circuits denoted by reference numerals 10-3 and 10-4 in FIG. 27 input and output differential signals. Therefore, two signal lines are connected to the driver / receiver, and each signal line has a sign. Are transmitted. In this case, two signal lines are paired to form a differential signal line for differential transmission. The impedance that characterizes the signal transmission characteristics in this transmission system is not the characteristic impedance of a single wire but the differential impedance of a differential signal line. If the two signal lines are sufficiently separated, the sum of the characteristic impedances of the two single lines is the differential impedance. When the two lines are close to each other and electromagnetically affect each other, a value (a value smaller than the simple sum) in consideration of the effect is the differential impedance. This differential impedance value is determined by the shape, size, interval, and material constant of the signal wiring. As shown by 4-3 and 4-4 in the figure, the intersymbol interference suppression resistance forms a pair of two. This is because two signal lines form a set. The resistance value at this time is determined by the difference between the differential impedance Zo of the substrate wiring and the differential impedances Za and Zb of the shaping wiring. That is, an intersymbol interference suppression resistor having a value of the difference between the differential impedance of the main line and the differential impedance of the shaping wiring is inserted between the two main lines and the shaping wiring. Further, the output impedances Rxd and Ryd of the differential driver are smaller than the differential impedance of the shaped wiring, and the input impedances Rxr and Ryr of the differential receiver need to be equal to the differential impedance of the shaped wiring. Based on the above configuration, the first to fifth embodiments can be realized also in a differential transmission system.
[0093]
FIG. 26 shows an embodiment (sixth embodiment) in a case where this method is mounted on a multichip module. 100-1 denotes a chip, 100-2 denotes a chip module, 100-3 denotes an I / O pad of the chip, 2-2 denotes a wiring in the module, 4-1 denotes an intersymbol interference suppression resistor made of a high-resistance thin film. , 100-3 are I / O pads between the intermediate substrates. In this figure, a differential line is assumed, and the paired lines are wired with equal lengths in the intermediate substrate, so that the differential impedance of the main line of the substrate and the differential impedance of the differential signal line of the intermediate substrate are different. A signal is transmitted to the substrate via a resistor having a difference.
[0094]
In signal transmission between LSIs having an information processing function, a shaped wiring having an appropriate wiring impedance and an appropriate delay time and an intersymbol interference suppression resistor having an appropriate resistance value are inserted between a main line and a driver and / or receiver. Thus, the drive waveform is shaped from a rectangular wave to a pre-emphasis waveform using the reflected wave generated by the impedance mismatch, thereby forming a high-speed signal transfer system.
[0095]
By this method, the pre-emphasis waveform transfer is realized by simply changing or adding a part of the wiring and the resistance of the printed circuit board and the LSI intermediate board without complicated circuit configuration on the LSI side, thereby reducing jitter and suppressing ISI. Thus, an increase in the eye opening voltage is realized, and the high-speed performance of signals in a unidirectional or bidirectional point-to-point signal transfer system is improved.
[0096]
That is, it is possible to speed up signal transfer in a point-to-point connection type signal transfer system in which semiconductor devices are connected to the same signal line and perform data transfer.
[0097]
Further, by inserting this resistor between the intermediate substrate wiring and the substrate wiring, the multiple reflection due to the difference in the characteristic impedance of the wiring between the substrate and the intermediate substrate is suppressed on the receiver side. Thereby, the influence of ISI due to multiple reflection can be reduced, and the high-speed response performance is improved.
[0098]
【The invention's effect】
According to the present invention, it is possible to form a high-speed signal transfer system by shaping a drive waveform from a rectangular wave to a pre-emphasis waveform by using a reflected wave generated by impedance mismatch.
[Brief description of the drawings]
FIG. 1 shows a high-speed signal bidirectional transfer system according to the present invention.
FIG. 2 shows a conventional signal transfer method including a substrate on which a semiconductor chip is mounted.
FIG. 3 shows a conventional signal transfer method.
FIG. 4 is a configuration example of a driver circuit;
FIG. 5 is a configuration example of a receiver circuit.
FIG. 6 is a configuration example of an input / output circuit;
FIG. 7 is a high-speed signal unidirectional transfer system of the present invention.
FIG. 8 is a circuit model of a high-speed signal one-way transfer system according to the present invention.
FIG. 9 is a diagram illustrating generation of a pre-emphasis signal according to the present invention.
FIG. 10 is a diagram for explaining the difference between the conventional system and the present invention system.
FIG. 11 is a circuit model of a conventional system.
FIG. 12 is a circuit model of a high-speed signal bidirectional transfer system according to the present invention;
FIG. 13 shows an example of a conventional eye pattern.
FIG. 14 shows an example of an eye pattern according to the present invention.
FIG. 15 is a view for explaining the first embodiment;
FIG. 16 is a specific example of the first embodiment.
FIG. 17 shows an example of realizing an intersymbol interference suppression resistance element.
FIG. 18 is a diagram illustrating a second embodiment.
FIG. 19 is a specific example of the second embodiment.
FIG. 20 is a view for explaining a third embodiment;
FIG. 21 is a specific example of the third embodiment.
FIG. 22 is a view for explaining a fourth embodiment;
FIG. 23 is a specific example of the fourth embodiment.
FIG. 24 is a view for explaining a fifth embodiment;
FIG. 25 is a specific example of the fifth embodiment.
FIG. 26 is a specific example of the sixth embodiment.
FIG. 27: Basic configuration in a differential transmission system
[Explanation of symbols]
2-1, 2-4 ... Main line
2-2 to 2-3
2-10 to 2-12... Differential signal lines
3-1 Printed circuit board
3-2 ··· Via in printed circuit board
3-3 ··· Main line in printed circuit board
3-4: Shaped wiring in printed circuit board
4-1 to 4-2... Inter-symbol interference suppression resistance
4-3, 4-4... Inter-symbol interference suppression resistance pair
6-1..Chip resistance (for intersymbol interference suppression resistance)
10-1 to 10-2 ... Semiconductor device for data transfer (memory, processor, etc.)
100-1 ... LSI chip
100-2... Substrate on which LSI chip is mounted
100-3 ... LSI chip I / O pad
100-4... I / O pad of substrate on which semiconductor chip is mounted
100-5 ···· Substrate adhesive (BGA-ball etc.)
100-6... Via in substrate on which semiconductor chip is mounted
100-7... In-board wiring for mounting semiconductor chips
100-8 ···· High-resistance wiring in the substrate on which the semiconductor chip is mounted (intersymbol interference suppression resistance wiring)
100-9 ····· Main line in substrate on which semiconductor chip is mounted
Rxd: Driver output resistance of signal transfer master
Rxr ······ Receiver input resistance of signal transfer master
Ryd ····· Driver output resistance of signal transfer slave
Ryr ... Receiver input resistance of signal transfer slave
Ra, Rb: Inter-symbol interference suppression resistance
Zo: Characteristic impedance of main line
Za, Zb ... Characteristic impedance of shaped wiring
tdo: Main line propagation delay time
tda, tdb ... propagation delay time of shaped wiring
Vo ... ・ Drive pulse signal amplitude
tr: Rise time of drive pulse
Tj1, Tj2 ... Jitter
Va1, Va2... Eye opening voltage of eye pattern

Claims

A semiconductor device having a semiconductor chip including a signal input / output circuit and a substrate on which the semiconductor chip is mounted,
The semiconductor device is mounted on a printed circuit board,
The board on which the semiconductor chip is mounted has a value of a difference between a characteristic impedance of a first signal line connecting the semiconductor chip and the printed board and a characteristic impedance of a second signal line on the printed board. And a resistor for connecting the first signal line and the second signal line.

The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the resistor is arranged on the first signal line near the printed circuit board.

A signal transfer system having a semiconductor device and a printed circuit board on which the semiconductor device is mounted,
The first semiconductor device has a first semiconductor chip, a first resistor connected to the printed circuit board, and a first signal line connecting the first semiconductor chip and the first resistor. And
The second semiconductor device has a second semiconductor chip, a second resistor connected to the printed board, and a second signal line connecting the second semiconductor chip and the second resistor. And
The printed circuit board has a third signal line connecting the first semiconductor device and the second semiconductor device,
The characteristic impedance of the first signal line and the characteristic impedance of the second signal line are smaller than the characteristic impedance of the third signal line,
A resistance value of the first resistor is equal to a difference between a characteristic impedance of the third signal line and a characteristic impedance of the first signal line;
A resistance value of the second resistor is equal to a difference between a characteristic impedance of the third signal line and a characteristic impedance of the second signal line;
The output impedance of the driver of the input / output circuit in the first semiconductor device is smaller than the characteristic impedance of the first signal line, and the input impedance of the receiver of the second signal input / output circuit is the second signal line. A signal transfer system characterized by being equal to a characteristic impedance of a signal.

The signal transfer system according to claim 3,
A signal transfer system, wherein a round-trip propagation delay time of a second signal line and a round-trip delay time of a third signal line are longer than a transition time of a signal transferred between input / output circuits and shorter than a cycle of the signal.

A signal transfer system for transferring a signal between a first semiconductor device having a first signal output circuit and a second semiconductor device having a second signal input circuit,
The first signal output circuit is a first signal line, the second signal input circuit is a second signal line, the first signal line and the second signal line are connected by a resistor,
The characteristic impedance of the first signal line is lower than the characteristic impedance of the second signal line, the round-trip delay time of the first signal line is longer than the transition time of the output signal of the signal output circuit, Shorter than the period of the signal,
The resistor has a resistance equal to the difference between the characteristic impedance of the second signal line and the characteristic impedance of the first signal line,
The output impedance of the driver of the signal output circuit is smaller than the characteristic impedance of the second signal line, and the input impedance of the receiver of the signal input circuit is equal to the characteristic impedance of the second signal line. Transfer system.

A semiconductor device having a semiconductor chip including a signal input / output circuit and a substrate on which the semiconductor chip is mounted,
The semiconductor device is mounted on a printed circuit board,
The substrate on which the semiconductor chip is mounted has a second signal line having a characteristic impedance larger than an output impedance of a driver of the signal input / output circuit and smaller than a characteristic impedance of a first signal line on the printed circuit board;
A substrate input / output terminal of a substrate on which the semiconductor chip is mounted has a resistance having a resistance value that is a difference between a characteristic impedance of the first signal line and a characteristic impedance of the second signal line,
A semiconductor device, wherein a round-trip propagation delay time of the second wiring is longer than a transition time of a signal transferred from the signal input / output circuit and shorter than a cycle of the transferred signal.

A semiconductor device having a semiconductor chip including a signal input / output circuit and a substrate on which the semiconductor chip is mounted,
The semiconductor device is mounted on a printed circuit board,
A substrate on which the semiconductor chip is mounted, a first signal line connected to the signal input / output circuit, a second signal line connecting the printed board to input / output terminals of the substrate on which the semiconductor chip is mounted, A resistor for connecting the first signal line and the second signal line,
The printed board has a third signal line connecting the input / output terminal and the printed board,
The characteristic impedance of the first signal line is lower than the characteristic impedance of the third signal line, the characteristic impedance of the second signal line is equal to the characteristic impedance of the third signal line,
The resistor has a resistance value that is a difference between a characteristic impedance of the second signal line and a characteristic impedance of the first signal line;
The semiconductor device according to claim 1, wherein a round-trip delay time of the first signal line is longer than a transition time of a signal transferred from the input / output signal circuit and shorter than a cycle of the transferred signal.

A printed board for mounting a semiconductor device having a semiconductor chip including a signal input / output circuit and a board for mounting the semiconductor chip,
The printed board has a resistance between a board input / output terminal of the semiconductor device and a signal line of the printed board,
A printed circuit board, wherein the resistor has a resistance value that is a difference between a characteristic impedance of a signal line of the board on which the semiconductor chip is mounted and a characteristic impedance of the signal line on the printed circuit board.

A printed board for mounting a semiconductor device having a semiconductor chip including a signal input / output circuit and a board for mounting the semiconductor chip,
The printed circuit board includes a first signal line, a second signal line connecting the printed circuit board and an input / output terminal of the board on which the semiconductor chip is mounted, and the first signal line and the second signal line. And a resistor for connecting
A substrate on which the semiconductor chip is mounted has a third signal line connecting the input / output terminal and the signal input / output circuit,
The characteristic impedance of the second signal line is equal to the characteristic impedance of the third signal line,
The sum of the round-trip delay time of the second signal line and the round-trip delay time of the third signal line is longer than the transition time of the signal transferred from the input / output signal circuit and shorter than the cycle of the transferred signal. ,
A printed circuit board, wherein the resistor has a resistance value that is a difference between a characteristic impedance of the first signal line and a characteristic impedance of the second signal line.

A printed circuit board on which a semiconductor device having a semiconductor chip including a signal input / output circuit is mounted,
The printed circuit board includes a first signal line, a second signal line connecting the printed circuit board to an input / output terminal of the semiconductor device, and a resistor connecting the first signal line and the second signal line. And having
The characteristic impedance of the second signal line is smaller than the characteristic impedance of the first signal line,
A round-trip delay time of the second signal line is longer than a transition time of a signal transferred from the input / output signal and shorter than a cycle of the transferred signal;
A printed circuit board, wherein the resistor has a resistance value that is a difference between a characteristic impedance of the first signal line and a characteristic impedance of the second signal line.

A semiconductor device having a semiconductor chip including a differential signal input / output circuit and a substrate on which the semiconductor chip is mounted,
The semiconductor device is mounted on a printed circuit board having a differential signal line including two signal lines having the same characteristic impedance as a signal transfer path,
The substrate on which the semiconductor chip is mounted includes a differential impedance of a first differential signal line connecting the semiconductor chip and the printed board, and a differential impedance of a second differential signal line formed on the printed board. A semiconductor device having a value of a difference from impedance and comprising a resistor connecting the first differential signal line and the second differential signal line.

The semiconductor device according to claim 11, wherein
The semiconductor device according to claim 1, wherein the resistor is arranged on the first differential signal line near the printed circuit board.

A signal transfer system including a semiconductor device having a differential signal input / output circuit and a printed circuit board on which the semiconductor device is mounted,
The first semiconductor device includes a first semiconductor chip, a first resistor pair connected to the printed circuit board, and a first differential connecting the first semiconductor chip and the first resistor pair. Having a signal line,
The second semiconductor device includes a second semiconductor chip, a second resistor pair connected to the printed circuit board, and a second differential connecting the second semiconductor chip and the second resistor pair. Having a signal line,
The printed circuit board has a third differential signal line connecting the first semiconductor device and the second semiconductor device,
A differential impedance of the first differential signal line and a differential impedance of the second differential signal line are smaller than a differential impedance of the third differential signal line;
Each resistance value of the first pair of resistors is equal to the difference between the differential impedance of the third differential signal line and the differential impedance of the first differential signal line;
Each resistance value of the second resistor pair is equal to the difference between the differential impedance of the third differential signal line and the differential impedance of the second differential signal line;
The output impedance of the driver of the input / output circuit in the first semiconductor device is smaller than the differential impedance of the first differential signal line, and the input impedance of the receiver of the second signal input / output circuit is the second impedance. A signal transfer system, wherein the differential impedance is equal to the differential impedance of the differential signal line.

The signal transfer system according to claim 13,
The round trip propagation delay time of the first differential signal line and the round trip delay time of the second differential signal line are longer than the transition time of the differential signal transferred between the differential input / output circuits, and are longer than the period of the differential signal. A differential signal transfer system characterized by being short.

A signal transfer system for transferring a differential signal between a first semiconductor device having a first differential signal output circuit and a second semiconductor device having a second differential signal input circuit,
The first differential signal output circuit is a first differential signal line, the second differential signal input circuit is a second differential signal line, and the first differential signal line is connected to the second differential signal line. The motion signal lines are connected by a resistor pair,
The differential impedance of the first differential signal line is lower than the differential impedance of the second differential signal line, and the round-trip delay time of the first differential signal line is equal to the output of the differential signal output circuit. Longer than the transition time of the signal, shorter than the cycle of the output signal,
The resistance pair includes a resistance equal to a difference between a differential impedance of the second differential signal line and a differential impedance of the first differential signal line,
The output impedance of the driver of the differential signal output circuit is smaller than the differential impedance of the second differential signal line, and the input impedance of the receiver of the differential signal input circuit is the differential impedance of the second differential signal line. A signal transfer system characterized by being equal to a dynamic impedance.

A semiconductor device having a semiconductor chip including a differential signal input / output circuit and a substrate on which the semiconductor chip is mounted,
The semiconductor device is mounted on a printed circuit board,
A substrate on which the semiconductor chip is mounted has a differential impedance that is greater than the output impedance of the driver of the differential signal input / output circuit and smaller than the differential impedance of the first differential signal line on the printed circuit board. Having a differential signal line,
A substrate input / output terminal of a substrate on which the semiconductor chip is mounted is a resistor including a resistor having a resistance value equal to the difference between the differential impedance of the first differential signal line and the differential impedance of the second differential signal line. Have a pair,
A semiconductor device, wherein a round-trip propagation delay time of the second wiring is longer than a transition time of a differential signal transferred from the differential signal input / output circuit and shorter than a cycle of the transferred differential signal. .

A semiconductor device having a semiconductor chip including a differential signal input / output circuit and a substrate on which the semiconductor chip is mounted,
The semiconductor device is mounted on a printed circuit board,
The substrate on which the semiconductor chip is mounted is a first differential signal line connected to the differential signal input / output circuit, and a second connecting the printed board and the input / output terminal of the substrate on which the semiconductor chip is mounted. A differential signal line, a resistor pair connecting the first differential signal line and the second differential signal line,
The printed board has a third differential signal line connecting the input / output terminal and the printed board,
The differential impedance of the first differential signal line is lower than the differential impedance of the third differential signal line, and the differential impedance of the second differential signal line is the third differential signal line. Equal to the differential impedance of
The resistor pair includes a resistor having a resistance value equal to a difference between a differential impedance of the second differential signal line and a differential impedance of the first differential signal line,
A round-trip delay time of the first differential signal line is longer than a transition time of a differential signal transferred from the input / output differential signal circuit and shorter than a cycle of the transferred differential signal. Semiconductor device.

A printed board for mounting a semiconductor device having a semiconductor chip including a differential signal input / output circuit and a board for mounting the semiconductor chip,
The printed board has a resistor pair between a board input / output terminal of the semiconductor device and a differential signal line of the printed board,
The resistor pair may include a resistor having a resistance value equal to a difference between a differential impedance of a differential signal line on a substrate on which the semiconductor chip is mounted and a differential impedance of a differential signal line on the printed circuit board. Printed circuit board.

A printed board for mounting a semiconductor device having a semiconductor chip including a differential signal input / output circuit and a board for mounting the semiconductor chip,
The printed circuit board includes a first differential signal line, a second differential signal line connecting the printed circuit board and an input / output terminal of a substrate on which the semiconductor chip is mounted, and the first differential signal line and the first differential signal line. A resistor pair for connecting the second differential signal line to the second differential signal line;
A substrate on which the semiconductor chip is mounted has a third differential signal line connecting the input / output terminal and the differential signal input / output circuit,
A differential impedance of the second differential signal line is equal to a differential impedance of the third differential signal line;
The sum of the round trip delay time of the second differential signal line and the round trip delay time of the third differential signal line is longer than the transition time of the differential signal transferred from the input / output differential signal circuit, and Shorter than the period of the differential signal
The printed circuit board according to claim 1, wherein the resistor pair includes a resistor having a resistance value equal to a difference between a differential impedance of the first differential signal line and a differential impedance of the second differential signal line.

A printed circuit board on which a semiconductor device having a semiconductor chip including a differential signal input / output circuit is mounted,
The printed circuit board includes a first differential signal line, a second differential signal line connecting the printed circuit board and an input / output terminal of the semiconductor device, and a first differential signal line and the second differential signal line. A resistor pair for connecting to a motion signal line,
A differential impedance of the second differential signal line is smaller than a differential impedance of the first differential signal line;
A round-trip delay time of the second differential signal line is longer than a transition time of a differential signal transferred from the input / output differential signal, and shorter than a cycle of the transferred differential signal;
The printed circuit board according to claim 1, wherein the resistor pair includes a resistor having a resistance value equal to a difference between a differential impedance of the first differential signal line and a differential impedance of the second differential signal line.