JP2004265283A - Method and apparatus for automatically determining access mode of SPI memory - Google Patents

Abstract

A method of detecting a time interval between a response bit at the head of read data output from a Do port of a serial memory and a head of a read command and determining a memory size based on the time interval is provided with a response bit. This method cannot be applied to an SPI-compliant serial memory. [MEANS FOR SOLVING PROBLEMS] A write process is performed by giving a 4-byte zero (00h) following a write command to the DI port of the memory 1 having the memory size, and performing the next step (step f1). , Four bytes of zero (00h) are given following the read command, and the determination data is read (step f2). Then, the access mode of the memory is determined from the output pattern of 00h in the determination data read in the read processing.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for automatically determining an access mode in a serial memory, particularly in an SPI-compliant serial memory.
[0002]
[Prior art]
In recent years, the capacity of a memory mounted on an electronic device such as a portable terminal has been increasing more and more with the progress of semiconductor technology. It is well known that a memory having a serial interface, which has a small number of input / output ports and is easy to cope with miniaturization, is widely used.
FIG. 7 is a block diagram of a general serial memory and an access timing chart. As shown in FIG. 1A, the general serial memory 11 has at least four ports of DI (input), Do (output), Cs (chip select), and SK (serial clock). .
The DI port is a port for inputting a write command or a read command and a series of serial data specifying an address, and the Do port is a port for outputting serial data read from a memory.
The Cs port is a port for making the memory accessible. When the Cs port is set to a predetermined level, the memory is in an active state, and the data can be written or read. .
Further, the SK port is a port for inputting a serial clock. After setting the Cs port to a predetermined level, the SK port inputs a serial clock and performs predetermined writing and reading in synchronization with the clock signal.
[0003]
FIGS. 2B and 2C are timing charts of writing and reading of the serial memory, respectively.
As shown in FIG. 2B, when writing data to the serial memory, the Cs port is temporarily set from Hi level to Lo level, and a write command, a write address, and a write data are serially transmitted to the DI port. Enter as data.
Then, when the Cs port returns from the Lo level to the Hi level, writing to the memory is executed in synchronization with the serial clock signal.
On the other hand, as shown in FIG. 3C, when reading data from the memory, the Cs port is set from the Hi level to the Lo level, and the serial clock signal is input to the SK port. When a read command, a read address, and dummy data of a required number of bytes are input to the DI port as a series of serial data, data corresponding to the read address is output from the Do port in synchronization with the serial clock signal.
[0004]
Generally, serial memories mounted on electronic devices are provided in various memory sizes, but the serial memories differ only in the bit length of the read or write address depending on the memory size. .
Therefore, if only the bit length of the corresponding address is changed depending on the memory size, it is possible to execute a read / write operation on serial memories having various sizes.
Then, even if the size of the memory mounted on the device or the like is unknown, the timing of the beginning of the serial data input to the DI port and the timing of the read data output from the Do port differs depending on the memory size. A method for automatically recognizing a memory size is disclosed in Japanese Patent Application Laid-Open No. 2000-122921.
[0005]
[Problems to be solved by the invention]
However, the automatic memory size recognition method disclosed in Japanese Patent Application Laid-Open No. 2000-122921 has the following problems.
That is, the memory size automatic recognition method described in the above-mentioned publication is characterized in that when a read command and a read address of a predetermined bit length are input to a DI port of a serial memory whose memory size is unknown, Is detected, and the memory size is determined based on this time interval.
However, in this case, it is assumed that the response bit at the Lo level is added to the head of the read data.
For this reason, for example, there is a problem that this automatic recognition method cannot be applied to a serial memory of a generally widespread interface such as SPI (Serial Peripheral Interface) to which no response bit is added.
The present invention has been made in order to solve the above-mentioned problem, and provides a determination method capable of automatically determining an access mode of a serial memory of an interface compliant with an SPI to which a response bit is not added. The purpose is to:
[0006]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention according to claim 1 is a method of accessing a serial memory conforming to an SPI and automatically determining a memory size of the serial memory, wherein a predetermined size including a write command is included. Supplying initial data having a bit configuration to the serial memory memory and writing the data; and supplying read data having a predetermined bit configuration including a read command to the serial memory after the writing process, Performing a process of reading judgment data based on initial data; and an access mode of the serial memory when the number of bytes of address data required by the memory is defined as a memory access mode based on the judgment data. And performing a process of determining.
[0007]
According to a second aspect of the present invention, in the first aspect, the potential of the data output terminal of the serial memory is at a Hi level, and the initial data is a write command and one byte of 00h, 00h, 00h, 00h following the command. The read data is a read command and one byte of 00h, 00h, 00h, 00h following the command, and the determination data is 3-byte output data read from the memory, and the read determination data is , The access mode of the serial memory is determined from the output pattern of 00h.
[0008]
The invention according to claim 3 is an apparatus for automatically determining the memory size of a serial memory conforming to the SPI, comprising a pull-up resistor for setting a potential of a data output terminal of the serial memory to a Hi level, and An initial data write processing unit that outputs initial write data having a configuration, a determination data read processing unit that reads determination data based on the initial write data while supplying read data having a predetermined bit configuration to the serial memory, A judgment processing unit for judging an access mode of the serial memory based on the judgment data.
[0009]
According to a fourth aspect of the present invention, in the third aspect, the initial write data is a fixed bit string of 00h, 00h, 00h, and 00h of 1 byte following the write command and the command, respectively, and the read data is a read command and a read command. A fixed bit string of 00h, 00h, 00h, 00h of 1 byte following each command. Based on the read determination data, the determination processing unit accesses the serial memory from the output pattern of 00h in the determination data. The mode is determined.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described based on an embodiment shown in the drawings. FIG. 1 is a connection wiring diagram for accessing a serial memory having an SPI-compliant interface by a device for automatically determining a memory size of a serial memory according to the present invention, and a flowchart of an access mode determination process.
As shown in FIG. 1A, this discriminating device is composed of a CPU 2 and a pull-up resistor 3, and Do, DI, SK, and Cs ports of a serial memory 1 whose memory size is unknown and surrounded by a dotted line in FIG. It is connected to each corresponding I / O pin of CPU2.
The Do port is connected to a power supply circuit via a pull-up resistor 3, and the potential is always at Hi level.
In the circuit configuration shown in the figure, the procedure for the CPU 2 to determine the memory size of the memory 1 includes an initial data write process (f1), a determination data read process (f2), and a process shown in the flowchart of FIG. This is realized by sequentially performing the procedure of the determination process (f3).
[0011]
Before describing the processing procedure shown in the flowchart, the data structure of the serial memory of the interface conforming to the SPI, and page writing and reading will be described.
Generally, the concept of a page is used in the serial memory of the SPI interface. This will be described using an 8-bit address memory as an example.
FIGS. 2A and 2B show the data structure of an 8-bit address memory.
In the memory of the 8-bit address shown in FIG. 9A, the address can be specified from 00h to FFh (hexadecimal notation; hereinafter, when address, data, etc. are expressed in hexadecimal notation, h is added at the end). , D1 to D256 (each data is in units of 1 byte), and a total of 256 bytes of data can be written and stored.
[0012]
A group of several bytes of each data in the memory is called one page.
Normally, one page has a page size that is a multiple of 4, such as 4, 8, 16, 32, or 256 bytes, depending on the memory size.
Assuming 4 bytes / page according to the above, the memory of the 8-bit address has a data structure of 64 pages.
[0013]
When writing data to the memory, as shown in the timing chart of FIG. 7B, a write command and a 1-byte address are input to the DI port, and then write data is continuously input for a predetermined number of bytes. . Then, the write data is successively written in the same page one byte at a time starting from the address. For example, when an address is designated as 00h in an 8-bit address memory and four bytes of data are subsequently input as 00h, 01h, 02h, and 03h, addresses 00h to 03h are obtained as shown in FIG. , Data 00h, 01h, 02h, and 03h are successively written to the memory.
[0014]
On the other hand, in the case of reading, an address is input together with a read command, and subsequently, the same number of dummy data as the number of bytes of data to be read is input.
Then, data is successively read out one byte at a time in accordance with the input of the dummy data in the order of addresses continuous from the address.
In addition, in the case of reading, if dummy data is added, reading can be continuously performed regardless of the page. The dummy data may be any data as long as it is one byte.
[0015]
Next, the procedure of the initial data write processing (f1), the determination data read processing (f2), and the determination processing (f3) shown in the flowchart of the present invention in FIG. 1B will be described.
Here, the number of bytes of address data required by the memory is defined as an access mode of the memory, and the memory is classified according to the capacity of the memory as shown in the access mode classification table of FIG.
[0016]
FIG. 4 is a flowchart of the details of the initial data writing process, a fixed bit string output from the CPU for writing the initial data, and a recognition table for each access mode of the fixed bit string.
As shown in the flow of FIG. 4A, in the initial data write processing, after setting the Cs port from the Hi level to the Lo level (f11), the CPU 2 sets the initial data fixed form shown in FIG. Bit strings (1), (2), (3), (4), and (5) are output. That is, first, the write command (1) is output (f12), and subsequently, 4-byte zeros (00h) (2) to (5) are output (f13 to f16).
[0017]
Next, when a predetermined serial clock signal is input to the SK port and the Cs port is returned from the Lo level to the Hi level (f17), the 4-byte zero (00h) is input to the memory 1, and the predetermined address is input. Is written as described later.
When inputting the initial data or reading out the determination data described later, a predetermined signal is given to the Cs port and the SK port as shown in FIG. 7, but for simplicity of description, Hereinafter, the description thereof will be omitted.
[0018]
The four-byte zero (00h) of (2) to (5) in the fixed bit string composed of (1) to (5) output from the CPU 2 to the memory 1 differs depending on the access mode of the memory 1. Will be.
FIG. 4C is a table showing a difference in recognition of the 4-byte zero (00h) for each access mode.
As shown in the figure, in the case of the access mode 1, the first zero (2) is an address (address 0), and the second to fourth zeros (3) to (5) are the first to third write data. (00h).
In the case of access mode 2, the first zero (2) is the upper address, the second zero (3) is the lower address, the third zero (4), and (5) are the first and second write data. (00h).
[0019]
In the case of access mode 3, the first zero (2) is the upper address, the second zero (3) is the middle address, the third zero (4) is the lower address, and the fourth zero (5) is the write. Data (00h) is recognized.
Therefore, in any case, the data is written from the address 0 by the initial data writing process, but the number of bytes to be written differs depending on the access mode of the memory. That is, in the case of the access modes 1, 2, and 3, three bytes, two bytes, and one byte of zero (00h) are written.
[0020]
FIG. 5 is a detailed flowchart of the determination data reading process, a fixed bit string output from the CPU for reading the determination data, and a recognition table for the fixed bit string for each access mode.
As shown in FIG. 5A, in the determination data read processing, first, the Cs port is set from the Lo level to the Hi level (f21), and then the CPU 2 sets the fixed bit string (1) shown in FIG. ), (2), (3), (4), and (5) are output.
That is, first, the read command (1) is output (f22), and then two bytes of zeros (2) and (3) are output. (F23, f24)
[0021]
When the two bytes of zeros (2) and (3) are output, the first determination data is output from the Do port as described later. (F25)
After the second zero (3), the third zero (4) and the fourth zero (5) are output from the CPU 2 (f26, f28), the second determination data, 3 are output from the Do ports (f27, f29), the Cs port is set from the Hi level to the Lo level, and the determination data reading process ends (f30).
The four bytes of zeros (2) to (5) of the fixed bit sequence for reading the determination data are recognized differently for each memory access mode, as in the case of the initial data writing process.
[0022]
FIG. 5C is a table showing a difference in recognition of the 4-byte zeros (2) to (5) for each memory access mode.
As shown in the figure, in the case of the access mode 1, the required number of bytes of the address data is 1, so the first zero (2) is the address (address 0), and the second to fourth 1 byte each Are recognized as dummy data of the output instruction.
In the case of the access mode 2, since the number of bytes of the required address data is 2, the first zero (2) is the upper address, the second zero (3) is the lower address, the third zero, the fourth zero ( 4) and (5) are recognized as dummy data of the output instruction.
[0023]
In the case of the access mode 3, since the number of bytes of the required address data is 3, the first zero (2) is the upper address, the second zero (3) is the middle address, and the third zero (4). Is the lower address, and the fourth zero (5) is recognized as dummy data for output instruction.
Therefore, in any case, data is read from the address 0 by the determination data read processing, but the number of bytes of data read from the memory differs depending on the access mode of the memory.
[0024]
FIG. 6 is a detailed flowchart of the list of read data and the determination process for each access mode in the determination data read process f2.
In the determination data read process, when the first and second zeros (2) and (3) are input to the memory 1 following the read command (1), as shown in FIG. When the memory is in the access mode 1 in exchange for the zero (3), data zero (00h) is read from the address 0 of the memory to the Do port.
However, if the memory is in access mode 2, the first and second zeros (2), (3) specify the upper and lower addresses, and if the memory is in access mode 3, The first and second zeros (2) and (3) specify the upper and middle addresses, respectively.
[0025]
In the case of the access modes 2 and 3, as long as the required number of bytes of the address (2 bytes in the access mode 2 and 3 bytes in the access mode 3) are not input to the memory, the port shown in FIG. The data in the state of FFh is output in hexadecimal notation by the potential suspended at Hi by the pull-up resistor 3 connected to the Do port.
Thus, data obtained from the Do port in exchange for the second zero is used as first determination data.
Similarly, the data read from the Do port in exchange for the third zero (4) and the fourth zero (5) are referred to as second and third determination data, respectively.
[0026]
FIG. 6B is a detailed flowchart of the determination process. The determination process is performed based on the first to third determination data. As shown in FIG. 3, if the first determination data is zero (00h) (f31), the memory in the access mode 1 is used. Is determined.
If the first determination data is other than zero and the second determination data is zero (00h) (f32), the access mode 2 and the second determination data are also other than zero and the third determination data is zero (00h). ), The access mode 3 is determined (f33). If the third determination data is not zero, it is determined that the memory has failed (f34).
[0027]
As described above, by the processing steps shown in FIGS. 4, 5, and 6, the SPI-compliant serial memory can be used in any one of the address modes 1, 2, and 3, that is, whether the number of address bits is 9 bits or less or 16 bits or less. Alternatively, it can be determined whether it is 24 bits or less.
[0028]
【The invention's effect】
As described above, the method for determining the access mode of a serial memory according to the present invention performs a write process on a serial memory having an unknown memory size by giving a 4-byte zero following a write command. A read process is performed by giving 4 bytes of zero following the read command.
Then, the access mode of the memory is determined based on the first, second, and third determination data obtained in the read processing.
As a result, the present invention can reliably and automatically determine the access mode of a memory even if the memory is of a type in which a response bit is not added to read data, such as an SPI interface memory.
Therefore, the memory size determination method of the present invention is extremely effective in providing a method for determining a high processing speed with a very simple low-cost configuration for a serial memory compliant with an SPI whose memory size is unknown.
[Brief description of the drawings]
FIG. 1A is a connection wiring diagram for accessing a memory having an SPI-compliant interface according to the present invention, and FIG. 1B is a flowchart of an access mode determination process .
2A is a diagram illustrating a data structure of an 8-bit address serial memory, and FIG. 2B is a diagram illustrating a state where data is written to the serial memory of FIG. 2A.
FIG. 3 is an access mode classification table.
4A is a detailed flowchart of an initial data writing process, FIG. 4B is a configuration diagram of a fixed bit sequence output from a CPU for writing initial data, and FIG. 4C is a fixed bit sequence of FIG. Recognition table for each access mode.
5A is a detailed flowchart of a determination data reading process, FIG. 5B is a fixed bit sequence output from the CPU for reading the determination data, and FIG. 5C is access to the fixed bit sequence of FIG. Recognition table for each mode.
6A is a list of read data for each access mode in a determination data read process, and FIG. 6B is a detailed flowchart of the determination process.
FIG. 7A is a block diagram of a general serial memory, and FIG. 7B is a timing chart of serial memory access.
[Explanation of symbols]
1. Serial memory of unknown size with SPI interface
2. CPU, 3. Pull-up resistor 11, Serial memory with SPI interface

Claims (4)

A method of accessing a serial memory conforming to the SPI and automatically determining the memory size of the serial memory,
Performing a process of supplying initial data having a predetermined bit configuration including a write command to the serial memory memory and writing the data;
Supplying read data having a predetermined bit configuration including a read command to the serial memory after the write process, and performing a process of reading determination data based on the initial data;
Performing a process of determining the access mode of the serial memory when the number of bytes of address data required by the memory is defined as an access mode of the memory based on the determination data. A method for automatically determining the access mode of a serial memory of an SPI interface. The potential at the data output terminal of the serial memory is at the Hi level, the initial data is a write command and one byte of 00h, 00h, 00h, 00h following the command, and the read data is a read command and the command. Followed by 1 byte 00h, 00h, 00h, 00h, respectively.
The determination data is 3-byte output data read from a memory,
2. The method according to claim 1, wherein an access mode of the serial memory is determined from an output pattern of 00h in the read determination data. An apparatus for automatically determining a memory size of a serial memory conforming to an SPI, comprising a pull-up resistor for setting a potential of a data output terminal of the serial memory to a Hi level,
An initial data write processing unit that outputs initial write data having a predetermined bit configuration; and a determination data read process that reads determination data based on the initial write data while supplying read data having a predetermined bit configuration to the serial memory. Department and
A determination processing unit for determining an access mode of the serial memory based on the determination data, wherein a serial memory access mode automatic determination device for an SPI interface is provided. The initial write data is a fixed bit string of 00h, 00h, 00h, 00h of 1 byte following the write command and the command, respectively, and the read data is 00h, 00h, 1 byte of 1 byte following the read command and the command, respectively. 00h, 00h is a fixed bit string,
4. The SPI interface serial memory according to claim 3, wherein, based on the read determination data, the determination processing unit determines an access mode of the serial memory from an output pattern of 00h in the determination data. Access mode automatic discrimination device.

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