JP2004260372A - Demultiplexer - Google Patents

Abstract

The present invention relates to a demultiplexer suitable for use in a receiver or the like in an optical communication system employing an electric time division multiplexing technique, and to reduce power consumption while maintaining high speed of demultiplexing operation.
SOLUTION: First stage D latches 28 and 32 constituting flip-flops 27 and 31 for signal separation have an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and D latches other than the first stage. Reference numerals 29, 30, and 33 denote low-speed D latches having operating speeds corresponding to electric signals having a bit rate of 6.7 Gb / s.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a demultiplexer (DEMUX) suitable for use in a receiver or the like in an optical communication system employing an electric time division multiplexing technique (ETDM).
[0002]
2. Description of the Related Art In an optical communication system employing an electric time division multiplexing technique, which is a technique for increasing transmission capacity, a transmitter (MUX) for multiplexing electric signals of a plurality of channels into an electric signal of a single channel is indispensable for a transmitter. The demultiplexer must return a multiplexed single-channel electric signal to a multi-channel electric signal.
[0003]
[Prior art]
FIG. 7 is a circuit diagram showing an example of a conventional 1: 2 demultiplexer. In FIG. 7, reference numeral 1 denotes a master-slave-master D flip-flop (Master-Slave-Master D-FF) for signal separation formed by cascade-connecting three D latches 2, 3, and 4; This is a master-slave D flip-flop (Master-Slave D-FF) for signal separation, which is formed by cascade-connecting D latches 6 and 7.
[0004]
FIG. 8 is a circuit diagram showing a configuration of the D latches 2, 3, 4, 6, and 7 (for example, see Patent Document 1). Each of the D latches 2, 3, 4, 6, and 7 is configured by an edge trigger type latch circuit using a source coupled FET logic (SCFL), which is a kind of CML (current mode logic), and has a bit rate of 10 Gb / s. The circuit constants are set so as to have an operation speed corresponding to the electric signal described below.
[0005]
8, GND is a ground power supply, VSS is a negative power supply, D is a positive phase data input terminal, ND is a negative phase data input terminal, C is a positive phase clock input terminal, NC is a negative phase clock input terminal, and Q is a positive phase data input terminal. A data output terminal, NQ, is a negative-phase data output terminal.
[0006]
Reference numerals 8 to 16 denote transistors (for example, HEMT: high electron mobility transistor), and the transistors 8 and 9 constitute a differential pair to which positive-phase input data and negative-phase input data are input. It constitutes a differential pair to which normal phase output data and negative phase output data are input.
[0007]
The transistors 12 and 13 form a differential pair to which a normal phase clock and a negative phase clock are input, the transistors 14 and 15 form a source follower circuit, and the transistors 16 and 18 form a current source. VC1 is a control voltage of the transistor 16, and VC2 is a control voltage of the transistors 17 and 18.
[0008]
Reference numerals 19 to 21 denote diodes for level shift, reference numerals 22 to 26 denote resistors, a resistance 23 is a load resistance of the transistor 8, a resistance 24 is a load resistance of the transistor 9, and resistors 25 and 26 stabilize a current source. It is a resistance for.
[0009]
In the D latch shown in FIG. 8, when the positive-phase clock input terminal C is at the H level and the negative-phase clock input terminal NC is at the L level, the transistors 8 and 9 are activated and the transistors 10 and 11 are deactivated. The input data is output as it is as output data.
[0010]
On the other hand, when the positive-phase clock input terminal C is at L level and the inverted clock input terminal NC is at H level, the transistors 8 and 9 are inactive and the transistors 10 and 11 are active. As a result, the input data becomes The output data immediately before is latched and output without being output.
[0011]
A master-slave-master type D flip-flop can be configured by cascade-connecting three D-latches and alternately inputting clocks having a phase difference of 180 ° to each D-latch. A master-slave type D flip-flop can be configured by cascading two D latches and alternately inputting clocks having a 180 ° phase difference to each D latch.
[0012]
In the conventional 1: 2 demultiplexer shown in FIG. 7, a 10 Gb / s single-channel electric signal DATA obtained by time-division multiplexing two-channel electric signals DATA-A and DATA-B having a bit rate of 5 Gb / s. AB is distributed to D flip-flops 1 and 5;
[0013]
On the other hand, a clock CLK of 5 GHz which is half the frequency of 10 Gb / s which is the bit rate of the electric signal DATA-AB is supplied to the D flip-flops 1 and 5 at phases different from each other by 180 °.
[0014]
As a result, the electric signal DATA-AB is alternately latched by the D flip-flops 1 and 5 at a cycle of 1/10 nsec, and the D flip-flops 1 and 5 output the parallelized 5 Gb / s two-channel electric signal. DATA-A and DATA-B are output.
[0015]
FIG. 9 is a timing chart showing the operation of the conventional 1: 2 demultiplexer shown in FIG. FIG. 9A shows the operation of the D flip-flop 1, and shows the electric signal DATA-AB, the clock CLK, the output of the D latch 3, the reverse phase clock / CLK, and the separated electric signal DATA-A. FIG. 9B shows the operation of the D flip-flop 5, showing the electric signal DATA-AB, the negative-phase clock / CLK, and the separated electric signal DATA-B.
[0016]
The reason why one D flip-flop 1 is a master-slave-master type and the other D flip-flop 5 is a master-slave type is that the output timing of the output signal DATA-A of the D flip-flop 1 is delayed by a half cycle. This is to match the output timing of the output signal DATA-B of the D flip-flop 5.
[0017]
[Patent Document 1]
JP-A-7-273668
[Problems to be solved by the invention]
FIG. 10 is a timing chart for explaining the problems of the conventional 1: 2 demultiplexer shown in FIG. 7, and includes an electric signal DATA-AB, a clock CLK, an output of a D latch 2, an inverted clock / CLK, and a D latch. 3 shows the output.
[0019]
In the D flip-flop 1, the first stage D latch 2 operates with a clock CLK having a frequency (5 GHz) lower than the bit rate (10 Gb / s) of the electric signal DATA-AB. For this reason, the period of the electric signal DATA-A input to the subsequent D latch 3 becomes longer. Assuming that the period of the electric signal DATA-AB is T and the period of the electric signal DATA-A input to the D latch 3 is T ′, T <T ′ <2T.
[0020]
That is, assuming that the bit rate of the electric signal DATA-AB is BR, the bit rate BR ′ of the electric signal DATA-A output from the D latch 2 is (multiplicity 2-1) × BR <BR ′ <multiplicity 2 × BR. As a result, it can be said that the D latches 3 and 4 need a circuit that operates at a lower speed than the D latch 2. Similarly, it can be said that the D-latch 7 is a circuit that operates at a lower speed than the D-latch 6.
[0021]
However, in the conventional 1: 2 demultiplexer shown in FIG. 7, the D-latches 3, 4, and 7 have an operation speed corresponding to an electric signal of 10 Gb / s, like the D-latches 2 and 6. Therefore, there is a problem that current consumption is large.
[0022]
In view of the foregoing, an object of the present invention is to provide a demultiplexer capable of reducing power consumption while maintaining high-speed demultiplexing operation.
[0023]
[Means for Solving the Problems]
The present invention relates to a demultiplexer having a plurality of latch circuits connected in cascade and a plurality of flip-flops for signal separation to which a time-division multiplexed signal is distributed, wherein the plurality of latch circuits include a latch circuit other than a first stage. Is that the operation speed is lower than that of the first-stage latch circuit.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a first embodiment and a second embodiment of the present invention will be described with reference to FIGS.
[0025]
(1st Embodiment ... FIGS. 1-3)
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The first embodiment of the present invention is an application of the present invention to a 1: 2 demultiplexer. In FIG. 1, reference numeral 27 denotes a master-slave-master D flip-flop for signal separation, which is formed by connecting three D latches 28, 29, and 30 in cascade.
[0026]
The D latch 28 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and has a configuration shown in FIG. The D latches 29 and 30 are low speed D latches having an operation speed corresponding to an electric signal having a bit rate of 6.7 Gb / s, and have a configuration described later.
[0027]
Reference numeral 31 denotes a master / slave type D flip-flop for signal separation, which is formed by connecting two D latches 32 and 33 in cascade. The D latch 32 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and has a configuration shown in FIG. The D-latch 33 is a low-speed D-latch having an operation speed corresponding to an electric signal having a bit rate of 6.7 Gb / s, and has a configuration described later.
[0028]
Here, if the period of the electric signal DATA-AB is T and the period of the electric signal DATA-A input to the D latch 29 is T ', then 1T <T'<2T. Therefore, assuming that T 'is 1.5T which is between 1T and 2T, the operation speed of the D latches 29, 30, and 33 can correspond to an electric signal of 10 Gb / s ÷ 1.5 = 6.7 Gb / s. If there is, it will be enough.
[0029]
FIG. 2 is a circuit diagram showing a configuration of the D latches 29, 30, and 33. Here, the gate width of the transistor 16 shown in FIG. 8 is Wg1, the gate width of the transistors 17 and 18 shown in FIG. 8 is Wg2, the resistance value of the resistor 22 shown in FIG. 8 is R1, and the resistance value of the resistors 23 and 24 is R2. 2, the gate width of the transistor 16 shown in FIG. 2 is Wg1 × 0.5, the gate width of the transistors 17 and 18 is Wg2 × 0.5, and the resistance value of the resistor 22 is R1. × 2, the resistance values of the resistors 23 and 24 are R2 × 2, the resistance values of the resistors 25 and 26 are R3 × 2, and the driving current is １ ／ of that in the case of the D latch shown in FIG.
[0030]
As described above, when the drive currents of the D latches 29, 30, and 33 are reduced, the gate widths of the transistors 8 to 15 are reduced so that the bias of each node of the circuit becomes the same as that of the D latches 28 and 32. It is necessary to increase the resistance value by increasing the gate length. Further, since the current density is reduced, the size of the diodes 19 to 21 can be reduced.
[0031]
FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention. FIG. 3A shows the operation of the D flip-flop 27, and shows the electric signal DATA-AB, the clock CLK, the output of the D latch 29, the negative-phase clock / CLK, and the separated electric signal DATA-A. FIG. 3B shows the operation of the D flip-flop 31, showing the electric signal DATA-AB, the negative-phase clock / CLK, and the separated electric signal DATA-B.
[0032]
In the first embodiment of the present invention, a 10 Gb / s single-channel electric signal DATA-AB obtained by time-division multiplexing two-channel electric signals DATA-A and DATA-B with a bit rate of 5 Gb / s is D Distributed to flip-flops 27 and 31.
[0033]
On the other hand, a clock CLK of 5 GHz which is half the frequency of 10 Gb / s which is the bit rate of the electric signal DATA-AB is supplied to the D flip-flops 27 and 31 at phases different from each other by 180 °.
[0034]
As a result, the electric signal DATA-AB is alternately latched by the D flip-flops 27 and 31 at a cycle of 1/10 nsec, and the D flip-flops 27 and 31 output the parallelized 5 Gb / s two-channel electric signal. DATA-A and DATA-B are output.
[0035]
According to the first embodiment of the present invention, the first-stage D latches 28 and 32 constituting the signal-separating flip-flops 27 and 31 have an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s. Since the D-latches 29, 30, and 33 other than the first stage are low-speed D-latches having an operation speed corresponding to an electric signal having a bit rate of 6.7 Gb / s, demultiplexing is performed for each 1: 2 demultiplexer. High-speed operation can be maintained, and current consumption of the D latches 29, 30, and 33 other than the first stage can be reduced, and power consumption can be reduced.
[0036]
In the D latches 29, 30, and 33, when the size of the transistors 8 to 15 is reduced in accordance with the reduction in the drive current, the chip area can be reduced and the chip cost can be reduced. . On the other hand, when the gate length of the transistors 8 to 15 is increased, the power consumption can be further reduced, the reliability of the circuit can be improved, and the yield can be improved.
[0037]
(Second embodiment: FIGS. 4 to 6)
FIG. 4 is a circuit diagram showing a second embodiment of the present invention. The second embodiment of the present invention is an application of the present invention to a 1: 4 demultiplexer. In FIG. 4, reference numeral 34 denotes a signal separating master / slave / master D flip-flop in which three D latches 35, 36 and 37 are connected in cascade. The D latch 35 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s. The D latches 36 and 37 have an operation speed corresponding to an electric signal having a bit rate of 4 Gb / s. It has a low-speed D latch.
[0038]
Reference numeral 38 denotes a master / slave type D flip-flop in which two D latches 39 and 40 are connected in cascade. The D-latch 39 is a D-latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and the D-latch 40 is a low-speed having an operation speed corresponding to an electric signal having a bit rate of 4 Gb / s. D latch.
[0039]
Reference numeral 41 denotes a master-slave-master D flip-flop for signal separation, which is formed by connecting three D latches 42, 43, and 44 in cascade. The D latch 42 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s. The D latches 43 and 44 have an operation speed corresponding to an electric signal having a bit rate of 4 Gb / s. It has a low-speed D latch.
[0040]
Reference numeral 45 denotes a master / slave type D flip-flop in which two D latches 46 and 47 are connected in cascade. The D latch 46 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and the D latch 47 is a low speed having an operation speed corresponding to an electric signal having a bit rate of 4 Gb / s. D latch.
[0041]
Here, the D latches 35, 39, 42, and 46 have the configuration shown in FIG. 8, and the D latches 36, 37, 40, 43, 44, and 47 correspond to the transistors 16, The gate widths of the transistors 17 and 18 are further reduced, and the resistance values of the resistors 22 to 26 are further increased so that the gate-source voltages of the transistors 17 and 18 become the same as those of the transistors 17 and 18 shown in FIG. Can be configured.
[0042]
Reference numeral 48 denotes a toggle flip-flop for dividing the frequency of the clock CLK of 5 GHz and outputting two clocks CLK0 ° and CLK90 ° of 2.5 GHz with a phase difference of 90 °. The clock CLK90 ° is a clock delayed by 90 ° from the clock CLK0 °.
[0043]
In the second embodiment of the present invention, a 10 Gb / s single-channel electric signal obtained by time-division multiplexing four 2.5 Gb / s electric signals DATA-A, DATA-B, DATA-C, and DATA-D is used. The signal DATA-ABCD is distributed to D flip-flops 34, 38, 41, 45.
[0044]
Also, a clock CLK0 ° of 2.5 GHz is supplied to the D flip-flops 34 and 38 at phases different from each other by 180 °, and the electric signals DATA-A and DATA-C in the electric signal DATA-ABCD are output at a period of 1/20 nsec. The data is alternately latched by the flip-flops 34 and 38.
[0045]
Further, a clock CLK90 ° of 2.5 GHz is supplied to the D flip-flops 41 and 45 at phases different from each other by 180 °, and DATA-B and DATA-D in the electric signal DATA-ABCD are D flip-flops at a period of 1/20 nsec. 41 and 45 are alternately latched.
[0046]
As a result, the parallelized 2.5 Gb / s four-channel electric signals DATA-A, DATA-C, DATA-B, and DATA-D are output from the D flip-flops 34, 38, 41, and 45. Will be.
[0047]
FIG. 5 is a timing chart showing the operation of the second embodiment of the present invention, in which the electric signal DATA-ABCD, the clock CLK0 °, the separated electric signals DATA-A, DATA-C, the clock CLK90 °, the separated electric signal The signals DATA-B and DATA-D are shown.
[0048]
FIG. 6 is a timing chart showing the operation of the D flip-flop 34, which shows the electric signal DATA-ABCD, the clock CLK0 °, the output of the D latch 35, the clock / CLK0 °, and the output of the D latch 36.
[0049]
Here, in the D flip-flop 34, the first stage D latch 35 operates with the clock CLK having a frequency (2.5 GHz) lower than the bit rate (10 Gb / s) of the electric signal DATA-ABCD. Therefore, the period of the electric signal DATA-A input to the subsequent D latch 36 becomes longer.
[0050]
Here, assuming that the period of the electric signal DATA-ABCD is T and the period of the electric signal DATA-A input to the D latch 36 is T ′, 2T <T ′ <3T. Therefore, assuming that T ′ is 2.5T which is between 2T and 3T, the operation speed of the D latches 36, 37, 40, 43, 44, and 47 becomes 10 Gb / s ÷ 2.5 = 4 Gb / s electric signal. Anything that can handle it will suffice.
[0051]
According to the second embodiment of the present invention, the first-stage D latches 35, 39, 42, and 46 constituting the signal-separating flip-flops 34, 38, 41, and 45 convert an electric signal having a bit rate of 10 Gb / s. The D-latches 36, 37, 40, 43, 44 and 47 other than the first stage are low-speed D-latches having an operation speed corresponding to an electric signal having a bit rate of 4 Gb / s. Therefore, for the 1: 4 demultiplexer, the high speed of the demultiplex operation is maintained, and the current consumption of the D latches 36, 37, 40, 43, 44, and 47 other than the first stage is reduced, and the power consumption is reduced. Can be planned.
[0052]
In the D latches 36, 37, 40, 43, 44, and 47 other than the first stage, when the size of the transistors 8 to 15 is reduced due to the reduction in the drive current, the chip area is reduced. Cost can be reduced. On the other hand, when the gate length of the transistors 8 to 15 is increased, the power consumption can be further reduced, the reliability of the circuit can be improved, and the yield can be improved.
[0053]
In the first embodiment and the second embodiment of the present invention, the case where the HEMT is used as the transistor has been described. However, a transistor having another structure such as a bipolar transistor may be used.
[0054]
Further, in order to align the phases of the electric signals DATA-A, DATA-C, DATA-B, and DATA-D output from the D flip-flops 34, 38, 41, 45, the D flip-flops 34, 38, 41, 45 A D-latch that operates with a 2.5 GHz clock may be provided at the subsequent stage.
[0055]
【The invention's effect】
As described above, according to the present invention, the operation speed of the latch circuits other than the first stage among the plurality of latch circuits constituting the plurality of flip-flops for signal separation is lower than that of the first stage latch circuit. By using a high-speed latch circuit, the high-speed demultiplexing operation can be maintained, the current consumption of the latch circuits other than the first stage can be reduced, and the power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a low-speed D latch provided in the first embodiment of the present invention;
FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing a second embodiment of the present invention.
FIG. 5 is a timing chart showing the operation of the second embodiment of the present invention.
FIG. 6 is a timing chart showing the operation of a master-slave-master D flip-flop provided in a second embodiment of the present invention.
FIG. 7 is a circuit diagram showing an example of a conventional demultiplexer.
8 is a circuit diagram showing a configuration of a D latch included in the conventional demultiplexer shown in FIG.
FIG. 9 is a timing chart showing the operation of the conventional demultiplexer shown in FIG.
FIG. 10 is a timing chart for explaining problems of the conventional demultiplexer shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Master-slave-master type D flip-flop 2, 3, 4 ... D-latch 5 ... Master-slave type D flip-flop 6, 7 ... D-latch 8-18 ... Transistors 19-21 ... Diodes 22-26 ... Resistor 27 master-slave-master D flip-flops 28, 29, 30 D latch 31 Master-slave D flip-flops 32, 33 D latch 34 Master-slave-master D flip-flop 35 , 36, 37 D latch 38 Master / slave type D flip-flop 39, 40 D latch 41 Master / slave master type D flip-flop 42, 43, 44 D latch 45 Master / slave type D flip-flops 46, 47 ... D latch

Claims (4)

A demultiplexer having a plurality of latch circuits connected in cascade and a plurality of flip-flops for signal separation in which a time-division multiplex signal is distributed,
The demultiplexer is characterized in that, of the plurality of latch circuits, the operation speed of the latch circuits other than the first-stage latch circuit is lower than that of the first-stage latch circuit. 2. The demultiplexer according to claim 1, wherein the latch circuits other than the first-stage latch circuit are configured such that a drive current by a transistor forming a current source is smaller than that of the first-stage latch circuit. 3. The demultiplexer according to claim 2, wherein the latch circuits other than the first-stage latch circuit have a resistance value for applying a feedback to a transistor forming a current source larger than that of the first-stage latch circuit. 3. The demultiplexer according to claim 2, wherein the latch circuits other than the first stage have the same DC bias as the first stage latch circuit.

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