JP2004254078A - Crystal oscillation circuit and bias current setting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a manufacturing yield is lowered because a variation in element manufacturing or the like causes difficulty in constant current biasing as a design value in a crystal oscillation circuit for applying constant current biasing to a direct current bias of an amplifying part by a reference current source. <P>SOLUTION: This crystal oscillation circuit is provided with a plurality of reference resistances of the reference current source for applying constant current biasing to the amplifying part, actually measures bias current, subsequently adjusts a combined reference resistance value by selecting a reference resistance to be used to be able to place the bias current within an allowable range, consequently improving a manufacturing yield. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a crystal oscillation circuit in which a resonance unit including a crystal unit and an oscillation capacitor is excited by an amplification unit configured by complementary field-effect transistors.
[0002]
[Prior art]
As a conventional technique in a crystal oscillation circuit, the configuration and operation of a crystal oscillation circuit particularly suitable for driving with low power consumption will be described with reference to FIG. As shown in FIG. 6, the crystal oscillation circuit 8 includes an oscillation circuit 30 including a reference current source 51, a resonance unit 10, and an amplification unit 20. These all operate using a battery or the like as a power supply.
[0003]
In a general crystal oscillation circuit in which a high resistance is connected between the input and output of the inverter and combined with a resonance unit, the DC bias point is automatically determined to be の of the power supply voltage. It requires about twice the threshold voltage of the transistor, and there is a limit to driving at a low voltage.
[0004]
On the other hand, the crystal oscillation circuit 8 shown in FIG. 6 can determine the DC bias point independently by the reference current source 51 regardless of the power supply voltage, can operate near the threshold voltage of the inverter, and operate at a low voltage. This is a configuration suitable for driving.
Next, each circuit block will be described in detail.
[0005]
First, the configuration of the reference current source 51 will be described. The reference current source 51 includes a reference resistor 42 and a reference current generating means 52. The reference current generating means 52 includes a first column 49 and a second column 50. The first column 49 includes a first PMOSFET (45) and a first NMOSFET (46), and the second column 50 includes a second PMOSFET (47) and a second NMOSFET (48). are doing.
[0006]
The first column 49 and the second column 50 connect the gates of the first PMOSFET (45) and the second PMOSFET (47), and form a first NMOSFET (46) and a second NMOSFET (48). Are connected to each other. The gate and drain of the second PMOSFET 47 are connected, and the gate and drain of the first NMOSFET (46) are connected.
[0007]
The source of the first PMOSFET (45) is connected to the reference resistor 42 at the connection point 44a, and the source of the second PMOSFET (47) is connected to the reference potential 91. The source of the first NMOSFET (46) and the source of the second NMOSFET (48) are connected to the power supply voltage 93. This is a generally known band gap reference type constant voltage circuit, and the voltage of the output terminal 50 a is determined by the reference resistor 42.
[0008]
Next, the oscillation circuit 30 will be described. The oscillation circuit 30 includes the resonance unit 10 and the amplification unit 20. The resonance unit 10 includes a first oscillation capacitor 11, a second oscillation capacitor 12, and a crystal unit 13. For example, when applied to a clock circuit, the resonance unit 10 is adjusted so that the resonance frequency is 32.768 kHz. The amplitude of the crystal unit 13 is amplified by the amplification unit 20, and positive feedback is provided to the resonance unit 10. When applied, the attenuation of the mechanical vibration is compensated and the oscillation continues.
[0009]
The first oscillation capacitor 11 is connected between the reference potential 91 and the input terminal 23a of the amplifier 20, and the second oscillation capacitor 12 is connected between the reference potential 91 and the output terminal 23b of the amplifier 20. The crystal unit 13 is connected between the input terminal 23a and the output terminal 23b of the amplification unit 20.
[0010]
The amplifying section 20 includes an amplifying PMOSFET (21), an amplifying NMOSFET (22), a first high resistance 24, a second high resistance 25, and a first coupling capacitance 26, which operate complementarily to an input signal. It comprises the second coupling capacitance 27.
[0011]
The first high resistance 24 and the second high resistance 25 have a resistance value of several hundred MΩ in consideration of the temperature coefficient and the manufacturing variation of the resistance so that the AC signal of the oscillation circuit 30 is not fed back to the reference current source 51. .
[0012]
The first coupling capacitance 26 and the second coupling capacitance 27 are for transmitting the AC component generated by the oscillation circuit 30 to the gates of the amplifying PMOSFET (21) and the amplifying NMOSFET (22). In consideration of the voltage dividing ratio, the capacitance value is set to 10 times or more the gate capacitance of these MOSFETs. For example, if the gate capacitance is 1 pF, the coupling capacitances 26 and 27 are set to about 10 pF.
[0013]
One terminal of the first coupling capacitor 26 and the second coupling capacitor 27 is connected to the input terminal 23a of the amplifier 20, and the other terminal of the first coupling capacitor 26 is connected to the gate of the amplifying PMOSFET (21). , And the other terminal of the second coupling capacitor 27 is connected to the gate of the amplifying NMOSFET (22). With the first coupling capacitance 26 and the second coupling capacitance 27, the fluctuation of the DC bias point that occurs when a leakage current flows through the input terminal 23a due to humidity or the like can be reduced.
[0014]
The first high resistance 24 is connected between the output terminal 50a of the reference current source 51 and the gate of the amplification PMOSFET (21), and the second high resistance 25 is connected to the output terminal 23b of the amplification unit 20 and the amplification terminal. It is connected between the gate of the NMOSFET (22). Thus, the amplifying PMOSFET (21) is biased at a constant current by the reference current source 51 via the first high resistance 24, and the amplifying NMOSFET (22) is negatively DC-biased by the second high resistance 25. By providing feedback, self-bias is performed in accordance with the result of bias by the amplifying PMOSFET (21).
[0015]
Next, the operation of the crystal oscillation circuit of FIG. 6 will be described in detail. With this configuration of the crystal oscillation circuit, the DC bias point of the amplifier 20 can be determined by the reference current source 51 without depending on the power supply voltage. When the amplifying PMOSFET (21) constituting the amplifying unit 20 is DC-biased near the threshold voltage by the reference current source 51, it operates in a region where the drain current increases exponentially. Here, the reference potential 91 is 0 V, and the power supply voltage 93 is a negative voltage.
[0016]
When the threshold voltage of the amplifying PMOSFET (21) is set to -0.5V and the threshold voltage of the amplifying NMOSFET (22) is set to 0.5V, and the reference current source 51 biases the amplifying PMOSFET (21) near the threshold voltage, The oscillation circuit 30 can operate even when the power supply voltage 93 is -0.5 V.
[0017]
As described above, the amplification factor of the MOSFET in the exponential function region where the gate voltage is equal to or lower than the threshold voltage increases in proportion to the drain current similarly to the current amplification factor of the bipolar transistor. In other words, this means that the characteristics of the oscillation circuit change as the bias current increases or decreases.
[0018]
Patent Document 1 below relates to the oscillation circuit 30 using the constant current bias as described above, and Patent Document 2 relates to the reference current source 51.
[0019]
[Patent Document 1]
JP-A-57-187684 (page 6-7, FIG. 8A)
[Patent Document 2]
JP-A-53-38249 (page 2, FIG. 6 to FIG. 9)
[0020]
[Problems to be solved by the invention]
In the circuit calculation, the bias current flowing through the amplification section of the oscillation circuit 30 shown in the conventional example is calculated based on the width / length (W / L) of the channel of the first PMOSFET constituting the reference current source 51 and the PMOSFET of the amplification section. It is determined by the ratio of W / L and the current flowing in the first column. However, actually, due to the deviation of the MOSFET characteristics due to the processing accuracy of the process and the current error flowing through the reference current source 51 due to the process variation of the reference resistance, the current value does not always become the value calculated by the circuit. Causes variation. This variation causes a reduction in the final production yield.
[0021]
SUMMARY OF THE INVENTION An object of the present invention is to provide a crystal oscillation circuit in which a DC bias point of an amplification unit is set by a reference current source. An object of the present invention is to provide a crystal oscillation circuit which is adjusted to an appropriate value, improves the production yield, and has excellent stability.
[0022]
[Means for Solving the Problems]
In order to achieve the above object, the crystal oscillation circuit of the present invention employs the following configuration.
[0023]
A crystal oscillation circuit according to the present invention includes a resonance unit including an oscillation capacitor and a crystal resonator, an amplification unit that excites the resonance unit, and a reference current source, and the amplification unit according to a reference current generated by the reference current source. A constant current bias is applied to one of the MOSFETs constituting the CMOSFET, and the other MOSFET is self-biased, and the oscillation amplitude is input to both MOSFETs of the amplifying unit in an AC manner, and the oscillation is maintained by positive feedback to the resonance unit. In the circuit, the reference current source is constituted by a reference resistance switching means, a reference resistance selection means, a reference resistance determination means, a plurality of reference resistances, and a reference current generation means. The current flowing through one of the CMOSFETs constituting the unit can be adjusted.
[0024]
In order to suppress the bias current within a certain range, the current flowing through one of the MOSFETs constituting the amplifying unit is measured during the inspection of the electrical characteristics in the form of a silicon wafer, and the reference resistance is determined in accordance with the result. Is determined and stored in the reference resistance determining means. Then, a selection signal is output from the reference resistance selection means based on the determined content, and the reference resistance switching means combines the reference resistances so that the current value falls within a predetermined range.
[0025]
As a result, the deviation of MOSFET characteristics due to the processing accuracy of the process and the deviation of the bias current due to the current error of the reference current source due to the variation of the reference resistance during the process are adjusted during the inspection of the electric characteristics, thereby improving the production yield. To achieve.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the configuration of the crystal oscillation circuit according to the preferred embodiment of the present invention will be described with reference to the drawings.
[0027]
First, the basic configuration of the crystal oscillation circuit of the present invention will be described with reference to the block diagram shown in FIG. The crystal oscillation circuit 8 includes a reference resistance switching unit 1, a reference resistance selection unit 2, a reference resistance determination unit 3, a plurality of reference resistors, and a reference current generation unit 52 including a first column 49 and a second column 50. A reference current source 51 and an oscillation circuit 30 including the resonance unit 10 and the amplification unit 20. These all operate using a battery or the like as a power supply. The oscillating circuit 30 has the same configuration as that of the conventional example, and a detailed description is omitted.
[0028]
Next, the configuration of the reference current source 51, which is a point of the present invention, will be described. Variations in the bias current due to process fluctuations and the like affect the characteristics of the oscillation circuit 30. The feature of the present invention is that a plurality of reference resistors are provided in the reference current source 51 in order to adjust this within a certain range. A bias current flowing through the amplification unit 20 is measured once during the inspection of electrical characteristics in the form of a silicon wafer, and when the current value is out of a set range, a combination of a plurality of reference resistors is changed by an external signal. Thus, it is possible to converge on the bias current value at the time of circuit design. In order to realize this, the reference current source 51 includes the reference resistance switching means 1, the reference resistance selection means 2, the reference resistance determination means 3, and a plurality of reference resistances.
[0029]
Next, a simplest case of a 1-bit switching, which is the simplest case of a specific configuration, will be described with reference to FIG. 2 as a first embodiment. The oscillation circuit 30 is as described above, and the description is omitted. In the reference current source 51 shown in FIG. 2, two reference resistors, a first reference resistor 111 and a second reference resistor 112, are connected in series, and a connection point 12a between the two reference resistors is connected to the reference resistor switching means 1. , The drain electrode of the PMOSFET (201), which is a switch element, is connected, and the source electrode is connected to the reference potential 91. Then, the gate electrode is connected to the output terminal of the inverter 202 constituting the reference resistance selection means 2, and the PMOSFET (201) is turned on / off according to the output of the inverter 202, so that only the first reference resistance 111 is used or Whether to use the combined resistance of the first reference resistance 111 and the second reference resistance 112 can be selected.
[0030]
For example, assuming that the first reference resistor 111 is 5 MΩ and the second reference resistor 112 is 0.5 MΩ, when the input of the inverter 202 is at a high level, the PMOSFET (201) is turned on and the first reference resistor 111 has 5 MΩ. The determined current flows to the reference current generating means 52. Then, the current flowing through the second column 50 of the reference current generating means 52, the W / L of the second PMOSFET (47), and the W / L of the amplifying PMOSFET (21) constituting the amplifying unit 20 of the oscillation circuit 30 are set. , A bias current determined by the ratio flows through the amplifier 20.
[0031]
Further, when the input of the inverter 202 is set to a low level, the PMOSFET (201) is turned off, and the resistance obtained by the parallel combination of the PMOSFET (201) and the second reference resistance 112 and the first reference resistance 111 is almost infinite. The current value is determined by the series combined resistance of the oscillating circuit 30 and the bias current corresponding thereto flows to the amplification unit 20 of the oscillation circuit 30.
[0032]
In this example, when the input of the inverter 202 is at a high level, the combined reference resistance value is 5 MΩ, and when the input of the inverter 202 is at a low level, the combined reference resistance value is 5.5 MΩ. That is, when the initial state is when the input of the inverter 202 is at the high level, the current flowing to the reference current source 51 changes by -10% by setting the input of the inverter 202 to the low level. As a result, the bias current flowing through the amplification section 20 of the oscillation circuit 30 also changes by -10%.
[0033]
As described above, one bit, that is, a two-state bias current can be set according to the input state of the inverter 202. In the case of actual use, since the adjustment range is narrow in setting the current value of one bit, an example in which two bits, that is, four states, can be set will be described as a second embodiment with reference to FIG.
[0034]
The second embodiment of FIG. 3 has a configuration in which the reference current source 51 has a 2-bit bias current adjustment function. As a reference resistor for determining a current flowing in the reference current source 51, a first reference resistor 111, a second reference resistor 112, a third reference resistor 113, and a fourth reference resistor 114 are connected in series from the connection point 44a. I have. The connection point between the first reference resistance 111 and the second reference resistance 112 is 34a, the connection point between the second reference resistance 112 and the third reference resistance 113 is 28a, the third reference resistance 113 and the fourth The connection point with the reference resistor 114 is 12a. The other of the fourth reference resistors 114 is the connection point 10a.
[0035]
One of the electrodes of the PMOSFETs (121) to (124) constituting the reference resistance switching means 1 is connected to these connection points 10a, 12a, 28a and 34a, and the other electrode is connected to the reference potential 91. ing. PMOSFETs (121) to (124) are switch elements that turn on / off by receiving an output from the reference resistance selecting means 2 at the gate electrode. That is, ON / OFF of the PMOSFETs (121) to (124) is determined by the output state of the reference resistance selecting means 2, and a reference resistance to be used is selected.
[0036]
Next, the reference resistance selecting means 2 in FIG. 3 will be described. This is composed of an inverter 210, an inverter 220, and four two-input NAND circuits 131 to 134. As input signals to the four NAND circuits, four types of signal combinations are created from input signals and output signals of the inverters 210 and 220 and input.
[0037]
The combinations of the input states of the inverters 210 and 220 and the output states of the NAND circuits are as shown in the table of FIG. In the table, 1 indicates a high level and 0 indicates a low level. As described above, the reference resistance selecting means 2 can determine different output states depending on the state of the input signal, and such a circuit is generally called a decoder circuit. Since two states of high and low are generated for one input signal, an output state of 2 n can be generated when the number of input terminals is n. It is understood that the output of the input signal is determined by the NAND circuit, which requires 2 n powers.
[0038]
FIG. 4 described above shows an example of a state in which the reference resistance is switched in two bits and four stages. The first reference resistor 111, the second reference resistor 112, the third reference resistor 113, and the fourth reference resistor 114 in FIG. 3 are 5 MΩ, 0.5 MΩ, 0.5 MΩ, and 0.5 MΩ, respectively. As described above, the combined reference resistance value can be changed according to the two input signal states of the reference resistance selection means 2 as shown in FIG.
[0039]
The table of FIG. 4 shows a combined reference resistance value determined by selecting connection or non-connection of the four reference resistances 111 to 114 based on the output state of the NAND circuit, and the rate of change of the bias current caused thereby. .
[0040]
Initially, the state where the inputs of the inverters 210 and 220 in FIG. 3 are 0 and 0, the output of the NAND circuit is 1, 1, 1, and 0, and only the first reference resistance 111 is connected and the combined reference resistance is 5 MΩ. The circuit is designed so that the bias current at that time is 9 nA.
[0041]
In the setting shown in FIG. 4, the combined reference resistance can be changed from the initial state value of 5.0 MΩ to 6.5 MΩ in 0.5 MΩ steps.
The bias current at this time decreases at the same rate with respect to the increase in the connected reference resistance. That is, since the combined reference resistance changes by + 30% from the initial state, the bias current can also be changed by -30% from the initial state.
[0042]
If the number of terminals of the reference resistance selecting means 2 is increased, advantages such as a wide adjustment width and an increase in resolution can be obtained. Thus, the number of terminals can be freely set according to the purpose of use.
[0043]
Once the set reference resistance value must be fixedly stored in some way, for example, a fuse is made of a wiring material such as polysilicon or aluminum which is generally used in LSI manufacturing, and the wiring is formed by laser. It is possible to use a method of disconnecting the wire, burning off the wiring by flowing an overcurrent, or a memory such as a one-time ROM (hereinafter referred to as an OTROM) that can electrically write data to the ROM only once. .
[0044]
Next, a method of setting the reference resistance according to the present invention will be specifically described. Normally, after the end of the LSI manufacturing, electrical characteristics are inspected in a wafer state using an inspection machine called an IC tester. By this inspection, individual IC chips formed on the wafer are sorted into non-defective products and defective products. As described above, the characteristics of the crystal oscillation circuit used in the present invention are greatly affected by the bias current, and those whose bias current deviates from the standard set value due to manufacturing variations are determined to be defective.
[0045]
The graph of FIG. 5 shows a measured value distribution when a bias current is actually measured by a tester for an LSI including a crystal oscillation circuit of the present invention formed on a wafer. The total number of measurements is 1000, the horizontal axis indicates the bias current, and the vertical axis indicates the number within the bias current range. The design value of the bias current at this time is 9 nA.
[0046]
As seen in FIG. 5, the measured values vary widely from 7 nA to 15 nA. Assuming that the inspection standard value is 8 nA to 10 nA, all the values outside the range are defective. In the case of FIG. 5, a defect rate of 25% occurs.
[0047]
When the inspection standard value is 8 nA to 10 nA as in this example, the bias current correction is performed by switching the reference resistance by using the present invention, and the LSI chip of 8 nA to 12.7 nA passes the inspection as a non-defective product. It can be done. The defect rate in this case decreases from 25% before the bias current correction to 7%.
[0048]
The actual bias current correction is performed by measuring a bias current that is an initial value, determining how much correction is to be performed so that the value falls within the inspection standard, and determining the amount of correction to be performed by the reference resistance selecting unit 2 in accordance with the determination. Determine the input state.
[0049]
The reference resistance determining means 3 holds the state, and is configured by using an OTROM or the like as described above. Since the inspection of the LSI is performed for each chip, the above operation is repeatedly performed for each chip.
[0050]
Thus, by measuring the initial value of the bias current and correcting the difference from the design value by the same inspection machine, a chip that was previously defective can be used as a good chip. As a result, the manufacturing yield increases, and the chip unit cost can be reduced.
[0051]
【The invention's effect】
As described above, in the crystal oscillation circuit of the present invention, by arbitrarily setting the reference resistance value, it is possible to increase the rate at which the bias current of the crystal oscillation circuit falls within the range of the design value. The yield can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a basic configuration of a crystal oscillation circuit according to the present invention.
FIG. 2 is a circuit diagram showing a first embodiment of the crystal oscillation circuit of the present invention.
FIG. 3 is a circuit diagram showing a crystal oscillation circuit according to a second embodiment of the present invention.
FIG. 4 is a table summarizing a terminal input state of the reference current source of the present invention and a change ratio of a combined reference resistance value and a bias current value.
FIG. 5 is a graph showing an example of a test result of a crystal oscillation circuit according to the related art.
FIG. 6 is a circuit diagram showing a conventional crystal oscillation circuit.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 reference resistance switching means 2 reference resistance selection means 3 reference resistance determination means 10 resonance unit 20 amplification unit 30 oscillation circuit 42 reference resistance 51 reference current source 52 reference current generation means 91 reference potential 93 power supply voltage 111 first reference resistance 112 2nd reference resistance 113 3rd reference resistance 114 4th reference resistance

Claims (5)

A resonating unit including an oscillation capacitor and a crystal oscillator, an amplifying unit for exciting the resonating unit, and a reference current source, and one of the CMOSFETs constituting the amplifying unit according to a reference current generated by the reference current source A constant current bias, and the other MOSFET is self-biased, and the oscillation amplitude is AC-input to both MOSFETs to maintain oscillation,
The reference current source includes a reference current generating unit, a plurality of reference resistors, a reference resistor switching unit that performs a connection operation of the reference resistors, a reference resistor selection unit that selects a reference resistor to be used, and a selection content of the reference resistor. A crystal oscillation circuit comprising a reference resistance determining means for storing, wherein a current flowing through one of the CMOSFETs constituting the amplification section can be adjusted by arbitrarily selecting a reference resistance. 2. The crystal oscillation circuit according to claim 1,
A crystal oscillation circuit characterized in that the reference resistor comprises a plurality of resistors connected in series. 2. The crystal oscillation circuit according to claim 1,
A crystal oscillation circuit, wherein the reference resistance switching means has one or more switch elements. 2. The crystal oscillation circuit according to claim 1,
A crystal oscillation circuit, wherein the reference resistance selecting means is a decoder circuit. 2. A method for setting a bias current of a crystal oscillation circuit according to claim 1, wherein
When inspecting electrical characteristics in the form of a silicon wafer, a current flowing through one of the CMOSFETs constituting the amplifying section is measured, and a reference resistance to be used is selected according to the result to determine a combined reference resistance value. A bias current setting method for the crystal oscillation circuit, wherein the current is kept within a predetermined range.

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