JP2004247926A - Marker detector, data transfer control apparatus, and digital camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a marker detector capable of detecting markers included in encoded data at a high speed and detect the markers of optional kinds. <P>SOLUTION: A marker register 54 of the marker detector 51 latches marker data MV[15:0] to be detected. Data registers 52, 53 capture and separate segment data SD by each bit length of the marker data MV[15:0] to be detected into a plurality of comparison data. Comparators 55a to 55d compare the marker data to be detected with the comparison data and provide outputs of comparison signals Pa to Pd denoting the comparison result to an address output circuit 59. When any data among a plurality of the comparison data are coincident with the marker data MV[15:0] to be detected on the basis of the comparison result, the address output circuit 59 outputs address data ADR for designating the coincident comparison data, and an address register 57 latches the address data ADR. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an apparatus for detecting an identifier (marker) indicating the type of encoded data from encoded data.
[0002]
[Prior art]
2. Description of the Related Art In an image processing apparatus such as a digital still camera or a digital video camera, light transmitted through an optical system is detected by an image sensor such as a CCD sensor or a CMOS sensor and photoelectrically converted into an image signal. After the image signal is A / D converted to a digital signal, it is subjected to various image processing such as pixel interpolation, color space conversion, contour enhancement and resolution conversion. Next, the signal that has been subjected to the image processing is compressed and encoded according to a predetermined format and then written to a recording medium.
[0003]
Generally, in a compression encoding format such as JPEG or MPEG, a marker code (hereinafter, simply referred to as a “marker”), which is an identifier indicating the type of the encoded data, is embedded in the encoded data. The decoder needs to detect and interpret the marker to decode the encoded data. For example, in the case of JPEG compression encoding, a marker is composed of 2 bytes, and defines an SOF marker indicating the start of a frame, an SOI marker indicating the start of an image, an EOI marker indicating the end of an image, and a definition of a quantization table. DQT markers and the like are defined.
[0004]
A technique for embedding this kind of marker in a compressed file is described in, for example, Japanese Patent Application Laid-Open No. 2002-84493, and a DMA controller having a marker detection function is disclosed in Japanese Patent Application Laid-Open No. 2002-84493. 2002-262099).
[0005]
[Patent Document 1]
JP 2002-84493 A [Patent Document 2]
JP-A-2002-262099
[Problems to be solved by the invention]
Generally, from the viewpoint of improving the speed of the decoding process, it is preferable that the marker detection process is performed by hardware. However, depending on the hardware, there are markers that can be supported and markers that are not supported. In an apparatus incorporating such hardware, a marker that is not supported by hardware must be detected by software processing, but this software processing has caused a reduction in the overall processing speed.
[0007]
Further, the microprocessor handles encoded data in word units such as 32 bits and 64 bits, whereas a marker is composed of about 2 bytes. Therefore, when detecting a marker by software processing, it is necessary to scan each encoded data in units of 2 bytes to detect the marker. In particular, when detecting a marker located on a boundary between coded data of each word (hereinafter, referred to as a “word boundary”), the marker exists in two coded data across the word boundary. There has been a problem that the detection processing is complicated and the overall processing speed is reduced.
[0008]
In view of the above situation, an object of the present invention is to provide (1) a marker detection device capable of detecting a marker included in encoded data at high speed, and (2) a marker detection device capable of corresponding to an arbitrary type of marker, and the marker detection device. Another object of the present invention is to provide a data transfer control device and a digital camera incorporating the above.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a first invention is a marker detection device for detecting marker data embedded in encoded data, wherein the marker detection device detects the encoded data captured in a predetermined word unit at a predetermined cycle. Means for dividing a plurality of comparison data for each bit length of marker data to be detected, a plurality of comparators for comparing the marker data to be detected with each of the comparison data and outputting a comparison result, An address output for outputting address data designating the comparison data when any of the plurality of comparison data matches the marker data to be detected based on the comparison result output from the plurality of comparators And a circuit.
[0010]
According to a second aspect, in the marker detection device according to the first aspect, the encoded data is divided into the plurality of pieces of comparison data such that bit positions overlap each other.
[0011]
According to a third invention, in the marker detection device according to the first or second invention, a marker register for variably holding the marker data to be detected is provided.
[0012]
In a fourth aspect, in the marker detection device according to any one of the first to third aspects, the address output circuit generates a plurality of pieces of address data by adding / subtracting an offset value to / from a current address data value. And a selection circuit that selects and outputs, from the plurality of pieces of address data, address data that specifies the comparison data that matches the marker data to be detected, based on the comparison result. .
[0013]
According to a fifth aspect, in the marker detection device according to any one of the first to fourth aspects, the marker detection device further includes a data register for holding the encoded data inputted one cycle before, and One comparator has a function of comparing the comparison data located on a boundary between the current coded data and the coded data held in the data register with the marker data to be detected.
[0014]
According to a sixth aspect, in the marker detection device according to any one of the first to fifth aspects, the marker detection apparatus further includes an address register for holding address data output from the address output circuit.
[0015]
In a seventh aspect based on the marker detection apparatus according to the sixth aspect, the address register has a plurality of registers for holding a plurality of the address data specifying the detected plurality of the marker data.
[0016]
An eighth invention is a data transfer control device incorporating the marker detection device according to any one of the first to seventh inventions.
[0017]
A ninth invention is a data transfer control device according to the eighth invention, comprising a plurality of DMA (Direct Memory Access) channels for generating address data of the coded data to be transferred. The marker detection device is configured to generate address data that is incorporated in each of the DMA channels and that specifies marker data using the address data.
[0018]
A tenth invention is a digital camera equipped with the data transfer control device according to the eighth or ninth invention.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram schematically showing the configuration of the digital camera according to the present embodiment. The digital camera 1 includes an optical mechanism 10 having a lens group, a prism, an AF (auto focus; automatic focusing) function, an automatic exposure adjustment function, and the like. The incident light IL from the subject passes through the optical mechanism 10, passes through an optical LPF (low-pass filter) 11, and is received by the image sensor 12.
[0020]
Further, the imaging element 12 converts the incident light into an analog image signal AS and outputs the analog image signal AS to the analog signal processing circuit 13. Note that a CCD area sensor or a CMOS area sensor may be used as the image sensor 12. Although not explicitly shown in the figure, the analog signal processing circuit 13 includes a CDS (Correlated Double Sampling) circuit, an AGC (Automatic Gain Control; automatic gain control) circuit, and an A / D conversion circuit. The image sensor 12 outputs a reference signal having a reference level of a normal black level and an image signal including the reference signal alternately in a time-division manner. Therefore, the CDS circuit samples the reference signal and the image signal in order to remove a noise component in the image signal, and extracts and outputs a difference signal between the two signals. The AGC circuit outputs a signal obtained by optimizing the signal level of the difference signal input from the CDS circuit, and the A / D conversion circuit samples the input signal from the AGC circuit and quantizes the signal with a predetermined number of quantization bits. The digital image signal DS obtained by the conversion is output to the integrated circuit unit 14.
[0021]
The integrated circuit unit 14 includes a CPU 18, an SPU (Signal Processing Unit) 16, an RPU (Real-time Processing Unit) 17, a DMA controller (DMAC) 19, an MIU (Memory Interface Unit) 20, a card interface 21, a compression processing unit 22, It comprises an IDU (Image Display Unit) 23 and a TV encoder 24. A plurality of processing modules 16 to 23 are interconnected via a bus 15. The bus 15 includes an address bus, a data bus, a DMA transfer bus, and the like.
[0022]
A RAM (Random Access Memory) 26 and a ROM (Read Only Memory) 27 are connected to the bus 15 via the MIU 20, and a memory card 28 is connected to the bus 15 via the card interface 21.
[0023]
The SPU 16 performs pre-processing such as defective pixel correction on the digital image signal DS input from the analog signal processing circuit 13 and outputs the digital image signal DS to the bus 15 or the RPU 17. The RPU 17 performs various kinds of digital image processing such as shading correction processing, pixel interpolation processing, gamma correction processing, color space conversion processing, contour enhancement processing, and resolution conversion processing on an image signal input from the SPU 16 in real time. have. The signals output from the RPU 17 and the SPU 16 to the bus 15 can be stored in the RAM 26 via the MIU 20 under the control of the CPU 18. The data transfer via the bus 15 may be performed by the DMA controller 19 instead of the CPU 18.
[0024]
The CPU 18 can perform various software processes on the image data read from the RAM 26 by loading and executing the program from the ROM 27. Further, the CPU 18 can activate the compression processing unit 22 and apply image data to the compression processing unit 22 to perform compression encoding, or supply compression-encoded data to perform decoding. The data compressed and encoded by the compression processing unit 22 (hereinafter, referred to as “encoded data”) is transferred to the card interface 21 and written to the memory card 28.
[0025]
In the present embodiment, it is assumed that the compression processing unit 22 executes JPEG encoding / decoding processing. The image data is encoded in segment units, and the above-described markers are embedded in each segment data. FIG. 2 is a diagram schematically showing the structure of the segment data. The segment data is composed of a series of one-byte areas with “0”, “1”,..., “N−1”, “N” (N is a positive integer), and one word (32 bytes) of four bytes. Bits). In this segment data, 2-byte marker data 30 and 31 are inserted. Since the CPU 18 processes data of one word (32 bits) in one cycle, the segment data is divided by a boundary called a word boundary for each 4-byte area. In the present embodiment, the bit length of one word is 32, but the present invention is not limited to this, and the bit length of one word may be expressed as 16, 64, or 128.
[0026]
Further, the CPU 18 can control the captured image data to be displayed on the display device 25. Specifically, the image data output from the RPU 17 is transferred to the TV encoder 24 via the IDU 23, converted to an image format such as the YCbCr format, and then output to the display device 25 for display.
[0027]
In addition, the user of the digital camera 1 can perform framing, exposure adjustment, setting of shutter speed, and determination of a shooting timing of a subject while viewing the image displayed on the display device 25. When the user presses a release button (not shown) at the moment of shooting, the CPU 18 detects the state and controls the RPU 14 to output high-resolution image data. The high-resolution image data output from the RPU 14 is subjected to compression encoding by the compression processing unit 22 and then written to the memory card 28.
[0028]
In the digital camera 1 having the above configuration, the marker detector according to the present embodiment is incorporated in the DMA controller 19. As shown in FIG. 1, the DMA controller 19 includes a bus controller (BC) 19a for controlling the bus 15 and a plurality of DMA channels CH0 to CHn (n is a positive integer of 2 or more), as shown in FIG. As described above, the marker detector 51 is incorporated in the DMA channel CHk (k is any one of 0 to n).
[0029]
Next, a decoding procedure of the encoded data compressed by the compression processing unit 22 will be described with reference to FIG. The RAM (main memory) 26 stores segment data S1, S2 (SD) including marker data M1 to M4. The DMA controller 19 reads out 32-bit segment data (encoded data) SD from the RAM 26 and DMA-transfers it to the compression processing unit 22. In the compression processing section 22, the input FIFO circuit 40 receives the segment data SD transferred by DMA, converts it into an 8-bit signal, and outputs it to the encoder / decoder 41. The encoder / decoder 41 outputs an 8-bit signal obtained by decoding the output signal of the input FIFO circuit 40 to the output FIFO circuit 42. Then, the output FIFO circuit 42 converts the 8-bit signal into 32-bit decoded data DD and sends it out. The decoded data DD is transferred to the RAM 26 by the DMA controller 19 and stored.
[0030]
The marker detector 51 has a function of taking in the segment data SD read by the DMA controller 19 and detecting the marker data M1 to M4 included in the segment data SD. The addresses ADR of the detected marker data M1 to M4 are taken into the CPU 18.
[0031]
FIG. 4 is a diagram schematically showing a circuit configuration of the marker detector 51. The marker detector 51 includes a first data register 52, a second data register 53, an address counter 50, an address output circuit 59, a marker register 54, comparators 55a to 55d, an OR circuit (logical sum operation circuit) 56, and an address register. 57. Further, a data acknowledge signal (DATA Acknowledge signal) Ac and a clock signal CLK are supplied to the marker detector 51, and the marker signal is input to the address counter 50, the second data register 53, and the address counter 50.
[0032]
Further, the marker register 54 holds the marker MV to be detected provided from the CPU 18. The marker register 54 holds the marker data MV [15: 0] of 2 bytes (16 bits) and supplies it to each of the comparators 55a to 55d. Note that, in general, data X [L-1: 0] (L is a positive integer) represents data having an L-bit length, and L data of X [0], X [1], ..., X [L-1] Of 1-bit data. X [p: q] (p and q are positive integers less than L) represent the qth to pth bits of the L-bit data X [L-1: 0].
[0033]
The first data register 52 latches the 32-bit (1 word) segment data SD in each cycle of the clock signal CLK during the high level period of the data acknowledge signal Ac, and stores the 32-bit data Q [31: 0] as the 32-bit data Q [31: 0]. 2 to the data register 53. The second data register 53 latches the data Q [31: 0] input from the first data register 52 for each cycle of the clock signal CLK during the high level period of the data acknowledge signal Ac, and outputs a 32-bit QQ [31]. : 0]. Therefore, the second data register 53 holds data delayed by one cycle as compared with the first data register 52.
[0034]
FIG. 5 schematically shows the structure of the segment data held in the first data register 52 and the second data register 53. The first data register 52 and the second data register 53 hold one-word data Q [31:24] to Q [7: 0] and QQ [31:24] to QQ [7: 0], respectively. , A word boundary WB exists between each word data.
[0035]
The 32-bit data Q [31: 0] and QQ [31: 0] output from the first data register 52 and the second data register 53 are provided for each bit length (= 16) of the marker data MV [15: 0]. The data is divided into a plurality of comparison data Q [31:16], Q [23: 8], Q [15: 0], Q [7: 0] and QQ [31:24], which are supplied to comparators 55a to 55d. You. Specifically, comparison data Q [31:16] of the upper 16 bits of 32-bit data Q [31: 0] is supplied to comparator 55d, and 32-bit data Q [31] is supplied to comparator 55c. : 0], the comparison data Q [23: 8] of the middle 16 bits is supplied to the comparator 55b. The comparison data Q [15: 0] of the lower 16 bits of the 32-bit data Q [31: 0] is supplied to the comparator 55b. ] Has been supplied. The comparator 55a merges the lower 8 bits Q [7: 0] of the data Q [31: 0] and the upper 8 bits QQ [31:24] of the data QQ [31: 0] one cycle before. The comparison data Q [7: 0] + QQ [31:24] are supplied. Therefore, as shown in FIG. 5, these comparison data are divided such that the bit positions overlap each other. The comparison data Q [7: 0] + QQ [31:24] input to the comparator 55a exists on the word boundary WB.
[0036]
Then, the comparators 55a to 55d compare the marker data MV [15: 0] supplied from the marker register 54 with the comparison data, and output comparison signals Pa to Pd as the comparison results. The output level of the comparison signals Pa to Pd is at a high level during a period in which both match, and the output signal is at a low level during a period in which they do not match. The OR circuit 56 supplies a signal obtained by performing a logical sum operation of these comparison signals Pa to Pd to the enable terminal EN of the address register 57.
[0037]
On the other hand, since the address counter 50 counts addresses in word units, address data ADR [31: 2] in word units is obtained by incrementing the address for each pulse of the clock signal CLK during the high level period of the data acknowledge signal Ac. Generate The address data ADR [31: 0] in byte units obtained by adding the lower two bits of the zero value to the address data ADR [31: 2] in word units is supplied to the address output circuit 59. Hereinafter, the address data ADR [31: 0] indicates an address in byte units. Here, the value of the current address data ADR [31: 0] corresponds to the lower 16 bits of the comparison data Q [15: 0] of the 32-bit data Q [31: 0].
[0038]
The address output circuit 59 includes adder / subtractors 60 to 62 for adding / subtracting an offset value (= −1, +1, +2) to / from the current value of the address data ADR [31: 0], and a selection circuit 63. The current address data ADR [31: 0] is directly input to the second input terminal Db of the selection circuit 63. The adder / subtractor 60 specifies the comparison data Q [7: 0] + QQ [31:24] on the word boundary WB by adding “−1” to the current value of the address data ADR [31: 0]. And outputs the generated address data to the first input terminal Da of the selection circuit 63. The adder / subtractor 61 generates address data specifying the comparison data Q [23: 8] by adding “+1” to the current value of the address data ADR [31: 0]. Output to the third input terminal Dc. Then, the adder / subtracter 62 generates address data designating the comparison data Q [31:16] by adding “+2” to the current value of the address data ADR [31: 0]. Output to the fourth input terminal Dd. As described above, the address output circuit 59 can output a plurality of address data that can specify a marker with a relatively simple circuit configuration.
[0039]
The selection circuit 63 selects, based on the signal levels of the comparison signals Pa to Pd, comparison data that matches the detected marker data from among the plurality of address data input to the first input terminal Da to the fourth input terminal Dd. The address data to be specified is selected and output to the address register 57. More specifically, the comparison signals Pa, Pb, Pc, and Pd are input to selection control terminals A, B, C, and D of the selection circuit 63, respectively. , Correspond to the input terminals Da, Db, Dc, Dd of the selection circuit 63. When a high-level comparison signal is input to any of the selection control terminals A to D, address data to be input to the input terminals Da, Db, Dc or Dd corresponding to the selection control terminal is selected and output to the address register 57. You. For example, when the comparator 55c outputs a high-level comparison signal Pc, address data to be input to the third input terminal Dc is selected.
[0040]
The address register 57 latches the data input from the address output circuit 59 at the rising edge of the clock signal CLK during the high-level period of the signal input to the enable terminal EN, and outputs the address data specifying the detected marker. Output as ADR. The CPU 18 can acquire the address data ADR from the address register 57 when necessary.
[0041]
As described above, according to the marker detector 51 according to the present embodiment, it is possible to quickly detect a marker embedded in the segment data SD input in units of words and output the address data ADR specifying the marker. is there. In addition, since this marker detection process is performed in parallel with the DMA transfer process, and is also performed in parallel with the decoding process of the segment data SD in the compression processing unit 22 (FIG. 3), very high processing efficiency is achieved. Markers can be detected.
[0042]
The comparator 55a compares the comparison data Q [7: 0] + QQ [31:24] (FIG. 5) located on the word boundary WB with the marker data MV [15: 0]. Markers on WB can be detected at high speed.
[0043]
Further, since the marker data MV [15: 0] stored in the marker register 54 can be variably set by the CPU 18, it is possible to detect any type of marker at any timing according to the situation.
[0044]
Next, a modified example of the above embodiment will be described. FIG. 6 is a diagram schematically illustrating a part of a circuit configuration of a marker detector 51 according to the present modification. This marker detector 51 has the same configuration as the marker detector 51 shown in FIG.
[0045]
The marker detector 51 according to this modification is characterized in that a register group REG is provided instead of the address register 57. The register group REG includes a plurality of registers 57 ₀ , 57 ₁ ,..., 57 _K that hold K + 1 (K: an integer of 2 or more) address data output from the address output circuit 59. The registers REG is a shift register of K + 1 stages of connecting the K + 1 two registers ₅₇ 0 to 57 _K in series, each register ₅₇ 0 to 57 _K, the clock in the high level period of the output signal of the OR circuit 56 Address data input to terminal D is latched at the rising edge of signal CLK and output from terminal Q. The CPU18 can obtain the address data _AD 0 to AD _K output from the register ₅₇ 0 to 57 _K.
[0046]
Thus can have multiple address data _AD 0 to AD _K by the marker detector 51 comprises a register group REG, it is possible to refer simultaneously by CPU 18. In this modification, a shift register is used for the register group REG. However, a similar effect can be obtained by using a parallel register that holds a plurality of address data in parallel.
[0047]
By the way, as shown in FIG. 1, the DMA controller 19 has a plurality of DMA channels CH0 to CHn. However, as shown in FIG. it may comprise a marker detector ₅₁ 0 to 51 _n having the same configuration as the marker detector 51 in accordance with. This makes it possible to hold different types of marker data in each marker register in the marker detector 51 ₀ to 51 _n, it becomes possible to perform detection processing of a plurality of types of markers parallel and at high speed.
[0048]
【The invention's effect】
As described above, according to the marker detection device of the present invention, it is possible to rapidly detect a marker embedded in encoded data input in units of words and output the address data. A data transfer control device incorporating this marker detection device can detect marker data at high speed in parallel with the transfer of encoded data.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a configuration of a digital camera according to an embodiment of the present invention.
FIG. 2 is a diagram schematically showing a structure of segment data.
FIG. 3 is a block diagram for explaining a procedure for decoding segment data.
FIG. 4 is a diagram schematically showing a circuit configuration of a marker detector according to the embodiment.
FIG. 5 is a diagram schematically showing a structure of segment data.
FIG. 6 is a diagram schematically showing a part of a circuit configuration of a marker detector according to a modified example of the embodiment.
FIG. 7 is a block diagram schematically showing a configuration of a DMA controller according to a modification of the present embodiment.
[Explanation of symbols]
1 digital camera 50 address counters 51 marker detector 52, 53 a data register 54 marker register 55a~55d comparator 56 OR circuits 57, 57 ₀ to 57 _K address register 59 address output circuit

Claims (10)

A marker detection device for detecting marker data embedded in encoded data,
Means for dividing the encoded data taken in a predetermined word unit at a predetermined cycle into a plurality of comparison data for each bit length of marker data to be detected;
A plurality of comparators that output the comparison result by comparing the marker data to be detected with each of the comparison data,
An address for outputting address data specifying the comparison data when any of the plurality of comparison data matches the marker data to be detected, based on the comparison result output from the plurality of comparators. An output circuit;
A marker detection device comprising: 2. The marker detection device according to claim 1, wherein the encoded data is divided into the plurality of pieces of comparison data such that bit positions overlap each other. 3. The marker detecting device according to claim 1, further comprising a marker register variably holding the marker data to be detected. The marker detection device according to any one of claims 1 to 3, wherein the address output circuit comprises:
An addition / subtraction circuit that generates a plurality of address data by adding / subtracting an offset value to / from the current address data value;
A selection circuit that selects and outputs address data that specifies the comparison data that matches the marker data to be detected, from the plurality of address data based on the comparison result;
A marker detection device comprising: In the marker detection device according to any one of claims 1 to 4,
A data register for holding the encoded data input one cycle before;
One of the plurality of comparators is a marker data to detect the comparison data located on a boundary between the current coded data and the coded data held in the data register. A marker detecting device having a function of comparing with a marker. The marker detection device according to any one of claims 1 to 5, further comprising an address register holding address data output from the address output circuit. 7. The marker detecting device according to claim 6, wherein the address register has a plurality of registers for holding a plurality of the address data specifying the detected plurality of the marker data. A data transfer control device incorporating the marker detection device according to any one of claims 1 to 7. The data transfer control device according to claim 8, wherein
A DMA controller having a plurality of DMA (direct memory access) channels for generating address data of the encoded data to be transferred and transferring the encoded data by a DMA method;
The data transfer control device, wherein the marker detection device is incorporated into each of the DMA channels and generates address data specifying marker data using the address data. A digital camera equipped with the data transfer control device according to claim 8.

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