JP2004241844A - Signal processing apparatus and endoscope apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing apparatus and an endoscope apparatus capable of normally displaying a video image with a simple configuration without causing out-of-synchronism and display of an unnecessary junk component even at application of power. <P>SOLUTION: A CCD solid-state imaging device 12 is provided to a tip of an insert part 11 of a scope 10. A processor 20 generates a video signal on the basis of an output from the CCD solid-state imaging device 12. A CPU 22 acts like a video signal output control means for controlling the presence/absence of an output of a video signal to be outputted to a monitor 50 for displaying a video image corresponding to the video signal at application of power synchronously with a prescribed synchronizing signal. Further, the CPU 22 acts like a synchronizing signal output control means for controlling the presence/absence of an output of the synchronizing signal to be outputted to the monitor 50 at application of power. An SSG 25 acts like an output timing adjustment means for adjusting the start timing of the output of the synchronizing signal subjected to output control by the synchronizing signal output control means. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal processing device and an endoscope device that display an image captured by an imaging unit on a video signal display unit.
[0002]
[Prior art]
Conventionally, endoscopes have been widely used in the medical and industrial fields. In recent years, medical endoscopes equipped with a television camera externally equipped with a television camera equipped with an imaging means at the eyepiece of an optical endoscope or an electronic endoscope with a built-in imaging means at the distal end have been recently developed. Electronic endoscope imaging devices that display images on a monitor are also becoming popular.
[0003]
For example, in a medical field combined with a monitor, by turning on the power of the electronic endoscope apparatus at the start of an examination, an endoscopic image in a body cavity can be promptly observed through the monitor, and the lesion can be observed during the examination. It can be developed for early detection and treatment of parts and the like.
[0004]
By the way, a monitor for displaying an endoscope image is of a television system represented by NTSC or PAL. These are for displaying an image by 525 or 625 scanning lines in an interlaced system.
[0005]
FIG. 8 is a timing chart showing a signal supplied to a monitor for displaying such a conventional endoscope image. FIG. 8A shows an odd / even field discrimination signal for discriminating an odd field and an even field. FIG. 8B shows a synchronization signal, and FIG. 8C shows a video signal.
[0006]
As shown in FIGS. 8A, 8B, and 8C, the monitor displays the odd / even field discrimination signal, the synchronization signal, and the video signal even during the out-of-synchronization period Ta from the power-on. Supplied.
[0007]
In recent years, video equipment has been rapidly developed, and an HD television system having 1125 scanning lines and other monitors capable of displaying a high-quality video whose information amount is more than doubled is becoming widespread. It is expected that an endoscope image will be displayed on a monitor. With the use of HD television monitors as well as conventional television monitors in electronic endoscope devices, the role of monitors for observing endoscopic images has become extremely high.
[0008]
There is also a plasma display panel device that can reliably prevent meaningless images from being displayed during an initial operation such as when power is turned on (for example, see Patent Document 1).
[0009]
[Patent Document 1]
JP-A-11-282417 (page 3-5, FIG. 1-4)
[0010]
[Problems to be solved by the invention]
Considering such plasma display devices currently on the market, utilization in the medical field is considered to be unsuitable due to problems such as size, power consumption, and issuance efficiency.
[0011]
In addition, the conventional electronic endoscope apparatus has a circuit configuration in which a video signal and a synchronization signal are simultaneously output when the power is turned on. Therefore, the endoscope displayed on the monitor side as shown in FIG. Until the image is synchronized, an out-of-sync image may be displayed, for example, while flowing horizontally. In addition, during the period required for the initialization at the time of turning on the power, there is a problem that unnecessary dust components such as noise output from the signal processing circuit are also displayed.
[0012]
Even though the power is turned on for a short period of time, for an operator performing many inspections a day, seeing out-of-sync images for each inspection may be a factor that promotes an increase in fatigue. Further, in a state where an out-of-sync image is output or an unnecessary dust component is output, it is not preferable in terms of image quality, and it may not be possible to immediately start operation of the connected device. Was.
[0013]
The present invention has been made in view of the above circumstances, and a signal processing device and an endoscope capable of normally displaying images with a simple configuration without displaying out-of-sync or unnecessary dust components even when the power is turned on. It is intended to provide a mirror device.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, a signal processing device according to claim 1 is a signal processing device that generates a video signal based on an output from an imaging unit, wherein the signal processing device responds to the video signal in synchronization with a predetermined synchronization signal. For the video signal output to the video display means for displaying the video, when the power is turned on, the video signal output control means for controlling the presence or absence of the output of this video signal, and for the synchronization signal output to the video display means At the time of power-on, a synchronization signal output control means for controlling the presence or absence of the output of the synchronization signal, output timing adjustment means for adjusting the start timing of the output of the synchronization signal output controlled by the synchronization signal output control means, It is characterized by having.
[0015]
The signal processing device according to claim 2 is the signal processing device according to claim 1, wherein the output timing adjustment unit adjusts the output start timing of the synchronization signal based on a predetermined signal corresponding to the synchronization signal. It is characterized by doing.
[0016]
The signal processing device according to claim 3 is the signal processing device according to claim 2, wherein the predetermined signal is an odd / even field discrimination signal indicating an odd / even field of a scanning line of the video display unit. The output timing adjusting means performs control so as to start outputting a synchronization signal when the field discrimination signal is switched to an odd field.
[0017]
5. The endoscope apparatus according to claim 4, wherein the endoscope includes an imaging unit, an image display unit that displays an image according to an output from the imaging unit in synchronization with a predetermined synchronization signal, and the image A video signal output control means for controlling whether or not the video signal is output when the power is turned on for a video signal output to the display means; and a power supply for a synchronization signal output to the video display means. A synchronizing signal control means for controlling whether or not the synchronizing signal is output at the time of inputting; and an output timing adjusting means for adjusting a start timing of the synchronizing signal output controlled by the synchronizing signal output control means, A signal processing device for generating a video signal based on an output from the means.
[0018]
The endoscope apparatus according to claim 5, wherein the output timing adjustment unit is configured to output the synchronization signal based on a predetermined signal corresponding to the synchronization signal. Is adjusted.
[0019]
The endoscope apparatus according to claim 6 is the endoscope apparatus according to claim 5, wherein the predetermined signal is an odd / even field discrimination signal indicating an odd / even field of a scanning line of the image display means. The output timing adjusting means controls to start outputting the synchronization signal when the field discrimination signal is switched to the odd field.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment)
1 to 7 relate to an embodiment of the present invention. FIG. 1 is a block diagram showing an entire configuration of an electronic endoscope device, FIG. 2 is an explanatory diagram showing input / output of a latch circuit, and FIG. FIG. 4 is an explanatory diagram showing a second menu screen, FIG. 5 is a timing chart showing an operation of the electronic endoscope apparatus, FIG. 6 is a timing chart showing a mute signal generating operation, and FIG. 9 is a flowchart showing a latch operation of a mute signal.
[0021]
(Constitution)
As shown in FIG. 1, the electronic endoscope apparatus 1 includes a scope 10, a processor 20, and a monitor 50 as a video signal display unit.
[0022]
The scope 10 is an endoscope provided with an image pickup means, and is provided with a CCD solid-state image pickup device 12 as an image pickup means at the tip of an insertion section 11.
[0023]
The processor 20 includes a connector 21, a central processing unit (hereinafter, referred to as a CPU) 22, a drive circuit 23, a preprocessing circuit 24, an SSG (signal sync generator) 25 as a synchronizing signal generation unit, and a red (R), green (G), and blue (B) simultaneous memories 26R, 26G, and 26B, selector circuits 27R, 27G, and 27B, and digital / analog converters (hereinafter, referred to as D / A converters) 28R and 28G. , 28B and post-processing circuits 29R, 29G, 29B, 29S.
[0024]
The connector 21 is electrically connected to the CCD solid-state imaging device 12 provided at the tip of the insertion section 11.
[0025]
The CPU 22 has a control line connected to each circuit, and includes a preprocessing circuit 24, an SSG 25, synchronization memories 26R, 26G, 26B, selector circuits 27R, 27G, 27B, D / A converters 28R, 28G, 28B.
[0026]
The SSG 25 controls the clock (hereinafter referred to as CLK) and the internal synchronization signal so that appropriate signal processing can be performed toward the drive circuit 23, the preprocessing circuit 24, and the synchronization memories 26R, 26G, and 26B based on the control from the CPU 22. Furthermore, an external synchronization signal according to the standard television system is generated and supplied to the synchronization memories 26R, 26G, 26B, the selector circuits 27R, 27G, 27B and the post-processing circuit 29S to perform signal processing and the like. ing.
[0027]
In this embodiment, the standard television system is the NTSC system, and the SSG 25 outputs an interlaced synchronization signal having a field frequency of 59.94 Hz and the number of scanning lines is 525.
[0028]
The drive circuit 23 drives the CCD solid-state imaging device 12 at the tip of the scope 10 via the connector 21 under the control of the CPU 22 to cause the CCD solid-state imaging device 12 to perform imaging.
[0029]
A signal captured by the CCD solid-state imaging device 12 is input to a preprocessing circuit 24 in the processor 20 via the connector 21.
[0030]
The preprocessing circuit 24 includes a plurality of circuits (not shown) described below, and performs preprocessing on an input signal based on control from the CPU 22.
[0031]
Further, the pre-processing will be described in detail. The pre-processing circuit 24 converts the input signal into a correlated double sampling circuit (hereinafter, referred to as a CDS circuit) through a pre-amplifier circuit to perform a correlated double sampling process (hereinafter referred to as a CDS circuit). After the CDS process, the digital video signal is generated by A / D conversion. Next, the preprocessing circuit 24 inputs the generated digital video signal to an OB clamp circuit through an insulating circuit such as a photocoupler and performs a digital clamp process, and further performs a white balance process and an automatic gain control process (hereinafter, referred to as an automatic gain control process). After the AGC process, the color tone is adjusted, and γ correction is performed by a γ correction circuit. Next, the pre-processing circuit 24 performs electronic enlargement / reduction processing on the γ-corrected signal at an enlargement / reduction circuit at an enlargement ratio corresponding to the size of the endoscope image displayed on the monitor by the enlargement / reduction circuit. After the structure emphasis processing and the outline emphasis processing are performed, the data is supplied to the synchronization memories 26R, 26G, and 26B.
[0032]
Synchronization memories 26R, 26G, and 26B have time-sequentially written frame-sequential digital video signals of R, G, and B color components output from the structure enhancement circuit in the preprocessing circuit 24, And output it.
[0033]
The selector circuits 27R, 27G, and 27B add character / mask signals generated from the CPU 22 to the synchronized frame-sequential digital video signals of R, G, and B color components, respectively, or perform menu screens and test screens. (Such as a color bar).
[0034]
Here, since the OB clamp circuit to the selector circuits 27R, 27G, and 27B are configured in a large-scale FPGA (field programmable gate array), they can be programmed and rewritten.
[0035]
The D / A converters 28R, 28G, and 28B respectively perform D / A conversion of the plane-sequential digital video signals of the R, G, and B color components from the selector circuits 27R, 27G, and 27B, and perform analog R, G, and B conversion. The signals are converted into signals and supplied to post-processing circuits 29R, 29G, and 29B, respectively.
[0036]
The post-processing circuits 29R, 29G, and 29B use an internal circuit (not shown) to process analog R, G, and B signals for, for example, synthesizing an image with an endoscope shape detection device or switching an image with a filing device. After performing a synthesis switching process with an input image from an external device as described above, further performing a gain adjustment, and the like, through a 75Ω drive circuit, the monitor 50 or an external recording device such as a video printer (not shown) as an endoscope image. send.
[0037]
The post-processing circuit 29S performs post-processing on the synchronizing signal from the SSG 25, and generates a synchronizing signal corresponding to the analog R, G, and B signals output from the post-processing circuits 29R, 29G, and 29B, and the monitor 50, Send to external recording device.
[0038]
The CPU 22 realizes not only the above-described addition of the character / mask signal and the switching between the menu screen and the test screen, but also the functions included in the pre-processing circuit 24 by operating the keyboard (not shown). And control signals are also sent to the D / A converters 28R, 28G, and 28B to control the output of video signals and synchronization signals.
[0039]
When the power is turned on, the electronic endoscope apparatus 1 outputs the CLK and each synchronization signal from the SSG 25, activates a reset IC (not shown) provided in the CPU 22, and starts a timer. Also, the CPU 22 sends a mute signal of H polarity to the SSG 25 and the D / A converters 28R, 28G, 28B at the same time as the activation of the timer, and independently outputs the video signal and the synchronization signal for a preset time. (Hereinafter referred to as mute).
[0040]
The SSG 25 is provided with a latch circuit 31 shown in FIG.
As shown in FIG. 2, the latch circuit 31 includes an odd / even field discrimination signal a1 for discriminating between an odd field and an even field of the monitor scanning line, and an SSG mute signal b1 from the CPU 22 before latch for muting the synchronization signal. Is entered.
[0041]
The latch circuit 31 latches the SSG mute signal b1 based on the odd / even field discrimination signal a1 and outputs the latched SSG mute signal c1.
[0042]
With such a configuration, the pre-processing circuit 24, the synchronization memories 26R, 26G, 26B, the selector circuits 27R, 27G, 27B, the D / A converters 28R, 28G, 28B, and the post-processing circuits 29R, 29G, 29B. , 29S are signal processing devices for generating a video signal based on the output from the imaging means.
[0043]
The monitor 50 serves as video signal display means for displaying the video signal generated by the signal processing device.
[0044]
The CPU 22 controls a video signal output for controlling whether or not the video signal is output when the power is turned on, in response to a video signal output to a video display unit that displays a video corresponding to the video signal in synchronization with a predetermined synchronization signal. It is a control means.
[0045]
Further, the CPU 22 is a synchronous signal output control means for controlling whether or not the synchronous signal output to the video display means is output when the power is turned on.
[0046]
The latch circuit 31 serves as an output timing adjusting unit that adjusts the start timing of the output of the synchronization signal whose output is controlled by the synchronization signal output control unit.
[0047]
The latch circuit 31 adjusts the output start timing of the synchronization signal based on a predetermined signal corresponding to the synchronization signal.
[0048]
The predetermined signal in the latch circuit 31 is an odd / even field discrimination signal a1 indicating an odd / even field of the scanning line of the video display means.
[0049]
The latch circuit 31 controls so as to start outputting a synchronization signal when the odd / even field discrimination signal a1 is switched to an odd field.
[0050]
(Action)
In such an embodiment, the mute time by the timer of the CPU 22 can be set independently from a keyboard (not shown) using the menu screens 51 and 52 shown in FIGS. 3 and 4, and the mute time of the video signal is synchronized. It is set so that it is always set longer than the signal mute time. Alternatively, the mute time of the synchronization signal may be freely changed, and the mute time of the video signal with respect to the synchronization signal may be fixed.
[0051]
Hereinafter, the operation of the electronic endoscope apparatus will be described with reference to the timing chart of FIG.
FIG. 5 (a) shows the latched SSG mute signal c1, and FIG. 5 (b) shows the latched D / A mute signal d1 supplied by the CPU 22 to the D / A converters 28R, 28G, 28B. 5 (c) shows the odd / even field discrimination signal a1, FIG. 5 (d) shows the synchronizing signal f1 output from the SSG 25, and FIG. 5 (e) shows the analog output from the D / A converters 28R, 28G, 28B. A video signal g1 as R, G, and B signals is shown.
[0052]
The SSG mute signal c1 shown in FIG. 5A changes from H polarity to L polarity after a lapse of a mute time (mute period Tb). When the SSG mute signal c1 has the L polarity, the SSG 25 can output the synchronization signal {synchronization pulse of the synchronization signal f1 shown in FIG. 5E}, and is connected to the outside via the post-processing circuit 29S and the output terminal. Is sent to the monitor 50 or the external recording device (not shown).
[0053]
The D / A mute signal d1 shown in FIG. 5B changes from H polarity to L polarity after the mute time (mute period Tb + Tc) has elapsed. When the SSG mute signal c1 has the L polarity, the D / A converters 28R, 28G, and 28B can output the video signal {the video component of the video signal g1 shown in FIG. 5D}, and the post-processing circuit 29R, The data is sent to the monitor 50 or the external recording device (not shown) via the output terminals 29G and 29B.
[0054]
That is, when the power is turned on, first, the signal output of both the video signal g1 and the synchronization signal f1 is muted. Next, only the output of the video signal g1 is kept muted, but the muting of the synchronization signal f1 is released. The endoscope image is displayed on the monitor 50 according to the flow of mute release of g1, and observation can be started.
[0055]
Here, detailed mute control in the SSG 25 and the D / A converters 28R, 28G, 28B will be described.
[0056]
The mute signal generated by the CPU 22 includes a signal for a video signal and a signal for a synchronization signal, one of which is a D / A converter control signal (D / A mute signal d1), the other is an SSG control signal (SSG mute signal c1). Become.
[0057]
The D / A converter control signal (D / A mute signal d1) controls the video signal g1 output from the D / A converters 28R, 28G, and 28B. The output of the signal g1 is muted, and the output is started at the L polarity. The video signal g1 when the power is turned on is controlled by the D / A converters 28R, 28G, 28B so as to be at the GND level during the mute period.
[0058]
The SSG control signal (SSG mute signal c1) controls the output of the synchronizing signal f1 output from the SSG 25. As described above, the output of the synchronizing signal f1 is muted with H polarity, and output is started with L polarity. It is configured so that
[0059]
The synchronization signal f1 at the time of turning on the power is controlled in the SSG 25 so as to be at the GND level during the mute period. In the SSG 25, an odd / even field discrimination signal a1 shown in FIG. 5C for discriminating odd / even fields in synchronization with the synchronization signal f1 is generated in addition to the synchronization signal f1 in accordance with the NTSC system. The mute signal input from the CPU 22 is latched by this field discrimination signal, and the control of the mute is switched at the beginning of the odd field.
[0060]
Thereby, in the present embodiment, it is possible to prevent the video signal g1 from being unmuted and output an image in the middle of the field. That is, when the mute is released, the video display starts, but the synchronization signal If the mute is released irrespective of f1 (without timing adjustment), an image is displayed on the monitor from the middle of the field of the video signal g1 and the quality is reduced. By adjusting the mute release timing based on the corresponding predetermined signal (odd / even field discrimination signal a1 in the present embodiment), it is possible to prevent the image signal g1 from being output from the middle of the field. it can.
[0061]
Further, in the present embodiment, since image display is started from an odd field, image output can be prevented from starting from an even field in the middle of one frame.
[0062]
Hereinafter, the operation of the latch circuit 31 shown in FIG. 2 in the SSG 25 will be described with reference to the timing chart of FIG.
[0063]
6A shows an odd / even field discrimination signal a1 for discriminating an odd field and an even field, FIG. 6B shows an SSG mute signal b1 before latching, and FIG. 6C shows an SSG mute signal after latching. The mute signal c1 is shown.
[0064]
The latch circuit 31 shown in FIG. 2 in the SSG 25 latches the mute signal as shown in FIG. That is, the latch circuit 31 sets the timing before the odd / even field discrimination signal a1 shown in FIG. 6A switches from the even field to the odd field with respect to the SSG mute signal b1 before the latch shown in FIG. The latch is performed during the period Td, and the latched signal is output as the SSG mute signal c1 shown in FIG.
[0065]
As a result, the synchronization signal f1 output from the SSG 25 shown in FIG. 5E always starts from the odd field with respect to the NTSC system synchronization signal after the end of the mute period. It is sent to the external recording device.
[0066]
Next, the control of the mute time of the SSG 25 by the CPU 22 will be described with reference to FIG.
[0067]
First, when the power is turned on, in step S1 of FIG. 7, the CPU 22 activates the reset IC to generate a reset pulse to reset the timer, and further, the SSG mute signal b1 shown in FIG. To occur.
[0068]
This timer measures the time by using a timer built in the CPU 22. When a reset pulse generated by the reset IC is given, the timer starts the time measurement shown in step S2 in FIG. That is, the CPU 22 starts timer activation measurement in step S2 of FIG.
[0069]
Next, in step S3 in FIG. 7, the CPU 22 determines whether or not the time of the timer has reached the set time. If the time has not reached the set time, the CPU 22 returns to the process in step S2 in FIG. If the time has been reached, the process proceeds to the process of step S4 in FIG.
[0070]
As a result, the timer of the CPU 22 starts time measurement when a reset pulse generated by the reset IC is given, and when the preset time elapses as a mute period, the CPU 22 determines in step S4 of FIG. The polarity is controlled from H polarity to L polarity.
[0071]
The SSG mute signal b1 for SSG control is a time period during which an incorrect synchronization signal is not output to the monitor 50 or the external recording device (not shown) due to an unstable state when the power of the processor 20 is turned on. When the processor 20 and the monitor 50 or the external recording device (not shown) are turned on at the same time, when the connected device of the processor 20 is unstable such as initialization, the synchronization signal is not input for a sufficient time. Set.
[0072]
On the other hand, the mute period by the D / A mute signal d1 for controlling the D / A converter is set to a time sufficient for synchronizing the monitor 50 and the external recording device (not shown).
[0073]
(effect)
According to such an embodiment, when the power is turned on, an odd field, that is, a normal synchronization signal starting from the first line is supplied to the monitor 50 connected to the processor 20 or an external recording device such as a video printer (not shown). And then output the normal video signal g1 from the beginning of the odd field, so that even when the power is turned on, the video can be displayed normally with a simple configuration without any loss of synchronization or unnecessary dust components. In other words, it is possible to reduce the fatigue of the operator who performs the examination many times a day, improve the image quality, and start the operation of the connected device quickly.
[0074]
Further, in the present embodiment, since the synchronization control can be performed on the processor side, the synchronization control can be performed without being affected by the monitor. That is, it is possible to perform the synchronization control that is not affected even when the monitor is changed or different types of monitors.
In this embodiment, the control of the mute signal is muted with the H polarity and released with the L polarity. However, it goes without saying that the polarity may be reversed. Although the NTSC system has been described, other television systems such as PAL, SECAM, and HD television which are the same interlace system may be used. Further, although the mute control of the video output is performed by the D / A converter, in the present embodiment, it may be performed by the selector circuits 29R, 29G, and 29B provided in the FPGA.
[0075]
[Appendix]
According to the above-described embodiment of the present invention, the following configuration can be obtained.
[0076]
(Additional Item 1) An endoscope provided with an imaging means,
Signal processing means for generating a video signal based on an output from the imaging means,
Synchronization signal generation means for generating a synchronization signal;
Video signal display means for displaying the video signal generated by the signal processing means in synchronization with the synchronization signal generated by the synchronization signal generation means,
Video signal output control means for controlling the output to the video signal output to the video display means at the time of power on,
Synchronous signal output control means for controlling the output to the synchronous signal output to the video display means when power is turned on,
Control timing adjustment means for adjusting the control timing of the synchronization signal output control means,
An endoscope apparatus comprising:
[0077]
(Additional Item 2) The endoscope apparatus according to Additional Item 1, wherein the control timing adjusting means adjusts the control timing based on a signal output from the synchronization signal generating means.
[0078]
(Additional Item 3) The endoscope apparatus according to Additional Item 2, wherein the signal output from the synchronization signal generation means is an odd / even field discrimination signal.
[0079]
(Additional Item 4) An electronic endoscope provided with an imaging unit, a signal processing unit that performs signal processing on the imaging unit to generate a video signal, a synchronization signal generation unit that generates a synchronization signal, and the synchronization signal generation unit In an electronic endoscope comprising video display means for displaying the video signal generated by the signal processing means in synchronization with the synchronization signal generated in
A video signal output control unit provided in the signal processing unit and performing output control on a video signal output to the video display unit when power is turned on;
Synchronous signal output control means for controlling the output to the synchronous signal output to the video display means when power is turned on,
Control timing adjustment means for adjusting the control timing of the synchronization signal output control means,
An endoscope apparatus comprising:
[0080]
(Additional Item 5) The video signal output control means and the synchronization signal output control means perform the output stop of the video signal and the synchronization signal for a predetermined time when the power is turned on. Endoscope device.
[0081]
(Supplementary note 6) The output timing control means adjusts the timing of starting the output of the synchronization signal by making the output suspension period variable by the synchronization signal output control means. Endoscope device.
[0082]
【The invention's effect】
As described above, according to the present invention, even when the power is turned on, out-of-synchronization and unnecessary dust components are not displayed, the image can be normally displayed with a simple configuration, and the inspection can be performed many times a day. It is possible to reduce the operator's fatigue, improve the image quality, and quickly start the operation of the connected device.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of an electronic endoscope apparatus according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing inputs and outputs of a latch circuit according to the embodiment of the present invention.
FIG. 3 is an explanatory diagram showing a first menu screen according to the embodiment of the present invention.
FIG. 4 is an explanatory diagram showing a second menu screen according to the embodiment of the present invention.
FIG. 5 is a timing chart showing an operation of the electronic endoscope apparatus according to the embodiment of the present invention.
FIG. 6 is a timing chart showing a mute signal generation operation according to the embodiment of the present invention.
FIG. 7 is a flowchart showing a mute signal latch operation according to the embodiment of the present invention.
FIG. 8 is a timing chart showing signals supplied to a monitor that displays a conventional endoscope image.
[Explanation of symbols]
1. Electronic endoscope device
10. Scope
12… CCD solid-state imaging device
20 ... Processor
21… Connector
22 ... CPU
23… Drive circuit
24 ... pre-processing circuit
25… SSG
26R, 26G, 26B ... Synchronized memory
27R, 27G, 27B ... selector circuit
28R, 28G, 28B ... D / A converter
29R, 29G, 29B, 29S ... post-processing circuit
50… Monitor

Claims (6)

A signal processing device that generates a video signal based on an output from an imaging unit,
In response to a video signal output to a video display unit that displays a video corresponding to the video signal in synchronization with a predetermined synchronization signal, a video signal output control unit that controls whether or not to output the video signal when power is turned on. ,
For a synchronization signal output to the video display means, when power is turned on, a synchronization signal output control means for controlling whether or not this synchronization signal is output,
Output timing adjustment means for adjusting the start timing of the output of the synchronization signal controlled by the synchronization signal output control means,
A signal processing device comprising: 2. The signal processing device according to claim 1, wherein the output timing adjusting means adjusts an output start timing of the synchronization signal based on a predetermined signal corresponding to the synchronization signal. The predetermined signal is an odd / even field discrimination signal indicating an odd / even field of a scanning line of the video display means, and the output timing adjustment means outputs a synchronization signal when the field discrimination signal is switched to the odd field. 3. The signal processing device according to claim 2, wherein control is performed so as to start outputting. An endoscope having imaging means;
In synchronization with a predetermined synchronization signal, video display means for displaying a video according to the output from the imaging means,
For a video signal output to the video display means, when power is turned on, a video signal output control means for controlling the presence / absence of output of the video signal, and a synchronization signal output to the video display means A synchronization signal control unit that controls the presence or absence of the output of the synchronization signal when the power is turned on, and an output timing adjustment unit that adjusts a start timing of the output of the synchronization signal whose output is controlled by the synchronization signal output control unit, A signal processing device that generates a video signal based on an output from the imaging unit,
An endoscope apparatus comprising: The endoscope apparatus according to claim 4, wherein the output timing adjusting means adjusts the output start timing of the synchronization signal based on a predetermined signal corresponding to the synchronization signal. The predetermined signal is an odd / even field discrimination signal indicating an odd / even field of a scanning line of the video display means, and the output timing adjustment means outputs a synchronization signal when the field discrimination signal is switched to the odd field. The endoscope apparatus according to claim 5, wherein control is performed to start output of the endoscope.

Images