JP2004241116A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To overcome the problem wherein power consumption cannot be reduced due to the generation of the excessive discharge in bit lines BL<SB>1</SB>-BL<SB>4</SB>. <P>SOLUTION: This device comprises a plurality of memory cells C, located at the intersections of a plurality of word lines WL and a plurality of bit lines BL, a plurality of data storage circuits 111 connected in one-to-one manner with the plurality of bit lines BL, and a plurality of selectors 112 connected to one of the plurality of bit lines which have one-to-one connection to the plurality of data storing circuits 111, and to which the plurality of connected data storage circuits 111 are connected. Each of the plurality of data storing circuits stores the data stored in one of the plurality of the memory cells connected to the bit lines connected based on control signal READ. Each of a plurality of selectors 112 outputs any one of the data stored in one of the plurality of the memory cells, connected with one of the plurality of the bit lines based on the control signal READ, or the data stored in the plurality of connected data storage circuits 111. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device such as a register file, a cache RAM, an instruction memory, and a data memory.

  Generally, semiconductor memory devices include an asynchronous type and a synchronous type. In an asynchronous semiconductor memory device, when an address is given, data corresponding to the address is always output. In recent years, the demand for high speed has been increased, and the synchronous type has been widely used. In an asynchronous semiconductor memory device, the bit line is charged up through a transistor inside the RAM cell. In a synchronous semiconductor memory device, the charge-up transistor takes over the operation and the read operation is performed. Before the bit line is precharged at high speed. A clock or the like is used as the precharge signal φ for controlling the precharge operation.

  However, the conventional semiconductor memory device has the following problems. That is, in the synchronous semiconductor memory device, for example, since charge-up is performed every cycle of the precharge signal φ, depending on data stored in the memory cell, power consumption becomes enormous as the frequency becomes higher. . For example, when the RAM cell stores "0", the bit line is charged up every clock cycle, "0" is read, and discharge is performed. Therefore, power consumption increases as the frequency increases.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, one of the semiconductor memory devices of the present invention includes a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of word lines arranged at intersections of the plurality of word lines and the plurality of bit lines. A memory cell, a precharge circuit for precharging a plurality of bit lines based on a control signal, a plurality of data storage circuits connected one-to-one with the plurality of bit lines, and a one-to-one connection with the plurality of data storage circuits A plurality of selectors connected to one of a plurality of bit lines connected to and connected to the plurality of data storage circuits connected to the plurality of data storage circuits, each of the plurality of data storage circuits being connected based on a control signal. The data stored in one of the plurality of memory cells connected to one of the plurality of memory cells connected to one of the plurality of bit lines is stored based on a control signal. One Stored in a plurality of data storage circuits are data or connections are stored outputs one of the data is.

  One of the semiconductor memory devices of the present invention includes a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of word lines arranged at intersections of the plurality of word lines and the plurality of bit lines. A memory cell; a plurality of data storage circuits each storing data stored in one of the plurality of memory cells connected to the plurality of bit lines connected one-to-one with the plurality of bit lines; A plurality of selectors connected to one of a plurality of bit lines connected to a plurality of data storage circuits connected one-to-one with the data storage circuit, and activating a plurality of word lines based on address data. A control circuit for controlling a plurality of word lines when address data indicating a continuous address with the address indicated by the previously input address data is not activated. To output the data stored in Luo plurality of data storage circuits.

  The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. The semiconductor memory device of the present invention is configured to selectively output data stored in the data storage means without reading data from a plurality of memory cells, depending on an input address. Therefore, power consumption during reading on the bit line can be reduced.

  Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention. FIG. 1 shows RAM cells 1 and 2 of memory cells in a semiconductor memory device, and NMOSs 3 and 4 connecting the RAM cells 1 and 2 to a bit line BL, respectively. The gate electrode of the NMOS3 is connected to a word line WL _1, the gate electrode of the NMOS4 is connected to the word line WL _2. Gates 5 and 6 are connected to the input sides of the word lines WL ₁ and WL ₂ , respectively. Each of the gates 5 and 6 transmits the address level of each word line selection signal to the word lines WL ₁ and WL ₂ when the precharge signal φ is “0”. Further, a PMOS 7 is provided between the bit line BL and the power supply, which is a precharge means for charging up the bit line BL. Note that the outputs of the pair of CMOS inverters are cross-connected in the RAM cells 1 and 2 to hold the written data. The above configuration is the same as that of the conventional semiconductor memory device, but the semiconductor memory device of the present embodiment is further provided with a two-input NAND gate 10 which is a logic means for controlling the charge-up operation. The NAND gate 10 is configured to receive the precharge signal φ and the enable signal RAME. The condition for charging up the bit line BL includes the condition that the precharge signal φ is “1” and the signal RAME. Is added to the condition that the level is "1".

FIG. 2 is a waveform diagram illustrating the operation of FIG. 1. The operation of FIG. 1 will be described with reference to FIG. It is assumed that the RAM cell 1 connected to the word line WL ₁ holds data of “0”, and the RAM cell 2 connected to the word line WL ₂ holds data of “1”. The signal RAME is supplied as "1" when instructing a read operation. During the cycle Cy1 and the cycle Cy3 shown in FIG. 2, the signal RAME is "1" and the read operation is being performed. In the cycle Cy2, since the signal RAME is "0", no external reading is performed. When reading the data of the RAM cells 1 to activate the address for selecting the word lines WL _1, in the period of a cycle Cy1 and cycle Cy3 in FIG 2, when the precharge signal φ is "1", the charge of the bit lines BL Up is done. However, when the level of the bit line BL before the cycle Cy1 is "1", the level of "1" is maintained. Thereafter, when the precharge signal φ changes to "0", the NMOS 3 is turned on, and the RAM cell 1 is connected to the bit line BL. Since the data held in the RAM cell 1 is "0", the bit line BL is discharged. In the cycle Cy2, the signal RAME is "0", the PMOS 7 is turned off, and the bit line BL is not charged up even if the signal φ becomes "1". When the word line WL ₂ is read is activated by RAM cells 2 data, since the data is held in the RAM cell 2 is "1", the bit line BL is not discharged even once. That is, there is no current consumption due to discharge. As described above, in the present embodiment, since the NAND gate 10 is provided in the conventional synchronous semiconductor memory device, the logic condition of the signal RAME is added to the charge-up condition of the bit line BL. Therefore, when data reading is not required, setting the signal RAME to "0" eliminates the need to charge up the bit line BL. That is, useless precharge current can be reduced by adding a small amount of hardware.

Second Embodiment FIG. 3 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention. Elements common to FIG. 1 are denoted by common reference numerals. As in the first embodiment, this semiconductor memory device includes RAM cells 1 and 2 and NMOSs 3 and 4 for connecting the RAM cells 1 and 2 to the bit lines BL. The gate electrode of the NMOS3 is connected to a word line WL _1, the gate electrode of NMOS4 is connected to the word line WL _2. Between the bit line BL and the power supply, an NMOS 8 serving as precharge means for charging up the bit line BL is connected. This embodiment is different from the first embodiment in that the precharge signal φ is directly input to the gate electrode of the NMOS 8. In addition, each word lines WL _1, WL _2, the output side of the 3-input gates 11 and 12 is a logical unit that activated only when needed the word lines WL _1, WL ₂ are connected, respectively. An address which is a word line selection signal is input to one input terminal of each of the gates 11 and 12. A precharge signal φ and a signal RAME are commonly input to the other input terminals of the gates 11 and 12, respectively. That is, when the precharge signal φ is “0”, the signal RAME is “1”, and the address is “1”, the levels of the word lines WL ₁ and WL ₂ are set to “1”. This is a configuration that functions to perform

FIG. 4 is a waveform diagram illustrating the operation of FIG. 3. The operation of the semiconductor memory device of FIG. 3 will be described with reference to FIG. It is assumed that the RAM cell 1 connected to the word line WL ₁ holds data of “0”, and the RAM cell 2 connected to the word line WL ₂ holds data of “1”. Unlike the first embodiment, the semiconductor memory device of this embodiment always turns on the NMOS 8 and charges up the bit line BL when the precharge signal φ is "1". When reading a "0" of the data held in the RAM cells 1 connected to the word line WL _1, along with the address corresponding to the word line WL ₁ is activated, the precharge signal φ cycle Cy11 in FIG When "1", the bit line BL is charged up. When the signal RAME precharge signal φ is "0" becomes "1", the word line WL ₁ is activated to "1". As a result, the NMOS 3 turns on. When the NMOS 3 is turned on, the bit line BL is discharged because the held data is “0”. In the period of the cycle Cy12, the bit line BL is once precharged, since the word line WL ₁ is not activated, the bit line BL is not discharged. In the subsequent cycle Cy13, even if the precharge signal φ becomes "1", the level of the bit line BL has already become "1", so that a new charge-up is not performed and the data "0" is set. Is read.

If the address corresponding to the word line WL ₂ is read is activated by RAM cells 2 data, since the data is held in the RAM cell 2 is "1", the bit line BL is not discharged even once. That is, there is no current consumption due to discharge. As described above, the gates 11 and 12 provided in the second embodiment, when not needed, and so as not to activate the word lines WL ₁ and the word line WL _2. Therefore, unnecessary discharge on the bit line BL is eliminated, and current consumption is reduced. If the signal RAME becomes "1" before the fall of the precharge signal φ, reading is possible, and the accuracy of the circuit that generates the signal RAME can be reduced.

Third Embodiment FIG. 5 is a circuit diagram of a semiconductor memory device according to a third embodiment of the present invention. The semiconductor memory device is a multi-bit length of RAM used in the register file, etc., and includes a plurality of RAM cells 20 ₁ to 20 _n of the same structure. RAM cells 20 ₁ to 20 _n, the bit line pair BLw, and BLr, the word line pairs WLw, are connected between WLr. Each RAM cell 20 ₁ to 20 _n is 7 transistor configuration, it has become one having a read port R and the write port W, respectively. In each RAM cell 20 ₁ ~20 _n, NMOS21 is connected to the bit line BLw for writing. The output side of the NMOS 21 is connected to a flip-flop in which two inverters 22 and 23 are cross-connected, and the output side of the flip-flop is connected to the gate electrode of the NMOS 24. The output side of the NMOS 24 is connected via the NMOS 25 to the read bit line BLr. The gate electrode of the NMOS 21 is connected to the word line WLw, and the gate electrode of the NMOS 25 is connected to the word line WLr. Between each bit line BLr and the power supply, PMOS 30 ₁ to 30 _n of the pre-charge means for charging up the bit line BLr is connected.

In the semiconductor memory device having such a configuration, when data held in the respective RAM cells 20 ₁ to 20 _n are all "0", power consumption is increased and reads the data. Therefore, in the semiconductor memory device of the present embodiment, the gate 41 which is a writing means for inverting the input data Di0 to Din given to each bit line BLw for writing by the selection signal S, respectively, and each bit line BLr for reading And a gate 42 which is a reading means for inverting the output data Do0-Don read out by the signal S, respectively.

Next, the operation of the semiconductor memory device of FIG. 5 will be described. Depending on the application to be executed, it is checked beforehand whether the data has a large number of "0" or "1" in the data. From the result of this investigation, if there are many "0" s in the data to be written, the level of the signal S is set to "1". When writing data, the write to the RAM cell 20 ₁ to 20 _n by inverting the level of the input data Di0~Din as the write data by the signal S. Thus, the data written into the RAM cells 20 ₁ to 20 _n is a number "1". At the time of data reading, similarly, the read data is inverted by the signal S, and the output data Do0 to Don are inverted and output from each gate 42. As a result, data to be read is output. As described above, in this third embodiment, since the provided gate 41, can be written by inverting the input data Di0~Din the RAM cells 20 ₁ to 20 _n. Therefore, the data held in the RAM cells 20 ₁ to 20 _n is "1" is increased, thereby reducing the Day scan charge amount when they read. That is, current consumption can be reduced.

Fourth Embodiment FIG. 6 is a circuit diagram of a semiconductor memory device according to a fourth embodiment of the present invention. Elements common to FIG. 5 are denoted by the same reference numerals. This semiconductor memory device is different from the semiconductor memory device according to the third embodiment in that an S signal generation circuit 50 as data determination means for determining data Di0 to Din and generating a selection signal S having a level corresponding to the determination result. A RAM cell 51 for storing the output of the S signal generation circuit 50 is provided. The S signal generation circuit 50 is connected to input data Di0 to Din. The S signal generation circuit 50 includes, for example, a majority decision circuit (not shown). If the input data Di0 to Din has "1", the signal S generates "1" indicating non-inversion, and if the "0" is large, it indicates inversion. It has a function to generate "0". The output side of the S signal generation circuit 50 is connected to the write port W of the RAM cell 51 as the storage means. Internal structure of the RAM cell 51 has the same configuration as the other RAM cells 20 ₁ to 20 _n, the RAM51 are connected word line pair WLw, the WLr. The read port R of the RAM 51 is connected to the power supply via the PMOS 52, and is also commonly connected to the input side of the gate 42 that outputs the output data Do0 to Don.

Next, the operation of the semiconductor memory device of FIG. 6 will be described. At the time of writing data, the S signal generation circuit 50 determines whether the input data Di0 to Din have many “1” or many “0”. The level of the signal S is set to "1" when there are many "1" in the determination result, and is set to "0" when there are many "0". The level of the signal S is held as data in the RAM cell 51 and is given to each gate 41. Based on the signal S, the gate 41 is respectively given a reversal or non-inverting level input data Di0~Din the bit line BLw, data to each RAM cell 20 ₁ to 20 _n are written respectively incorporated. When reading data from the RAM cell 20 ₁ to 20 _n, the data stored in the RAM cell 51 is read, the data is provided as a signal S to the gate 42. For data read from the RAM cell 20 ₁ to 20 _n via the bit line BLr, each gate 42 outputs the output data Do0~Don or as a non-inverting inverted. As described above, in the fourth embodiment, since the S signal determination circuit 50 and the RAM cell 51 are further provided in the semiconductor memory device of the third embodiment, what kind of data group the input data Di0 to Din is. Even in this case, the amount of discharge on the bit line BLr can be reduced. That is, current consumption can be reduced.

Fifth Embodiment FIG. 7 is a circuit diagram of a semiconductor memory device according to a fifth embodiment of the present invention. Generally, in a large-capacity RAM, a configuration called column division is adopted in order to ensure performance. This embodiment is intended to reduce the power consumption of a column-divided RAM. FIG. 7 shows a portion related to a read operation of a large-capacity RAM. This semiconductor storage device is a RAM having a capacity of 4 bits × 16 words and includes four columns 60, 70, 80, and 90. Each column 60 to 90 has the same structure, the four RAM cells C0~C3 commonly connected to the word line WL _1, four RAM cells connected in common to the word line WL ₂ C4 to and C7, and four RAM cells C8~C11 commonly connected to the word line WL _3, and four RAM cells connected in common to the word line WL ₄ C12-C15, has. Each RAM cell C0, C4, C8, C12 are connected to the bit lines BL ₁ orthogonal to the word lines WL ₁ to WL _4. Similarly, each RAM cell C1, C5, C9, C13 to the bit line BL _2, each RAM cell C2, C6, C10, C14 is the bit line BL _3, each RAM cell C3, C7, C11, C15 is BL ₄ It is connected to the. Each bit line BL ₁ to BL ₄ are respectively connected to a power source via four NPMOSt1~t4 a precharge circuit.

Each of the word lines WL _{1 to} WL ₄ is connected to a decoder (decoder) 100 for decoding an address. The read control unit 110 is connected to the output side of the bit lines BL _{1 to} BL ₄ of each column 60 to 90. The output side of the read control unit 110 is connected to four selectors (Sel) 120, 130, 140, and 150, which are output means corresponding to each of the columns 60 to 90. The lower two bits of the address are given to the selectors 120, 130, 140, and 150. Each of the selectors 120 to 150 selects the output of the read control unit 110 corresponding to each of the columns 60 to 90 based on the lower two bits. Output. The gate electrode of NMOSt1~t4 of each column 60 to 90, the output-side connection of the gate 160 is a precharge signal φ and read operation control signal READ control means to input charge-up of the bit lines BL ₁ to BL ₄ a Have been. This signal READ is also connected to the decoder 100 and the read control unit 110. The features of the semiconductor memory device of this embodiment are that this signal READ is used and that the read control unit 110 and the gate 160 are provided in a conventional semiconductor memory device.

The inside of the read control unit 110 is configured by the same circuit corresponding to each of the columns 60 to 90. In each of its circuits, each bit line BL ₁ to BL ₄ includes four data storage unit 111a for storing the data on the bit lines BL ₁ to BL _4, respectively, 111b, 111c, and 111d. The output side of the data storage means 111 a to 111 d, the selector 112a selecting means for selecting and outputting data on the storage data and the bit lines BL ₁ to BL ₄ of the data storage means 111 a to 111 d, 112b, 112c, 112d Connected to each other. A signal READ is commonly applied to each of the data storage units 111a to 111d as a write enable WE, and a signal READ is commonly input to each of the selectors 112a to 112d.

FIG. 8 is a time chart showing the operation of FIG. 7, and the operation of the semiconductor memory device of FIG. 7 will be described with reference to FIG. This semiconductor memory device is given a 4-bit address. The upper two bits of the address are the row address. The same read operation of the semiconductor memory device is performed for each of the columns 60 to 90, and each of the selectors 120 to 150 outputs the data held in the RAM cell selected in each of the columns 60 to 90 to the output data Do1 to Do1, respectively. Output as Do3. In the presence address A is given, the signal φ and the signal READ becomes "1", each NMOSt1~t4 are turned on, the bit lines BL ₁ to BL ₄ are precharged respectively as shown in FIG. After the precharge operation, the signal φ is "0", and the decoder 100 is activated such as word line WL ₁ indicated by the upper 2 bits of the address A. Than this, each bit line BL ₁ to BL _4, data in the RAM cell C0~C3 are given respectively. Data on the bit lines BL ₁ to BL ₄ is the selection of the selectors 112 a to 112 d, is given to the selector 120-150. At this time, since the signal READ is "1", the data of the RAM cells C0 to C3 are stored in the data storage units 111a to 111d, respectively. The selectors 120 to 150 make a selection based on the lower two bits of the address A, and select, for example, the data of the RAM cell C0 in each of the columns 60 to 90. The data of each of the selected RAM cells C0 is output as output data Do1 to Do3.

  Subsequently, when address A + 1 is applied, signal φ remains "0". Also, the level of the signal READ is “0”. In this state, each of the selectors 112a to 112d selects the data stored in the data storage means 111a to 111d and supplies it to the selectors 120 to 150. The selectors 120 to 150 select the data of the RAM cells C1 in the columns 60 to 90, respectively. The data of each of the selected RAM cells C1 is output as output data Do1 to Do3. The same operation as when address A + 1 is applied is also performed at addresses A + 2 and A + 3, and the data in RAM cells C2 and C3 are read. That is, in the case of an address having the same row address as the previously read data, reading is possible without setting the signal READ to “1”. This semiconductor memory device is mainly used for an instruction cache RAM. In the instruction cache RAM, the address is incremented to +1 except when a branch occurs, so that a READ signal can be easily generated by using a counter circuit or the like. Only when the lower two bits of the address are "0" or a branch address, the level of the signal READ may be set to "1". As described above, in the fifth embodiment, since the read control unit 110 and the gate 160 are provided in the conventional semiconductor memory device, data corresponding to a continuous address can be read from the data storage units 111a to 111d. Power consumption of the bit line can be reduced as compared with the related art. When the semiconductor memory device of this embodiment is used as an instruction cache, the power consumption of the read operation can be reduced to a maximum of 1/4.

Sixth Embodiment FIG. 9 is a circuit diagram of a semiconductor memory device according to a sixth embodiment of the present invention, in which components common to those in FIG. This semiconductor storage device is a RAM having a capacity of 4 bits × 16 words, and has four columns 60, 70, 80, and 90 as in the fifth embodiment. A read control unit 110 is connected to the output side of the bit lines BL _{1 to} BL ₄ of each column 60 to 90, and the output side of the read control unit 110 includes four selectors 120, 130, 140, and 150 are connected. In this embodiment, a decoder 100A different from the decoder 100 of the fifth embodiment is provided, and an address control unit 170 is provided. The gate electrode of NMOSt1~t4 bit lines BL ₁ to BL ₄ and the power source connected to precharge circuit between each column 60 to 90, a configuration directly precharge signal φ is inputted.

The address control unit 170 includes an address storage unit 171 that stores upper two bits of an address corresponding to data stored in each of the data storage units 111a to 111d as a tag, and a flag circuit 172 of a flag unit that outputs a valid signal valid as a flag. And a comparator 173 which is a comparing means for comparing the upper two bits of the given address with the tag stored in the address storage means 171, and outputs a coincidence signal S 173 output from the comparator 173 based on the signal valid. And an AND gate 174. The output side of the AND gate 174 is commonly connected to the plurality of selectors 112a to 112d in the read control unit 110, and is also connected to the word line control circuit 190 via the inverter 180. The AND gate 174, the inverter 180, and the word line control circuit 190 constitute a control unit, and perform a read operation of the RAM cell. The output signal of the inverter 180 is also used as a write enable signal WE for the address storage unit 171 and the data storage units 111a to 111d. The word line control circuit 190 includes four two-input AND gates 191 to 194 each having one input terminal connected to four output terminals of the decoder 100A. The output terminal of the inverter 180 is commonly connected to the other input terminal of each of the AND gates 191 to 194. The output side of the AND gates 191 to 194 are respectively connected to word lines WL ₁ to WL _4.

FIG. 10 is a time chart showing the operation of FIG. Signal φ is "1", the bit lines BL ₁ to BL ₄ is charged up. If the signal valid is "0" in this state, the level of "0" is output from the AND gate 174. The decoder 100A outputs the high-order two bits of the decoded result of the address A, the word line control circuit 190, for example, the level of the word line WL ₁ is set to "1". Thus, data in each RAM cell C0~C3 is read to the bit lines BL ₁ to BL _4. Data on the bit lines BL ₁ to BL ₄ are stored in the fifth embodiment similarly to the data storage means 111 a to 111 d, also, the upper two bits of the address is stored in the address storage unit 171. When an address is stored in the address storage unit 171, the signal valid output from the flag circuit 172 becomes "1". At this time, each of the selectors 120 to 150 makes a selection based on the lower two bits of the address, and one of the data of the RAM cells C0 to C3 is output as output data Do1 to Do3.

Then, for example, when the address A + 1 is given, the signal φ is again "1", the bit lines BL ₁ to BL ₄ is charged up. Here, when the upper two bits of the address A + 1 are the same as the address A, the comparator 173 outputs the signal S of “1”, and the gate 174 outputs the signal S of “1” as it is. Output signal S of the gate 174 via the inverter 180 is applied to the word line control circuit 190, the level of each word line WL ₁ to WL ₄ are all "0". That is, all the word lines WL _{1 to} WL ₄ are not activated. At the same time, the selectors 112a to 1112d to which the signal S of "1" is given select the data of the data storage units 111a to 111d and supply them to the selectors 120 to 150. Each of the selectors 120 to 150 selects the data of the RAM cell C1 in each of the columns 60 to 90 according to the lower two bits of the address A + 1. The data of each of the selected RAM cells C1 is output as output data Do1 to Do3. The same operation as when address A + 1 is applied is performed at addresses A + 2 and A + 3, and the data in RAM cells C2 and C3 are read. That is, when the address having the same row address as the previously read data, since each word line WL ₁ to WL ₄ does not activate, the discharge of the bit line does not occur. If tag a different address stored by the address storing means 171 is inputted, the level of the signal S173 becomes "0", the reading of data for each bit lines BL ₁ to BL ₄ is performed, a new Then, data is stored in the data storage units 111a to 111d and tags are stored in the address storage unit 171.

As described above, in the sixth embodiment stores the read data in the data storage means 111a~111d and once activated bit lines BL ₁ to BL _4, the upper which is a tag address 2 bits are the same some data, without activating the word lines WL ₁ to WL _4, since reads from the data storage means 111 a to 111 d, excess discharge is not generated in the bit lines BL ₁ to BL _4, power consumption can be reduced . Also, since the address control unit 170 that outputs the timing of reading data from the data storage units 111a to 111d by itself is provided, it can be used not only as an instruction cache RAM but also as a data cache or an independent general RAM or ROM. Is possible. The present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(1) In the first, second, fifth, and sixth embodiments, examples in which the present invention is applied to a RAM are shown, but the present invention is also applicable to a ROM.
(2) Although the third and fourth embodiments show examples in which the present invention is applied to a RAM, the present invention can be applied to a ROM if write data is selected by inverting or non-inverting from the beginning and written. is there.
(3) In the fifth embodiment, when the upper two bits of the applied address is the same as the previous address has a configuration that does not perform the charge-up of the bit lines BL ₁ to BL _4, implementation of the sixth example the word lines WL ₁ to WL ₄ as a configuration that does not activate may be performed a reduction in current consumption.
(4) In the sixth embodiment, when the upper two bits of the applied address is the same as the previous address has a configuration that does not activate the word lines WL ₁ to WL _4, the bit lines BL ₁ to BL The same effect can be expected even if the charge-up of ₄ is not performed.
(5) In the fourth embodiment, the inversion and non-inversion are performed by the gates 41 and 42 using the S signal generation circuit 50 constituted by a majority circuit, but the sign bits of the input data Di0 to Din (for example, It is also possible to perform inversion and non-inversion using the upper 2 bits). In this case, the probability that the inversion and the non-inversion are appropriate is inferior to that of the above embodiment, but since there are usually more data with a small absolute value, a sufficient effect can be expected even if a sign bit is used. Further, even if the RAM cell 51 is not separately provided, a RAM cell holding sign bit data can be used instead.

FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a waveform diagram illustrating the operation of FIG. 1. FIG. 6 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention. FIG. 4 is a waveform diagram illustrating the operation of FIG. 3. FIG. 9 is a circuit diagram of a semiconductor memory device showing a third embodiment of the present invention. FIG. 11 is a circuit diagram of a semiconductor memory device showing a fourth embodiment of the present invention. FIG. 11 is a circuit diagram of a semiconductor memory device according to a fifth embodiment of the present invention. 8 is a time chart showing the operation of FIG. FIG. 14 is a circuit diagram of a semiconductor memory device showing a sixth embodiment of the present invention. 10 is a time chart illustrating the operation of FIG. 9.

Explanation of reference numerals

1,2,20O ~20n, C0~C16 RAM cell _{7,8,30 0 ~30 n, t1~t4 PMOS,} NMOS ( precharge circuit)
10, 11, 12 Logic means 41, 42 Writing means, reading means 50 S signal generation circuit (input data determination means)
51 storage means 111a-111d data storage means 112a-112d selector (selection means)
120-150 Selector (output means)
160 control means 171 address storage means 172 flag means 173 comparator (comparison means)
BL, BL ₁ ~BL ₄ bit lines WL, WL1 ~WL ₄ word line

Claims (7)

Multiple word lines,
A plurality of bit lines crossing the plurality of word lines;
A plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines;
A precharge circuit for precharging the plurality of bit lines based on a control signal;
A plurality of data storage circuits connected one-to-one with the plurality of bit lines;
A plurality of selectors connected one-to-one with the plurality of data storage circuits and connected to one of the plurality of bit lines connected to the plurality of connected data storage circuits;
Each of the plurality of data storage circuits, based on the control signal, stores data stored in one of the plurality of memory cells connected to the connected bit line,
Based on the control signal, each of the plurality of selectors stores data stored in one of the plurality of memory cells connected to one of the plurality of bit lines or the plurality of connected plurality of memory cells. A semiconductor memory device for outputting any one of data stored in a data storage circuit. 2. The semiconductor memory device according to claim 1, further comprising a decoder for activating one of the plurality of word lines based on the address data. The plurality of data storage circuits may store data stored in the plurality of memory cells connected to a common word line at a time via the plurality of bit lines connected to the memory cell. 3. The semiconductor memory device according to claim 2, wherein: 4. The semiconductor memory device according to claim 3, wherein said selector outputs said data stored in said plurality of data storage circuits when a part of said address data is equal. Multiple word lines,
A plurality of bit lines crossing the plurality of word lines;
A plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines;
A plurality of data storage circuits connected one-to-one with the plurality of bit lines and respectively storing data stored in one of the plurality of memory cells connected to the connected bit lines;
A plurality of selectors connected one-to-one with the plurality of data storage circuits and connected to one of the plurality of bit lines to which the plurality of connected data storage circuits are connected;
A control circuit for controlling activation of the plurality of word lines based on the address data,
The control circuit does not activate the plurality of word lines when inputting address data indicating an address continuous with the address indicated by the previously input address data. A semiconductor memory device for outputting stored data. The control circuit includes:
A decoder for decoding the address data;
An address control unit that determines whether an address indicated by the input address data is continuous with an address indicated by the previously input address data,
6. The semiconductor memory device according to claim 5, further comprising: a word line control circuit that controls whether to activate the plurality of word lines based on an output of the address control unit. The address control unit includes:
An address storage unit that stores, as a tag, some common data of the address data corresponding to the data stored in the data storage circuit;
A flag unit that outputs a valid signal as a flag,
A comparing unit that outputs a comparison result between the input address data and the tag,
7. The semiconductor memory circuit according to claim 6, comprising: a logic circuit that outputs the comparison result based on the valid signal.

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