JP2004241004A - Semiconductor storage device - Google Patents

Abstract

A semiconductor memory device having a small memory cell size, good readout of stored data, and high layout flexibility is provided.
A volatile part A and a non-volatile part B composed of a CMOS latch circuit and pass transistors (six transistors) are connected via a bit line pair of bit lines BL and BL_. In the non-volatile section B, one electrode of each of the ferroelectric capacitors C1 and C2 is connected to a bit line pair via the source-drain electrodes of the selection transistors ST1 and ST2. The gate electrodes of the select transistors ST1 and ST2 are connected to the word line WL2. The other electrodes of the ferroelectric capacitors C1 and C2 are connected to the plate line PL.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a volatile part and a nonvolatile part.
[0002]
[Prior art]
As a type of semiconductor memory device, so-called semiconductor memory, there is a random access memory (RAM). The RAM is basically volatile and retains recording data while the power is on, but loses the recording data when the power is off. Therefore, a nonvolatile RAM has been proposed in which a nonvolatile portion is connected to a volatile portion so that print data is retained even after the power is turned off.
[0003]
FIG. 10 shows an example of a configuration of a memory cell of a nonvolatile static RAM (hereinafter, simply referred to as nonvolatile SRAM). The memory cell of the nonvolatile SRAM shown in FIG. 10 includes a volatile portion A and a nonvolatile portion B. The volatile part A can store two values of “1” and “0”. For example, in the case of a complementary metal oxide semiconductor (CMOS) type SRAM, the volatile portion A is configured by a latch circuit of four MOSs (metal oxide semiconductors) and two pass transistors, as shown in FIG. That is, the volatile part A has six transistors. Although the configuration is omitted in FIG. 10 to be described later, the non-volatile section B can also store binary values.
[0004]
In order to improve the efficiency, such a nonvolatile SRAM memory cell generally uses a volatile section A having good performance while the power is on, and uses a nonvolatile nonvolatile section B while the power is off. Works. Therefore, data is exchanged between the volatile unit A and the nonvolatile unit B. For example, when the power is switched from on to off, the storage data of the volatile portion A is written to the non-volatile portion B, which is called “store”. When the power is switched from off to on, the non-volatile portion B Writing stored data to the volatile portion A is called "recall".
[0005]
The non-volatile section B can be configured by using a ferroelectric capacitor. Patent Document 1 listed below describes a nonvolatile SRAM memory cell in which a nonvolatile portion B is formed using a ferroelectric capacitor.
[0006]
[Patent Document 1]
JP-A-64-68699
[0007]
FIG. 11 shows an example of a configuration of a memory cell in which a nonvolatile portion B is formed using a ferroelectric capacitor and a transistor described in Patent Document 1. As described above, the volatile portion A is constituted by the latch circuit composed of four MOSs and two pass transistors. That is, the volatile part A has six transistors.
[0008]
The non-volatile section B- (1) is configured as follows. One electrode of each of the ferroelectric capacitors C11 and C12 is connected to the two storage nodes N1 and N2 of the volatile unit A via the selection transistors ST11 and ST12, respectively. One electrode of each of the ferroelectric capacitors C11 and C12 is further connected to a ground line via a selection transistor ST21 or ST22. The other electrodes of the ferroelectric capacitors C11 and C12 are connected to the plate line PL. The two selection transistors ST21 and ST22 on the ground line side are required as a reset circuit for setting the voltage applied to the ferroelectric capacitors C11 and C12 to 0 V before reading data.
[0009]
FIG. 12 shows another example of the configuration of the memory cell in which the nonvolatile portion B is formed using only two ferroelectric capacitors. In the non-volatile section B-2 shown in FIG. 12, the ferroelectric capacitors C13 and C14 are directly connected to the two storage nodes N1 and N2 of the volatile section A, respectively. Therefore, the entire memory cell has only six transistors and two capacitors, and its size is small.
[0010]
As described above, a nonvolatile SRAM using a ferroelectric capacitor can be combined with a volatile portion to form a nonvolatile SRAM.
[0011]
[Problems to be solved by the invention]
However, the memory cell as an example of the above-described nonvolatile SRAM has a configuration including ten transistors and two ferroelectric capacitors in total. That is, in this case, there is a problem that the size of the memory cell becomes large because the memory cell includes the reset circuit.
[0012]
In the memory cell of another example of the above-described nonvolatile SRAM, one electrode of the ferroelectric capacitors C13 and C14 is directly connected to the storage nodes N1 and N2 of the volatile portion A. Therefore, this node potential is applied to dielectric capacitors C13 and C14. The continuous application of an electric field in one direction to the ferroelectric capacitors C13 and C14 is called imprint, and the hysteresis loop becomes asymmetric. Therefore, in this case, there is a problem that erroneous reading of the storage data in the nonvolatile portion B- (2) is likely to occur.
[0013]
Further, in the above-described nonvolatile SRAM memory cell, it is difficult to arrange the volatile part and the nonvolatile part separately, so that the degree of freedom in layout is low.
[0014]
Therefore, an object of the present invention is to provide a semiconductor memory device having a small memory cell size, good readout of stored data, and high layout flexibility.
[0015]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention according to claim 1 is connected to a bit line pair via a bit line pair, a word line crossing the bit line pair, and a transistor controlled by the potential of the word line. A nonvolatile memory for holding data read from the latch circuit to the bit line pair in a nonvolatile manner and supplying the held data to the latch circuit via the bit line pair. A semiconductor storage device comprising storage means.
[0016]
The invention according to claim 3 is controlled by a potential of a bit line pair including a bit line and a complementary bit line, a first word line and a first plate line crossing the bit line pair, and a potential of the first word line. A semiconductor memory device comprising: a latch circuit connected to a pair of bit lines via a transistor; a second word line; and a first and a second capacitor having one electrode connected to a first plate line. A dielectric capacitor, a first transistor connected between the bit line and the other electrode of the first ferroelectric capacitor, and a gate connected to the second word line; a complementary bit line and a second ferroelectric capacitor; A semiconductor memory device comprising: a second transistor connected between the other electrode of the dielectric capacitor and a gate connected to a second word line.
[0017]
The semiconductor memory device according to the present invention may be configured such that data read from a latch circuit to a bit line pair is held in a nonvolatile manner, and the held data is supplied to the latch circuit through the bit line pair to be nonvolatile. And the separation between the latch circuit and the non-volatile storage means is facilitated, and the degree of freedom in layout can be increased.
[0018]
Therefore, when the bit line pair is connected to the first and second ferroelectric capacitors via the first and second transistors, respectively, and the nonvolatile memory means is configured, the first and second ferroelectric capacitors are formed. There is no need to provide a reset circuit for setting the applied voltage of the ferroelectric capacitor to 0 V for each nonvolatile storage means, and the size of the nonvolatile portion can be reduced. Further, one electric field is not continuously applied to the ferroelectric capacitor, and it is possible to prevent erroneous reading from easily occurring.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration diagram of an example of the semiconductor memory device according to the first embodiment of the present invention. The semiconductor memory device shown in FIG. 1 is a nonvolatile CMOS SRAM memory cell. This memory cell includes a volatile part A and a non-volatile part B.
[0020]
The volatile portion A includes a CMOS latch circuit including drive transistors DT1 and DT2 formed of nMOS (n-channel MOS), drive transistors DT3 and DT4 formed of pMOS (p-channel MOS), and pass transistors PT1 and PT2 formed of nMOS. It consists of. That is, the volatile part A is constituted by six transistors.
[0021]
In the volatile part A, the sources of the driving transistors DT1 and DT2 are grounded, and the sources of the driving transistors DT3 and DT4 are connected to the power supply Vcc. The drains of the drive transistors DT1 and DT3 are connected to the gates of the drive transistors DT2 and DT4 (storage node N1). The drains of the driving transistors DT2 and DT4 are connected to the gates of the driving transistors DT1 and DT3 (storage node N2).
[0022]
The storage nodes N1 and N2 hold information of “0” and “1”. In the volatile part A, it is determined whether the recording data is “0” or “1” based on the potential difference between the storage nodes N1 and N2. Thereby, the volatile part A records a binary value. The data recorded in the volatile portion A is lost when the power is turned off. That is, the volatile portion A has a volatile configuration.
[0023]
The storage node N1 is connected to the bit line BL by the source-drain path of the pass transistor PT1. The storage node N2 is connected to the bit line BL_ (_ represents negative logic) complementary to the bit line BL by the source-drain path of the pass transistor PT2. The gates of the pass transistors PT1 and PT2 are connected to the word line WL1.
[0024]
The bit line pair of the bit lines BL and BL_ is used, for example, for selecting a specific memory cell in a column direction, and the word line WL1 is used, for example, for selecting a memory cell of a specific volatile portion A in a row direction. Used.
[0025]
The non-volatile section B includes ferroelectric capacitors C1 and C2 and select transistors ST1 and ST2.
[0026]
In the nonvolatile portion B, one electrode of the ferroelectric capacitor C1 is connected to the bit line BL by a source-drain path of the selection transistor ST1. One electrode of the ferroelectric capacitor C2 is connected to the bit line BL_ by the source-drain path of the selection transistor ST2. The other electrodes of the ferroelectric capacitors C1 and C2 are connected to the plate line PL. The gates of the select transistors ST1 and ST2 are connected to the word line WL2.
[0027]
The word line WL2 is, for example, a line for selecting a memory cell of a specific nonvolatile portion B in the row direction. In the non-volatile section B, whether the recording data is "0" or "1" is determined based on the polarization direction of the ferroelectric capacitors C1 and C2. Thereby, the non-volatile portion B records the binary value. The polarization states of the ferroelectric capacitors C1 and C2 remain the same even when the power is turned off. That is, the non-volatile section B has a non-volatile configuration.
[0028]
Accordingly, the memory cell of the nonvolatile CMOS SRAM shown in FIG. 1 has a volatile portion A composed of six transistors used for a CMOS latch circuit and a pass transistor, two transistors and two ferroelectrics. The non-volatile portion B composed of a body capacitor is connected via a bit line pair of bit lines BL and BL_.
[0029]
The write, read, store, and recall operations of the memory cell of the nonvolatile CMOS SRAM shown in FIG. 1 will be described below.
[0030]
<Write operation (1)>
First, writing of data to only the volatile portion A will be described. When writing recording data only to the volatile portion A, a writing operation similar to that of a normal SRAM is performed. For example, the correspondence between the recording data “0” and “1” is “0” when the storage node N1 of the memory cell shown in FIG. 1 has a low potential and the storage node N2 has a high potential, and the storage node N1 is When the potential is high and the storage node N2 is low, it is defined as "1". In this case, an example of the operation of writing “1” to the memory cell will be described with reference to the timing chart of FIG.
[0031]
As shown in FIG. 2B, power supply voltage Vcc which is a high potential is applied to bit line BL, and ground potential 0V which is a low potential is applied to bit line BL_.
[0032]
Then, as shown in FIG. 2A, the word line WL1 rises. As a result, the pass transistors PT1 and PT2 become conductive. Since the power supply voltage Vcc, which is a high potential, is applied to the bit line BL, the potential of the storage node N1 increases. That is, the potentials of the gates of the drive transistors DT2 and DT4 are high. Therefore, the driving transistor DT4 becomes non-conductive, and the driving transistor DT2 becomes conductive. This state is maintained even if the pass transistor PT1 is turned off.
[0033]
Further, since a low potential of 0 V is applied to the bit line BL_, the potential of the storage node N2 is lowered. That is, the potentials of the gates of the drive transistors DT1 and DT3 are low. Therefore, the driving transistor DT1 is turned off and the driving transistor DT3 is turned on. This state is maintained even if the pass transistor PT2 is turned off.
[0034]
Therefore, in this state, as shown in FIG. 2A, the word line WL1 is returned to the ground potential 0 V, and the pass transistors PT1 and PT2 are turned off, so that the latch circuit is disconnected from the outside and "1" Is latched.
[0035]
<Write operation (2)>
Next, an example of an operation when data is written to the volatile portion A and also to the nonvolatile portion B will be described with reference to the timing chart of FIG. In this case, the same writing as that of the FeRAM (Ferroelectric RAM) is performed. That is, in the case where "1" is written to the memory cell in the correspondence between the recording data "0" and "1", as shown in FIG. 3B, the power supply voltage Vcc which is a high potential is applied to the bit line BL, and A ground potential of 0 V is applied to bit line BL_.
[0036]
Then, as shown in FIG. 3D, the word line WL2 rises at time T1, and the ferroelectric capacitor C1 is polarized by an electric field in one direction. Next, as shown in FIG. 3C, the plate line PL is raised at time T2, and the ferroelectric capacitor C2 is polarized by the electric field in the opposite direction. According to the polarization direction of the ferroelectric capacitors C1 and C2, the recording data "1" is written in the nonvolatile portion B. This polarization state is maintained even when the power is turned off.
[0037]
At times T1 and T2, as shown in FIG. 3A, the word line WL1 of the volatile portion A is activated, and the recording data “1” is also written to the volatile portion A.
[0038]
As described above, by writing data to the nonvolatile portion B in addition to the volatile portion A, data loss due to an instantaneous power failure or the like can be eliminated, and data reliability can be improved.
[0039]
<Read operation>
An example of the operation when data is read from the volatile unit A will be described with reference to the timing chart of FIG. When reading data from the volatile portion A, a read operation similar to that of a normal SRAM is performed. That is, as shown in FIG. 4B, the potential Vcc-α is supplied from the load to the bit line pair BL, BL_. In this state, as shown in FIG. 4A, the word line WL1 rises, and the pass transistors PT1 and PT2 are turned on.
[0040]
In the above-described correspondence between the recording data “0” and “1”, for example, when “1” is read, the driving transistor DT3 is conductive, the driving transistor DT1 is nonconductive, and the pass transistor PT1 is conductive. The potential of the bit line BL is raised. Further, since the driving transistor DT4 is non-conductive, the driving transistor DT2 is conductive, and the pass transistor PT2 is conductive, the potential of the bit line BL_ is reduced. That is, in this case, as shown in FIG. 4B, the potential of the bit line BL_ is slightly lower than the potential of the bit line BL. As described above, the sense amplifier (not shown) detects the potential difference generated in the bit line pair, so that the recording data is read.
[0041]
<Store>
When the recording data is stored, when the power is turned off from the power-on state, the recording data of the volatile section A is read out to the bit line by the above-described read operation, then amplified to 0 V / Vcc, and then stored in the nonvolatile section B. Is written to.
[0042]
FIG. 5 shows a timing chart of an example of a specific operation of the store. Here, a case where the recording data “1” is stored in correspondence with the recording data “0” and “1” described above will be described. First, similarly to the read operation, as shown in FIG. 5B, the potential Vcc-α is supplied from the load to the pair of bit lines BL and BL_. In this state, as shown in FIG. 5A, the word line WL1 rises at time T1, and the recording data "1" is read from the potential difference generated in the bit line pair shown in FIG. 5B.
[0043]
At time T2, the bit line BL is amplified to Vcc, and the bit line BL_ is amplified to 0V. Next, as shown in FIG. 5D, the word line WL2 rises at time T3, and the ferroelectric capacitor C1 is polarized by an electric field in one direction. Further, as shown in FIG. 5C, the plate line PL is activated at time T4, and polarization is applied to the ferroelectric capacitor C2 by the electric field in the opposite direction. According to the polarization direction of the ferroelectric capacitors C1 and C2, the recording data "1" is written in the nonvolatile portion B. This polarization state is maintained even when the power is turned off.
[0044]
In the above-described write operation, it is needless to say that if the recording data is also written in the non-volatile section B (in the case of the write operation (2)), it is not necessary to store.
[0045]
<Recall>
In the recall of the recording data, when the power is turned on from the power-off state, the recording data in the non-volatile section B is read out to the bit line, amplified to 0 V / Vcc, and then written to the volatile section A.
[0046]
FIG. 6 shows a timing chart in an example of a specific operation of the recall. Here, a case where the recording data “1” is recalled in correspondence with the recording data “0” and “1” described above will be described. First, as shown in FIG. 6B, the bit line pair BL, BL_ is discharged to 0 V and brought into a floating state. In this state, the word line WL2 rises as shown in FIG. 6D, and the plate line PL rises at time T1 as shown in FIG. 6C. Thus, as shown in FIG. 6B, a high potential appears on the bit line BL, and a low potential appears on the bit line BL_.
[0047]
At time T1, the bit line BL is continuously amplified to Vcc, and the bit line BL_ is amplified to 0V. Thereafter, as shown in FIG. 6A, the word line WL1 rises at time T2, and the recording data “1” is written to the volatile portion A.
[0048]
Note that both store and recall are performed for each row (for each word line), so the store time and the recall time increase by the number of word lines.
[0049]
When reading data from a ferroelectric capacitor, it is necessary to set the plate line PL to 0 V immediately before reading, discharge the potential of the electrode opposite to the plate line electrode to 0 V via the ferroelectric capacitor, and set the plate line in a floating state. There is. In this memory cell, the applied voltage of the ferroelectric capacitors C1 and C2 is discharged by the rise of the word line WL2 and the reset circuit including two transistors (not shown) at the bit line end.
[0050]
As described above, in the semiconductor memory device according to the first embodiment of the present invention, the volatile portion A including the CMOS latch circuit and the six transistors used for the pass transistor, the two transistors and the two Is connected via a bit line pair of bit lines BL and BL_. As a result, a reset circuit including two transistors and the like is provided at the end of the bit line, and by applying the reset circuit and the rise of the word line WL2, the applied voltage of the ferroelectric capacitors C1 and C2 can be discharged. There is no need to provide a reset circuit consisting of two transistors in the cell. Therefore, the size of the memory cell can be reduced.
[0051]
In addition, since the storage nodes N1 and N2 of the volatile portion A forming the memory cell are not directly connected to one electrode of the ferroelectric capacitors C1 and C2, the related art as described with reference to FIG. There is no imprint problem with the memory cells.
[0052]
Further, since the volatile portion A and the non-volatile portion B have a common bit line pair, when a semiconductor memory device such as an SRAM is configured using a plurality of memory cells, it is easy to arrange them separately and collectively. Become. Therefore, when a nonvolatile SRAM is constituted by a plurality of memory cells, the degree of freedom in the layout of the memory cells is increased.
[0053]
Next, a second embodiment of the present invention will be described. FIG. 7 shows a configuration diagram of an example of the semiconductor memory device according to the second embodiment of the present invention. The semiconductor memory device shown in FIG. 7 is an equivalent circuit of four memory cells.
[0054]
As shown in FIG. 7, the semiconductor memory device includes a volatile part A1 of a first memory cell, a volatile part A2 of a second memory cell, a volatile part A3 of a third memory cell, and a fourth memory. The volatile part A4 of the cell is connected via bit lines BL and BL_. The nonvolatile portion B1 of the first memory cell, the nonvolatile portion B2 of the second memory cell, the nonvolatile portion B3 of the third memory cell, and the nonvolatile portion B4 of the fourth memory cell are connected to the bit lines BL, They are connected via BL_.
[0055]
The volatile portions A1 to A4 and the non-volatile portions B1 to B4 are arranged collectively in the bit line direction, and the collected volatile portions A1 to A4 and the non-volatile portions B1 to B4 are connected to the bit lines BL and BL_. Connected through. The volatile units A1 to A4 have the same configuration as the volatile unit A of the memory cell described in the first embodiment, and the nonvolatile units B1 to B4 are the same as those in the first embodiment. The configuration is the same as that of the nonvolatile portion B of the memory cell described above.
[0056]
When performing store, recall, or the like, a word line is selected by a row decoder (not shown) so that the volatile section and the nonvolatile section appropriately correspond to each other (for example, the volatile section A1 and the nonvolatile section B1). You.
[0057]
In the semiconductor memory device according to the second embodiment of the present invention, since the volatile portions A1 to A4 and the non-volatile portions B1 to B4 are collectively arranged, an efficient memory cell layout is possible.
[0058]
Next, a semiconductor memory system according to a third embodiment of the present invention will be described. Here, the semiconductor storage system refers to a logical collection of a plurality of semiconductor storage devices such as a cache memory and a main memory. It is assumed that the semiconductor storage system has a memory cell configuration having a bit line pair including bit lines BL and BL_, and has a main memory which is a nonvolatile semiconductor memory forming a large-capacity memory cell array, and a cache memory. In this case, the main memory is configured to obtain, for example, a large capacity from a low-cost memory cell having a small cell size, and the cache memory has a large cell size but high performance (high-speed writing / reading). The configuration is such that, for example, a small capacity can be obtained from the memory cells described in the first embodiment.
[0059]
FIG. 8 shows a specific configuration example of a memory cell used for the main memory. The memory cell illustrated in FIG. 8A is an example of a two-transistor two-ferroelectric capacitor type FeRAM including two transistors TR21 and TR22 and two ferroelectric capacitors C21 and C22.
[0060]
The memory cell used for the main memory may be an FeRAM composed of two ferroelectric capacitors C31 and C32 shown in FIG. 8B. Further, a flash memory including two floating gate transistors TR23 and TR24 shown in FIG. 8C may be used. Further, a flash memory including two MONOS (or MNOS) transistors TR25 and TR26 shown in FIG. 8D may be used.
[0061]
FIG. 9 shows an example of the configuration of the semiconductor memory system according to the third embodiment of the present invention. The semiconductor memory system shown in FIG. 9 has a memory cell array configuration having 128 bit line pairs of bit lines BL1 and BL_1 to bit lines BL128 and BL_128. The cache memory CM1 is configured by 4 Rows (4 word lines). The main memory MM1 is configured such that a large capacity of the memory cell of the above-described FeRAM of FIG. 8A can be obtained.
[0062]
The unit of data transferred between the cache memory CM1 and the main memory MM1 is called a block, and one row of data is one block. The bit line pair of the cache memory CM1 and the bit line pair of the main memory MM1 are connected via a selection circuit, for example, the source-drain paths of the selection transistors T1 to T256 shown in FIG. In FIG. 9, a selection circuit is provided between the cache memory CM1 and the main memory MM1 for easy control, but may be directly connected without using the selection circuit.
[0063]
According to the semiconductor memory system according to the third embodiment of the present invention, since the recording data is directly exchanged via the bit lines, there is no limitation on the bus width. Therefore, conventionally, the bus width is about 8 to 32 bits, so that, for example, one block of data of 128 bits is transferred by 4 to 12 times, but in the semiconductor memory system according to the third embodiment, Can be performed in one transfer. As a result, the time required for recovery processing at the time of a cache miss, that is, so-called miss penalty, is reduced.
[0064]
The present invention is not limited to the embodiment of the present invention described above, and various modifications and applications are possible without departing from the gist of the present invention. For example, the volatile part A in the first embodiment is a CMOS type SRAM memory cell including a CMOS latch circuit and six transistors forming a pass transistor. However, the present invention is not limited thereto. , DT4 instead of the volatile portion A using a high resistance load type latch circuit using a high resistance, or a latch using a thin film transistor load using a thin film transistor (TFT: Thin Film Transistor) instead of the driving transistors DT3 and DT4. Another volatile memory cell configuration having a bit line pair, such as a configuration of the volatile portion A in a circuit, may be used.
[0065]
Further, for example, in the above-described embodiment, two ferroelectric capacitors are used in the non-volatile portion B and the like. However, since the ferroelectric capacitors can represent two different states, these are combined into one ferroelectric capacitor. It is also possible to use a dielectric capacitor.
[0066]
【The invention's effect】
As described above, according to the present invention, the data read from the latch circuit to the bit line pair is held in a nonvolatile manner, and the held data is supplied to the latch circuit via the bit line pair. Accordingly, it is possible to provide a semiconductor memory device which is non-volatile, easily separates the latch circuit and the non-volatile storage means, and has a high degree of freedom in layout.
[0067]
When the bit line pair is connected to the first and second ferroelectric capacitors via the first and second transistors, respectively, and the nonvolatile memory means is configured, the first and second ferroelectric capacitors are connected to each other. There is no need to provide a reset circuit for setting the applied voltage of the ferroelectric capacitor to 0 V for each nonvolatile storage means, and the memory cell size including the volatile part and the nonvolatile part is reduced to eight transistors and two transistors. Since it can be configured with a ferroelectric capacitor, the size can be reduced. Further, one electric field is not continuously applied to the ferroelectric capacitor, and it is possible to prevent erroneous reading from easily occurring.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating a configuration of an example of a semiconductor memory device according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an example of a timing chart when recording data is written to the semiconductor memory device according to the first embodiment of the present invention;
FIG. 3 is a schematic diagram showing a timing chart of another example when writing recording data to the semiconductor memory device according to the first embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating an example of a timing chart when recording data is read from the semiconductor memory device according to the first embodiment of the present invention;
FIG. 5 is a schematic diagram showing a timing chart of an example when storing recording data in the semiconductor memory device according to the first embodiment of the present invention;
FIG. 6 is a schematic diagram showing a timing chart of an example when recalling recording data in the semiconductor memory device according to the first embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a configuration of an example of a semiconductor memory device according to a second embodiment of the present invention;
FIG. 8 is a schematic diagram showing a specific configuration of a main memory used in a semiconductor memory device according to a third embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating a configuration of an example of a semiconductor memory device according to a third embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating a configuration of an example of a memory cell of a nonvolatile SRAM;
FIG. 11 is a schematic diagram illustrating a configuration of an example of a memory cell of a nonvolatile SRAM using a conventional ferroelectric capacitor.
FIG. 12 is a schematic diagram illustrating a configuration of another example of a memory cell of a nonvolatile SRAM using a conventional ferroelectric capacitor.
[Explanation of symbols]
DT1, DT2, DT3, DT4 ... drive transistors, PT1, PT2 ... pass transistors, ST1, ST2 ... select transistors, C1, C2 ... ferroelectric capacitors, A, A1 to A4 ... Volatile part, B, B1 to B4: Non-volatile part, CM1: Cache memory, MM1: Main memory

Claims (8)

A semiconductor memory device comprising: a bit line pair; a word line intersecting the bit line pair; and a latch circuit connected to the bit line pair via a transistor controlled by a potential of the word line,
Non-volatile storage means for holding the data read from the latch circuit to the bit line pair in a nonvolatile manner and supplying the held data to the latch circuit via the bit line pair. Semiconductor storage device. 2. The semiconductor memory device according to claim 1, further comprising a memory cell connected to said bit line pair and holding data transmitted through said bit line pair. A bit line pair including a bit line and a complementary bit line, a first word line and a first plate line intersecting the bit line pair, and a transistor controlled by a potential of the first word line. A latch circuit connected to the bit line pair.
A second word line;
First and second ferroelectric capacitors each having one electrode connected to the first plate line;
A first transistor connected between the bit line and the other electrode of the first ferroelectric capacitor and having a gate connected to the second word line;
A second transistor connected between the complementary bit line and the other electrode of the second ferroelectric capacitor and having a gate connected to the second word line; apparatus. A third word line crossing the bit line pair;
A second plate line crossing the bit line pair,
Third and fourth ferroelectric capacitors each having an electrode connected to the second plate line,
A third transistor connected between the bit line and the other electrode of the third ferroelectric capacitor and having a gate connected to the third word line;
A fourth transistor connected between the complementary bit line and the other electrode of the fourth ferroelectric capacitor and having a gate connected to the third word line. Item 4. The semiconductor memory device according to item 3. A third plate line intersecting the bit line pair;
A fifth ferroelectric capacitor connected between the other electrode of the third ferroelectric capacitor and the third plate line;
5. The semiconductor memory according to claim 4, further comprising a sixth ferroelectric capacitor connected between the other electrode of said fourth ferroelectric capacitor and said third plate line. apparatus. A third word line crossing the bit line pair;
A source line crossing the bit line pair;
A third transistor connected between the bit line and the source line and having a gate connected to the third word line;
4. The semiconductor memory device according to claim 3, further comprising a fourth transistor connected between said complementary bit line and said source line and having a gate connected to said third word line. . 7. The semiconductor memory device according to claim 6, wherein said third and fourth transistors have a floating gate. 7. The semiconductor memory device according to claim 6, wherein said third and fourth transistors are MONOS transistors or MNOS transistors.

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