JP2004119472A - Semiconductor device and its manufacturing method, circuit board, and electronic equipment - Google Patents

Abstract

An object of the present invention is to improve reliability and structural freedom of a semiconductor device and to facilitate a manufacturing process.
A groove is formed from a first surface in a semiconductor substrate on which an integrated circuit and an electrode are formed. At least the insulating layer 40 is formed on the inner surface of the groove 30. The semiconductor substrate 10 is polished from the second surface 22 opposite to the first surface 20 to a thickness at which the groove 30 is exposed, and the semiconductor substrate 10 is divided into a plurality of semiconductor chips 70.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, a circuit board, and an electronic device.
[0002]
BACKGROUND OF THE INVENTION
2. Description of the Related Art There is known a technique of dividing a semiconductor wafer into a plurality of thin semiconductor chips by forming a groove on one surface of a semiconductor wafer and polishing the other surface of the semiconductor wafer to a thickness that exposes the groove. According to this, the step of dividing the semiconductor chip and the step of thinning the semiconductor chip can be performed at the same time, so that the productivity can be improved.
[0003]
However, a semiconductor portion (silicon) is exposed on the side surface of the semiconductor chip thus formed. As a result, when routing the wiring on the semiconductor chip, the wiring must be routed avoiding the side surface of the semiconductor chip, and the degree of freedom in design may be limited. Further, since silicon is also exposed at the corners of the semiconductor chip, chipping may occur or the integrated circuit element may peel off. On the other hand, if the semiconductor chips after the division are subjected to the insulation treatment, the semiconductor chips are subjected to overlapping steps, resulting in poor productivity.
[0004]
SUMMARY OF THE INVENTION It is an object of the present invention to improve the reliability and structural freedom of a semiconductor device and to simplify a manufacturing process.
[0005]
[Means for Solving the Problems]
(1) A method of manufacturing a semiconductor device according to the present invention includes: (a) forming a groove from a first surface in a semiconductor substrate on which an integrated circuit and an electrode are formed;
(B) forming an insulating layer on at least the inner surface of the groove;
(C) polishing the semiconductor substrate from a second surface opposite to the first surface to a thickness at which the groove is exposed, and dividing the semiconductor substrate into a plurality of semiconductor chips.
[0006]
According to the present invention, the insulating layer is formed on the inner surface of the groove of the semiconductor substrate. The inner surface of the groove of the semiconductor substrate corresponds to the side surface of the plurality of semiconductor chips. Therefore, the side surfaces of the plurality of semiconductor chips can be collectively subjected to the insulation treatment in the state of the semiconductor substrate. Further, since the insulating layer is formed before polishing the semiconductor substrate, it is possible to manufacture an extremely thin semiconductor device while avoiding cracking and damage of the semiconductor substrate.
[0007]
(2) In this method of manufacturing a semiconductor device,
In the step (a), the groove may be formed avoiding the electrode.
[0008]
(3) In this method of manufacturing a semiconductor device,
In the step (b), the insulating layer may be formed continuously from the inner surface of the groove to the first surface.
[0009]
Thus, the corners of the semiconductor chip can be covered with the insulating layer. Therefore, since the corners of the semiconductor chip can be protected by the insulating layer, occurrence and enlargement of chipping can be reduced, and separation of elements and wirings of the integrated circuit formed on the first surface can be prevented. Can be.
[0010]
(4) In this method of manufacturing a semiconductor device,
Prior to the step (a), further comprising forming a second insulating layer on the first surface of the semiconductor substrate;
In the step (b), a part of the insulating layer may be formed on the second insulating layer.
[0011]
(5) In the method of manufacturing a semiconductor device,
After the step (b), the method may further include forming a conductive layer on the insulating layer on the inner surface of the groove.
[0012]
Thus, a conductive layer can be formed on the side surface of the semiconductor chip. Therefore, the degree of freedom of the wiring structure on the semiconductor chip can be improved.
[0013]
(6) In this method of manufacturing a semiconductor device,
In the step of forming the conductive layer, the conductive layer may be formed continuously from the inner surface of the groove to the first surface.
[0014]
(7) In this method of manufacturing a semiconductor device,
In the step of forming the conductive layer, the conductive layer may be electrically connected to the electrode.
[0015]
According to this, external terminals can be easily formed on the side surfaces of the semiconductor chip.
[0016]
(8) In this method of manufacturing a semiconductor device,
The step (c) may be performed in a state where a sheet is attached to the semiconductor substrate from the first surface.
[0017]
According to this, since the sheet is attached to the semiconductor substrate from the first surface, a plurality of divided semiconductor chips can be held at once. Therefore, handling of the plurality of semiconductor chips after division can be facilitated.
[0018]
(9) In this method of manufacturing a semiconductor device,
The step (c) may be performed in a state where a filler is provided in the groove.
[0019]
According to this, since the filler is provided in the groove at the time of the polishing step, it is possible to prevent powdery foreign matter generated in the polishing step from entering the groove. Therefore, damage to the semiconductor chip and attachment of foreign matter can be prevented, and the reliability of the semiconductor device can be improved.
[0020]
(10) In this method of manufacturing a semiconductor device,
After the step (c), the method may further include forming a third insulating layer on a polished surface of the plurality of semiconductor chips in a state where the plurality of semiconductor chips are held on the sheet.
[0021]
According to this, the third insulating layer is formed on the polished surface of the semiconductor chip. Therefore, electrical conduction with the outside on the polished surface of the semiconductor chip can be prevented. In addition, since the plurality of semiconductor chips are held on a sheet, the polished surfaces of the plurality of semiconductor chips can be collectively subjected to insulation treatment.
[0022]
(11) A semiconductor device according to the present invention is manufactured by the above method.
[0023]
(12) A semiconductor device according to the present invention includes a semiconductor chip having an integrated circuit and electrodes formed thereon and having a first surface;
An insulating layer formed continuously from the first surface of the semiconductor chip to a side surface continuous with the first surface;
A conductive layer formed on the insulating layer on a side surface of the semiconductor chip,
Including
A portion of the side surface of the semiconductor chip exposed from the conductive layer is covered with the insulating layer.
[0024]
According to the present invention, since the portion of the side surface of the semiconductor chip exposed from the conductive layer is covered with the insulating layer, it is possible to cut off the electrical continuity with the outside in the portion other than the conductive layer.
[0025]
(13) In this semiconductor device,
The semiconductor device further includes a second insulating layer formed on the first surface of the semiconductor chip,
A part of the insulating layer may be formed on the second insulating layer.
[0026]
(14) In this semiconductor device,
The conductive layer may be formed continuously from a side surface of the semiconductor chip to the first surface.
[0027]
(15) In this semiconductor device,
The conductive layer may be electrically connected to the electrode.
[0028]
(16) In this semiconductor device,
A third insulating layer may be formed on a second surface of the semiconductor chip opposite to the first surface.
[0029]
According to this, it is possible to cut off electrical continuity with the outside on the second surface of the semiconductor chip.
[0030]
(17) The semiconductor device is mounted on a circuit board according to the present invention.
[0031]
(18) An electronic device according to the present invention includes the above-described semiconductor device.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 11 are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied. In the present embodiment, a semiconductor substrate (for example, a silicon substrate) 10 is used. The semiconductor substrate 10 may be a semiconductor wafer. FIG. 1 shows a part of a semiconductor wafer. The planar shape of the semiconductor substrate 10 is not limited. For example, in the case of a semiconductor wafer, it is generally circular.
[0033]
On a semiconductor substrate 10, a plurality of integrated circuits (for example, circuits having transistors and memories) 12 are formed. A plurality of electrodes (for example, pads) 14 are formed on the semiconductor substrate 10. Each electrode 14 is electrically connected to the integrated circuit 12. Each electrode 14 may be formed in a region that does not overlap with the integrated circuit 12 (a region outside the integrated circuit in FIG. 1). Each electrode 14 may be formed of an aluminum-based or copper-based metal. The shape of the surface of the electrode 14 is not particularly limited, but is often rectangular. When the semiconductor substrate 10 is a semiconductor wafer, two or more (one group) of electrodes 14 are formed in each region to be a plurality of semiconductor chips. In the example shown in FIG. 1, the electrodes 14 are arranged along four sides of a region to be a semiconductor chip. However, the electrodes 14 may be arranged along two sides or in the center.
[0034]
The semiconductor substrate 10 has a first surface 20 on the side on which the integrated circuit 12 is formed, and a second surface 22 opposite thereto. The plurality of electrodes 14 are exposed from the first surface 20 to the outside.
[0035]
At least one insulating layer (second insulating layer) 16 is formed on the semiconductor substrate 10. In the example shown in FIG. 2, the insulating layer 16 is formed on the first surface 20 of the semiconductor substrate 10. The insulating layer 16 is called a passivation film, and can be formed of, for example, SiO ₂ , SiN, polyimide resin, or the like. The insulating layer 16 has an opening 18 exposing at least a part of the electrode 14. After the insulating layer 16 is formed to cover the surface of the electrode 14, a part of the insulating layer 16 may be etched to expose a part of the electrode 14. As shown in FIG. 2, the insulating layer 16 may be formed so as to open the center of the electrode 14 and cover the outer peripheral end.
[0036]
The virtual line 24 shown in FIGS. 1 and 2 divides the semiconductor substrate 10 into a plurality of regions (regions serving as semiconductor chips). The virtual line 24 may be formed avoiding the integrated circuit 12 and the electrode 14. The outer shape of each region (semiconductor chip) may be a rectangle, a circle, or another polygon, and is not limited.
[0037]
As shown in FIG. 3, a groove 30 is formed in the semiconductor substrate 10 from the first surface 20. In the present embodiment, the groove 30 is formed along the virtual line 24. That is, the groove 30 is formed so as to partition the semiconductor substrate 10 into regions that become a plurality of semiconductor chips. In the example shown in FIG. 3, the groove 30 is formed avoiding the integrated circuit 12 and the electrode 14. The groove 30 may be formed mechanically by cutting the semiconductor substrate 10 with a blade or the like, may be formed chemically by etching or the like, or may be formed optically by laser or the like. .
[0038]
The groove 30 may have a wall surface provided with a taper inclined from the first surface 20 (for example, a taper expanding in the opening direction of the groove), or a wall surface falling vertically from the first surface 20. May be. The groove 30 may have a concave shape with a bottom surface formed, or may have a V shape without a bottom surface.
[0039]
The groove 30 is formed so as not to penetrate the semiconductor substrate 10. The groove 30 is formed so as to be deeper than the thickness of the semiconductor chip as a finished product. Further, the groove 30 is formed so as to be deeper than elements and wirings of the integrated circuit 12 formed inside the semiconductor substrate 10. Note that a semiconductor portion (for example, silicon) is exposed on the inner surface of the groove 30 of the semiconductor substrate 10.
[0040]
As shown in FIG. 4, the insulating layer 40 is formed on the semiconductor substrate 10. Examples of the material of the insulating layer 40 include an oxide film (for example, SiO ₂ ), a nitride film (for example, SiN), and a resin (for example, a polyimide resin).
[0041]
The insulating layer 40 is formed at least on the inner surface of the groove 30. In the example shown in FIG. 4, the insulating layer 40 is formed on the inner wall surface and the bottom surface of the groove 30, but may be formed only on the inner wall surface of the groove 30. However, the insulating layer 40 is formed so as not to fill the groove 30. That is, a groove (or a concave portion) is formed by the insulating layer 40. In the example shown in FIG. 4, the entire inner surface (the inner wall surface and the bottom surface in FIG. 4) of the groove 30 is covered with the insulating layer 40.
[0042]
The insulating layer 40 may be formed continuously from the inner surface of the groove 30 to the first surface 20. For example, the insulating layer 40 may be formed so as to cover the first surface 20 of the semiconductor substrate 10 and the inner surface of the groove 30, and a necessary portion may be etched to be exposed from the insulating layer 40. In the example shown in FIG. 4, a portion of the insulating layer 40 covering the electrode 14 is etched to form an opening 42 exposing the electrode 14.
[0043]
Since the corner between the inner surface (specifically, the inner wall surface) of the groove 30 and the first surface 20 corresponds to the corner of the semiconductor chip, the corner of the semiconductor chip can be covered by the insulating layer 40. Therefore, since the corners of the semiconductor chip can be protected by the insulating layer, occurrence and enlargement of chipping are reduced, and separation of elements and wiring of the integrated circuit 12 formed on the first surface 20 is prevented. be able to.
[0044]
When the insulating layer (second insulating layer) 16 is formed on the first surface 20, a part of the insulating layer 40 (portion on the first surface) is formed as an insulating layer (second insulating layer). 16 is formed.
[0045]
As shown in FIG. 5, a conductive layer 50 may be formed on the semiconductor substrate 10 as needed. The conductive layer 50 is made of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium tungsten (Ti-W), gold (Au), aluminum (Al), nickel vanadium (NiV), tungsten Any of (W) may be stacked or formed of any one layer. The conductive layer 50 may be formed by etching after applying photolithography, may be formed by sputtering, or may be formed by applying an additive method using electroless plating. Good. Alternatively, the conductive layer 50 may be formed using an inkjet method. According to this, it is possible to provide the material of the conductive layer 50 at high speed and economically without waste by applying the technology practically used for the ink jet printer.
[0046]
The conductive layer 50 is formed on the insulating layer 40 on the inner surface (specifically, the inner wall surface) of the groove 30. In the example shown in FIG. 5, the conductive layer 50 is formed on the inner wall surface and the bottom surface of the groove 30, but may be formed only on the inner wall surface of the groove 30. However, the conductive layer 50 is formed so as not to fill the groove 30. That is, a groove (or a concave portion) is formed by the insulating layer 50. Since the insulating layer 40 is interposed between the inner surface of the groove 30 and the conductive layer 50, the electrical connection between the two is cut off.
[0047]
The conductive layer 50 may be formed on the inner surface of the groove 30 so as to extend along the depth direction. Alternatively, the conductive layer 50 may be formed in a land shape (such as a circle or a rectangle). The portion of the inner surface of the groove 30 that is exposed from the conductive layer 50 has the insulating layer 40 exposed.
[0048]
FIG. 6 is a sectional view taken along line VI-VI of FIG. In the example shown in FIG. 6, the conductive layer 50 is formed so as to protrude from the surface of the insulating layer 40 in the direction inside the groove 30.
[0049]
As a modification, as shown in FIG. 7, the conductive layer 54 may be formed so as to be flush with the surface of the insulating layer 44 on the inner surface of the groove 32. In that case, the conductive layer 54 enters the inside of the insulating layer 44. As another modification, as shown in FIG. 8, the conductive layer 56 may be formed so as to be recessed on the inner surface of the groove 34 than the surface of the insulating layer 46. Also in that case, the conductive layer 56 enters the inside of the insulating layer 46. However, the conductive layer 56 is exposed without being covered with the insulating layer 46.
[0050]
According to these modifications, the adhesion between the conductive layers 54 and 56 and the insulating layers 44 and 46 is increased, so that the conductive layers 54 and 56 can be hardly peeled off from the insulating layers 44 and 46. Note that, if necessary, after the conductive layer forming step, the insulating layer forming step may be performed again to form a thick portion around the conductive layer in the insulating layer.
[0051]
As shown in FIG. 5, the conductive layer 50 may be formed continuously from the inner surface of the groove 30 to the first surface 20. That is, the conductive layer 50 may be formed as a wiring so as to extend from the inner surface of the groove 30 toward the first surface 20.
[0052]
As shown in FIG. 5, the conductive layer 50 may be electrically connected to the electrode 14. The conductive layer 50 extends to the first surface 20 and has a connecting portion 52 that is electrically connected to the electrode 14 in the openings 18 and 42 of the plurality of insulating layers 16 and 40. The connection section 52 may be formed so as to cover the electrode 14.
[0053]
As a modification, the conductive layer 50 may not be electrically connected to the electrode 14. That is, the conductive layer 50 may be formed as a dummy wiring (a wiring that does not conduct with the integrated circuit).
[0054]
According to this, the conductive layer 50 can be formed on the side surface of the semiconductor chip. For example, if the conductive layer 50 is electrically connected to the electrode 14, external terminals electrically connected to the integrated circuit 12 can be easily formed on the side surface of the semiconductor chip. Therefore, the degree of freedom of the wiring structure on the semiconductor chip can be improved.
[0055]
Next, the semiconductor substrate 10 is polished to divide it into a plurality of semiconductor chips 70. In the present embodiment, the semiconductor substrate 10 is polished while being held by the sheet 60. The sheet 60 is a holding member for the semiconductor substrate 10.
[0056]
As shown in FIG. 9, a sheet 60 is attached to the semiconductor substrate 10 from the first surface 20. The sheet 60 holds the semiconductor substrate 10 from the first surface 20. The sheet 60 may be an adhesive, for example, a UV tape made of an ultraviolet-curable resin. According to the UV tape, the adhesive force of the sheet 60 can be controlled depending on the presence or absence of the irradiation of the ultraviolet light, so that the UV tape is suitable for holding the semiconductor substrate 10 and peeling the semiconductor chip 70.
[0057]
In the example shown in FIG. 9, a filler 62 such as a resin is provided between the sheet 60 and the semiconductor substrate 10, and the sheet 60 holds the semiconductor substrate 10 via the filler 62. The filler 62 fills at least the groove 30 of the semiconductor substrate 10 and may be provided on the first surface 20 as shown in FIG. The filler 62 may be applied to the semiconductor substrate 10 from the first surface 20 before attaching the sheet 60, or may be provided on the sheet 60 in advance and provided in the groove 30 by attaching the sheet 60. You may.
[0058]
As a modification, the sheet 60 may be attached to the semiconductor substrate 10 without the filler 62. Alternatively, a part of the sheet 60 may be the filler 62.
[0059]
Thus, the semiconductor substrate 10 is polished from the second surface 22 as shown in FIG. That is, the back surface of the semiconductor substrate 10 is polished. For example, the semiconductor substrate 10 to which the sheet 60 is attached is fixed to a stage (not shown), and the semiconductor substrate 10 is mechanically moved from the second surface 22 by a grindstone provided on a polishing jig (not shown). Grind. In this step, the semiconductor substrate 10 is polished to a thickness at which the groove 30 is exposed. Thereby, the semiconductor substrate 10 can be divided into a plurality of semiconductor chips 70 and each semiconductor chip 70 can be thinned.
[0060]
According to this, since the sheet 60 is adhered to the semiconductor substrate 10 from the first surface 20, a plurality of semiconductor chips 70 divided separately can be held collectively. Therefore, the plurality of divided semiconductor chips 70 can be easily handled.
[0061]
In addition, since the filling material 62 is provided in the groove 30 at the time of the polishing step, it is possible to prevent powdery foreign matter generated in the polishing step from entering the groove 30. Therefore, damage to the semiconductor chip 70 and attachment of foreign matter can be prevented, and the reliability of the semiconductor device can be improved.
[0062]
As shown in FIG. 11, if necessary, an insulating layer (third insulating layer) 72 may be formed on the polished surfaces of the plurality of semiconductor chips 70. If the plurality of semiconductor chips 70 are held on the sheet 60, the polished surfaces of the plurality of semiconductor chips 70 can be collectively subjected to insulation treatment. Further, as shown in FIG. 11, if the filler 62 is provided between the plurality of semiconductor chips 70, for example, after forming the insulating layer 72 on the entire surface including the polished surfaces of the plurality of semiconductor chips 70, The portion of the filler 62 in the layer 72 may be removed by etching. The insulating layer 72 may be formed of the same material as the insulating layer 40. By forming the insulating layer 72, electrical conduction between the polished surface of the semiconductor chip 70 and the outside can be cut off. In addition, since the entire surface of the semiconductor portion (for example, silicon) of the semiconductor chip 70 can be covered with the insulating layers 16, 40, and 72, the portion other than the terminals (for example, the conductive layer 50) of the semiconductor chip 70 may be connected to the outside. Electrical conduction can be cut off.
[0063]
After that, the semiconductor chip 70 is separated from the sheet 60. When the filler 62 is provided between the semiconductor chip 70 and the sheet 60, the semiconductor chip 70 is separated from the filler 62. For example, each semiconductor chip 70 is picked up via a sheet 60 by a tool (not shown). Thus, the individual semiconductor chips 70 can be taken out.
[0064]
According to the method for manufacturing a semiconductor device according to the present embodiment, insulating layer 40 is formed on the inner surface of groove 30 of semiconductor substrate 10. The inner surface of the groove 30 of the semiconductor substrate 10 corresponds to the side surface of the plurality of semiconductor chips 70. Therefore, in the state of the semiconductor substrate 10, the side surfaces of the plurality of semiconductor chips 70 can be collectively subjected to the insulation treatment. Further, since the insulating layer 40 is formed before the semiconductor substrate 10 is polished, it is possible to manufacture an extremely thin semiconductor device while avoiding cracking and damage of the semiconductor substrate 10.
[0065]
Through the above steps, a semiconductor device can be manufactured. 12 and 13 are diagrams illustrating an example of the semiconductor device according to the present embodiment.
[0066]
The semiconductor device 1 includes a semiconductor chip 70 on which the integrated circuit 12 and the electrode 14 are formed, and an insulating layer 40. The insulating layer 40 is formed continuously from the first surface (the surface on which the integrated circuit and the electrodes are formed in FIG. 12) of the semiconductor chip 70 to the side surface continuous therewith. The insulating layer 40 preferably covers the entire side surface of the semiconductor chip 70.
[0067]
In the example shown in FIG. 12, the semiconductor device 1 further includes a conductive layer 50. The conductive layer 50 is formed on the insulating layer 40 on the side surface of the semiconductor chip 70. The portion of the side surface of the semiconductor chip 70 exposed from the conductive layer 50 is covered with the insulating layer 40. The conductive layer 50 has an electrical connection 52 with the electrode 14, and a bump 74 is formed on the connection 52. The bump 74 may be formed by electroless or electroplating, or may be formed of a material containing gold. The bump 74 is electrically connected to the electrode 14. The other configuration is the content obtained by the above-described manufacturing method.
[0068]
As a modification, as shown in FIG. 13, the conductive layer 50 may be omitted. That is, the side surface of the semiconductor chip 70 is covered with the insulating layer 40. In the example shown in FIG. 13, the semiconductor device 3 is mounted on a wiring board (interposer) 80. The wiring substrate 80 has a substrate 82 and a wiring pattern 84 formed on the substrate 82, and electrical connection can be made from both sides through a through hole 86. External terminals (for example, solder balls) 90 may be formed on the side of the wiring substrate 80 opposite to the semiconductor device 3. The semiconductor device 3 is face-down bonded to the wiring board 80. Examples of the form of electrical connection between the two include metal joining, brazing joining, joining with an anisotropic conductive material, and the like. An underfill material (for example, resin) 88 is provided between the semiconductor device 3 and the wiring board 80. Note that the entirety of the semiconductor chip 70 mounted on the wiring board 80 may be referred to as a semiconductor device.
[0069]
FIG. 14 is a diagram showing a circuit board according to the present embodiment. The circuit board (motherboard) 100 has a board 102 and a wiring pattern 104 formed on the board 102. Both the semiconductor device 3 and the wiring pattern 104 may be electrically connected by the brazing material 106. On the circuit board 100, other electronic components (not shown) such as resistors, capacitors, and coils are mounted. According to the present embodiment, the semiconductor device 3 can be mounted on a bare chip.
[0070]
The semiconductor device according to the present embodiment includes a configuration derived from any specific item selected from the above-described manufacturing method, and the effect has the above-described effect. The semiconductor device according to the present embodiment includes one manufactured by a method different from the above-described manufacturing method.
[0071]
As an electronic apparatus having the above-described semiconductor device, a notebook personal computer 1000 is shown in FIG. 15, and a mobile phone 2000 is shown in FIG.
[0072]
The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the invention includes configurations substantially the same as the configurations described in the embodiments (for example, a configuration having the same function, method, and result, or a configuration having the same object and result). Further, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. Further, the invention includes a configuration having the same operation and effect as the configuration described in the embodiment, or a configuration capable of achieving the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.
[Brief description of the drawings]
FIG. 1 is a diagram showing a part of a semiconductor substrate used in an embodiment of the present invention.
FIG. 2 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a sectional view taken along line VI-VI of FIG. 5;
FIG. 7 is a view showing a modification of the method for manufacturing a semiconductor device according to the embodiment of the present invention;
FIG. 8 is a view showing a modification of the method of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 9 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 10 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 11 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 12 is a diagram showing a semiconductor device according to an embodiment of the present invention.
FIG. 13 is a diagram showing a semiconductor device according to an embodiment of the present invention.
FIG. 14 is a diagram showing a circuit board according to an embodiment of the present invention.
FIG. 15 is a diagram showing an electronic apparatus according to the embodiment of the present invention.
FIG. 16 is a diagram illustrating an electronic device according to an embodiment of the present invention.
[Explanation of symbols]
Reference Signs List 10 semiconductor substrate, 12 integrated circuit, 14 electrodes, 16 second insulating layer, 20 first surface, 22 second surface, 30, 32, 34 groove, 40, 44, 46 insulating layer, 50, 54, 56 Conductive layer, 60 sheets, 62 filler, 70 semiconductor chip, 72 third insulating layer

Claims (18)

(A) forming a groove from a first surface in a semiconductor substrate on which an integrated circuit and an electrode are formed;
(B) forming an insulating layer on at least the inner surface of the groove;
(C) polishing the semiconductor substrate from a second surface opposite to the first surface to a thickness at which the groove is exposed, and dividing the semiconductor substrate into a plurality of semiconductor chips; Device manufacturing method. The method for manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein in the step (a), the groove is formed avoiding the electrode. The method for manufacturing a semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein in the step (b), the insulating layer is continuously formed from an inner surface of the groove to the first surface. The method for manufacturing a semiconductor device according to claim 3,
Prior to the step (a), further comprising forming a second insulating layer on the first surface of the semiconductor substrate;
In the method (b), a part of the insulating layer is formed on the second insulating layer. The method of manufacturing a semiconductor device according to claim 1, wherein
A method of manufacturing a semiconductor device, further comprising forming a conductive layer on the insulating layer on the inner surface of the groove after the step (b). The method for manufacturing a semiconductor device according to claim 5,
In the method of manufacturing a semiconductor device, in the step of forming the conductive layer, the conductive layer is continuously formed from an inner surface of the groove to the first surface. The method for manufacturing a semiconductor device according to claim 6,
In the method for manufacturing a semiconductor device, the conductive layer is electrically connected to the electrode in the step of forming the conductive layer. The method for manufacturing a semiconductor device according to claim 1, wherein
A method of manufacturing a semiconductor device, wherein the step (c) is performed in a state where a sheet is attached to the semiconductor substrate from the first surface. The method for manufacturing a semiconductor device according to claim 8,
A method of manufacturing a semiconductor device, wherein the step (c) is performed in a state where a filler is provided in the groove. The method for manufacturing a semiconductor device according to claim 8, wherein:
After the step (c), a method for manufacturing a semiconductor device, further comprising forming a third insulating layer on a polished surface of the plurality of semiconductor chips in a state where the plurality of semiconductor chips are held on the sheet. A semiconductor device manufactured by the method according to claim 1. A semiconductor chip having an integrated circuit and electrodes formed thereon and having a first surface;
An insulating layer formed continuously from the first surface of the semiconductor chip to a side surface continuous with the first surface;
A conductive layer formed on the insulating layer on a side surface of the semiconductor chip,
Including
A semiconductor device in which a portion of a side surface of the semiconductor chip exposed from the conductive layer is covered with the insulating layer. The semiconductor device according to claim 12,
The semiconductor device further includes a second insulating layer formed on the first surface of the semiconductor chip,
A semiconductor device in which a part of the insulating layer is formed over the second insulating layer. The semiconductor device according to claim 12 or 13,
The semiconductor device, wherein the conductive layer is continuously formed from a side surface of the semiconductor chip to the first surface. The semiconductor device according to any one of claims 12 to 14,
The semiconductor device, wherein the conductive layer is electrically connected to the electrode. The semiconductor device according to any one of claims 12 to 15,
A semiconductor device in which a third insulating layer is formed on a second surface of the semiconductor chip opposite to the first surface. A circuit board on which the semiconductor device according to claim 11 is mounted. An electronic apparatus comprising the semiconductor device according to claim 11.

Images