JP2004117168A - Semiconductor integrated circuit and inspection method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit as a mass-produced LSI for greatly reducing the number of external terminals without impairing user-friendliness in evaluating/bugging firmware and in inspecting the semiconductor integrated circuit when shipped. <P>SOLUTION: On a chip of the semiconductor integrated circuit, a bonding pad is prepared for address signals and instruction data signals ranging from a micro-controller to a built-in ROM. While all signals are connected to the external terminals for an evaluation package, the data signals are only connected to the external terminals for a mass-produced package and the address signals are not connected thereto, thus greatly reducing the number of the external terminals. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a built-in microcontroller, and more particularly to a test circuit configuration and a test method for the semiconductor integrated circuit.
[0002]
[Prior art]
In recent years, many semiconductor integrated circuits mainly mounted in information devices have built-in microcontrollers. In these integrated circuits, firmware rather than hardware has become more remarkable, and how perfect the firmware is Whether to improve the quality is a deciding factor in the success or failure of the final semiconductor integrated circuit.
[0003]
Conventionally, in order to improve the completeness of the firmware, a RAM for storing instruction data is mounted inside the semiconductor integrated circuit, and a circuit for downloading instruction data from an external nonvolatile memory is mounted, or the semiconductor integrated circuit itself is used. A method has been adopted in which an evaluation LSI equipped with a non-volatile memory is manufactured, firmware is sufficiently evaluated and debugged on the evaluation LSI, and then a mass-production LSI in which instruction data is stored in a ROM is manufactured.
[0004]
On the other hand, there has been proposed a semiconductor integrated circuit and a manufacturing method capable of evaluating and debugging firmware with a mass-production LSI in which instruction data is stored in a ROM without manufacturing such an evaluation LSI (for example, see Patent Reference 1).
[0005]
FIG. 7 is a block diagram showing a conventional semiconductor integrated circuit. In FIG. 7, reference numeral 101 denotes a semiconductor integrated circuit main body (including a package). Reference numeral 102 denotes an external memory for storing instruction data, which stores firmware for evaluation / debugging or modified firmware. 103a to 103d and 103f are external terminals of the semiconductor integrated circuit. Reference numeral 105 denotes an internal ROM, which stores firmware at the time of manufacturing the semiconductor integrated circuit 101. Reference numeral 107 denotes a selector for selecting and outputting command data from the internal ROM or command data from an external memory input via the external terminal 103b in accordance with a signal from the external terminal 103c. Reference numeral 106 denotes a microcontroller (including peripheral circuits) that operates according to the instruction data selected by the selector 107.
[0006]
The operation of the conventional semiconductor integrated circuit configured as described above will be described below.
[0007]
In FIG. 7, when "1" is input to the external terminal 103c, the selector 107 selects the internal ROM 105 side, and the instruction data is sequentially read from the internal ROM 105 to the microcontroller 106 along the address output from the microcontroller 106. It is. That is, the semiconductor integrated circuit 101 operates according to the initial firmware stored in the internal ROM 105. If there is no particular problem in this operation, the semiconductor integrated circuit 101 becomes a mass production LSI as it is.
[0008]
On the other hand, if there is any problem when operating in the above state, the initial firmware stored in the internal ROM 105 needs to be modified. In that case, by inputting "0" to the external terminal 103c, the selector 107 selects the external terminal 103b side, and the microcontroller 106 is set to a mode in which it operates according to the firmware stored in the external memory 102. In this mode, the modified firmware is sufficiently verified by storing the evaluation / debugging or modified firmware in the external memory 102 and operating the semiconductor integrated circuit 101. Next, the corrected firmware data is re-formed in the internal ROM 105, and the semiconductor integrated circuit is re-manufactured. At this time, since the corrected portion is only the data in the internal ROM 105, it is not necessary to perform the re-layout or the timing verification.
[0009]
As described above, if this conventional semiconductor integrated circuit is used, when shifting from an evaluation LSI to a mass production LSI, it is necessary to start over from the first step in manufacturing a semiconductor integrated circuit, such as layout and timing verification. There is no.
[0010]
[Patent Document 1]
JP-A-2000-252423 (page 3-4, FIG. 1)
[0011]
[Problems to be solved by the invention]
However, the conventional semiconductor integrated circuit having the above configuration requires extra external terminals for securing an address bus and a data bus connected to an external memory, in addition to the external terminals necessary for normal operation of the semiconductor integrated circuit. Become. In general, an increase in the number of external terminals as an LSI has various disadvantageous conditions, such as an increase in cost and reliability of a package and an increase in a mounting area in a small device. Therefore, the conventional semiconductor integrated circuit has these problems accompanying the increase in external terminals.
[0012]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and greatly reduces the number of external terminals as a mass-produced LSI without impairing the ease of firmware evaluation / debugging and the ease of shipment inspection of semiconductor integrated circuits. It is an object to provide a semiconductor integrated circuit that can be reduced.
[0013]
[Means for Solving the Problems]
According to the first aspect of the present invention, a memory for storing instruction data, an external terminal for inputting instruction data from outside, and selecting and outputting one of output data from the memory and data from the external terminal. A selection circuit, and a logic circuit operating in accordance with output data of the selection circuit, and determining whether to connect an address output by the logic circuit to an external terminal according to a type of a package of the semiconductor integrated circuit. A feature of the semiconductor integrated circuit is that in a mass-production package having a small number of external terminals, the number of external terminals can be significantly reduced by not connecting the address output by the logic circuit to the external terminals.
[0014]
According to a fourth aspect of the present invention, there is provided a memory for storing instruction data, a first external terminal for externally inputting instruction data, and one of output data from the memory and data from the first external terminal. A semiconductor integrated circuit including a selection circuit for selecting and outputting, a second external terminal for inputting a selection signal of the selection circuit, and a logic circuit operating in accordance with output data of the selection circuit, wherein the first external terminal Command data input from the semiconductor device and a selection signal input from the second external terminal from the semiconductor inspection device during the shipment inspection of the semiconductor integrated circuit. Inspection can be performed by supplying only from the outside, and the number of inspection program development steps can be reduced.
[0015]
According to a sixth aspect of the present invention, there is provided a memory for storing instruction data, a first external terminal for externally inputting instruction data, and one of output data from the memory and data from the first external terminal. A first selection circuit for selecting and outputting, a logic circuit operating according to output data of the first selection circuit, an internal oscillation circuit for generating a clock signal, and a second external terminal for inputting an external clock signal A second selection circuit that selects and outputs one of a clock signal from the internal oscillation circuit and a clock signal from the second external terminal; and the first selection circuit outputs a signal from the first external terminal. A selection signal input terminal of a second selection circuit that is enabled only when data is selected; and a pull-up resistor connected to the selection signal input terminal. A semiconductor integrated circuit that determines whether or not to connect to the external terminal according to the type of package of the semiconductor integrated circuit. By not connecting the selection signal to the external terminals, the number of external terminals can be further reduced.
[0016]
According to a ninth aspect of the present invention, there is provided an internal oscillating circuit for generating a clock signal, an external terminal for inputting an external clock signal, and selecting one of a clock signal of the internal oscillating circuit and a clock signal from the external terminal. A semiconductor integrated circuit, comprising: a selection circuit that outputs the selected signal; and a clock detection circuit that detects the presence or absence of a clock signal from the external terminal and generates a selection signal for the selection circuit. It is not necessary to separately provide an external terminal for automatically detecting and controlling the switching of the circuit inside, and the number of external terminals can be further reduced.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
FIG. 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment, corresponding to the first aspect of the present invention. 1 (a) and 1 (b) show a state of being mounted on a mass production LSI package and a state of being mounted on an evaluation LSI package, respectively. In FIG. 1, 1a is an LSI package for mass production, 1b is an LSI package for evaluation, 2 is a semiconductor integrated circuit chip body, 3a to 3f are external terminals of the LSI package, 4a to 4f are bonding pads on the semiconductor integrated circuit chip, 5 Is an internal ROM storing a normal operation program, 6 is a microcontroller, 7 is a peripheral circuit controlled by the microcontroller, 8a is an LSI tester, 8b is an external memory for storing a correction program, 9 and 10 are selectors, 11 Is an internal VCO oscillation circuit for generating an internal clock.
[0018]
The operation of the semiconductor integrated circuit according to the first embodiment configured as described above will be described below. First, FIG. 1B in a state of being mounted on an evaluation LSI package will be described.
[0019]
In FIG. 1B, “0” is input to the external terminal 3e, the selector 10 selects the internal VCO oscillation circuit 11 as a clock source, and the semiconductor integrated circuit 2 operates by the clock generated by the internal VCO oscillation circuit 11. I do. This is the same as the normal operation state. When "1" is input to the external terminal 3c, the selector 9 selects the internal ROM 5 side, and instruction data is sequentially read from the internal ROM 5 to the microcontroller 6 along the address output from the microcontroller 6. That is, the semiconductor integrated circuit 2 operates in accordance with the original firmware stored in the internal ROM 5. If there is no particular problem in this operation, the semiconductor integrated circuit 2 is directly mounted on a mass production LSI package to be a mass production LSI.
[0020]
On the other hand, if there is any problem when operating in the above state, the initial firmware stored in the internal ROM 5 needs to be modified. In this case, by inputting "0" to the external terminal 3c, the selector 9 selects the external terminal 3b side, and the microcontroller 6 enters a mode in which it operates according to the firmware stored in the external memory 8b. In this mode, the modified firmware is sufficiently verified by storing the evaluation / debug or modified firmware in the external memory 8b and operating the semiconductor integrated circuit 2. Next, the corrected firmware data is re-formed in the internal ROM 5, and the semiconductor integrated circuit 2 is re-manufactured. At this time, since the correction portion is only the data in the internal ROM 5, it is not necessary to perform the re-layout or the timing verification.
[0021]
Next, FIG. 1A in a state where the semiconductor integrated circuit 2 is mounted on a mass production LSI package will be described.
[0022]
In FIG. 1A, "1" is input to the external terminal 3e, and the selector 10 selects, as a clock source, an external clock signal input from the LSI tester 8a via the external terminal 3d. That is, the semiconductor integrated circuit 2 is driven by the clock generated by the LSI tester 8a, which is the same as the state where the shipment inspection of the LSI is performed. When "0" is input to the external terminal 3c, the selector 9 selects the external terminal 3b side, the microcontroller 6 operates according to the command data output from the LSI tester 8a, and the operation of each part in the semiconductor integrated circuit 2 Perform diagnostics. At this time, since an external clock is supplied to the semiconductor integrated circuit 2 from the LSI tester 8a, the timing and order of instruction data supplied from the LSI tester 8a via the external terminal 3b can be uniquely determined on the tester side. This means that the address generated by the microcontroller 6 is not necessarily required on the LSI tester 8a side. Therefore, at the stage of mounting the semiconductor integrated circuit 2 on the mass production LSI package 1a, the connection from the bonding pad 4a to the external terminal 3a existing in the evaluation LSI package 1b is not performed, so that the external terminal 3a can be deleted. In general, since the bit width of the address bus output by the microcontroller is large, the effect of reducing the external terminals 3a is very large.
In such a semiconductor integrated circuit according to the first embodiment, in a semiconductor integrated circuit having an internal ROM and a built-in microcontroller that can be connected to an external memory, an address output from the microcontroller is connected to an external terminal in a mass production package. By not doing so, the number of external terminals can be significantly reduced.
[0023]
(Embodiment 2)
FIG. 2 is a block diagram showing a method for testing a semiconductor integrated circuit according to a second embodiment, corresponding to the fourth aspect of the present invention. FIG. 3 is a time chart showing an example of the procedure of the inspection method. In FIG. 2, all components are the same as those having the same numbers in FIG. 1A of the first embodiment, and the external terminal 3c for inputting the selection signal of the selector 9 is connected to the LSI tester 8a. Only the different parts are different. Further, the selection signal of the selector 9 is newly described as IESEL, the external instruction data supplied by the LSI tester 8a is described as DT, the internal instruction data supplied from the internal ROM 5 is described as DR, and the output of the selector 9 is described as DI.
[0024]
The operation of the semiconductor integrated circuit inspection method according to the second embodiment configured as described above will be described below. The operation of each unit is the same as that of FIG. 1A of the first embodiment, except that the switching of the selector 9 is controlled by the LSI tester 8a. Hereinafter, an example of the operation will be described with reference to FIG. When power is applied to the semiconductor integrated circuit, the LSI tester 8a gives "1" to the external terminal 3c and keeps the signal IESEL at "1". In this state, the selector 9 selects the instruction data DR from the internal ROM and supplies it to the microcontroller 6. Immediately after the power is turned on, the firmware stored in the internal ROM usually performs initialization of the microcontroller internal registers. Subsequently, the firmware stored in the internal ROM attempts to initialize each component (for example, a register or a buffer) of the peripheral circuit 7 controlled by the microcontroller 6, but at this time, the microcontroller 6 has already performed the normal operation. This is a step of controlling the peripheral circuit 7, and the inspection of the semiconductor integrated circuit becomes redundant. Therefore, at the stage when the instruction data DR from the internal ROM 5 has completed the initial setting of the microcontroller 6, the LSI tester 8a sets the selection signal IESEL to "0", and thereafter the microcontroller 6 sets the instruction data DT from the tester 8a. To the mode that operates according to. Here, the LSI tester 8a supplies the microcontroller with instruction data DT for performing processing required for the shipment inspection of the LSI (for example, Read / Write / Verify of a register or buffer in the peripheral circuit 7).
The inspection method of the semiconductor integrated circuit according to the second embodiment has two major advantages. One is that the logical path (address, data) between the microcontroller 6 and the internal ROM 5 can be inspected with the same inspection pattern as compared with the first embodiment in which the selector 9 is fixed on the external instruction data side. . Another is that the instruction code during the operation of the internal ROM 5 does not need to be included in the inspection program. Therefore, an efficient inspection of a semiconductor integrated circuit can be performed with a small number of inspection steps.
[0025]
(Embodiment 3)
FIG. 4 is a block diagram showing a semiconductor integrated circuit according to a third embodiment corresponding to the invention described in claim 6. FIGS. 4A and 4B show a state in which the semiconductor device is mounted on a mass production LSI package and a state in which the semiconductor device is mounted on an evaluation LSI package, respectively. In FIG. 4, reference numerals 1a, 1b to 11 are the same as those in FIG. Reference numeral 12 denotes a pull-up resistor built in the semiconductor integrated circuit, and reference numeral 13 denotes an AND circuit.
[0026]
The operation of the semiconductor integrated circuit according to the third embodiment configured as described above will be described below. First, FIG. 4B in a state of being mounted on an evaluation LSI package will be described.
[0027]
In FIG. 4B, the operation of each part is the same as that of FIG. 1B of the first embodiment, but the selection signal of the selector 10 is the inverse logic of the selection signal of the selector 9 and the input signal from the bond pad 4e. The difference between the logical product of the selection signal of the selector 10 in FIG. 1B and the connection of the pull-up resistor 12 to the input signal from the bonding pad 4e is different. By inputting "0" to the external terminal 3c, the selector 9 selects the external terminal 3b side, and the microcontroller 6 enters a mode in which it operates according to the firmware stored in the external memory 8b. At this time, since the A input of the AND circuit 13 is "1", the selection signal of the selector 10 is determined by the logic input to the external terminal 3e. In this mode, it is necessary to store the corrected firmware in the external memory 8b and operate the semiconductor integrated circuit 2 in the normal operation mode. Therefore, the external terminal 3e is fixed to "0" and the clock of the internal VCO oscillation circuit is set. To enable. There is no difference between the operation state of the semiconductor integrated circuit 2 and the case of FIG. 1B of the first embodiment.
[0028]
Next, FIG. 4A in a state where the semiconductor integrated circuit 2 is mounted on an LSI package for mass production will be described.
[0029]
In FIG. 4A, the operation of each part is the same as that of FIG. 1A of the first embodiment, but the selection signal of the selector 10 is the inverse of the selection signal of the selector 9 and the input signal (from the bonding pad 4e). In FIG. 1A, the difference between the logical product of the selection signal of the selector 10) and the connection of the pull-up resistor 12 to the input signal from the bonding pad 4e is different. When "0" is input to the external terminal 3c, the selector 9 selects the external terminal 3b side, the microcontroller 6 operates according to the command data output from the LSI tester 8a, and the operation of each part in the semiconductor integrated circuit 2 Perform diagnostics. At this time, since the A input of the AND circuit 13 is "1", the selection signal of the selector 10 is determined by the logic input to the bonding pad 4e. However, the state in which "0" is input to the external terminal 3c in the mass production LSI package 1a is a test state by the LSI tester 8a. In this case, the circuit is not operated by the clock of the internal VCO oscillation circuit 11, and is always operated. The circuit is operated by an externally supplied clock from the LSI tester 8a. Therefore, in the package for mass production, the B input of the AND circuit 13 only needs to be “1” at all times. Therefore, by connecting the B input of the AND circuit 13 to the pull-up resistor 12 inside the semiconductor integrated circuit 2, The connection from the terminal 3e to the bonding pad 4e becomes unnecessary, and the number of external terminals 3e in the mass production LSI package 1a can be reduced. Incidentally, when operating the mass production LSI package 1a in the normal operation mode, inputting "1" to the external terminal 3c enables the internal ROM 5 and the internal VCO oscillation circuit 11.
In the semiconductor integrated circuit according to the third embodiment, the input signal for switching between the internal VCO clock and the external input clock as the driving clock is not connected to the external terminal in the mass production package. In addition, the number of external terminals can be reduced.
[0030]
(Embodiment 4)
FIG. 5 is a block diagram showing a semiconductor integrated circuit according to a fourth embodiment, corresponding to the ninth aspect of the present invention. In FIG. 5, reference numerals 1a to 11 are the same as those in FIG. 14 is a clock detection circuit for detecting that an external clock is supplied to the external terminal 3d, 141 is an OR circuit, and 142 is a D flip-flop.
[0031]
The operation of the semiconductor integrated circuit according to the fourth embodiment configured as described above will be described below.
[0032]
In FIG. 5, the operation of each unit is the same as that of FIG. 2 of the second embodiment, but the selection signal of the selector 10 is set not by the input value from the external terminal 3e but by the output of the clock detection circuit 14. Is different. Hereinafter, the operation of the clock detection circuit 14 will be described with reference to FIG. The D flip-flop 142 holds “0” as an initial value when the power is turned on. Here, the signal RESET is used to initialize the D flip-flop 142 to “0” when the power is turned on, and may be supplied from inside or outside the semiconductor integrated circuit 2. If the external clock signal ECLK input from the input terminal 3d is "1" while the D flip-flop 142 is outputting "0", the output of the OR circuit 141 becomes "0" and the internal Even after the supply of the VCO clock signal ICLK, the D flip-flop 142 keeps “0”. As a result, the selection signal CKSEL of the selector 10 is fixed at “0”, and the entire circuit operates with the internal VCO clock ICLK. That is, by fixing the input of the external terminal 3d to "1", the circuit operates in the normal operation state.
[0033]
On the other hand, when the present LSI is inspected before shipment by the tester 8a, it is necessary to supply an external clock from the LSI tester 8a to operate the LSI. Assuming that the external clock ECLK is supplied from the external terminal 3d while the D flip-flop 142 holds “0” and the internal VCO oscillation circuit 11 is operating, as shown in FIG. The output CKSEL of the clock detection circuit 14 becomes "1" from the point in time when the level "" is detected. The internal operation of the clock detection circuit 14 will be described in detail. When the external clock signal ECLK becomes “0”, the output of the OR circuit 141 becomes “1”. Next, when the internal clock signal ICLK is supplied to the D flip-flop 142, the value of the D flip-flop 142 is updated to “1”. When the value of the D flip-flop 142 becomes "1", the OR circuit 141 always outputs "1" regardless of the value of the external clock signal ECLK, so that the D flip-flop 142 keeps holding "1" as it is. As a result, the selection signal CKSEL of the selector 10 is fixed at "1", and the entire circuit operates with the external clock ECLK supplied from the external terminal 3d. That is, when an external clock is supplied to the external terminal 3d, the clock detection circuit 14 detects the external clock and automatically sets the entire circuit to a mode in which the circuit operates with the external clock.
[0034]
In such a semiconductor integrated circuit according to the fourth embodiment, an external clock signal input from an external terminal is detected, and when a clock signal is detected, the entire circuit is automatically switched to an external clock drive mode. In addition, it is possible to eliminate the need for inputting a clock selection signal set from the outside, and to reduce the number of external terminals.
[0035]
【The invention's effect】
As described above, according to the semiconductor integrated circuit of the present invention, by adopting a circuit configuration for minimizing inputs and outputs to be connected as external terminals when mounting a mass-production LSI package, it is easy to evaluate and debug firmware. The number of external terminals can be greatly reduced without impairing the performance and ease of shipping inspection of the semiconductor integrated circuit, and the practical effect is extremely large.
[Brief description of the drawings]
FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment; FIG. 2 is a block diagram illustrating a test method of a semiconductor integrated circuit according to a second embodiment; FIG. FIG. 4 is a block diagram of a semiconductor integrated circuit according to a third embodiment; FIG. 5 is a block diagram of a semiconductor integrated circuit according to a fourth embodiment; FIG. 6 is a time chart for explaining the operation of the clock detection circuit; 7 is a block diagram of a conventional semiconductor integrated circuit and its inspection method.
1a Mass production LSI package 1b Evaluation LSI package 101 Semiconductor integrated circuit (including package)
2 Semiconductor integrated circuit body chips 3a to 3f, 103a to 103d, 103f External terminals 4a to 4f of LSI Bonding pads on chip 5, 105 Internal ROM
6, 106 Microcontroller 7 Peripheral circuit 8a LSI tester 8b, 102 External memory 9, 10, 107 Selector 11 Internal VCO oscillation circuit 12 Pull-up resistor 13 Logical product circuit 14 Clock detection circuit 141 Logical sum circuit 142 D flip-flop

Claims (10)

A memory for storing instruction data;
An external terminal for inputting instruction data from outside,
A selection circuit that selects and outputs one of output data from the memory and data from the external terminal,
A semiconductor circuit comprising a logic circuit operating in accordance with output data of the selection circuit, and determining whether or not to connect an address output by the logic circuit to an external terminal according to a type of a package of the semiconductor integrated circuit; Integrated circuit. The semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit wherein an address output from the logic circuit is connected to an external terminal in a package having a large number of external terminals, and an address output from the logic circuit is not connected to an external terminal in a package having a small number of external terminals. The semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit, wherein an address output from the logic circuit is connected to an external terminal in a package for mass production, and an address output from the logic circuit is not connected to an external terminal in a package for function evaluation. A memory for storing instruction data;
A first external terminal for inputting instruction data from outside;
A selection circuit that selects and outputs one of output data from the memory and data from the first external terminal;
A second external terminal for inputting a selection signal of the selection circuit;
In a semiconductor integrated circuit having a logic circuit operating in accordance with output data of the selection circuit, command data input from the first external terminal and a selection signal of the selection circuit input from the second external terminal are output from the semiconductor device. A method for inspecting a semiconductor integrated circuit, wherein the method is supplied from a semiconductor inspection apparatus at the time of an inspection for shipping the integrated circuit. The inspection method of a semiconductor integrated circuit according to claim 4,
A method for inspecting a semiconductor integrated circuit, wherein the semiconductor inspection apparatus supplies an instruction code required for shipping inspection to the semiconductor integrated circuit when the selection circuit selects data from outside. A memory for storing instruction data;
A first external terminal for inputting command data from outside, a first selection circuit for selecting and outputting any of output data from the memory and data from the first external terminal,
A logic circuit that operates according to output data of the first selection circuit;
An internal oscillation circuit for generating a clock signal,
A second external terminal for inputting an external clock signal;
A second selection circuit that selects and outputs one of a clock signal from the internal oscillation circuit and a clock signal from the second external terminal;
A selection signal input terminal of a second selection circuit that is enabled only when the first selection circuit is selecting data from the first external terminal;
A pull-up resistor connected to the selection signal input terminal is provided, and whether or not the selection signal input terminal of the second selection circuit is connected to an external terminal is determined according to the type of the package of the semiconductor integrated circuit. A semiconductor integrated circuit characterized by the above-mentioned. 7. The semiconductor integrated circuit according to claim 6, wherein a selection signal of said second selection circuit is connected to an external terminal in a package having a large number of external terminals, and a selection signal of said second selection circuit is transmitted in a package having a small number of external terminals. A semiconductor integrated circuit not connected to an external terminal. 7. The semiconductor integrated circuit according to claim 6, wherein a selection signal of said second selection circuit is connected to an external terminal in a package for mass production, and a selection signal of said second selection circuit is connected to an external terminal in a package for function evaluation. A semiconductor integrated circuit not connected. An internal oscillation circuit for generating a clock signal,
An external terminal for inputting an external clock signal,
A selection circuit that selects and outputs one of a clock signal of the internal oscillation circuit and a clock signal from the external terminal;
A semiconductor integrated circuit, comprising: a clock detection circuit that detects the presence or absence of a clock signal from the external terminal and generates a selection signal of the selection circuit. 10. The semiconductor integrated circuit according to claim 9, wherein the clock detection circuit includes an OR circuit and a D flip-flop.

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