JP2004194468A - DC / DC converter - Google Patents

Abstract

A DC / DC converter capable of preventing a switch element from being continuously turned on and damaged even when an off-timing pulse cannot be detected.
The DC / DC converter includes a chopping switch, a V / F circuit for generating an on-timing pulse, a processing circuit for generating an off-timing pulse, and a drive pulse voltage. Turning on / off the output of the drive pulse voltage Vp supplied from the voltage supply means 11 in accordance with the voltage supply means (here, the V / F circuit 11) for supplying Vp and the pulses Son and Soff generated by the circuits 11 and 13. And a generating circuit 15 for driving the switch 3 on and off with the driving pulse P. The voltage supply means 11 supplies a square pulse voltage to the generating circuit 15 as the driving pulse voltage Vp. .
[Selection] Fig. 2

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a DC / DC converter, and more particularly, to a technique for on / off control of chopping switch means.
[0002]
[Prior art]
Some DC / DC converters of the zero-current switching system include a current resonance switch so that the zero-current switching is performed reliably even if the cycle in which the resonance current of the current resonance switch becomes zero or less changes due to aging or the like. It is known that a turn-off cycle is corrected in accordance with a change in a cycle at which the resonance current becomes equal to or less than zero (Patent Document 1).
[0003]
FIG. 1 is a schematic diagram of the above-described conventional zero-current switching type DC / DC converter, FIG. 4 is a schematic diagram of the PFM control unit 107 in FIG. 1, and FIG. 5 is an output from each processing circuit in the PFM control unit 107. FIG. 4 is a timing chart of a processed signal to be performed. In FIG. 1, Vout is an output voltage obtained by stepping down the input voltage Vin, I is a resonance current flowing through the resonance reactor L1, and P is a drive pulse for driving the chopping switch element Q of the current resonance switch 3 on and off. , Vp are drive pulse voltages.
[0004]
In the PFM control unit 107 of the above-described conventional zero-current switching DC / DC converter 100, a drive pulse P is generated as described below, and the switch element Q is turned on and off. That is, in the PFM control section 107, as shown in FIGS. 4 and 5, the output voltage Vout matches the target value based on the output voltage Vout by the (1) voltage frequency conversion circuit (hereinafter referred to as V / F circuit) 11. The on-timing pulse Son is generated while the repetition period T1 of the on-timing pulse Son is adjusted so as to be supplied to the generation circuit 15, and the (2) off-timing pulse is generated by the processing circuit system 13 based on the resonance current I. An off-timing pulse Soff is generated and supplied to the generation circuit 15 so that the rising point of Soff is included in a period in which the resonance current I is equal to or less than zero. (3) The generation circuit 15 turns on and off the output of the drive pulse voltage Vp supplied from the predetermined voltage supply means in accordance with the pulses Son and Soff, thereby generating the drive pulse P and outputting it to the switch element Q. The switching element Q is turned on and off by the driving pulse P. In particular, by the above process (2), the turn-off cycle of the switching element Q of the current resonance switch 3 is corrected so as to coincide with the cycle at which the resonance current I becomes zero or less.
[0005]
[Patent Document 1] JP-A-2002-58240
[Problems to be solved by the invention]
However, in the conventional zero-current switching type DC / DC converter 100, when the off-timing pulse Soff is not detected by the generation circuit 15 due to a malfunction or the like, the output of the drive pulse voltage Vp continues to be turned on. Therefore, there is a problem that the switch element Q may be continuously turned on and damaged.
[0007]
Therefore, an object of the present invention is to provide a chopping circuit according to a drive pulse generated by turning on and off the output of a drive pulse voltage according to an on-timing pulse and an off-timing pulse, as in the zero current switching type DC / DC converter. In a DC / DC converter in which the switch element is turned on and off, a DC / DC converter capable of preventing the switch element from being continuously turned on and damaged even when the off-timing pulse cannot be detected. It is in.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention according to claim 1 includes switching means for chopping, first generating means for generating an on-timing pulse, and second generating means for generating an off-timing pulse. Voltage supply means for supplying a drive pulse voltage, and the drive supplied from the voltage supply means in accordance with the on-timing pulse and the off-timing pulse generated by the first generation means and the second generation means. A DC / DC converter comprising: a third generation unit that generates a drive pulse by turning on / off an output of a pulse voltage and drives the switch unit on / off by the drive pulse; A rectangular pulse voltage is supplied to the third generating means as a driving pulse voltage.
[0009]
In the invention described in claim 2, the voltage supply unit is shared by the first generation unit, and the drive pulse voltage is also shared by the on-timing pulse.
[0010]
According to a third aspect of the present invention, the switch unit is configured as a current resonance switch, and the second generation unit is configured to switch the off-state during a period in which a resonance current flowing through a resonance reactor of the current resonance switch becomes zero or less. By supplying a timing pulse to the third generating means, the switch means is switched to zero current, and the first generating means is configured to control the on-timing having a pulse width larger than a period during which the resonance current becomes zero or more. This is to generate a pulse.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
<First embodiment>
FIG. 1 is a schematic configuration diagram of a DC / DC converter according to a first embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a PFM control unit 7 in FIG. 1, and FIG. FIG. 4 is a timing chart of a processing signal output from a processing circuit.
[0012]
The DC / DC converter 1 according to this embodiment is configured as a zero current switching type DC / DC converter, and chops an input voltage Vin from a DC power supply B to a predetermined duty ratio as shown in FIG. A current resonance switch 3 (switch means), a low-pass filter 5 for smoothing a voltage chopped by the current resonance switch 3 and outputting the smoothed voltage as a DC output voltage Vout to a load R, and a PFM for PFM controlling the current resonance switch 3 And a control unit 7.
[0013]
The current resonance switch 3 includes, for example, a switching element Q for chopping connected in series to the anode of the DC voltage B, a diode D1 connected in parallel in the opposite direction to the switching element Q, and a downstream of the switching element Q, as in the related art. A resonance reactor L1 connected in series at one end, a resonance capacitor C1 interposed between a connection line g connecting the negative electrode of the power supply B and the downstream end of the load R, and a downstream end of the reactor L1. , A current detection circuit 9 interposed between the reactor L1 and the capacitor C1 to detect a resonance current I flowing through the reactor L1. The current detection circuit 9 outputs the detection result to the PFM control unit 7 as a voltage proportional to the resonance current I (hereinafter, referred to as a detection result voltage). The resonance current I is defined as positive (I> 0) when flowing from the upstream side to the downstream side of the reactor L1 (from the left side to the right side on the paper), and from the downstream side of the reactor L1 to the upstream side (the right side to the left side on the paper). The flow is assumed to be negative (I <0).
[0014]
The switching element Q is turned on and off by a driving pulse P output from the PFM control unit 7. When the switch element Q is turned on, zero current switching is performed by delaying the increase in current flowing through the switch element Q due to the electromagnetic induction of the reactor L1 accompanying the turn-on. The turn-off of the switch element Q is performed while the resonance current I is inverted from positive to negative (specifically, zero or less) and flows to the power supply B side via the diode D1, as described later (the switch element during this time). (The current flowing through Q becomes zero), thereby performing zero current switching.
[0015]
The low-pass filter 5 includes, for example, a smoothing reactor L2 interposed between a connection point between the current detection circuit 9 and the capacitor C1 and an upstream end of the load R, a reactor L2 and a load R A smoothing capacitor C2 interposed between a connection point between the capacitor C1 and the reactor L2 and a connection line g between the connection point g and the connection line g between the capacitor C1 and the reactor L2. And a circulation diode D2. The diode D2 serves to circulate and discharge electromagnetic induction energy generated in the reactor L2 as the switch element Q is turned off in the order of L2 → R → D2 → L2.
[0016]
The PFM control unit 7 is different from the conventional PFM control unit 107 in that a rectangular pulse-shaped voltage is used as the drive pulse voltage Vp and that the drive pulse voltage Vp is used in existing components. A signal (here, for example, an on-timing pulse Son) has the same configuration except that the on-timing pulse is used based on the output voltage Vout output from the low-pass filter 5 as shown in FIG. A V / F circuit 11 (first generating means and voltage supply means) for generating a Son, and a processing circuit system 13 (second processing circuit) for generating an off-timing pulse Soff based on the resonance current I detected by the current detecting circuit 9 Generating means), and driving pulses supplied from the existing components (here, for example, the V / F circuit 11) according to the pulses Son and Soff supplied from the circuits 11 and 13. And a generating circuit 15 for generating a driving pulse P by turning on and off the output voltage Vp (third generation means).
[0017]
The V / F circuit 11 and the processing circuit system 13 are configured as follows.
[0018]
2 and 3, the V / F circuit 11 adjusts the repetition period T1 of the on-timing pulse Son based on the output voltage Vout so that the output voltage Vout coincides with the target value, as shown in FIGS. While generating the ON-timing pulse Son and supplying the generated ON-timing pulse Son to the generating circuit 15 as a drive pulse voltage Vp. More specifically, in the process (1), for example, the V / F circuit 11 increases the pulse width T6 of the on-timing pulse Son to a value equal to or greater than the period T2 during which the resonance current I is equal to or less than zero (that is, I ≦ 0) ( That is, T6 ≧ T2) and the on-timing pulse Son is generated such that the pulse width T6 of the on-timing pulse Son becomes smaller than the maximum time T7 at which the switch element Q can be continuously turned on without failure (ie, T7 ≧ T6). (Here, for example, the pulse width T6 of the on-timing pulse Son is set to be half the repetition period T1 (that is, the duty ratio 0.5) when the repetition period T1 is adjusted to be the smallest). . The above condition (T6 ≧ T2) prevents the rising time and the falling time of the drive pulse P from being included in the period T2 arbitrarily and from being hard-switched without permission. Further, even when the off-timing pulse Soff is not detected by the generation circuit 15 under the above condition (T7 ≧ T6) (in this case, P = Vp = Son), the pulse width T6 of the driving pulse P is longer than the period T7. This prevents the switching element Q from being continuously turned on and causing a failure.
[0019]
The processing circuit system 13 includes a voltage dividing circuit 13a, a comparing circuit 13b, a first delay circuit 13c, a second delay circuit 13d, a NOT circuit 13e, and an AND circuit 13f.
[0020]
As shown in FIGS. 2 and 3, the voltage dividing circuit 13a gradually holds the peak value Ip of the resonance current I (specifically, a detection result voltage proportional to the resonance current I) detected by the current detection circuit 9. At the same time, a predetermined ratio of the held peak value Ip is output as a threshold value Ith to the comparison circuit 13b, and includes a capacitor C and resistors R1 and R2. The resistors R1 and R2 are connected in parallel to the capacitor C in a state where they are connected in series with each other, and a connection point between the resistors R1 and R2 is connected to the comparison circuit 13b. In the voltage dividing circuit 13a, when the capacitor C is charged with the resonance current I, the peak value Ip of the resonance current I (specifically, a detection result voltage proportional to the resonance current I) is gradually reduced by the capacitor C as a charging voltage. And a predetermined ratio (= R2 / (R1 + R2)) of the charging voltage is output to the comparison circuit 13b as the threshold value Ith.
[0021]
As shown in FIGS. 2 and 3, the comparison circuit 13b includes a resonance current I (specifically, a detection result voltage proportional to the resonance current I) detected by the current detection circuit 9 and a threshold value Ith obtained from the voltage division circuit 13a. And outputs the H level signal S1 to the first delay circuit 13c only during the period of I ≧ Ith.
[0022]
As shown in FIG. 3, the first delay circuit 13c is configured to delay the signal S1 from the comparison circuit 13b for a predetermined time so that the falling point of the signal S1 is delayed after the time point t1 when the resonance current I is inverted from positive to negative. The signal is delayed by T4 and output as a signal S2 to the second delay circuit 13d and the NOT circuit 13e. The falling point of the signal S2 is the rising point of the off-timing pulse Soff.
[0023]
The second delay circuit 13d delays the signal S2 from the first delay circuit 13c by a predetermined time T5 and outputs the signal S3 to the AND circuit 13f. The falling point of the signal S3 is the falling point of the off-timing pulse Soff.
[0024]
The NOT circuit 13e inverts the signal S2 from the first delay circuit 13c and outputs it as a signal S4 to the AND circuit 13f.
[0025]
The AND circuit 13f generates an off-timing pulse on Soff from the signals S3 and S4 from the circuits 13e and 13d and supplies the generated off-timing pulse on Soff to the generating circuit 15.
[0026]
According to the DC / DC converter 1 configured as described above, a rectangular pulse voltage is supplied to the generation circuit 15 as the drive pulse voltage Vp, so that the generation circuit 15 detects the off-timing pulse Soff due to a malfunction or the like. Even if the output of the driving pulse voltage Vp continues to be turned on without being turned on, the output of the driving pulse voltage Vp can be automatically turned off substantially by the L level period of the driving pulse voltage Vp itself. It is possible to prevent the Q from being continuously turned on and being damaged.
[0027]
Further, the voltage supply means is also used by an existing component (here, for example, the V / F circuit 11), and the drive pulse voltage Vp is used as the processing signal (here, for example, the on-timing pulse Son) used by the existing component. The driving pulse voltage Vp in the form of a square pulse can be supplied easily and inexpensively using existing components.
[0028]
The switching means for chopping is configured as the current resonance switch 3, and the processing circuit system 13 generates the off-timing pulse Soff while the resonance current I flowing through the resonance reactor L1 of the current resonance switch 3 is equal to or less than zero. The ON timing pulse Son is generated by the V / F circuit 11 so that the pulse width T6 of the ON timing pulse Son becomes larger than the period T2 during which the resonance current I is equal to or greater than zero, and is generated as the drive pulse voltage Vp. Since the current resonance switch 3 is subjected to zero current switching by being supplied to the generation circuit 15, the above effect can be easily applied to a DC / DC converter of a zero current switching system.
[0029]
In this embodiment, the voltage supply means is also used by an existing component (here, for example, the V / F circuit 11), and the driving pulse voltage Vp is used as a processing signal (here, a processing signal) used by the existing component. For example, the case where the voltage is shared by the ON timing pulse Son) has been described, but the voltage supply means may be provided as a dedicated power supply circuit for supplying the rectangular pulse voltage.
[0030]
【The invention's effect】
According to the first aspect of the present invention, a rectangular pulse-shaped voltage is supplied to the third generator as the drive pulse voltage, so that the off-timing pulse is not detected by the third generator due to a malfunction or the like. Even if the output of the drive pulse voltage continues to be turned on, the output of the drive pulse voltage can be automatically turned off substantially by the L level period of the drive pulse voltage itself, whereby the switch means continues to be turned on and damaged. Can be prevented.
[0031]
According to the second aspect of the present invention, the voltage supply unit is shared by the first generation unit and the second generation unit, and the drive pulse voltage is used in the process of generating the on-timing pulse and the on-timing pulse. Since the signal or the processing signal used in the process of generating the off-timing pulse is also used, the driving pulse voltage in the form of a square pulse can be supplied easily and inexpensively using existing components.
[0032]
According to the third aspect of the present invention, the switch means is configured as a current resonance switch, and the second generation means generates the off-timing pulse during a period in which the resonance current flowing through the resonance reactor of the current resonance switch becomes zero or less. The on-timing pulse is supplied to the third generating means, and the first generating means generates the on-timing pulse so that the pulse width of the on-timing pulse is larger than a period during which the resonance current is equal to or greater than zero. Since the switching means is switched to zero current by being supplied to the third generating means, the effect of claim 1 or 2 can be easily applied to a zero current switching type DC / DC converter. .
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a DC / DC converter according to a first embodiment of the present invention and a schematic configuration diagram of a conventional DC / DC converter.
FIG. 2 is a schematic configuration diagram of a PFM control unit 7 in FIG.
FIG. 3 is a timing chart of a processing signal output from each processing circuit in a PFM control unit 7 in FIG. 1;
FIG. 4 is a schematic configuration diagram of a PFM control unit 107 (that is, a conventional PFM control unit) in FIG. 1;
FIG. 5 is a timing chart of a processing signal output from each processing circuit in the PFM control unit 107 in FIG. 1;
[Explanation of symbols]
REFERENCE SIGNS LIST 1 DC / DC converter 3 current resonance switch 11 V / F circuit 13 processing circuit system 15 generation circuit Vp drive pulse voltage Son on-timing pulse Soff off-timing pulse P drive pulse I resonance current Q switch element

Claims (3)

Switch means for chopping, first generation means for generating an on-timing pulse, second generation means for generating an off-timing pulse, voltage supply means for supplying a drive pulse voltage, and the first generation means Means for generating a drive pulse by turning on and off the output of the drive pulse voltage supplied from the voltage supply means according to the on-timing pulse and the off-timing pulse generated by the means and the second generation means. A DC / DC converter comprising: a third generation unit that drives the switch unit on and off by a pulse;
The DC / DC converter, wherein the voltage supply unit supplies a square pulse voltage as the drive pulse voltage to the third generation unit. The voltage supply unit is shared by the first generation unit,
The DC / DC converter according to claim 1, wherein the drive pulse voltage is shared by the ON timing pulse. The switch means is configured as a current resonance switch,
The second generating means supplies the off-timing pulse to the third generating means during a period in which the resonance current flowing through the resonance reactor of the current resonance switch is equal to or less than zero, so that the switch means has a zero current. Switching,
3. The DC / DC converter according to claim 1, wherein the first generation unit generates the on-timing pulse having a pulse width larger than a period during which the resonance current is zero or more. 4.

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