JP2004194118A - Soft change-over switch and analog signal processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a soft change-over switch and an analog signal processing circuit using the soft change-over switch which are capable of reducing generation of change-over noises without taking special measures to invite cost increase in changeover of an analog signal and of decreasing a sense of acoustic incongruity by performing smooth changeover even if there are abrupt changes in level. <P>SOLUTION: The soft change-over switch is equipped with an analog switch 1 connecting an NMOS transistor 1a and a PMOS transistor 1b in parallel and a switch control circuit 2 for increasing and decreasing a gate voltage of the NMOS transistor 1a and the PMOS transistor 1b linearly or stepwise and performing complement so that on-resistance in intermediate state between on-state and off-state of the analog switch is connected. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a soft changeover switch and an analog signal processing circuit using the soft changeover switch.
[0002]
[Prior art]
In the field of audio, noise generated when switching an analog signal is output from a speaker as a very unpleasant sound, which is a problem. As a circuit for switching the analog signal, for example, there is a volume circuit for switching a set value. There are various types of volume circuits. Here, an electronic volume circuit described in Patent Document 1 will be described as an example.
[0003]
The electronic volume circuit includes a resistance ladder in which a plurality of resistance elements are connected in series, a plurality of switches for deriving one resistance value from the resistance ladder, and an OP amplifier for amplifying a signal indicating one derived resistance value. And a volume control circuit for turning on / off each switch.
[0004]
In this electronic volume circuit, the input analog signal changes every moment, but if the switch can be switched at the zero-cross point that matches the signal reference level, no switching noise occurs if the signal level does not change before and after the switching. . However, if there is a DC offset component in the output of the preceding circuit, the reference level is not crossed in the absence of a signal, so that the zero-cross switching cannot be performed.
[0005]
In preparation for such a case, when the zero crossing does not occur within the set time, the switch is forcibly switched, so that switching noise is inevitably generated. Therefore, it is often the case that a capacitor for cutting off the DC component is provided between the output terminal of the preceding circuit and the input terminal of the electronic volume circuit. In this case, since the capacitor for cutting the DC component has a large capacity and is difficult to realize in an integrated circuit, the integrated circuit is provided with a pin for externally connecting the capacitor.
[0006]
[Patent Document 1]
JP-A-2002-26670 (0002-0005, FIG. 6)
[0007]
[Problems to be solved by the invention]
However, in the method of coping with the generation of the switching noise by externally attaching a capacitor for cutting a DC component, the number of necessary pins of the integrated circuit increases in accordance with the number of signal channels to be handled, thereby increasing the package cost of the integrated circuit. Further, since input signals are different in all of the signal channels to be handled, a zero-cross detection circuit is required individually. As a result, the circuit scale and the chip area increase, which affects the price of the integrated circuit. On the other hand, even if the zero-cross switching can be executed correctly, if there is a sudden level change, a sense of incongruity occurs in the audibility as in the case of the occurrence of the switching noise.
[0008]
The above problem is a problem that occurs not only in a volume circuit but also in a circuit such as a mute circuit and a selector circuit that should not cause a rapid change when switching an analog signal, and an improvement is desired.
[0009]
The present invention has been made in view of the above, and it is possible to reduce the occurrence of switching noise without taking special measures that cause an increase in cost in switching analog signals, and to perform smooth switching even when there is a sudden level change. It is an object of the present invention to provide a soft changeover switch capable of reducing a sense of incongruity in hearing and an analog signal processing circuit using the soft changeover switch.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a soft changeover switch according to the present invention includes an analog switch in which an NMOS transistor and a PMOS transistor are connected in parallel, and a gate voltage of the NMOS transistor and the PMOS transistor that increases or decreases linearly or stepwise. A switch control circuit that complements the on-resistance of the analog switch in an intermediate state between the on state and the off state.
[0011]
According to the present invention, the ON resistance between the ON state and the OFF state of the analog switch is complemented so as to be connected and applied to the input analog signal, so that a smooth switching can be realized, and the analog signal is generated when the analog signal is switched. This makes it possible to reduce switching noise. Further, even if there is a sudden change at the time of switching the analog signal, the change can be slowed down, and it is possible to reduce a sense of discomfort in hearing. Therefore, it is possible to realize a circuit in which no abrupt change should occur when switching the analog signal.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0013]
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a configuration of a soft changeover switch according to Embodiment 1 of the present invention. The soft changeover switch shown in FIG. 1 includes an analog switch 1 in which an NMOS transistor 1a and a PMOS transistor 1b are connected in parallel, and controls the gate voltage of the NMOS transistor 1a and the PMOS transistor 1b in response to a switching command to reduce the on-resistance. And a switch control circuit 2 that changes continuously.
[0014]
Next, the operation of the soft changeover switch shown in FIG. 1 will be described with reference to FIGS. FIG. 2 is a characteristic diagram showing the relationship between the on-resistance and the control voltage of the analog switch shown in FIG. FIG. 3 is a time chart when the switch control circuit shown in FIG. 1 generates a control voltage by increasing or decreasing the control voltage linearly.
[0015]
In FIG. 2, the horizontal axis represents the control voltage applied to the analog switch 1, and the vertical axis represents the on-resistance indicated by the analog switch 1.
[0016]
The analog switch 1 is generally used in two states, an ON state and an OFF state. That is, at the time of switch-on, the NMOS transistor 1a is controlled at the highest voltage (control voltage of complete ON), and the PMOS transistor 1b is controlled at the lowest voltage (control voltage of complete ON). When the switch is turned off, the NMOS transistor 1a is controlled by the lowest voltage (completely off control voltage OFF), and the PMOS transistor 1b is controlled by the highest voltage (completely off control voltage OFF).
[0017]
Here, assuming that the analog switch 1 is a resistor, the on-resistance Ron when the analog switch 1 is completely off is infinite (Ron (∞)), and the on-resistance Ron when the analog switch 1 is completely on is: The minimum is (Ron (min)). The on-resistance Ron in the intermediate state is Ron (min) ≦ Ron ≦ Ron (∞). The on-resistance Ron in the intermediate state between the on-state and the off-state is, as shown in FIG. The connection can be complemented by changing the control voltage applied to the control signal 1.
[0018]
That is, the switch control circuit 2 enables the analog switch 1 to be used even in an intermediate state between the ON state and the OFF state. In the first embodiment, the switch control circuit 2 uses an analog circuit such as a CR delay circuit using a resistive element and a capacitive element and an integrator using an OP amplifier, for example, as shown in FIG. A control voltage which increases and decreases in a manner is generated and complemented in an analog manner.
[0019]
In FIG. 3, the switch control circuit 2 causes the switching command (1) input from the outside to rise from a low level (hereinafter, referred to as “L” level) to a high level (hereinafter, referred to as “H” level). , The control voltages (2) and (3) applied to the NMOS transistor 1a and the PMOS transistor 1b are generated. As shown in (2), a control voltage that rises linearly with a certain slope from the completely off level to the completely on level is applied to the gate electrode of the NMOS transistor 1a. Further, as shown in (3), a control voltage is applied to the gate electrode of the PMOS transistor 1b, which falls linearly with a certain slope from the completely off level to the completely on level.
[0020]
As a result, the ON resistance in the intermediate state between the ON state and the OFF state of the analog switch 1 can be continuously complemented, so that smooth switching can be realized. Therefore, it is possible to reduce the switching noise generated at the time of switching the analog signal without taking any special measures that cause an increase in cost. Further, even if there is a sudden change at the time of switching the analog signal, the change can be slowed down, and it is possible to reduce a sense of discomfort in hearing. In short, it is possible to realize a circuit in which no abrupt change should occur when switching the analog signal.
[0021]
Embodiment 2 FIG.
FIG. 4 is a circuit diagram showing a configuration of the soft changeover switch according to the second embodiment of the present invention. Note that, in FIG. 4, components that are the same as or equivalent to the configuration illustrated in FIG. 1 are denoted by the same reference numerals. Here, a description will be given focusing on a portion relating to the second embodiment.
[0022]
In the soft changeover switch shown in FIG. 4, a switch control circuit 11 is provided instead of the switch control circuit 2 in the configuration shown in FIG. The switch control circuit 11 uses a digital-to-analog conversion circuit to generate a control voltage that increases and decreases in a stepwise manner, for example, as shown in FIG. 5, and reduces the on-resistance of the analog switch 1 in an intermediate state between the on state and the off state. It complements discretely.
[0023]
FIG. 5 is a time chart in the case where the switch control circuit shown in FIG. 4 generates the control voltage by increasing or decreasing the control voltage in a stepwise manner. In FIG. 5, the switch control circuit 11 causes the switching command (1) input from the outside to rise from a low level (hereinafter, referred to as “L” level) to a high level (hereinafter, referred to as “H” level). , The control voltages (2) and (3) applied to the NMOS transistor 1a and the PMOS transistor 1b are generated. As shown in (2), a control voltage that rises stepwise with a certain slope from the completely off level to the completely on level is applied to the gate electrode of the NMOS transistor 1a. Further, as shown in (3), a control voltage is applied to the gate electrode of the PMOS transistor 1b, which falls stepwise with a certain slope from the completely off level to the completely on level.
[0024]
As a result, the on-resistance in the intermediate state between the on state and the off state of the analog switch 1 can be almost continuously complemented, so that smooth switching can be realized as in the first embodiment, and the same effect as in the first embodiment can be obtained. can get. In addition, when the number of bits of the digital-to-analog conversion circuit is increased, the number of steps (the number of switching) increases, so that more detailed switching is possible. In other words, the designer can freely design the switching type, and the user can freely select it.
[0025]
Embodiment 3 FIG.
FIG. 6 is a circuit diagram showing a configuration of a soft changeover switch according to Embodiment 3 of the present invention. In FIG. 6, components that are the same as or equivalent to the configuration shown in FIG. 4 are denoted by the same reference numerals. Here, a description will be given focusing on a portion relating to the third embodiment.
[0026]
In the soft changeover switch shown in FIG. 6, in the configuration shown in FIG. 4, between the switch control circuit 11 and the analog switch 1, delay elements 12 and 13 for reducing the step-like control voltage output from the switch control circuit 11 are provided. Is provided.
[0027]
FIG. 7 is a time chart for explaining the operation of the delay element shown in FIG. In FIG. 7 (2), the switch control circuit 11 generates a control voltage that rises stepwise with a certain slope from the complete off level to the complete on level, and the delay element 12 controls the stepwise control. The voltage is blunted and applied to the gate electrode of the NMOS transistor 1a. In FIG. 7 (3), the switch control circuit 11 generates a control voltage that drops stepwise with a certain slope from the complete off level to the complete on level, and the delay element 13 controls the stepwise control. The voltage is reduced and applied to the gate electrode of the PMOS transistor 1b.
[0028]
Thus, the step-like control voltage can be made close to the continuously changing control voltage described in the first embodiment, so that smooth switching can be realized as in the first embodiment. Similar effects can be obtained.
[0029]
Embodiment 4 FIG.
FIG. 8 is a circuit diagram showing a configuration of the analog signal processing circuit according to the fourth embodiment of the present invention. In the fourth embodiment, a configuration example of a variable volume circuit (1) is shown as an analog signal processing circuit (1) using the soft changeover switch described in the first to third embodiments. However, the delay element in the soft changeover switch shown in the third embodiment is not shown. This point is the same in the following embodiments.
[0030]
8, the soft changeover switch 19 includes the analog switch 20 and the switch control circuit 21 as described in the first to third embodiments. In the variable volume circuit shown in FIG. 8, a fixed resistance element 27 is connected to one terminal of the soft changeover switch 19, and the connection point 25 is used as a voltage dividing output terminal.
[0031]
FIG. 9 is a diagram illustrating the operation of the signal processing circuit (variable volume circuit) shown in FIG. The equivalent circuit of the variable volume circuit is a series circuit of the on-resistance value Ron (V) of the analog switch 20 and the resistance value R of the fixed resistance element 27, as shown in FIG.
[0032]
Assuming that an analog signal voltage applied to the analog switch 20 is Vin1 and an analog signal voltage applied to the fixed resistance element 27 is Vin2, the divided voltage appearing at the divided output terminal 25 is as shown in FIG. Then, it can be expressed as {R / (Ron (V) + R)} × Vin1 + {Ron (V) / (Ron (V) + R)} × Vin2. Since the on-resistance value Ron (V) can be variably set by the switch control circuit 21, a variable divided voltage is obtained at the divided output terminal 25.
[0033]
Embodiment 5 FIG.
FIG. 10 is a circuit diagram showing a configuration of the analog signal processing circuit according to the fifth embodiment of the present invention. In the fifth embodiment, a configuration example (2) of a variable volume circuit is shown as an analog signal processing circuit (2) using the soft changeover switch described in the first to third embodiments.
[0034]
In FIG. 10, the soft changeover switches 29 and 32 include analog switches 30 and 33 and switch control circuits 31 and 34 as described in the first to third embodiments. In the variable volume circuit shown in FIG. 10, the two soft changeover switches 29 and 32 are connected in series, and the connection point 36 is used as a voltage dividing output terminal.
[0035]
FIG. 11 is a diagram illustrating the operation of the signal processing circuit (variable volume circuit) shown in FIG. As shown in FIG. 9A, the equivalent circuit of the variable volume circuit is a series circuit of the on-resistance Ron (V1) of the analog switch 30 and the on-resistance Ron (V2) of the analog switch 33.
[0036]
Further, when specifically indicated by a symbol representing a resistance element, the on-resistance values Ron (V1) and Ron (V2) can be variably set by the switch control circuits 31 and 34, and as shown in FIG. It is a series circuit of two variable resistance elements.
[0037]
Assuming that the analog signal voltage applied to the analog switch 30 is Vin (1) and the analog signal voltage applied to the analog switch 33 is Vin (2), the divided voltage appearing at the divided output terminal 36 is as shown in FIG. As shown in 3), {Ron (V2) / (Ron (V1) + Ron (V2))} × Vin (1) + {Ron (V1) / (Ron (V1) + Ron (V2))} × Vin ( 2) can be expressed.
[0038]
According to this configuration, the on-resistance values Ron (V1) and Ron (V2) can both be variably set, so that a divided voltage controlled more finely than in the fourth embodiment can be obtained.
[0039]
Embodiment 6 FIG.
FIG. 12 is a circuit diagram showing a configuration of the analog signal processing circuit according to the sixth embodiment of the present invention. In the sixth embodiment, a configuration example of a mute circuit is shown as an analog signal processing circuit (part 3) using the soft changeover switch described in the first to third embodiments.
[0040]
In FIG. 12, the soft changeover switches 39 and 42 include analog switches 40 and 43 and switch control circuits 41 and 44 as described in the first to third embodiments.
[0041]
In the mute circuit shown in FIG. 12, an analog signal is input to one terminal of one of the soft changeover switches 39 and 42, and a signal reference voltage is input to one terminal of the other soft changeover switch 42. For example, a ground potential is input, and the other terminals are connected in common to output a muted analog signal.
[0042]
According to this configuration, a mute circuit that performs a smooth mute operation can be realized by switching between an analog signal input and a signal reference voltage (ground potential in the illustrated example) input.
[0043]
Embodiment 7 FIG.
FIG. 13 is a circuit diagram showing a configuration of an analog signal processing circuit according to Embodiment 7 of the present invention. In the seventh embodiment, a configuration example of a selector circuit is shown as an analog signal processing circuit (part 4) using the soft changeover switch described in the first to third embodiments.
[0044]
In FIG. 13, the soft changeover switches 45 and 48 are composed of analog switches 46 and 49 and switch control circuits 47 and 50 as described in the first to third embodiments.
[0045]
The mute circuit shown in FIG. 13 is configured such that an analog signal A is input to one terminal of one of the soft changeover switches 45 and 48 and an analog signal is input to one terminal of the other soft changeover switch 48. B is input and the other terminal is connected in common to output a selected analog signal.
[0046]
According to this configuration, since the switching of the signals is performed smoothly, a selector circuit that does not require an external mute can be obtained. Although FIG. 13 shows a configuration example using two soft changeover switches, a selector circuit using three or more soft changeover switches can be similarly configured, and the same effect can be obtained.
[0047]
Embodiment 8 FIG.
FIG. 14 is a circuit diagram showing a configuration of the analog signal processing circuit according to the eighth embodiment of the present invention. In the eighth embodiment, a configuration example of a volume setting circuit is shown as an analog signal processing circuit (part 5) using the soft changeover switch described in the first to third embodiments.
[0048]
In FIG. 14, software changeover switches 57 and 60 include analog switches 58 and 61 and switch control circuits 59 and 62 as described in the first to third embodiments.
[0049]
The volume setting circuit shown in FIG. 14 inputs the first volume setting value to one terminal A of one of the two soft changeover switches 57 and 60 and the other of the two soft changeover switches 60. The second volume set value is input to a terminal B, and the other terminals are connected in common to output the volume set value in sequence.
[0050]
In FIG. 14, the first volume set value and the second volume set value are generated as follows. That is, for a resistance ladder 52 in which a plurality of resistance elements are connected in series between a voltage input terminal 51 and the ground, a switch group 53 composed of a plurality of switches for deriving one resistance value from the resistance ladder 52 , 54 are provided. The volume control circuit 56 controls on / off of each switch of the switch groups 53 and 54, so that the switch groups 53 and 54 receive a voltage signal indicating a certain resistance value (volume set value) divided from the resistance ladder 52 by a terminal. Output to A and B.
[0051]
For example, if the first volume set value input to the terminal A is the set gain before switching and the second volume set value input to the terminal B is the set gain after switching, the signal level fluctuates at the time of setting, It also fluctuates when switching.
[0052]
However, according to the present embodiment, it is possible to switch from the set gain before switching to the set gain after switching without being affected by this. Then, the value can be adjusted in the decreasing direction by the soft changeover switch. If an amplifier is connected to the other terminal of the two soft change-over switches that are connected in common, the set gain can be adjusted in the increasing direction.
[0053]
【The invention's effect】
As described above, according to the present invention, the on-resistance between the on state and the off state of the analog switch is complemented so as to be connected and applied to the input analog signal, so that smooth switching can be realized. Therefore, it is possible to reduce the switching noise generated at the time of switching the analog signal without taking any special measures that cause an increase in cost. Further, even if there is a sudden change at the time of switching the analog signal, the change can be slowed down, and it is possible to reduce a sense of discomfort in hearing. As a result, by using the soft changeover switch according to the present invention, it is possible to realize an analog signal processing circuit in which no abrupt change should occur when switching an analog signal.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a soft changeover switch according to a first embodiment of the present invention;
FIG. 2 is a characteristic diagram showing a relationship between on-resistance and a control voltage of the analog switch shown in FIG.
3 is a time chart when the switch control circuit shown in FIG. 1 generates a control voltage by increasing or decreasing a control voltage linearly;
FIG. 4 is a circuit diagram showing a configuration of a soft changeover switch according to a second embodiment of the present invention;
5 is a time chart when the switch control circuit shown in FIG. 4 generates a control voltage by increasing or decreasing a control voltage in a stepwise manner.
FIG. 6 is a circuit diagram showing a configuration of a soft changeover switch according to a third embodiment of the present invention.
FIG. 7 is a time chart for explaining the operation of the delay element shown in FIG. 6;
FIG. 8 is a circuit diagram showing a configuration of an analog signal processing circuit according to a fourth embodiment of the present invention.
9 is a diagram illustrating the operation of the signal processing circuit shown in FIG.
FIG. 10 is a circuit diagram showing a configuration of an analog signal processing circuit according to a fifth embodiment of the present invention.
11 is a diagram illustrating an operation of the signal processing circuit illustrated in FIG.
FIG. 12 is a circuit diagram showing a configuration of an analog signal processing circuit according to a sixth embodiment of the present invention.
FIG. 13 is a circuit diagram showing a configuration of an analog signal processing circuit according to a seventh embodiment of the present invention.
FIG. 14 is a circuit diagram showing a configuration of an analog signal processing circuit according to an eighth embodiment of the present invention.
[Explanation of symbols]
1, 40, 43, 46, 49, 58, 61 analog switch, 1a NMOS transistor, 1b PMOS transistor, 2, 11, 21, 31, 34, 41, 44, 47, 50, 59, 62 switch control circuit, 12 , 13 Delay element, 39, 42, 45, 48, 57, 60 Soft changeover switch.

Claims (9)

An analog switch in which an NMOS transistor and a PMOS transistor are connected in parallel;
A switch control circuit that controls a gate voltage of the NMOS transistor and the PMOS transistor to complement an on-resistance of the analog switch in an intermediate state between an on state and an off state;
A soft changeover switch comprising: The switch control circuit,
An analog circuit that generates a control voltage that linearly increases or decreases the gate voltage,
The soft changeover switch according to claim 1, further comprising: The switch control circuit,
A digital-to-analog conversion circuit for increasing and decreasing the gate voltage stepwise,
The soft changeover switch according to claim 1, further comprising: A delay element is provided between an output terminal of the digital-to-analog conversion circuit and a gate electrode of each of the PMOS transistor and the NMOS transistor to transform a stair-like signal output by the digital-to-analog conversion circuit into a smooth signal. The soft changeover switch according to claim 3, wherein 2. An analog signal processing circuit, wherein a fixed resistance element is connected to one terminal of the soft changeover switch according to claim 1, and a divided point is output at a connection point with an attenuated signal level. 2. An analog signal processing circuit, wherein two soft changeover switches according to claim 1 are connected in series and a divided point is output at a connection point with an attenuated signal level. The two soft changeover switches according to claim 1,
An analog signal is input to one terminal of one soft changeover switch, a signal reference voltage is input to one terminal of the other soft changeover switch, and the other terminal is connected in common to output a muted analog signal. An analog signal processing circuit. 2. A plurality of soft changeover switches according to claim 1, wherein different analog signals are input to respective one terminals, and the other terminals are connected in common to output a selected analog signal. Analog signal processing circuit. 2. The two soft changeover switches according to claim 1, wherein a first volume set value is inputted to one terminal of one soft changeover switch and a second volume set value is inputted to one terminal of the other soft changeover switch. An analog signal processing circuit for connecting the other terminals in common and outputting the volume set values in sequence.

Images