JP2004186316A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the function of each of transistors in the cell array of a nonvolatile memory and in a high voltage circuit and the low voltage circuit of a peripheral circuit section, by reducing the number of manufacturing processes of a gate insulation film of the transistor in each region. <P>SOLUTION: The gate insulation films 21a and 21b are formed into two kinds of different thicknesses in the three regions, that is, in the cell array of the nonvolatile memory and in the high voltage circuit and the low voltage circuit of the peripheral circuit section. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a gate oxide film of a transistor in a cell array region and a peripheral circuit region of a nonvolatile memory having a floating gate and a method of forming the same. What is used.
[0002]
[Prior art]
Conventionally, in a nonvolatile memory having a floating gate, for example, a NOR type flash memory, the characteristics required for a cell transistor in a cell array and a transistor in a peripheral circuit portion are different, so that the thickness of each gate insulating film is different. I have. In the peripheral circuit portion, the thickness of the gate insulating film differs between the transistor of the high-voltage circuit to which a high voltage (such as a writing voltage) is applied and the transistor of the other low-voltage circuit.
[0003]
FIG. 37 is a cross-sectional view showing a state in which the thickness of a gate oxide film is different between a cell array region and a high-voltage circuit region and a low-voltage circuit region of a peripheral circuit portion in a conventional NOR flash memory.
[0004]
Here, 10 is a silicon substrate, 11 is an n-well, 12 is a p-well, 13 is an element isolation film, 21a, 21b and 21c are gate oxide films (silicon oxide films) having different thicknesses, 22, 23 and 24 are A first-layer polycrystalline silicon film having different thicknesses, 26 is a second-layer polycrystalline silicon film, 27 is an inter-gate insulating film (ONO film) of a cell transistor, and 28 is a third-layer polycrystalline silicon film.
[0005]
However, the conventional NOR flash memory having three types of gate oxide films 21a, 21b, and 21c having different thicknesses as described above has the following problems.
[0006]
The first problem is that since three types of gate oxide films 21a, 21b, 21c having different thicknesses are formed, complicated and many steps are required.
[0007]
The second problem is that since there are many thermal steps for forming the gate oxide film (three steps), the impurities doped in the well regions 11 and 12 and the channel region are diffused in the thermal step, and a desired impurity profile is obtained. This makes it difficult to control the channel and hinders miniaturization of the channel length of the transistor.
[0008]
The third problem is that since the gate oxide film 21c of the transistor of the high-voltage circuit in the peripheral circuit portion is thick (14 nm or more), the thermal oxidation time for forming the gate oxide film becomes long, and the well regions 11 and 12 and the channel The impurity doped in the region diffuses, a desired impurity profile is obtained, and it becomes difficult to control the channel, which hinders miniaturization of the channel length of the transistor.
[0009]
[Problems to be solved by the invention]
As described above, the conventional nonvolatile memory having a floating gate has various problems due to the different thicknesses of the gate oxide films in the cell array, the high-voltage circuit, and the low-voltage circuit.
[0010]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and reduces the number of steps of manufacturing a gate insulating film of a transistor in each region of a cell array of a nonvolatile memory and a high-voltage circuit and a low-voltage circuit of a peripheral circuit section. It is another object of the present invention to provide a semiconductor device capable of improving the function of a transistor in each region and a method for manufacturing the same.
[0011]
[Means for Solving the Problems]
According to a first semiconductor device of the present invention, in a semiconductor device having a cell array region of a nonvolatile memory, a high-voltage circuit region and a low-voltage circuit region in which peripheral circuit transistors are formed, a gate insulating film of a transistor in the cell array region And a first gate insulating film formed simultaneously as a gate insulating film of the transistor in the high-voltage circuit region, and a first gate insulating film formed as a gate insulating film of the transistor in the low-voltage circuit region. And a second gate insulating film having a small thickness.
[0012]
According to a second semiconductor device of the present invention, there is provided an electrically rewritable semiconductor device having a semiconductor substrate, an element isolation insulating film embedded in a groove formed in the semiconductor substrate, and a floating gate and a control gate stacked on the semiconductor substrate. Array region in which various nonvolatile memory cells are arranged and formed, and a high voltage system circuit region and a low voltage system peripheral transistor formed in the periphery of the cell array region of the semiconductor substrate and in which a high voltage system peripheral circuit transistor is formed And a transistor in the cell array region and a transistor in the high-voltage circuit region have a first gate oxide film of the same thickness, and a low-voltage circuit region in the low-voltage circuit region. The transistor has a second gate oxide film having a smaller thickness than the first gate oxide film.
[0013]
Note that the semiconductor device manufacturing method of the present invention has various embodiments.
[0014]
The first embodiment includes a step of forming a lowermost layer of a floating gate of a cell transistor and a lowermost layer of a gate electrode of a peripheral circuit transistor after forming an element isolation region before forming an element isolation region; In the lithography process for covering the cell array region and the high-voltage circuit region for removing the oxide film, a step of not directly applying a resist on the gate oxide film is employed.
[0015]
In the second embodiment, a state in which a post-isolation region forming process and separation of a floating gate for each memory cell are performed in a self-alignment manner by an isolation insulating film, and a control gate is opposed to an upper portion of a side surface of the floating gate The method is characterized by adopting a step of forming a substrate.
[0016]
In the third embodiment, the step of fabricating the element isolation region and the separation of the floating gate for each memory cell are performed in a self-aligned manner, and the control gate is formed so as not to face the upper part of the side surface of the floating gate. It is characterized by employing a process.
[0017]
In the fourth embodiment, an element isolation region pre-forming step for forming a floating gate of a cell transistor and a gate electrode of a peripheral circuit transistor after forming an element isolation region, and a method for removing a silicon oxide film in a low voltage circuit region. In the lithography step for covering the cell array region and the high-voltage circuit region, a step of not directly applying a resist on the gate oxide film is adopted.
[0018]
In a fifth embodiment, a resist is directly formed on a gate oxide film in another region during a post-forming step for an element isolation region and a lithography process for covering the other region in order to remove the silicon oxide film in the low-voltage circuit region. It is characterized by adopting a step of applying.
[0019]
In the sixth embodiment, a resist is directly formed on a gate oxide film in another region during a post-forming process for an element isolation region and a lithography process for covering another region in order to peel off a silicon oxide film in a low-voltage circuit region. Adopting a step of applying and a step of forming a state in which the control gate is opposed to the upper part of the side surface of the floating gate so that separation of the floating gate for each memory cell is performed in a self-aligned manner by the element isolation insulating film. It is characterized by.
[0020]
In a seventh embodiment, a resist is directly formed on a gate oxide film in another region during a post-forming process for an element isolation region and a lithography process for covering another region in order to peel off a silicon oxide film in a low-voltage circuit region. Adopting a step of applying and a step of forming a floating gate so that the control gate is not opposed to an upper portion of a side surface of the floating gate so that the memory cell is separated from the floating gate in a self-aligned manner by an element isolation insulating film. It is characterized by.
[0021]
The eighth embodiment is directed to a method of pre-forming an element isolation region and a method in which a resist is directly formed on a gate oxide film in another region in a lithography step of covering another region in order to peel off a silicon oxide film in a low-voltage circuit region. It is characterized by adopting a step of applying.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0023]
According to the present invention, for example, in a NOR type flash memory, the gate oxide film of a transistor of a high-voltage circuit in a peripheral circuit portion can be reduced to the same thickness as the gate oxide film of a cell transistor by lowering a data write voltage. Will be possible.
[0024]
This makes it possible to make the gate oxide film of the high-voltage circuit the same as the gate oxide film of the cell array, thereby reducing the number of steps and improving the function of the transistor in the high-voltage circuit.
[0025]
Hereinafter, the relationship between the step of forming the gate electrode and the element isolation region (in this example, STI; Shallow Trench Isolation structure) and the other regions (the cell array region and the high-voltage region) for removing the silicon oxide film in the low-voltage circuit region. In the lithography process that covers the voltage system circuit area), a combination of whether or not to apply a resist directly on the gate oxide film in another area and whether or not to separate the floating gate for each memory cell in a self-aligned manner is determined. A plurality of embodiments will be described.
[0026]
<First embodiment>
In the first embodiment, a step of forming a lowermost layer of a floating gate of a cell transistor and a lowermost layer of a gate electrode of a peripheral circuit transistor (formation method after STI) before forming an element isolation region; In the lithography step of covering the cell array region and the high-voltage circuit region in order to remove the oxide film, a step of not directly applying a resist on the gate oxide film is employed.
[0027]
FIG. 1 shows a cross section of a cell array region, a high-voltage circuit region and a low-voltage circuit region of a peripheral circuit portion in a manufacturing process of the NOR flash memory according to the first embodiment of the present invention.
[0028]
In FIG. 1, reference numeral 10 denotes a silicon substrate, 11 denotes an n-well, 12 denotes a p-well, 14 denotes a diffusion layer, 21a and 21b denote gate oxide films (silicon oxide films) having different thicknesses, and 22 and 24 denote respective thicknesses. , A second layer polycrystalline silicon film doped with P as an impurity, 27 an inter-gate insulating film (ONO film) of a cell transistor, and 28 a third layer polycrystalline silicon film. It is.
[0029]
2 to 12 show cross sections of the cell array region, the high-voltage circuit region and the low-voltage circuit region of the peripheral circuit portion in the manufacturing process of the NOR flash memory of FIG. .
[0030]
First, as shown in FIG. 2, before forming an element isolation region, an n-type impurity (for example, As) is added to a silicon substrate 10 in each circuit region (cell array region, high-voltage circuit region, and low-voltage circuit region). , P) to form an n-type well 11, and furthermore, a p-type impurity (eg, B, BF). ₂ ) To selectively form a p-type well 12 to form a cell array and a channel region of a peripheral circuit portion.
[0031]
Next, before forming the element isolation region, a first gate oxide film 21a of, for example, about 11 nm required for the cell array region and the high voltage circuit region is formed on the entire surface of the substrate.
[0032]
Next, as shown in FIG. 3, after a first polycrystalline silicon film 22 and a silicon oxide film 23 not doped with impurities are sequentially deposited on the entire surface, a cell array region and a high-voltage circuit region are formed by using lithography technology. And the silicon oxide film 23, the polycrystalline silicon film 22, and the gate insulating film 21a in the low-voltage circuit region are removed by etching. As a result, the first polycrystalline silicon film 22 remains as a first-layer polycrystalline silicon film in the cell array region and the high-voltage circuit region, becomes the lowermost layer of the floating gate in the cell array region, and becomes the lowermost layer in the high-voltage circuit region. The lowermost layer of the electrode.
[0033]
In the above lithography process, if a resist is directly applied on the gate oxide film 21a in the cell array region, the reliability of the gate oxide film 21a may be reduced. Therefore, as shown in FIG. Then, a polysilicon film 22 and a silicon oxide film 23 are deposited on the gate oxide film 21a.
[0034]
Next, as shown in FIG. 4, thermal oxidation is performed to form a gate oxide film 21b of, for example, about 7 nm in the low-voltage circuit region. Next, as shown in FIG. 5, a second polycrystalline silicon film 24 not doped with impurities is deposited on the entire surface.
[0035]
Next, as shown in FIG. 6, the second polycrystalline silicon film 24 laminated on the cell array region and the high-voltage circuit region and the underlying polycrystalline silicon film 24 are formed by using a lithography technique or a CMP (chemical mechanical polishing) technique. The silicon oxide film 23 is removed. As a result, the second polycrystalline silicon film 24 remains as the first-layer polycrystalline silicon film in the low-voltage circuit region and becomes the lowermost layer of the gate electrode in the low-voltage circuit region.
[0036]
According to the manufacturing process up to this point, three types of thermal oxidation processes for forming three types of gate oxide films, which were conventionally required, can be reduced to two thermal oxidation processes for forming two types of gate oxide films. Can be reduced. Further, diffusion of the well regions 11 and 12 and channel impurities can be suppressed, and the performance of the transistor in each circuit can be improved.
[0037]
Next, as shown in FIG. 7, after depositing a silicon nitride film 25 and a silicon oxide film (not shown), an element isolation groove is formed by using a lithography technique, and the element isolation insulating film 13 is buried. After that, the element isolation insulating film 13 is flattened by using the CMP technique.
[0038]
When forming the element isolation groove, if the cross section thereof has a reverse taper shape, it becomes difficult to completely bury the element isolation insulating film 13 later, so that the side surface of the element isolation groove is vertical (to be described later). It is preferable to form the device isolation insulating film 13 to be buried so that the side surface is vertical.
[0039]
Next, as shown in FIG. 8, the silicon nitride film 25 is peeled off, and a second polycrystalline silicon film 26a doped with an impurity (for example, P) is embedded.
[0040]
Next, as shown in FIG. 9, the third polycrystalline silicon film (third-layer polycrystalline silicon film) 26a in the cell array region is subjected to isolation etching on the element isolation region by using a lithography technique. In the cell array region, the stacked film of the first polycrystalline silicon film 22 and the second polycrystalline silicon film 26a becomes a floating gate. At this stage, in the direction perpendicular to the drawing, the floating gate is separated for each memory cell. Is not performed.
[0041]
Next, as shown in FIG. 10, an inter-gate insulating film (for example, ONO film) 27 for separating the floating gate of the memory cell and the control gate formed thereon is formed on the entire surface of the substrate.
[0042]
Next, as shown in FIG. 11, all (or part of) the inter-gate insulating film 27 in the peripheral circuit region is removed by etching using a lithography technique, and then a fourth polycrystalline silicon film (third layer polycrystalline silicon film) is formed. A crystalline silicon film 28 is deposited on the entire surface. The fourth polycrystalline silicon film 28 becomes a control gate in the cell array region and becomes the uppermost layer of the gate electrode in the peripheral circuit region. However, the etching removal of the inter-gate insulating film 27 in the peripheral circuit region can be omitted by directly forming a gate electrode contact on the second-layer polycrystalline silicon film 26a.
[0043]
Subsequently, as shown in FIG. 12 and FIG. 1 corresponding to a cross section in a direction orthogonal to the drawing, pattern processing of the gate electrode of each part is performed. At this time, in the cell array region, the third polycrystalline silicon film 28 is patterned as a continuous control gate as a word line, and the second polycrystalline silicon film 26a and the first polycrystalline silicon film are self-aligned. 22 is patterned to separate the floating gate of each memory cell as shown in FIG. In the peripheral circuit region, the third layer polycrystalline silicon film 28, the second layer polycrystalline silicon film 26a, and the first layer polycrystalline silicon film 22 or 24 are patterned to form respective gate electrodes.
[0044]
After that, a diffusion layer 14 having an optimum impurity concentration for the drain / source is selectively formed in the p-type well 12, and then a contact is formed in the control gate, the gate electrode and the diffusion layer 14.
[0045]
According to the NOR type flash memory of the first embodiment, the gate oxide film in the cell array region and the gate oxide film in the high-voltage circuit region are of the same type, so that three or more types conventionally required are obtained. The number of thermal oxidation steps for forming a gate oxide film can be reduced to at least two. Therefore, it is possible to reduce the number of manufacturing steps of the gate insulating film of the transistor in each area of the cell array of the nonvolatile memory and the high-voltage circuit and the low-voltage circuit of the peripheral circuit section.
[0046]
In addition, since a thermal process accompanying the formation of the gate oxide film can be reduced, diffusion of impurities in the well region and the channel region can be suppressed, and the performance of the transistor in each circuit region can be improved. That is, a high-performance peripheral circuit can be mounted.
[0047]
<Second Embodiment> (FIGS. 13 to 18)
In the second embodiment, a part of the process of the first embodiment is modified, the isolation of the floating gate for each memory cell is performed in a self-aligned manner by the element isolation insulating film, and the upper portion of the side surface of the floating gate is formed. An example in which control gates are formed to face each other is shown.
[0048]
First, steps similar to the steps of FIGS. 2 to 6 described in the first embodiment are performed, and first-layer polycrystalline silicon films 22 and 24 are formed as shown in FIG. At this time, the first-layer polycrystalline silicon films 22 and 24 shown in FIG. 13 are formed thicker than the first-layer polycrystalline silicon films 22 and 24 shown in FIG.
[0049]
Next, as shown in FIG. 14, the isolation of the first layer polycrystalline silicon film 22 in the cell array region for each memory cell is performed completely self-aligned by the element isolation insulating film 13. For this purpose, first, a silicon nitride film (not shown) and a silicon oxide film (not shown) are deposited in the same manner as in the step shown in FIG. 7 described in the first embodiment. Then, an element isolation groove is formed, and the element isolation insulating film 13 is buried. At this time, the element isolation groove is formed so that the side surface is vertical, and the side surface of the element isolation insulating film 13 is formed so as to be vertical. After that, the element isolation insulating film 13 is flattened by using the CMP technique. Thus, an element isolation region having a self-aligned structure (SA-STI structure) with respect to the floating gate is formed.
[0050]
Next, using a lithography technique, a region excluding the cell array region is covered with a resist (not shown), and impurity ions (for example, P) are implanted into the first polycrystalline silicon film 22 serving as a floating gate in the cell array region. Here, the first layer polycrystalline silicon film doped with P is represented by 22a.
[0051]
Next, as shown in FIG. 15, the entire surface of the element isolation insulating film 13 in the cell array region is etched to expose the upper portion of the side surface of the first-layer polycrystalline silicon film 22a.
[0052]
Next, as shown in FIG. 16, an inter-gate insulating film (ONO film) 27 is formed on the entire surface.
[0053]
Next, as shown in FIG. 17, the inter-gate insulating film 27 in the peripheral circuit region is removed by etching using a lithography technique.
[0054]
Next, as shown in FIG. 18, a polycrystalline silicon film 28 as a second layer gate electrode material film is deposited on the entire surface. This polycrystalline silicon film 28 becomes a control gate in the cell array region, and becomes a gate electrode together with the first polycrystalline silicon film 22 or 24 in the peripheral circuit region. Thereafter, the same steps as those in the first embodiment are performed. Obey.
[0055]
According to the above-described second embodiment, the floating gate composed of only the first-layer polycrystalline silicon film 22a is separated in a self-alignment manner in the cell array region, so that the cell size can be reduced. The floating gate made of the first-layer polycrystalline silicon film 22a does not extend to the element isolation insulating film 13, but is formed so that the control gate 28 also faces the upper part of the side surface. A large coupling capacitance between the gate 28 and the floating gate 22 can be ensured.
[0056]
<Third Embodiment> (FIGS. 19 to 20)
In the third embodiment, a part of the process of the first embodiment is modified so that the separation of the floating gate for each memory cell is performed in a self-aligned manner, and the control gate is provided above the side surface of the floating gate. An example is shown in which the electrodes are not opposed to each other.
[0057]
First, the same steps as those shown in FIGS. 2 to 8 described in the first embodiment are performed, and as shown in FIG. 19, a second-layer polycrystalline silicon film 26a containing P is formed.
[0058]
Next, as shown in FIG. 20, the second layer polycrystalline silicon film 26a is planarized by using the CMP method. Thereby, a floating gate is formed together with the first-layer polycrystalline silicon film 22 except for the second-layer polycrystalline silicon film 26a in a self-aligned manner only in the memory cell region sandwiched between the element isolation insulating films 13 in the cell array region. Can be.
[0059]
After that, the same steps as in the first embodiment are performed.
[0060]
<Fourth Embodiment> (FIGS. 21 to 28)
The fourth embodiment shows an example of an STI pre-fabrication method in which a floating gate of a cell transistor and a gate electrode of a peripheral circuit transistor are formed after an element isolation region is formed, as compared with the first embodiment.
[0061]
First, as shown in FIG. 21, after a silicon oxide film 21d is formed on the entire surface of the substrate, the silicon substrate 10 in each circuit region is doped with an n-type impurity (for example, As, P) before forming an element isolation region. An n-type well 11 is formed, and a p-type impurity (eg, B, BF ₂ ) To selectively form the p-type well 12 to form a cell array and a channel region of a peripheral circuit.
[0062]
Next, as shown in FIG. 22, an element isolation groove is formed by using a lithography technique, and the element isolation film 13 is embedded. After that, the element isolation insulating film 13 is flattened by using the CMP technique.
[0063]
Note that the element isolation groove and the element isolation insulating film 13 formed at this stage are shallower than the element isolation groove and the element isolation insulating film 13 formed in the process shown in FIG. Easy to manufacture.
[0064]
Next, as shown in FIG. 23, after removing the silicon oxide film 21d, a first gate oxide film 21a of, for example, about 11 nm required for the cell array region and the high-voltage circuit region is formed on the entire surface of the substrate.
[0065]
Next, as shown in FIG. 24, after a P-containing first-layer polycrystalline silicon film 22 and a silicon oxide film 23 are sequentially deposited on the entire surface of the substrate, the silicon oxide film in the low-voltage circuit region is formed by lithography. The film 23, the polycrystalline silicon film 22, and the gate insulating film 21a are removed by etching. Here, the P-containing polycrystalline silicon film 22 becomes a floating gate in the cell array region, and becomes the lowermost layer of the gate electrode in the high voltage circuit region.
[0066]
Next, as shown in FIG. 25, thermal oxidation is performed to form a gate oxide film 21b of a low-voltage circuit of about 7 nm.
[0067]
Next, as shown in FIG. 26, a second-layer polycrystalline silicon film 24 is deposited on the entire surface of the substrate. At this time, the polycrystalline silicon film 24 deposited on the low voltage system circuit becomes the lowermost layer of the gate electrode, but the polycrystalline silicon film 24 laminated on the cell array region and the oxide film 23 of the high voltage system circuit is unnecessary. is there.
[0068]
Then, as shown in FIG. 27, the polycrystalline silicon film 24 laminated on the cell array region and the high-voltage circuit region and the oxide film 23 thereunder are removed by using the lithography technique or the CMP technique.
[0069]
According to the manufacturing process up to this point, three types of thermal oxidation processes for forming three types of gate oxide films, which were conventionally required, can be reduced to two thermal oxidation processes for forming two types of gate oxide films. Can be reduced. Further, diffusion of the well regions 11 and 12 and channel impurities can be suppressed, and the performance of the transistor in each circuit can be improved.
[0070]
Next, as shown in FIG. 28, the first layer polycrystalline silicon film 22 is subjected to separation etching on the element separation region in the cell array region by using a lithography technique. In the cell array region, the first-layer polycrystalline silicon film 22 becomes a floating gate. At this stage, in the direction perpendicular to the drawing, the floating gate is not separated for each memory cell. After that, the same steps as in the first embodiment are performed.
[0071]
<Fifth Embodiment> (FIGS. 29 to 32)
The fifth embodiment employs a post-STI fabrication method as in the first to third embodiments, and uses another method in a lithography process for covering other regions in order to peel off a silicon oxide film in a low-voltage circuit region. An example in which a step of directly applying a resist on a gate oxide film in a region (different from the first to third embodiments) will be described.
[0072]
First, as shown in FIG. 29, after a silicon oxide film 21d is formed on the entire surface of the substrate, the silicon substrate 10 in each circuit region is doped with an n-type impurity (for example, As, P) before forming an element isolation region. An n-type well 11 is formed, and a p-type impurity (eg, B, BF ₂ ) To selectively form the p-type well 12 to form a cell array and a channel region of a peripheral circuit.
[0073]
Next, after the silicon oxide film 21d is peeled off, as shown in FIG. 30, a gate insulating film 21e of about 5 nm is formed on the entire surface of the substrate, and then the silicon oxide film in the low-voltage circuit region is removed by lithography. Etching is removed to leave the gate insulating film 21e in the cell array region and the high-voltage circuit region. At this time, since a resist (not shown) is directly applied so as to cover the silicon oxide film 21d in the cell array region and the high-voltage circuit region, a large amount of the resist is formed on the silicon oxide film 21d as in the first embodiment. The process is simpler than when a resist is applied through a crystalline silicon film.
[0074]
Next, after removing the resist, thermal oxidation is performed as shown in FIG. 31 to form a second gate oxide film 21b of about 7 nm in the low-voltage circuit region. At this time, the silicon oxide film 21e in the cell array region and the high-voltage circuit region is additionally oxidized to a first gate oxide film 21a of about 11 nm.
[0075]
Next, as shown in FIG. 32, a polycrystalline silicon film 22 is deposited on the entire surface, a silicon nitride film 25 and a silicon oxide film (not shown) are sequentially deposited. Is formed, and the element isolation insulating film 13 is embedded. After that, the element isolation insulating film 13 is flattened by using the CMP technique. After that, the same steps as in the first embodiment are performed.
[0076]
<Sixth embodiment>
The sixth embodiment is a combination of the steps shown in FIGS. 29 to 31 according to the fifth embodiment and the steps shown in FIGS. 13 to 18 according to the second embodiment.
[0077]
Therefore, the post-STI fabrication method and the step of directly applying a resist on the gate oxide film in the other region in the lithography process for covering the other region to remove the silicon oxide film in the low-voltage circuit region are adopted. As in the second embodiment, the floating gate is formed so that the memory cell is separated from each other in a self-aligned manner by the element isolation insulating film, and the control gate faces the upper part of the side surface of the floating gate. It becomes possible.
[0078]
<Seventh embodiment>
The seventh embodiment is a combination of the steps shown in FIGS. 29 to 31 according to the fifth embodiment and the steps shown in FIGS. 19 to 20 according to the third embodiment.
[0079]
Therefore, the post-STI fabrication method and the step of directly applying a resist on the gate oxide film in the other region in the lithography process for covering the other region to remove the silicon oxide film in the low-voltage circuit region are adopted. In addition, the floating gate can be separated for each memory cell in a self-aligned manner by the element isolation insulating film, and the control gate can be formed not to face the upper part of the side surface of the floating gate.
[0080]
<Eighth Embodiment> (FIGS. 33 to 36)
The eighth embodiment is a combination of the steps shown in FIGS. 21 to 22 in the fourth embodiment and the steps shown in FIGS. 30 to 32 in the fifth embodiment.
[0081]
That is, in the STI pre-fabrication method and the lithography process of covering the cell array region and the high-voltage circuit region in order to remove the silicon oxide film in the low-voltage circuit region, It employs a process of directly applying a resist.
[0082]
First, as shown in FIG. 33, the steps up to the STI forming step corresponding to FIG. 22 according to the fourth embodiment are performed. Subsequently, the silicon oxide film on the entire surface of the substrate is peeled off, and a gate insulating film 21e of about 5 nm is formed on the entire surface of the substrate.
[0083]
Next, as shown in FIG. 34, using a lithography technique, the silicon oxide film 21e in the low-voltage circuit region is removed by etching, leaving the gate insulating film 21e in the cell array region and the high-voltage circuit region. At this time, a resist (not shown) is directly applied so as to cover the silicon oxide film 21d in the cell array region and the high voltage circuit region.
[0084]
Next, after the resist is removed, as shown in FIG. 35, thermal oxidation is performed to form a second gate oxide film 21b of about 7 nm in the low-voltage circuit region. At this time, the silicon oxide film 21d in the cell array region and the high voltage circuit region is additionally oxidized to a first gate oxide film 21a of about 11 nm.
[0085]
Next, as shown in FIG. 36, a first-layer polycrystalline silicon film 22 containing P is deposited. The polycrystalline silicon film 22 is the lowermost layer of the gate electrode in the low-voltage circuit region, becomes a floating gate in the cell array region, and is the lowermost layer of the gate electrode in the high-voltage circuit region and the low-voltage circuit region. Become. Thereafter, the same steps as in the fourth embodiment are performed.
[0086]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, the number of steps of manufacturing the gate insulating film of the transistor in each region of the cell array of the nonvolatile memory and the high-voltage circuit and the low-voltage circuit of the peripheral circuit portion is reduced, The function of the transistor in the region can be improved. Further, since the number of heat steps accompanying the formation of the gate oxide film can be reduced, diffusion of impurities in the well and the channel region can be suppressed, and the performance of the transistor in each circuit region can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a cell array region, a high-voltage circuit region, and a low-voltage circuit region of a peripheral circuit portion in a manufacturing process of a NOR flash memory according to a first embodiment of the present invention.
2 is a cross-sectional view showing a cell array region, a high-voltage circuit region, and a low-voltage circuit region of a peripheral circuit portion viewed from a direction perpendicular to the plane of FIG. 1 for a part of the manufacturing process of the NOR flash memory of FIG. FIG.
FIG. 3 is a sectional view showing a step that follows the step of FIG. 2;
FIG. 4 is a sectional view showing a step that follows the step of FIG. 3;
FIG. 5 is a sectional view showing a step that follows the step of FIG. 4;
FIG. 6 is a sectional view showing a step that follows the step of FIG. 5;
FIG. 7 is a sectional view showing a step that follows the step of FIG. 6;
FIG. 8 is a sectional view showing a step that follows the step of FIG. 7;
FIG. 9 is a sectional view showing a step that follows the step of FIG. 8;
FIG. 10 is a sectional view showing a step that follows the step of FIG. 9;
FIG. 11 is a sectional view showing a step that follows the step of FIG. 10;
FIG. 12 is a sectional view showing a step that follows the step of FIG. 11;
FIG. 13 is a cross-sectional view showing a cell array region, a high-voltage circuit region and a low-voltage circuit region of a peripheral circuit portion in a part of the manufacturing process of the NOR flash memory according to the second embodiment of the present invention.
FIG. 14 is a sectional view showing a step that follows the step of FIG. 13;
FIG. 15 is a sectional view showing a step that follows the step of FIG. 14;
FIG. 16 is a sectional view showing a step that follows the step of FIG. 15;
FIG. 17 is a sectional view showing a step that follows the step of FIG. 16;
FIG. 18 is a sectional view showing a step that follows the step of FIG. 17;
FIG. 19 is a sectional view showing a cell array region, a high-voltage circuit region and a low-voltage circuit region of a peripheral circuit portion in a part of the manufacturing process of the NOR flash memory according to the third embodiment of the present invention.
FIG. 20 is a sectional view showing a step that follows the step of FIG. 19;
FIG. 21 is a cross-sectional view showing a cell array region, a high-voltage circuit region and a low-voltage circuit region of a peripheral circuit portion in a part of the manufacturing process of the NOR flash memory according to the fourth embodiment of the present invention.
FIG. 22 is a sectional view showing a step that follows the step of FIG. 21;
FIG. 23 is a sectional view showing a step that follows the step of FIG. 22;
FIG. 24 is a sectional view showing a step that follows the step of FIG. 23;
FIG. 25 is a sectional view showing a step that follows the step of FIG. 24;
FIG. 26 is a sectional view showing a step that follows the step of FIG. 25;
FIG. 27 is a sectional view showing a step that follows the step of FIG. 26;
FIG. 28 is a sectional view showing a step that follows the step of FIG. 27;
FIG. 29 is a sectional view showing a cell array region, a high-voltage circuit region, and a low-voltage circuit region of a peripheral circuit portion in a part of the manufacturing process of the NOR flash memory according to the fifth embodiment of the present invention;
FIG. 30 is a sectional view showing a step that follows the step of FIG. 29;
FIG. 31 is a sectional view showing a step that follows the step of FIG. 30;
FIG. 32 is a sectional view showing a step that follows the step of FIG. 31;
FIG. 33 is a sectional view showing a cell array region, a high-voltage circuit region, and a low-voltage circuit region of a peripheral circuit portion in a part of the manufacturing process of the NOR flash memory according to the sixth embodiment of the present invention;
FIG. 34 is a sectional view showing a step that follows the step of FIG. 33;
FIG. 35 is a sectional view showing a step that follows the step of FIG. 34;
FIG. 36 is a sectional view showing a step that follows the step of FIG. 35;
FIG. 37 is a cross-sectional view showing an example of a cell array region, a high-voltage circuit region, and a low-voltage circuit region of a peripheral circuit portion of a conventional NOR flash memory.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 11 ... N well, 12 ... P well, 13 ... Element isolation film, 14 ... Diffusion layer, 21a ... First gate oxide film, 21b ... Second gate oxide film, 22 ... First layer multiple Crystal silicon film (cell array region, high-voltage circuit region), 24 first-layer polycrystalline silicon film (low-voltage circuit region), 26a second-layer polycrystalline silicon film, 27 gate-to-gate insulating film (ONO film) ), 28: third layer polycrystalline silicon film.

Claims (18)

In a semiconductor device having a cell array region of a nonvolatile memory, a high voltage circuit region and a low voltage circuit region in which peripheral circuit transistors are formed,
A first gate insulating film formed simultaneously as a gate insulating film of the transistor in the cell array region and a gate insulating film of the transistor in the high-voltage circuit region;
A semiconductor device, comprising: a second gate insulating film formed as a gate insulating film of a transistor in the low-voltage circuit region and having a smaller thickness than the first gate insulating film. A semiconductor substrate;
An element isolation insulating film embedded in a groove formed in the semiconductor substrate,
A cell array region in which electrically rewritable nonvolatile memory cells in which a floating gate and a control gate are stacked on the semiconductor substrate are formed;
A high-voltage circuit region formed around the cell array region of the semiconductor substrate, where a high-voltage peripheral circuit transistor is formed, and a low-voltage circuit region where a low-voltage peripheral circuit transistor is formed, The transistor in the cell array region and the transistor in the high-voltage circuit region have a first gate oxide film having the same thickness, and the transistor in the low-voltage circuit region has a thickness greater than that of the first gate oxide film. A second gate oxide film having a small thickness. The device isolation insulating film is buried after forming the gate oxide film, at least the lowermost layer of the floating gate of the nonvolatile memory cell, and at least the lowermost layer of the gate electrode of the peripheral circuit transistor. Item 3. The semiconductor device according to item 2. 4. The semiconductor device according to claim 3, wherein at least the lowermost layer of the floating gate of the transistor in the cell array region is formed so as to be self-aligned with the element isolation insulating film. A floating gate of the transistor in the cell array region is formed of a first-layer gate electrode material film completely self-aligned with the element isolation insulating film;
5. The gate electrode of the peripheral circuit transistor is formed of a two-layer structure of the first-layer gate electrode material film and a second-layer gate electrode material film laminated thereon. Semiconductor device. The floating gate of the transistor in the cell array region has a two-layer structure of a first-layer gate electrode material film formed by being self-aligned with the element isolation insulating film and a second-layer gate electrode material film laminated thereon. Formed,
The gate electrode of the peripheral circuit transistor has a three-layer structure of the first-layer gate electrode material film, the second-layer gate electrode material film laminated thereon, and the third-layer gate electrode material film laminated thereon. The semiconductor device according to claim 4, wherein the semiconductor device is formed by: The element isolation insulating film is buried before forming at least the lowermost layer of the gate oxide film, the floating gate of the nonvolatile memory cell, and the gate electrode of the peripheral circuit transistor. 3. The semiconductor device according to claim 2, wherein: A floating gate of the transistor in the cell array region is formed by a first-layer gate electrode material film;
9. The gate electrode of the peripheral circuit transistor is formed by a two-layer structure of the first-layer gate electrode material film and a second-layer gate electrode material film laminated thereon. Semiconductor device. The control gate of the transistor in the cell array region is formed by being stacked so as to face the floating gate via an inter-gate insulating film deposited on the floating gate,
10. The gate electrode of the peripheral circuit transistor, wherein at least a part of the insulating film deposited simultaneously with the inter-gate insulating film remains between the stacked gate electrode materials. 13. The semiconductor device according to item 9. A semiconductor substrate, an element isolation insulating film embedded in a trench formed in the semiconductor substrate, and an electrically rewritable nonvolatile memory cell in which a floating gate and a control gate are stacked on the semiconductor substrate are arranged and formed. A high-voltage circuit region formed around the cell array region and having a high-voltage peripheral circuit transistor formed therein and a low-voltage circuit region having a low-voltage peripheral circuit transistor formed therein. When manufacturing a semiconductor device having a gate oxide film of the same thickness, the transistor in the cell array region and the transistor in the high-voltage circuit region
Forming a first gate oxide film on the entire surface of the semiconductor substrate;
Next, after depositing a first polycrystalline silicon film not doped with an impurity on the entire surface, the first polycrystalline silicon film and the first gate oxide film in the low-voltage circuit region are etched by using lithography technology. Removing the first polycrystalline silicon film and the first gate oxide film in the cell array region and the high-voltage circuit region;
Forming a second gate oxide film having a smaller thickness than the first gate oxide film in the low-voltage circuit region by performing thermal oxidation;
Next, after depositing a second polycrystalline silicon film which is not doped with impurities on the entire surface, the second polycrystalline silicon film in the cell array region and the high voltage circuit region is removed by using a lithography technique or a CMP technique. Leaving the second polycrystalline silicon film in the low-voltage circuit region.
Next, an element isolation groove is formed to a depth reaching the semiconductor substrate by using a lithography technique, and an element isolation insulating film is buried in the element isolation groove, and then the element isolation insulating film is planarized by using a CMP technique. Process and
Next, depositing a third polycrystalline silicon film doped with impurities on the entire surface;
Next, the first polycrystalline silicon film is etched in the cell array region by using a lithography technique so as to separate the third polycrystalline silicon film in the first direction on the element isolation region in the cell array region. Forming a floating gate made of a laminated film of a third polycrystalline silicon film and
Next, after depositing an inter-gate insulating film on the entire surface, a step of depositing a fourth polycrystalline silicon film to be the uppermost layer of the control gate in the cell array region and the gate electrode in the peripheral circuit region on the entire surface;
Next, a fourth polycrystalline silicon film, an inter-gate insulating film, a third polycrystalline silicon film and a first polycrystalline silicon film in the cell array region are patterned in a second direction orthogonal to the first direction. Processing to form a control gate / word line and a floating gate, and patterning the polycrystalline silicon film laminated in the high-voltage circuit region and the low-voltage circuit region to form a gate electrode or a gate wiring. ,
Next, after selectively forming a diffusion layer serving as a drain / source region on the semiconductor substrate, forming a contact on the control gate, the gate electrode and the diffusion layer. Production method. A semiconductor substrate, an element isolation insulating film embedded in a trench formed in the semiconductor substrate, and an electrically rewritable nonvolatile memory cell in which a floating gate and a control gate are stacked on the semiconductor substrate are arranged and formed. A high-voltage circuit region formed around the cell array region and having a high-voltage peripheral circuit transistor formed therein and a low-voltage circuit region having a low-voltage peripheral circuit transistor formed therein. When manufacturing a semiconductor device having a gate oxide film of the same thickness, the transistor in the cell array region and the transistor in the high-voltage circuit region
Forming a first gate oxide film on the entire surface of the semiconductor substrate;
Next, after depositing a first polycrystalline silicon film not doped with an impurity on the entire surface, the first polycrystalline silicon film and the first gate oxide film in the low-voltage circuit region are etched by using lithography technology. Removing the first polycrystalline silicon film and the first gate oxide film in the cell array region and the high-voltage circuit region;
Forming a second gate oxide film having a smaller thickness than the first gate insulating film in the low-voltage circuit region by performing thermal oxidation;
Next, after depositing a second polycrystalline silicon film which is not doped with impurities on the entire surface, the second polycrystalline silicon film in the cell array region and the high voltage circuit region is removed by using a lithography technique or a CMP technique. Leaving the second polycrystalline silicon film in the low-voltage circuit region.
Next, an element isolation groove is formed to a depth reaching the semiconductor substrate by using a lithography technique, and an element isolation insulating film is buried in the element isolation groove, and then the element isolation insulating film is planarized by using a CMP technique. Thereby, a step of completely aligning the first polycrystalline silicon film in the cell array region with the element isolation insulating film and separating each memory cell in the first direction;
Next, a step of implanting impurity ions into the first polycrystalline silicon film in the cell array region;
Next, a step of etching the entire surface of the element isolation insulating film in the cell array region to expose an upper portion of a side surface of the first polycrystalline silicon film;
Next, after forming an inter-gate insulating film on the entire surface, depositing a second polycrystalline silicon film on the entire surface;
Next, the second polycrystalline silicon film, the inter-gate insulating film, and the first polycrystalline silicon film in the cell array region are patterned in a second direction orthogonal to the first direction to form a control gate and word. Forming a line and a floating gate, patterning the laminated polycrystalline silicon film in the high-voltage circuit region and the low-voltage circuit region to form a gate electrode or a gate wiring;
Next, after selectively forming a diffusion layer serving as a drain / source region on the semiconductor substrate, forming a contact on the control gate, the gate electrode and the diffusion layer. Production method. A semiconductor substrate, an element isolation insulating film embedded in a trench formed in the semiconductor substrate, and an electrically rewritable nonvolatile memory cell in which a floating gate and a control gate are stacked on the semiconductor substrate are arranged and formed. A high-voltage circuit region formed around the cell array region and having a high-voltage peripheral circuit transistor formed therein and a low-voltage circuit region having a low-voltage peripheral circuit transistor formed therein. When manufacturing a semiconductor device having a gate oxide film of the same thickness, the transistor in the cell array region and the transistor in the high-voltage circuit region
Forming a first gate oxide film on the entire surface of the semiconductor substrate;
Next, after depositing a first polycrystalline silicon film not doped with an impurity on the entire surface, the first polycrystalline silicon film and the first gate oxide film in the low-voltage circuit region are etched by using lithography technology. Removing the first polycrystalline silicon film and the first gate oxide film in the cell array region and the high-voltage circuit region;
Forming a second gate oxide film having a smaller thickness than the first gate insulating film in the low-voltage circuit region by performing thermal oxidation;
Next, after depositing a second polycrystalline silicon film which is not doped with impurities on the entire surface, the second polycrystalline silicon film in the cell array region and the high voltage circuit region is removed by using a lithography technique or a CMP technique. Leaving the second polycrystalline silicon film in the low-voltage circuit region.
Next, after an insulating film serving as an etching mask is deposited on the entire surface, an element isolation groove is formed to a depth reaching the semiconductor substrate by using a lithography technique, and after the element isolation insulating film is embedded in the element isolation groove, Flattening the element isolation insulating film using a CMP technique;
Next, the insulating film serving as the etching mask is removed, a third polycrystalline silicon film doped with impurities is deposited, and then flattened using a CMP technique, so that an element isolation insulating film is formed in the cell array region. Forming a floating gate separated for each memory cell in a first direction together with the first-layer polycrystalline silicon film while leaving a third polycrystalline silicon film self-aligned only in the sandwiched memory cell region;
Next, after forming an inter-gate insulating film on the entire surface, a step of depositing a fourth polycrystalline silicon film to be the uppermost layer of the control gate in the cell array region and the gate electrode in the peripheral circuit region on the entire surface;
Next, a fourth polycrystalline silicon film, an inter-gate insulating film, a third polycrystalline silicon film and a first polycrystalline silicon film in the cell array region are patterned in a second direction orthogonal to the first direction. Processing to form a control gate / word line and floating gate, and patterning the laminated polycrystalline silicon film in the high-voltage circuit region and the low-voltage circuit region to form a gate electrode or gate wiring. ,
Next, after selectively forming a diffusion layer serving as a drain / source region on the semiconductor substrate, forming a contact on the control gate, the gate electrode and the diffusion layer. Production method. A semiconductor substrate, an element isolation insulating film embedded in a trench formed in the semiconductor substrate, and an electrically rewritable nonvolatile memory cell in which a floating gate and a control gate are stacked on the semiconductor substrate are arranged and formed. A high-voltage circuit region formed around the cell array region and having a high-voltage peripheral circuit transistor formed therein and a low-voltage circuit region having a low-voltage peripheral circuit transistor formed therein. When manufacturing a semiconductor device having a gate oxide film of the same thickness, the transistor in the cell array region and the transistor in the high-voltage circuit region
Forming a device isolation groove to a depth reaching the semiconductor substrate using lithography technology, embedding the device isolation film in the device isolation groove, and planarizing the device isolation insulating film using CMP technology;
Forming a first gate oxide film on the entire surface of the semiconductor substrate;
Next, after a first polycrystalline silicon film doped with impurities is deposited on the entire surface, the first polycrystalline silicon film and the first gate oxide film in the low-voltage circuit region are removed by etching using a lithography technique. Leaving the first polycrystalline silicon film and the first gate oxide film in the cell array region and the high-voltage circuit region.
Forming a second gate oxide film having a smaller thickness than the first gate oxide film in the low-voltage circuit region by performing thermal oxidation;
Next, after a second polycrystalline silicon film doped with impurities is deposited on the entire surface, the second polycrystalline silicon film stacked on the oxide film of the cell array region and the high-voltage circuit is formed by using the lithography technique or the CMP technique. Removing the polycrystalline silicon film to leave a second polycrystalline silicon film in the low-voltage circuit region;
Next, the first polycrystalline silicon film is etched in the cell array region using a lithography technique so as to separate the first polycrystalline silicon film in the first direction on the element isolation region. Forming a floating gate consisting of:
Next, after forming an inter-gate insulating film on the entire surface, a step of depositing a second polycrystalline silicon film, which is the uppermost layer of the control gate in the cell array region and the gate electrode in the peripheral circuit region, on the entire surface;
Next, the second polycrystalline silicon film, the inter-gate insulating film and the first polycrystalline silicon film in the cell array region are patterned in a second direction orthogonal to the first direction to form word lines and floating gates. Forming a gate electrode or gate wiring by patterning the laminated polycrystalline silicon film in the peripheral circuit region;
Next, after selectively forming a diffusion layer serving as a drain / source region on the semiconductor substrate, forming a contact on the control gate, the gate electrode and the diffusion layer. Production method. A semiconductor substrate, an element isolation insulating film embedded in a trench formed in the semiconductor substrate, and an electrically rewritable nonvolatile memory cell in which a floating gate and a control gate are stacked on the semiconductor substrate are arranged and formed. A high-voltage circuit region formed around the cell array region and having a high-voltage peripheral circuit transistor formed therein and a low-voltage circuit region having a low-voltage peripheral circuit transistor formed therein. When manufacturing a semiconductor device having a gate oxide film of the same thickness, the transistor in the cell array region and the transistor in the high-voltage circuit region
After a silicon oxide film is formed on the entire surface of the semiconductor substrate, a silicon oxide film in the low-voltage circuit region is formed by using a lithography technique in which a resist is directly applied so as to cover the silicon oxide film in the cell array region and the high-voltage circuit region. Etching away, leaving a silicon oxide film in the cell array region and the high voltage circuit region,
Next, after the resist is removed, thermal oxidation is performed to form a second gate oxide film in the low-voltage circuit region and additionally oxidize the silicon oxide film in the cell array region and the high-voltage circuit region. Forming a first gate oxide film comprising:
Next, a step of depositing a first polycrystalline silicon film not doped with an impurity on the entire surface;
Next, an element isolation groove is formed to a depth reaching the semiconductor substrate by using a lithography technique, and an element isolation insulating film is buried in the element isolation groove, and then the element isolation insulating film is planarized by using a CMP technique. Process and
Next, a step of depositing a second polycrystalline silicon film doped with impurities on the entire surface, and then, using a lithography technique, forming a second polycrystalline silicon film in the cell array region on the element isolation region in the first position. Forming a floating gate composed of a laminated film of a first polycrystalline silicon film and a second polycrystalline silicon film in the cell array region by performing etching so as to separate in the direction of
Next, after forming an inter-gate insulating film on the entire surface, a step of depositing a third polycrystalline silicon film to be the uppermost layer of the control gate in the cell array region and the gate electrode in the peripheral circuit region on the entire surface;
Next, the third polycrystalline silicon film, the inter-gate insulating film, the second polycrystalline silicon film, and the first polycrystalline silicon film in the cell array region are patterned in a second direction orthogonal to the first direction. Processing to form a word line and a floating gate, pattern processing of the laminated polycrystalline silicon film in the peripheral circuit region to form a gate electrode or a gate wiring,
Next, after selectively forming a diffusion layer serving as a drain / source region on the semiconductor substrate, forming a contact on the control gate, the gate electrode and the diffusion layer. Production method. A semiconductor substrate, an element isolation insulating film embedded in a trench formed in the semiconductor substrate, and an electrically rewritable nonvolatile memory cell in which a floating gate and a control gate are stacked on the semiconductor substrate are arranged and formed. A high-voltage circuit region formed around the cell array region and having a high-voltage peripheral circuit transistor formed therein and a low-voltage circuit region having a low-voltage peripheral circuit transistor formed therein. When manufacturing a semiconductor device having a gate oxide film of the same thickness, the transistor in the cell array region and the transistor in the high-voltage circuit region
After a silicon oxide film is formed on the entire surface of the semiconductor substrate, a silicon oxide film in the low-voltage circuit region is formed by using a lithography technique in which a resist is directly applied so as to cover the silicon oxide film in the cell array region and the high-voltage circuit region. Etching away, leaving a silicon oxide film in the cell array region and the high voltage circuit region,
Next, after the resist is removed, thermal oxidation is performed to form a second gate oxide film in the low-voltage circuit region and additionally oxidize the silicon oxide film in the cell array region and the high-voltage circuit region. Forming a first gate oxide film comprising:
Next, a step of depositing a first polycrystalline silicon film not doped with an impurity on the entire surface;
Next, an element isolation groove is formed to a depth reaching the semiconductor substrate by using a lithography technique, and an element isolation insulating film is buried in the element isolation groove, and then the element isolation insulating film is planarized by using a CMP technique. A step of separating the first polycrystalline silicon film in the cell array region for each memory cell in a first direction in a state of being completely self-aligned by the element isolation insulating film;
Next, using lithography technology, implanting impurity ions into the first polycrystalline silicon film in the cell array region;
Next, a step of etching the entire surface of the element isolation insulating film in the cell array region to expose an upper portion of a side surface of the first polycrystalline silicon film;
Next, after forming an inter-gate insulating film on the entire surface, depositing a second polycrystalline silicon film on the entire surface;
Next, the second polycrystalline silicon film, the inter-gate insulating film and the first polycrystalline silicon film in the cell array region are patterned in a second direction orthogonal to the first direction to form word lines and floating gates. Forming a gate electrode or gate wiring by patterning the laminated polycrystalline silicon film in the peripheral circuit region;
Next, after selectively forming a diffusion layer serving as a drain / source region on the semiconductor substrate, forming a contact on the control gate, the gate electrode and the diffusion layer. Production method. A semiconductor substrate, an element isolation insulating film embedded in a trench formed in the semiconductor substrate, and an electrically rewritable nonvolatile memory cell in which a floating gate and a control gate are stacked on the semiconductor substrate are arranged and formed. A high-voltage circuit region formed around the cell array region and having a high-voltage peripheral circuit transistor formed therein and a low-voltage circuit region having a low-voltage peripheral circuit transistor formed therein. When manufacturing a semiconductor device having a gate oxide film of the same thickness, the transistor in the cell array region and the transistor in the high-voltage circuit region
After a silicon oxide film is formed on the entire surface of the semiconductor substrate, a silicon oxide film in the low-voltage circuit region is formed by using a lithography technique in which a resist is directly applied so as to cover the silicon oxide film in the cell array region and the high-voltage circuit region. Etching away, leaving a silicon oxide film in the cell array region and the high voltage circuit region,
Next, after the resist is removed, thermal oxidation is performed to form a second gate oxide film in the low-voltage circuit region and additionally oxidize the silicon oxide film in the cell array region and the high-voltage circuit region. Forming a first gate oxide film comprising:
Next, a step of depositing a first polycrystalline silicon film not doped with an impurity on the entire surface;
Next, an element isolation groove is formed to a depth reaching the semiconductor substrate by using a lithography technique, and an element isolation insulating film is buried in the element isolation groove, and then the element isolation insulating film is planarized by using a CMP technique. Process and
Next, after depositing a second polycrystalline silicon film doped with an impurity, it is planarized by using a CMP technique, so that self-alignment is performed only in a memory cell region sandwiched between element isolation insulating films in a cell array region. Forming a floating gate separated for each memory cell in a first direction together with the first polycrystalline silicon film while leaving the second polycrystalline silicon film in a state where
Next, after forming an inter-gate insulating film on the entire surface, a step of depositing a third polycrystalline silicon film to be the uppermost layer of the control gate in the cell array region and the gate electrode in the peripheral circuit region on the entire surface;
Next, the third polycrystalline silicon film, the inter-gate insulating film, the second polycrystalline silicon film, and the first polycrystalline silicon film in the cell array region are patterned in a second direction orthogonal to the first direction. The word line and the floating gate are formed by processing, and the third polycrystalline silicon film, the second polycrystalline silicon film, and the first polycrystalline silicon film in the peripheral circuit region are patterned to form a gate electrode or a gate wiring. Forming,
Next, after selectively forming a diffusion layer serving as a drain / source region on the semiconductor substrate, forming a contact on the control gate, the gate electrode and the diffusion layer. Production method. A semiconductor substrate, an element isolation insulating film embedded in a trench formed in the semiconductor substrate, and an electrically rewritable nonvolatile memory cell in which a floating gate and a control gate are stacked on the semiconductor substrate are arranged and formed. A high-voltage circuit region formed around the cell array region and having a high-voltage peripheral circuit transistor formed therein and a low-voltage circuit region having a low-voltage peripheral circuit transistor formed therein. When manufacturing a semiconductor device having a gate oxide film of the same thickness, the transistor in the cell array region and the transistor in the high-voltage circuit region
Forming a device isolation groove to a depth reaching the semiconductor substrate using lithography technology, embedding the device isolation film in the device isolation groove, and planarizing the device isolation insulating film using CMP technology;
Next, after forming a silicon oxide film on the entire surface of the semiconductor substrate, the silicon in the low-voltage circuit region is formed by using a lithography technique in which a resist is directly applied so as to cover the silicon oxide film in the cell array region and the high-voltage circuit region. Removing the oxide film by etching to leave a silicon oxide film in the cell array region and the high-voltage circuit region;
Next, after the resist is removed, thermal oxidation is performed to form a second gate oxide film in the low-voltage circuit region and additionally oxidize the silicon oxide film in the cell array region and the high-voltage circuit region. Forming a first gate oxide film comprising:
Next, a step of depositing a first polycrystalline silicon film doped with impurities over the entire surface;
Next, the first polycrystalline silicon film in the cell array region is etched using a lithography technique to separate the first polycrystalline silicon film in the cell isolation region in the first direction on the element isolation region. Forming a floating gate consisting of:
Next, after forming an inter-gate insulating film on the entire surface, a step of depositing a second polycrystalline silicon film, which is the uppermost layer of the control gate in the cell array region and the gate electrode in the peripheral circuit region, on the entire surface;
Next, the second polycrystalline silicon film, the inter-gate insulating film and the first polycrystalline silicon film in the cell array region are patterned in a second direction orthogonal to the first direction to form word lines and floating gates. Forming a gate electrode or a gate wiring by patterning the second polysilicon film and the first polysilicon film in the peripheral circuit region;
Next, after selectively forming a diffusion layer serving as a drain / source region on the semiconductor substrate, forming a contact on the control gate, the gate electrode and the diffusion layer. Production method. Further comprising a step of etching and removing all or a part of the inter-gate insulating film in the peripheral circuit region using a lithography technique between the time when the inter-gate insulating film is deposited on the entire surface and the time when the polycrystalline silicon film is deposited. The method for manufacturing a semiconductor device according to claim 11, wherein the method is performed.

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