JP2004159071A - Clock generation circuit and semiconductor integrated circuit - Google Patents

Abstract

A clock generation circuit such as a PLL or a VCO has disadvantages such as a large circuit scale, high cost, high power consumption, and loss of synchronization.
A detection unit detects a pulse of a reference clock signal, an oscillator that starts oscillating based on a detection result of the detection unit, and an oscillation signal GENCK of the oscillator to be input and count the number of pulses. A counter 62 for instructing the oscillator 63 to stop the oscillation when the number of pulses reaches a predetermined number.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock generation circuit that generates a clock signal having a required frequency, and a semiconductor integrated circuit having the clock generation circuit.
[0002]
[Prior art]
For example, in a large-scale semiconductor integrated circuit (LSI) having a plurality of functional blocks including a CPU (central processing unit), the highest frequency required for operation has been increasingly higher in recent years.
For this reason, in many LSIs, a PLL (Phase-Locked Loop) circuit is used as a signal source for generating a high-frequency clock signal based on a reference clock signal supplied from the outside.
In a test using a higher-speed clock, it is difficult to directly input a high-speed clock from an external tester. Therefore, the test is often performed using the PLL circuit or a VCO (voltage-controlled oscillator).
[0003]
[Problems to be solved by the invention]
However, many semiconductor integrated circuits using a PLL circuit or a VCO have the following problems.
Normal PLL circuits and VCOs are composed of analog circuits, are more difficult to design than digital circuits, and require more time for design and operation verification.
Further, the occupied area of the PLL circuit is large. Although the area of digital circuits is steadily reduced due to the evolution of semiconductor manufacturing processes, the area of analog circuits is not easily reduced.
In the case of only a VCO, the area is relatively smaller than that of a PLL circuit. However, since the VCO alone cannot synchronize with an external reference clock, a means for synchronizing with some external data in a normal operation or a test is required. become.
In addition, when distributing clocks of different frequencies to a plurality of functional blocks, it is disadvantageous in terms of area to prepare a VCO or PLL circuit for each block, so that in many cases, the least common multiple of the clock frequency required for each block is used. A method is used in which a reference clock signal having a frequency is generated by one PLL, and the frequency is divided and distributed.
When the frequency of the least common multiple reference clock is very high, there are disadvantages such as difficulty in generating the reference clock signal or an increase in power consumption. If the frequency of the reference clock (the least common multiple) is determined while avoiding such disadvantages, the types of clock frequencies that can be selected are narrowed.
Further, in the conventional PLL circuit, it takes time until the oscillation frequency is stabilized, and the frequency cannot be switched in a short time. Therefore, if a PLL circuit is used in performing an operation test at a high frequency, the test takes a long time.
[0004]
A first object of the present invention is to provide a clock generation circuit capable of generating a high-speed clock signal with a small-scale circuit without using a large-scale circuit such as a PLL circuit or a VCO.
A second object of the present invention is to provide a semiconductor integrated circuit capable of generating a clock signal having a frequency suitable for a plurality of functional blocks and reducing power consumption accompanying high-speed clock signal distribution.
[0005]
[Means for Solving the Problems]
A clock generation circuit according to a first aspect of the present invention achieves the first object, and includes a detection unit that detects a pulse of a reference clock signal, and an oscillator that oscillates based on a detection result of the detection unit. It has an oscillator to start, and a counter that counts the number of pulses by inputting an oscillation signal of the oscillator, and instructs the oscillator to stop oscillation when the number of pulses reaches a predetermined number.
Preferably, the oscillator is connected between a gate circuit and an output and an input of the gate circuit, and switches the output of the gate circuit on and off according to a delay amount, and a pulse length according to the delay amount. And a delay circuit for generating the clock signal at the output of the gate circuit.
[0006]
A semiconductor integrated circuit according to a second aspect of the present invention achieves the second object, and is connected to and connected to a plurality of functional blocks and clock input terminals of the plurality of functional blocks, respectively. And a plurality of clock generation circuits for generating a clock signal having a frequency suitable for the function block based on a reference signal supplied from the outside.
Preferably, each of the plurality of clock generation circuits detects a pulse of a reference clock signal, an oscillator that starts oscillating based on a detection result of the detection unit, and a pulse that receives an oscillation signal of the oscillator and receives a pulse. A counter for counting the number of pulses and instructing the oscillator to stop oscillation when the number of pulses reaches a predetermined number.
[0007]
A clock generation circuit according to a first aspect includes a detection unit, an oscillator, and a counter.
The detection unit detects a pulse of the input reference clock signal and outputs the result. The oscillator starts to oscillate based on the detection result of the detection unit. The counter counts the number of pulses of the oscillation signal by monitoring the output of the oscillator. When the number of pulses reaches a predetermined number, the counter instructs the oscillator to stop oscillation. As a result, the oscillator stops oscillating. Next, each time the reference clock is detected, the above-described operation, that is, the start of the oscillation, the counting of the oscillation signal, and the stop of the oscillation are repeated. This oscillator preferably comprises a gate circuit and a delay circuit. In this case, a clock signal of a pulse corresponding to the delay amount of the delay circuit is output from the gate circuit. The generation and stop of the clock signal are controlled by the counter, and the counter operates in synchronization with the reference clock signal. Therefore, the clock signal output from the gate circuit is synchronized with the reference clock signal.
[0008]
A clock generation circuit according to a second aspect has a plurality of functional blocks and a clock generation circuit connected to each clock input terminal.
Since the clock generation circuit preferably includes a gate circuit and a delay circuit connected between the output and the input of the gate circuit, the output of the gate circuit is turned on and off according to the delay amount of the delay circuit. Is switched, whereby a clock signal having a pulse length corresponding to the delay amount is generated at the output of the gate circuit. This clock signal is generated based on a common reference signal. When each of the plurality of clock generation circuits generates and outputs a clock signal having a frequency suitable for the connected functional block, the output clock signal is immediately supplied from the clock input terminal into the functional block.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.
[0010]
[First Embodiment]
FIG. 1 is a block diagram illustrating a configuration of the clock generation circuit according to the first embodiment.
The clock generation circuit 56 illustrated in FIG. 1 has an edge detector 61 that receives a reference clock signal CLKR and detects a voltage change of the reference clock signal CLKR, a counter 62, and an oscillator 63 with an enable terminal.
The output of the edge detector 61 is connected to the clear inverting input terminal C_X of the counter 62. The reset signal RST_X is input to the reset inverting input terminal R_X of the counter 62.
The output terminal CO_X of the counter 62 is connected to the enable terminal EN of the oscillator 63, and the clock signal GENCK generated from the output of the oscillator 63 is output. The clock signal GENCK is input to the clock input CK of the counter 62, and the counter 62 counts the number of pulses.
[0011]
FIG. 2 is a circuit diagram illustrating a configuration example of the edge detector.
The edge detector 61 has a NAND gate circuit 71 to which one input receives the reference clock signal CLKR. An inverter 72 and a delay circuit 73 are connected in series between the reference clock input terminal and the other terminal of the NAND gate circuit 71.
[0012]
In the initial state where the reference clock signal CLKR is “L (low)”, the output of the delay circuit 73 (the other input of the NAND gate circuit 71) is “H”. Output signal (edge detection signal) CNTSTA becomes “L”. When a time corresponding to the delay amount by the inverter 72 and the delay circuit 73 elapses from the rise of the pulse of the reference clock, the other input of the NAND gate circuit 71 changes to “L”. The signal CNTSTA is returned to "H". As described above, the edge detector 61 detects the rise of the pulse of the reference clock signal CLKR and outputs a negative pulse of a predetermined length.
[0013]
FIG. 3 is a circuit diagram showing a configuration example of the counter.
The counter 62 includes, for example, four flip-flops 81, 82, 83 and 84 connected in series, and an inverter 85 connected between the Q terminal of the flip-flop 84 at the last stage and the output terminal CO_X of the counter. Have.
An “H” level voltage VE is applied to the D terminal of the first-stage flip-flop 81. An inverted signal of the reset signal RST_X can be applied to the set terminals S of the four flip-flops, and an inverted signal of the edge detection signal CNTSTA of the counter can be applied to the reset terminals R of the four flip-flops.
[0014]
In this counter 62, when the reset signal RST_X becomes “L”, all flip-flops are set to “H (1)” by the inverted signal. When the edge detection signal CNTSTA becomes "L", all flip-flops are reset to "L (0)" by the inverted signal (clear signal), and thereafter, every time the pulse of the clock signal GENCK rises to the clock input CK. Then, the “H” level potential applied to the D terminal of the first-stage flip-flop 81 is transferred to the D terminal of the flip-flop 82, the D terminal of the flip-flop 83, the D terminal of the flip-flop 84, and the input of the inverter 85. .
The output of the inverter, that is, the output signal OSC_EN of the counter 62 changes from "L" to "H" at the time of the above-described clearing. Thereafter, when the “H” potential is transferred to the inverter 85 at the rise of the fourth pulse of the clock signal GENCK, the output signal OSC_EN switches from “H” to “L”.
As described above, the counter 62 counts four pulses for each clear operation.
[0015]
FIG. 4 is a circuit diagram showing a configuration example of an oscillator with an enable terminal EN.
In the oscillator 63, a NAND gate circuit 81, a delay circuit 82, and an inverter 83 are connected in series between an enable terminal EN and an output terminal of a clock signal GENCK. One terminal of the NAND gate circuit 81 is connected to the enable terminal EN, and the other terminal is connected to the output of the delay circuit 82.
The oscillator 63 oscillates with a pulse width determined by the delay amount D of the delay circuit 82 while the signal OSC_EN input to the enable terminal EN is “H”, and outputs the clock signal GENCK.
[0016]
Note that, as shown in FIG. 5, a configuration in which the clock signal GENCK is extracted through the inverter 83 from the connection point between the NAND gate circuit 81 and the delay circuit 82 may be employed.
When the enable signal OCN_EN changes to “H (high)” level, the output voltage of the NAND gate circuit 81 changes in accordance with the change in the voltage of one input of the NAND gate circuit 81, and this change in the output voltage is delayed by the delay circuit 82. The signal is fed back to the other input of the NAND gate circuit 81 with a delay of the amount D. Therefore, the output of the NAND gate circuit 81 oscillates with a pulse width determined by the delay amount D. An inverted signal of the oscillation signal is output from the output of the inverter 83 as a clock signal GENCK.
[0017]
FIGS. 6A to 6E are timing charts of each signal of the clock generation circuit shown in FIG.
As shown in FIG. 6B, when the reference clock signal CLKR having a relatively low frequency is input to the edge detector 61 shown in FIG. 1, the reset signal RST_X shown in FIG. When the signal changes from "H" to "L", "H" is set in the four flip-flops of FIG. 3 as described above. The edge detection signal CNTSTA, which is the output signal of the NAND gate circuit 71 in FIG. 2, is generated for a short period determined by the delay amount of the inverter 72 and the delay circuit 73 by the rising edge of the pulse of the first reference clock signal CLKR. It changes from “H” to “L”.
When the edge detection signal changes from "H" to "L", the four flip-flops shown in FIG. 3 are reset as described above, and their held data simultaneously changes to "L". At the same time, the output signal OSC_EN of the counter changes from “L” to “H”, and the oscillator 63 shown in FIG. 4 or 5 starts oscillating.
As described above, the enable signal OSC_EN output from the counter 62 shown in FIG. 3 changes from “H” to “L” at the rising edge of the fourth pulse of the clock signal GENCK from the oscillator 63. Therefore, the oscillator 63 stops oscillating until the enable signal OSC_EN becomes “H” next.
[0018]
As shown in FIGS. 6A to 6E, the above series of operations is repeated every time the pulse of the reference clock signal CLKR rises. As a result, in this example, a clock signal GENCK having a frequency four times the frequency of the reference clock signal CLKR is generated.
In the above clock generation circuit 56, the number of flip-flop stages of the counter 62 is set in advance according to the frequency of the clock signal GENCK to be generated. When the frequency of the clock signal GENCK to be generated is high, the delay amount of the oscillator 63 is reduced in advance at the time of design to cope with the problem.
[0019]
FIGS. 7A to 7E are timing charts of respective signals when the delay amount of the oscillator 63 is smaller than expected. FIGS. 8A to 8E show the delay amount of the oscillator 63. The timing chart of each signal when it becomes larger than expected is shown.
There is no problem when the oscillation pulse length becomes short, but when the oscillation pulse length becomes long, as shown in FIG. 8 (E), if the pulse length becomes longer, a clock signal of a predetermined frequency may not be obtained. There is. In this case, it is convenient if the delay amount of the oscillator 63 can be changed.
[0020]
[Second embodiment]
The second embodiment relates to changing the amount of delay of an oscillator used for clock generation.
FIG. 9 shows a configuration example of an oscillator that can change the delay amount.
In the oscillator 63-1 shown in FIG. 9, for example, three delay circuits 82-1, 82-2, and 82-3 are connected in series, and a selector 84 that receives the potential of the output node of each of the delay circuits as an input is provided. . The selector 84 changes the amount of delay given to the other terminal of the NAND gate circuit 81 by changing the combination of inputs according to the control signal S6. As a result, the delay amount can be changed.
[0021]
Note that, as shown in FIG. 10, a configuration may be employed in which the clock signal GENCK is extracted through the inverter 83 from the connection point between the NAND gate circuit 81 and the delay circuit 82-3.
In the oscillator 63-1 shown in FIG. 10, the delay circuit 82-1 has a delay amount D1, the delay circuit 82-2 has a delay amount D2, and the delay circuit 82-3 has a delay amount D3. . The total delay amount is determined by a combination of these three delay amounts D1, D2, and D3.
A selector 84 as means for determining a combination of delay amounts is connected between three outputs of each delay circuit and the other input of the NAND gate circuit 81. The selector 84 is controlled by a control signal S6 input from outside.
[0022]
The delay amount D of the delay circuit 82 of the oscillator 63 is based on a value obtained by adding a slight margin with reference to the critical path of the circuit. In the oscillator 63-1 shown in FIG. 9, the entire delay amount can be changed according to the circuit margin. However, the oscillation frequency itself does not change.
[0023]
[Third Embodiment]
In a clock generation circuit, there is a case where it is desired to intentionally change the output frequency of an oscillator for measuring the maximum operable frequency of the circuit, increasing the speed of a test, or for other reasons. The third embodiment relates to changing the oscillation frequency of a clock generation circuit.
[0024]
FIG. 11 shows a configuration example of a clock generation circuit capable of changing the pulse count.
The clock generation circuit 56-1 shown in FIG. 11 includes a counter 62-1 for outputting the number of count pulses in four bits Y0 to Y3 and a comparator 64 for 4-bit data. A 4-bit output of the counter 62-1 is input to the comparator 64 as one input A0 to A3, and bit strings B0 to B3 of a 4-bit selection signal are input to the other input of the comparator 64. A clock signal GENCK to be generated is set by the selection signals B0 to B3. The comparator 64 compares the counter values A0 to A3 of the input counter pulses with the bit strings B0 to B3 of the selection signal. More specifically, a logical operation is performed on the exclusive OR of two inputs. As a result, the output of the comparator 64, that is, the enable signal OSC_EN is “1 (H)” when the counter values A0 to A3 of the counter pulses match the bit strings B0 to B3 of the selection signal, and is “0” when they do not match. (L) ". The start and stop of the oscillation of the oscillator 63 are controlled by the enable signal OSC_EN.
[0025]
FIG. 12 shows an example of the configuration of an oscillator for changing the clock frequency by changing the pulse count.
The oscillator 62-1 shown in FIG. 12 includes a four-input selector 86 that receives the outputs of the four flip-flops 81 to 84 as inputs. The selector 86 selects and outputs any one of the four input signals of the selector 86 according to the input count number control signal S7. For this reason, the enable signal OSC_EN output from the inverter 85 changes from “H” to “L” every count of an arbitrary pulse within the range of 1 to 4 pulses. Oscillation of the oscillator 63 in the next stage is stopped at every arbitrary number of pulses selected within the range of 1 to 4, so that the oscillation frequency can be changed.
[0026]
[Fourth Embodiment]
FIG. 13 is a block diagram illustrating a configuration of a clock generation circuit according to the fourth embodiment.
In the clock generation circuit 56-2 illustrated in FIG. 13, the set signal ST_X can be input between the output of the edge detector 61 and the clear inverted input terminal C_X of the counter 62. The set signals ST_X and RST_X are both low active but inverted signals, and the counter is set or reset according to the state. In the configuration example of the counter 62 shown in FIG. 3, when the reset signal RST_X changes from “H” to “L”, the flip-flops 81 to 84 are set, and the counter itself is reset, that is, the output of the counter 62 changes from “H”. It becomes “L”. Conversely, when the set signal ST_X input to the terminal C_X changes from “H” to “L”, the flip-flops 81 to 84 are reset, and the counter itself is set, that is, the output of the counter 62 changes from “L” to “H”. ".
[0027]
With the above configuration and control, the oscillator 63 can be maintained in the continuous oscillation state or the continuous stop state even when the reference clock signal CLKR is input. Thereby, there is an advantage that the oscillation frequency of the oscillator 63 itself can be determined from the output clock signal.
Note that the reset signal RST_X and the set signal ST_X in FIG. 13 correspond to an example of the “count output control signal” in the present invention.
[0028]
[Fifth Embodiment]
FIG. 14 is a block diagram illustrating a configuration of a clock generation circuit according to the fifth embodiment.
The clock generation circuit 56-3 illustrated in FIG. 14 includes a selector 64 that selects the clock signal GENCK output from the oscillator 63 and the reference clock signal CLKR. The selector 64 switches between the clock signal GENCK and the reference clock signal CLKR according to the clock bypass control signal S8, and outputs the same to the outside.
[0029]
With the above configuration and control, both the generated clock signal GENCK and the reference clock signal CLKR can be switched and output, so that the oscillation frequency can be automatically detected.
[0030]
The following advantages can be obtained from the clock generation circuits according to the first to fifth embodiments.
As a first advantage, since the clock generation circuit can be configured by a reference clock signal detection unit, an oscillator, and a simple counter, the area occupied by the circuit is significantly smaller than that of a PLL circuit or the like.
As a second advantage, in particular, in the clock generation circuit according to the second embodiment, the oscillation frequency (or pulse width) of the oscillator differs from the target value because the oscillation frequency can be changed by changing the delay amount of the oscillator. Even in such a case, the oscillation frequency can be changed electrically after forming the LSI.
As a third advantage, in particular, in the clock generation circuit according to the third embodiment, since the count value of the counter can be controlled, the frequency of the clock signal output from the clock generation circuit can be changed. For example, when the pulse length, that is, the amount of delay of the delay circuit slightly changes due to the surrounding temperature environment or the like, it is necessary to generate a required number of pulses in a certain period after detecting the edge of the reference clock signal. In such a case, if both the pulse count value and the pulse width can be adjusted, the degree of freedom in adjusting the frequency is greatly increased. Therefore, the combination of the second embodiment and the third embodiment is particularly preferable.
As a fourth advantage, in particular, in the clock generation circuit of the fourth embodiment, since the continuous oscillation and the continuous stop of the oscillator can be controlled, the frequency of the clock signal from the clock generation circuit is changed to the oscillation frequency until the oscillation frequency becomes the same. Can be as high as. Further, a test for examining the oscillation frequency is easy.
As a fifth advantage, in particular, in the clock generation circuit according to the fifth embodiment, since the clock signal generated by the clock generation circuit and the reference clock signal can be selectively output, the automatic detection of the oscillation frequency is not performed. It becomes possible.
[0031]
Next, a semiconductor integrated circuit using the above clock generation circuit will be described in the following sixth to eighth embodiments.
[0032]
[Sixth Embodiment]
FIG. 15 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit (LSI) according to the sixth embodiment.
The LSI 55 illustrated in FIG. 15 has a plurality of functional blocks, here, block A, block B, and block C. In this LSI 55, a circuit for generating a high-frequency clock signal such as a PLL circuit is omitted, and instead, a clock having a frequency suitable for the corresponding block is provided immediately near each of the clock input terminals of the plurality of blocks A to C. Clock generation circuits 56A, 56B and 56C for generating clock signals are provided.
[0033]
In the sixth embodiment, a clock generation circuit is provided for each of a plurality of functional blocks. As the clock generation circuit, the clock generation circuits described in the above first to fifth embodiments can be used. Alternatively, a clock generation circuit obtained by arbitrarily combining the first to fifth embodiments can be used.
[0034]
In any case, a simple and small-scale circuit combining a detection circuit for the reference clock, an oscillator, and a counter can be used. Such a small-scale clock generation circuit can be easily arranged in the space between the functional block and other components, and hardly increases the area of the LSI.
In addition, a low-frequency reference clock signal is supplied to the vicinity of a functional block by wiring, and a clock signal of a higher frequency than the reference clock signal is generated near a required functional block, so that there is no delay due to clock wiring. High frequency clock signals also reduce power consumption.
Furthermore, the need for a PLL circuit in which analog and digital circuits coexist is not required, which reduces process costs, and eliminates the need to divide the power supply between analog and digital circuits, reducing the occupied area and significantly reducing costs. It becomes.
[0035]
[Seventh Embodiment]
FIG. 16 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to the seventh embodiment. This figure shows a state in which a tester is connected during the operation test of the CPU.
A semiconductor integrated circuit (hereinafter, LSI) 1 illustrated in FIG. 16 includes a first block 2-1, a second block 2-2, and a CPU (central processing unit) 3 as a plurality of functional blocks. These functional blocks 2-1, 2-2, and 3 are connected to the internal bus 4. A RAM 5 as a storage circuit and an input / output (I / O) interface 6 are further connected to the internal bus 4.
The input / output interface 6 is connected to data and program input / output terminals of the external tester 100. The CPU 3 and the tester 100 are connected such that a reset signal SR supplied to a reset terminal of the CPU 3 is supplied from an external tester 100.
Information including a test program and data (test pattern) is stored in the RAM 5.
[0036]
A clock supply unit 10 that supplies an operation clock signal to each functional block is connected.
The clock supply unit 10 includes a PLL circuit 11, a test clock generation circuit 12, two selectors 13 and 14, and two frequency dividers 15 and 16.
The PLL circuit 11 generates a high-frequency operation clock CLK1 during normal operation of the CPU 3 based on a reference clock signal that is not input during the test of this example but is input during normal operation. Therefore, the input of the PLL circuit 11 is connected to the first external clock input terminal 1a. The output of the PLL circuit 11 is connected to one input of the selector 13.
[0037]
The illustrated LSI 1 has another external clock input terminal 1b as another means for inputting an external clock signal CLK2 input from the outside. The external clock input terminal 1b is connected to the other input of the selector 13. The external clock signal CLK2 is a low-frequency first test clock signal supplied from the tester 100 at the time of test data and program loading, which will be described later. In addition, when the external clock input means is used during the normal operation, in order to confirm the operation of the PLL circuit 11, a clock signal having the same high frequency as the operation clock CLK1 to be output from the PLL circuit 11 is used as the external clock signal CLK2. You can also enter.
The selector 13 selects and outputs either the clock signal CLK1 or CLK2 input to the two inputs according to the control signal S1 input from the external tester 100.
[0038]
The output of the selector 13 is connected to one input of the selector 14. The other input of the selector 14 is connected to the output of the test clock generation circuit 12.
The output of the selector 14 is connected to the clock input of the CPU 3. A 1 / n frequency divider 15 is connected between the output of the selector 14 and the functional block 2-1. A 1 / m frequency divider 16 is connected between the output of the selector and the functional block 2-2. The CPU 3 operates by the operation clock signal CLK1 having the highest frequency generated by the PLL 11, for example, a frequency of 100 to 200 MHz. The function block 2-1 operates with an operation clock signal in which the frequency of the operation clock signal CLK1 has been reduced to 1 / n, and the function block 2-2 has an operation clock signal in which the frequency of the operation clock signal CLK1 has been reduced to 1 / m. Works with As described above, the clock signal supply unit 10 generates a clock signal suitable for each of a plurality of functional blocks including the CPU 3, or supplies the clock signal from the outside.
[0039]
The test clock generation circuit 12 constitutes an embodiment of the clock generation circuit of the present invention. The test clock generation circuit 12 inputs a reference clock signal (or control signal) S2 synchronized with the external clock signal CLK2 from the external tester 100, and based on the reference clock signal S2, for example, is equivalent to the operation clock signal of the CPU 3 described above. A high test clock signal CLK1T of 100 to 200 MHz is generated. The test clock signal CLK1T is input to the other input of the selector 14.
[0040]
As the test clock generation circuit 12, the clock generation circuits of the above-described first to fifth embodiments or a clock generation circuit obtained by combining these can be used.
[0041]
Hereinafter, an operation test (operating frequency guarantee test) of the LSI 1 illustrated in FIG. 16 using the tester 100 at the same high frequency as that of the operation of the LSI 1 will be described.
First, in order to directly input the low frequency test clock signal CLK2 from the tester 100 to the CPU 3, the control signals S1 and S2 input from the tester 100 are both disabled. Thus, the selector 13 selects the input side of the first test clock CLK2, and the first test clock CLK2 is sent to the selector 14. Further, the selector 14 selects the normal clock side, that is, the output side of the tester 13. As a result, the first test clock signal CLK2 is input to the CPU 3. The CPU 3 is configured to select between a low-speed operation mode and a high-speed normal operation mode according to the frequency of the input clock. In this case, it operates in the low-speed operation mode. More specifically, a program and data (test pattern) for the operating frequency assurance test are temporarily stored (loaded) from the tester 100 to the RAM 5 via the input / output interface 6 and the internal bus 4 in synchronization with the test clock signal CLK2. ).
[0042]
Next, the tester 100 changes the control signal S2 to the enable state in synchronization with the test clock signal CLK2. As a result, the test clock generation circuit 12 operates, and the test clock generation circuit 12 generates and outputs the test clock signal CLK1T. At this time, since the selector 14 is switched by the change of the control signal S2 to the enable state, the generated test clock signal CLK1T is input to the CPU 3 via the selector 14. When the test clock signal CLK1T having a high frequency is input, the CPU 3 switches from the low-speed operation mode to the high-speed operation mode.
[0043]
After that, the reset signal SR is input from the tester 100 to the CPU 3. As a result, the CPU 3 calls the operating frequency guarantee test program and the test pattern from the RAM 5 and executes the program.
The operating frequency assurance test checks the function of the CPU 3 itself, or checks the function of the CPU 3 controlling other functional blocks. Therefore, the test is performed under the environment of the test clock signal CKL1T having the same high frequency as the normal operating clock signal CLK1. Executed in
The result of the test is temporarily written in the RAM 5 or a storage circuit in the input / output interface 6.
[0044]
When the operation frequency guarantee test is completed, the tester 100 returns the control signal S2 to the disabled state. As a result, the input signal of the selector 14 switches, and the first test clock signal CLK2 is input to the CPU 3 again.
In the low-speed operation mode based on the first test clock signal CLK2, the CPU 3 reads a test result from the RAM 5 or the input / output interface 6 via the internal bus 4. The CPU 3 determines whether the operation frequency assurance test is successful or not based on the read test result.
[0045]
In the seventh embodiment, a dedicated test clock generation circuit 12 generates a test clock signal CLK1T having the same high frequency as in a normal operation. The test clock generation circuit 12 has a smaller and simpler configuration than a PLL circuit or a VCO, and has an advantage that it can output a clock signal CLK1T having a predetermined frequency immediately after an oscillation command is issued. Therefore, even when the operation mode is switched from the low-speed operation mode to the high-speed operation mode, the test clock signal CLK1T required for the high-speed operation mode is quickly input, and almost no waiting time occurs.
Loading of programs and data and reading of test results at the time of a test are executed by the clock signal CLK2 from the tester 100. The frequency of the test clock signal CLK2 is, for example, one digit lower than that of the high-speed test clock signal. In addition, there is no need to use a large-scale, high-precision and expensive tester having a large internal clock generation unit.
Further, the built-in PLL circuit 11 used during normal operation is not used. Instead of the high-speed clock signal CLK1 generated by the PLL circuit 11, a test clock signal CLK1T is generated as a signal synchronized with the test clock signal CLK2 and the reference clock signal S2. As described above, since the test clocks are synchronized with each other, there is no fear of a synchronization shift during the test, and the test proceeds smoothly and accurately.
[0046]
Note that the test clock generation circuit 12 oscillates only when necessary under the control of the reference clock signal and / or the selection signal S2 and stops it when unnecessary, from the viewpoint of suppressing power consumption. Even if the oscillation is stopped frequently, the test clock generation circuit 12 rises, that is, the time until the predetermined frequency is stabilized is short, so that no time loss occurs.
Further, in the seventh embodiment, the PLL circuit 11 itself is omitted, and the oscillator 12 can be used during normal operation.
[0047]
[Eighth Embodiment]
FIG. 17 is a block diagram showing a configuration of a semiconductor integrated circuit according to the eighth embodiment. This figure shows a state in which a tester is connected during the operation test of the CPU.
The clock signal supply unit 30 of the semiconductor integrated circuit illustrated in FIG. 17 includes a test clock output unit (T.CK output unit) 31 that inputs the test clock signal CLK1T generated by the test clock oscillator (T.OSC) 12. Have. The test clock output unit 31 has a buffer or a frequency dividing circuit inside, and holds or divides the generated test clock signal CLK1T in this buffer. The tester 100 extracts a signal for confirming the frequency of the test clock signal CLK1T (or the test clock signal CLK1T itself) when necessary, and directly or indirectly measures the frequency of the test clock signal CLK1T. When the frequency of the test clock signal CLK1T is significantly different from the operation clock signal CLK1, an instruction to correct the frequency is issued. In this case, the test clock generation circuit 12 has a configuration in which the oscillation frequency is variable as described above, and the tester 100 controls the control signal S3 to change the oscillation frequency of the test clock signal CLK1T.
The other configuration of the clock signal supply unit 30 of this example is the same as that of the clock signal supply unit 10 shown in FIG.
[0048]
In the semiconductor integrated circuit shown in FIG. 17, a ROM 7 is connected to an internal bus 4. A test program is stored in the ROM 7 in advance, so that it is not necessary to load the program into the RAM 5 every time the operation frequency assurance test is performed as in the seventh embodiment, and the test time can be reduced. Further, the function of the tester 100 to load the program can be omitted. Note that the ROM 7 is not an essential component, and a program may be downloaded to the RAM 5 as in the seventh embodiment.
[0049]
An on-chip debugging architecture and its serial port are incorporated in the semiconductor integrated circuit shown in FIG. This architecture will be described below with reference to a CPU debug test, but can also execute a so-called boundary scan test. A boundary scan test is a self-scan that can execute a scan test on an I / O boundary (boundary) of each functional block from within the IC as if a tester is connected, and eliminates the need for a tester. Say test.
[0050]
A typical example of an architecture and a serial port for executing such a self test is a so-called JTAG (Joint Test Action Group) specification.
As a configuration corresponding to JTAG, a DUT (Debug Support Unit) 40 is incorporated in the CPU 3 in advance. An interface (TI / F) 45 for the JTAG test is connected between the reset input of the CPU 3 and the reset terminal 1c of the LSI. The test interface 45 is connected to the test clock generation circuit 12 and the selector 14 to supply a control signal S2 for permitting oscillation and switching of the selector and a control signal S4 for changing the frequency.
On the other hand, a JTAG debugger 101 is provided in the tester 100 in advance as a serial port for JTAD debugging. The tester 100 controls the DUT 40 and the test interface 45 via the JTAG debugger 101, thereby performing initialization (reset), control (reading of programs and test patterns, etc.) of the LSI necessary for the operation frequency guarantee test, and results. Is executed in the background of the CPU operation. Therefore, in the case of FIG. 17, it is not necessary to input the first test clock signal CLK1T having a low frequency, and it is not necessary to synchronize the test clocks.
[0051]
FIG. 18 is a block diagram showing an internal configuration of the DSU 40 and a partial configuration of the CPU.
The DSU 40 includes a control port 41 called a TAP (Test Access Port), a data holding register (D.REG, hereinafter referred to as a DSU data register) 42, a control unit (CON) 43, and an instruction code holding A register (C.REG, hereinafter referred to as a DSU instruction register) 44 is provided. The TAP 41 is connected to the external JTAG debugger 101. The TAP 41 is connected to a DSU data register 42, a control unit 43, and a DSU instruction register 44.
[0052]
The CPU 3 is connected to a general-purpose register (REG) 51, an instruction register (C.REG) 52, a selector 53 for switching between the input of the instruction register 52 and the input of the DSU instruction register 44, and the output of the selector 53. An instruction decoder (C. DEC) 54 is provided.
[0053]
In the operation frequency guarantee test (JTAG debug test) using the JTAG architecture, first, the JTAG debugger 101 sets the JTAG debug control input / output line L _{DI / F} To the test interface 45 to output a clock signal CLK1T of a high frequency (100 to 200 MHz) at which an operation frequency assurance test is to be performed (transmission command of the control signal S2). Then, the test clock generation circuit 12 receiving the control signal S2 starts oscillating at the designated frequency. The clock signal CLK1T is input to the CPU 3 via the selector 14 by the operation of the selector 14 receiving the control signal S2.
Subsequently, the JTAG debugger 101 inputs the reset signal SR to the CPU 3 via the test interface 45. As a result, the CPU 3 is reset and enters the high-speed operation mode.
[0054]
Next, a program for an operating frequency guarantee test is downloaded from the JTAG debugger 101. This download is unnecessary when the program is already stored in the ROM 7. When the ROM 7 is not provided, the JTAG debugger 101 sends the JTAG debug control input / output line L _{DI / F} , DSU 40, the CPU, and the internal bus 4, the program is downloaded to the RAM 5.
[0055]
Hereinafter, a procedure for downloading this program from the JTAG debugger to the RAM will be described in detail with reference to FIG.
First, from the JTAG debugger 101 to the JTAG debug control input / output line L _{DI / F} Is written to the DSU data register 42 via the TAP 41. Since the DSU data register usually has a small capacity, a program for operating frequency guarantee test cannot be written at a time. Therefore, a part of this program is written to the DSU data register 42.
[0056]
Next, from the JTAG debugger 101 to the JTAG debug control input / output line L _{DI / F} Is written to the DSU instruction register 44 via the TAP 41. The data transfer instruction is an instruction for transferring data from the DSU register 42 to the general-purpose register 51 in the CPU. At this stage, data transfer has not yet started.
After that, the JTAG debugger 101 instructs the control unit 43 to execute via the TAP 41. Accordingly, the control signal S5 is input from the control unit 43 to the selector 53, and the input of the selector 53 is switched to the DSU side. As a result, the data transfer instruction in the DSU instruction register is sent to the instruction decoder 54 of the CPU via the selector 53, where the data transfer instruction is executed. As a result, the operating frequency guarantee test program written in the DSU data register 42 is transferred to the general-purpose register 51 of the CPU.
[0057]
Similarly, the JTAG debugger 101 writes a store instruction to the DSU instruction register 44 via the TAP 41 and instructs the control unit 43 to execute. As a result, the selector 53 is switched by the control signal S5, and the store instruction in the DSU instruction register is sent to the instruction decoder 54, where the store instruction is executed. As a result, the operating frequency assurance test program transferred and held in the general-purpose register 51 is written from the CPU 3 via the internal bus 4 to a predetermined address in the RAM 5 and stored.
[0058]
The above procedure, ie, writing program data into the DSU register, transferring program data to the general-purpose register by holding and executing a data transfer instruction, transferring and storing program data into the RAM by holding and executing a store instruction Is repeated a required number of times, and the entire operating frequency assurance test program is downloaded to the RAM 5.
Through a similar procedure, data (test pattern) describing test conditions and the like is downloaded from the JTAG debugger 101 into the RAM 5.
[0059]
When the download of the program and the test data is completed, the JTAG debugger instructs the CPU 3 via the DSU 40 to execute the program. This execution instruction is transmitted to the CPU 3 through the same route as the above-described program transfer and store instructions. When decoding the execution instruction, the CPU 3 reads out the program and necessary test data from the RAM 5 and executes the program. This test result is written to a predetermined address in the RAM 5 by the CPU 3.
[0060]
After the execution of the program, the test result is read from the RAM 5 to the JTAG debugger 101. At this time, the program data is read out from the RAM 5 to the JTAG debugger 101 via a procedure and a path reverse to the above-described download of the program data.
The JTAD debugger 101 determines whether the test is successful or not by comparing the test result with an expected value. At this time, a signal is output from the test clock output unit 31, the frequency of the clock signal CLK <b> 1 </ b> T at the time of the test is confirmed based on the signal, and it is determined whether or not the test result is performed at an appropriate clock frequency.
[0061]
In the eighth embodiment, an operating frequency assurance test is executed in the background of the CPU using an on-chip debugging architecture such as JTAG and its serial port. The JTAG operation is performed by supplying a frequency lower than the operating frequency of the CPU 3 by one digit, for example, from the JTAG debugger 101 and is executed in synchronization therewith. However, the JTAG operation itself does not need to be synchronized with the CPU operation. Further, it is not necessary to input the low-frequency clock signal CLK2 from the tester 100, and the selector 13 for switching the clock signal CLK2 becomes unnecessary. When the PLL circuit 11 is omitted, the selector 14 becomes unnecessary.
The tester 100 does not need to exchange data via the input / output interface 6 of the LSI, and does not need to input the control signal S1. Therefore, the necessary functions of the tester 100 in the eighth embodiment are collected in the JTAG debugger 101, and the tester 100 itself is basically unnecessary if the JTAG debugger 101 is provided. As a result, a high-frequency operation test of the CPU built in the LSI can be performed without using an expensive high-speed tester.
[0062]
Further, as in the seventh embodiment, a large-scale clock generation circuit such as a PLL circuit is not required, and a waiting time for stabilizing a clock signal is almost unnecessary, and a test can be performed in a short time.
[0063]
By the way, in the case of the conventional operating frequency assurance test, since a clock supply system circuit such as an interface between the CPU and the outside and a PLL circuit is different for each LSI, even if the same CPU is used for the LSI, test data for the high-speed operation test is The expected value must be prepared for each LSI.
However, when the on-chip debugging of the JTAG specification is performed as in the present embodiment, the DSU 40 built in the CPU 3 and its interface are made common, so that if the CPU 3 is the same, the test data for the high-speed operation test is performed. And one set of expected value may be prepared for each function to be checked.
[0064]
【The invention's effect】
The clock generation circuit according to the present invention has a simple configuration that can be small and occupy a small area with a smaller number of gate circuits than a PLL circuit or a VCO. Therefore, if this clock generation circuit is mounted on an LSI, power consumption can be reduced, cost can be reduced, and the clock signal can be internally generated with a short waiting time until the clock signal is stabilized. Further, unlike the VCO, a signal synchronized with the reference clock signal can be generated. Further, since an analog circuit is not required, the design can be performed in the same manner as a general digital logic circuit, and there is no need to separate power supplies between the analog circuit and the digital circuit.
[0065]
According to the semiconductor integrated circuit of the present invention, since a clock generation circuit is provided for each of a plurality of functional blocks, a large-scale PLL circuit or the like is not required, and the occupied area, cost, and power consumption are reduced. Is eliminated. In addition, since oscillation is performed with a common reference clock signal, it is convenient when operations are to be synchronized among a plurality of functional blocks. Since the reference clock signal has a lower frequency, wiring delay and power consumption in the wiring are small.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a configuration example of a clock generation circuit according to a first embodiment.
FIG. 2 is a circuit diagram illustrating a configuration example of an edge detector.
FIG. 3 is a circuit diagram illustrating a configuration example of a counter.
FIG. 4 is a circuit diagram illustrating a configuration example of an oscillator having an enable terminal.
FIG. 5 is a circuit diagram illustrating a configuration example of an oscillator.
FIGS. 6A to 6E are timing charts of respective signals of the clock generation circuit.
FIGS. 7A to 7E are timing charts of signals when the delay amount of the clock generation circuit is smaller than expected.
FIGS. 8A to 8E are timing charts of signals when the delay amount of the oscillator is larger than expected.
FIG. 9 is a circuit diagram of an oscillator capable of changing a delay amount in the second embodiment.
FIG. 10 is a circuit diagram of an oscillator having another configuration that can change a delay amount.
FIG. 11 is a block diagram of a clock generation circuit capable of changing a pulse count in the third embodiment.
FIG. 12 is a circuit diagram of a counter capable of changing a pulse count in the third embodiment.
FIG. 13 is a block diagram illustrating a configuration of a clock generation circuit according to a fourth embodiment.
FIG. 14 is a block diagram illustrating a configuration of a clock generation circuit according to a fifth embodiment.
FIG. 15 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to a sixth embodiment;
FIG. 16 is a block diagram showing a configuration of a semiconductor integrated circuit according to a seventh embodiment.
FIG. 17 is a block diagram showing a configuration of a semiconductor integrated circuit according to an eighth embodiment.
FIG. 18 is a block diagram showing an internal configuration of a DSU and a partial configuration of a CPU.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2-1 etc .... Functional block, 3 ... CPU as one of functional blocks, 4 ... Internal bus, 5 ... RAM, 6 ... Input / output interface, 7 ... ROM, 10 ... Clock signal supply part , 11 PLL circuit, 12 test clock oscillator, 13, 14 selector, 15, 16 frequency divider, 30 clock signal supply unit, 31 test clock output unit as output means, 40 DSU, 41 .. TAP, 42... DSU data register, 43... DSU control unit, 44... DSU instruction register, 45... JTAG test interface as an input / output circuit dedicated to inspection, 51. 54: instruction decoder, 55: semiconductor integrated circuit, 56, 56-1 to 56-3, 56A to 56C: clock generation circuit, 61 Edge detector, 62,62-1 ... counter, 63,63-1 ... oscillator 81 ... gate circuit, 82,82-1～82-3 ... delay circuit, 100 ... tester, 101 ... JTAG debugger.

Claims (9)

A detection unit that detects a pulse of the reference clock signal;
An oscillator that starts oscillating based on the detection result of the detection unit,
A counter for inputting an oscillation signal of the oscillator, counting the number of pulses, and instructing the oscillator to stop oscillation when the number of pulses reaches a predetermined number;
A clock generation circuit having: The oscillator is
A gate circuit,
The output of the gate circuit is connected between the output and the input of the gate circuit, and the output of the gate circuit is turned on and off according to the delay amount, and a clock signal having a pulse length corresponding to the delay amount is generated at the output of the gate circuit. A delay circuit for
The clock generation circuit according to claim 1, further comprising: 3. The clock generation circuit according to claim 2, wherein the oscillator further includes a circuit for selecting a delay amount of the delay circuit fed back to an input of the gate circuit. 2. The clock generation circuit according to claim 1, wherein said counter includes means for setting and changing a count number according to an input count number control signal. 2. The clock generation circuit according to claim 1, wherein the counter has a control input for fixing the output of the counter to 0 or 1 according to the input count output control signal. 2. The clock generation circuit according to claim 1, wherein the oscillator includes means for selecting and outputting either the output of the oscillator or a reference clock input from outside according to the input clock bypass control signal. Multiple functional blocks,
A plurality of clock generation circuits respectively connected to clock input terminals of the plurality of functional blocks and generating a clock signal having a frequency suitable for the connected functional blocks based on a reference signal supplied from outside; circuit. Each of the plurality of clock generation circuits,
A detection unit that detects a pulse of the reference clock signal;
An oscillator that starts oscillating based on the detection result of the detection unit,
8. The semiconductor integrated circuit according to claim 7, further comprising: a counter that counts the number of pulses by inputting an oscillation signal of the oscillator, and instructs the oscillator to stop oscillation when the number of pulses reaches a predetermined number. 8. The semiconductor integrated circuit according to claim 7, further comprising output means for outputting the clock signal or a frequency-divided signal thereof to the outside in order to check the frequency of the clock signal generated by the clock generation circuit.

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