JP2004158799A - Light-emitting device array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light-emitting device array which avoids short-circuiting between interconnections, enhances a production yield of the light-emitting device array and prevents complications of the manufacturing process. <P>SOLUTION: In the light emitting device array 100, a plurality of light-emitting devices 101 are arrayed one-dimensionally, and a group 108 of the light-emitting devices which are isolated from each other is divided into two or more individual blocks 104. In each of the light-emitting devices 101, an individual interconnection 102 which is connected to the light-emitting device 101 on a one-to-one basis is formed, and common interconnections 103a, 103b are disposed on both sides of a light-emitting device string formed on the light-emitting device array 100. A common n-side electrode pad 106b is connected to an individual p-side electrode pad 107 via a connecting interconnection 130. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a light emitting element array used for an LED printer or the like.
[0002]
[Prior art]
In recent years, a light emitting element array has been used as a light source of an electrophotographic optical printer. This light-emitting element array is a semiconductor light-emitting device in which a plurality of light-emitting elements are formed one-dimensionally at equal intervals on a single semiconductor substrate. Conventionally, as a light emitting element array, a semiconductor laser array using a semiconductor laser as a light emitting element and an LED array using a light emitting diode (Light Emitting Diode; hereinafter, referred to as “LED”) as a light emitting element are used. Have been.
[0003]
FIG. 8 shows a schematic configuration of a multilayer wiring type LED array 200 according to a conventional example.
[0004]
As shown in the figure, in the multilayer wiring type LED array 200, a plurality of light emitting units 201 are arranged one-dimensionally, and a group of light emitting units separated from each other is divided into two or more blocks 204, Separation grooves 205 are formed for block separation. Further, in the multilayer wiring type LED array 200, individual wirings 202 connected to the light emitting elements 201 are formed, and the individual wirings 202 are connected to a common wiring 203 formed over a plurality of blocks 204 in a plane direction. Are connected so as to be substantially vertical. (For example, see Patent Document 1).
[0005]
[Patent Document 1]
JP-A-11-8409 (pages 8-9, 17, 19)
[0006]
[Problems to be solved by the invention]
However, in the above conventional example, since the individual wiring 202 and the common wiring 203 are formed as a multilayer wiring and the individual wiring 202 and the common wiring 203 intersect, the manufacturing process becomes complicated and a short circuit occurs between the wirings. As a result, the yield of the light emitting element array may be reduced. Further, since a current enough to fully light the light-emitting portion flows through the common wiring 203, its width and thickness are designed according to the current value, and when the number of individual wirings 202 connected to the common wiring 203 increases, the common wiring 203 becomes common. There has been a problem that the wiring width and thickness of the wiring 203 are increased, which affects the dimensions of the light emitting element array.
[0007]
An object of the present invention is to provide a light emitting element array that solves the above-mentioned problems, can avoid a short circuit between wirings, improves the yield of the light emitting element array, and can prevent the manufacturing process from being complicated. And
[0008]
[Means for Solving the Problems]
In order to solve the above problem, a light emitting element array of the present invention is a light emitting element array having two or more blocks obtained by dividing a light emitting element in a light emitting element column into a plurality of blocks, wherein each of the blocks is included in the block. Individual wirings connected one-to-one to the light emitting elements are formed, common wirings connected to the individual wirings are arranged on both sides of the light emitting element row across the block, and one of the blocks is provided with the common wiring outside. A bonding electrode for connection is provided, and the common wiring and the bonding electrode are connected by a connection wiring formed between light-emitting elements included in any of the blocks.
[0009]
Here, the bonding electrode is provided on one side of the light emitting element row, is a common wiring disposed on both sides of the light emitting element row across the block, and is disposed on the opposite side to the bonding electrode with respect to the light emitting element row. The common wiring may be connected to the bonding electrode by a connection wiring.
[0010]
Further, any one of the light emitting elements included in the block in which the connection wiring is formed and the bonding electrode are connected by another connection wiring provided in the block in which the connection wiring is formed. Things.
[0011]
Further, a group may be formed for each of a plurality of blocks, and a common wiring may be separately provided for each group.
[0012]
Further, the semiconductor device may include a semiconductor layer on which a plurality of light emitting elements are formed, and the semiconductor layer may be provided with a separation groove for separating blocks.
[0013]
The light-emitting element array of the present invention includes a semiconductor layer on which a plurality of light-emitting elements are formed, and includes a light-emitting element array having two or more blocks divided into two light-emitting elements. Is formed, and the P-type electrode is electrically connected to a P-type AlGaAs epilayer formed below the semiconductor layer via a P-type diffusion conduction layer formed on the element surface other than the light emitting region. It is characterized by having.
[0014]
Here, the semiconductor layer is formed on a GaAs substrate, and the semiconductor layer may be formed in the order of P-type and N-type.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view schematically showing an LED array according to an embodiment of the present invention. In the light emitting element array 100, a plurality of light emitting elements 101 are arranged one-dimensionally, and a group of light emitting elements separated from each other is divided into two or more individual blocks 104. Here, in each individual block 104, the light emitting elements 101 in the light emitting element row are divided and formed every two, but three or more light emitting elements may be formed in each individual block.
[0016]
Each light emitting element 101 is connected to an individual wiring 102 connected to the light emitting element 101 on a one-to-one basis. The individual wiring 102 is connected to common wirings 103 a and 103 b formed over a plurality of blocks 104. Have been. Here, the common wirings 103a and 103b are arranged on both sides of a light emitting element column formed on the light emitting element array 100.
[0017]
Of the two light emitting elements 101a and 101b formed in each block 104, the individual wiring 102a connected to the light emitting element 101a is connected to the common wiring 103a, and the individual wiring 102b connected to the light emitting element 101b is , Common wiring 103b.
[0018]
In the light emitting element array 100, separation grooves 105 for block separation are formed, and the individual blocks 104 are electrically separated from each other by the separation grooves 105. Further, a group 108 is formed for every two or more blocks 104, and the common wirings 103a and 103b are provided separately for each group. In this embodiment, a group is formed for each of the six blocks, and the connections of the individual wires 102a and 102b and the common wires 103a and 103b of each group are formed in the same pattern. In addition, the number of the blocks can be appropriately selected depending on the application. Any number of blocks may be used as long as a plurality of blocks are provided. A group may be formed for every two or more blocks.
[0019]
Further, as shown in FIG. 1, common n-side electrode pads (common n-side electrodes) 106a and 106b, which are n-side wire bonding pads, are formed in the block 104 forming the group 108. These common n-side electrode pads (common n-side electrodes) 106a and 106b are bonding pads (bonding electrodes) provided for connecting the common wirings 103a and 103b to the outside. It is provided on one side (that is, on the upper side in FIG. 1).
[0020]
Here, in the present embodiment, as shown in FIG. 1, the common n-side electrode pad 106a is one of the common wirings 103a and 103b arranged on both sides of the light emitting element column formed on the light emitting element array 100. The common n-side electrode pad 106b is connected to the common wiring 103b by a connection wiring 130 formed between the two light emitting elements 101a and 101b included in the block 104. There is a feature in the point.
[0021]
That is, the common n-side electrode pad 106b is connected to the column of the light emitting element 101 among the common wirings 103a and 103b arranged on both sides of the light emitting element 101 across the block 104 via the connection wiring 130. It is characterized in that it is connected to a common wiring 103b disposed on the side opposite to the side on which the n-side electrode pad 106b is formed (that is, on the lower side in FIG. 1).
[0022]
An individual p-side electrode pad 107 (individual p-side electrode), which is a p-side wire bonding pad, is formed one for each block 104. Here, the individual p-side electrode pad 107 is formed on the side opposite to the side on which the common n-side electrode pads 106a and 106b are formed with respect to the light emitting element row. In this embodiment, on the common n-side electrode pads 106a and 106b and on the individual p-side electrode pads 107, respectively, for the purpose of adjusting the height due to the convenience of connection with external electrodes, the convenience of wire bonding, etc. Further, another electrode pad can be formed.
[0023]
As described above, in the present embodiment, the common wiring 103a connected to the individual wiring 102a and the common wiring 103b connected to the individual wiring 102b are arranged on both sides of the light emitting element row over the block 104. The common n-side electrode pads (common n-side electrodes) 106a and 106b are provided on one side of the row of the light emitting elements 101, and the common n-side electrode pads 106a are connected to the common wiring 103a. The common n-side electrode pad 106b is opposite to the side on which the common n-side electrode pad 106b is formed with respect to the row of the light emitting elements 101 via the connection wiring 130 (ie, the lower side in FIG. 1). ) Are connected to the common wiring 103b arranged in the above.
[0024]
With this structure, it is possible to prevent the individual wirings 102a and 102b and the common wirings 103a and 103b from being multi-layered wirings, so that it is possible to prevent the manufacturing process from being complicated and to avoid a short circuit between the wirings. Retention can be improved.
[0025]
In the present embodiment, the common n-side electrode pad 106a is connected to the common wiring 103a, and the common n-side electrode pad 106b is connected to the row of the light emitting elements 101 via the connection wiring 130. The common n-side electrode pad 106b is connected to a common wiring 103b arranged on the opposite side to the side on which the common n-side electrode pad 106b is formed. Therefore, even if a current sufficient to light all the light emitting portions is supplied to the common wirings 103a and 103b, a current can be supplied to each light emitting element 101 uniformly (or a voltage can be applied). The emission intensity can be made uniform, and even if the current flowing through the common lines 103a, 103b increases due to the increase in the number of individual lines 102 connected to the common lines 103a, 103b, the common lines 103a, 103b Since the wiring width and thickness of 103b are hardly affected, it is possible to avoid the adverse effect of affecting the dimensions of the light emitting element array.
[0026]
In this embodiment, the common wirings 103a and 103b are separated for each group, and bonding electrodes 106a and 106b for connecting the common wirings 103a and 103b to the outside are provided for each group. With such a structure, characteristic inspection can be performed for each group.
Also, by increasing or decreasing the number of groups, a light emitting element array having desired dots can be manufactured.
[0027]
In the present embodiment, as described above, the common n-side electrode pad 106b is configured to be connected to the common wiring 103b via the connection wiring 130, but as shown in FIG. The electrode pad 106b is a common wiring among the light emitting elements 101a and 101b included in the block 104 on which the connection wiring 130 is formed by another connection wiring 131 provided on the block 104 on which the connection wiring 130 is formed. The light emitting element 101b connected to the light emitting element 103b may be connected to the light emitting element 101b.
[0028]
With such a configuration, in addition to the effect of the light emitting element array of FIG. 1 described above, in addition to the case where the distance between the light emitting elements 101a and 101b is very narrow, the connection wiring 130 must be narrowed. In the light emitting element array shown in FIG. 2, the current flowing only in the connection wiring 130 can be distributed to the connection wiring 130 and the other connection wiring 131 in the light emitting element array shown in FIG. The effect that overcurrent can be prevented from flowing through the device can be obtained.
[0029]
Next, an example of a method for manufacturing the LED array 100 according to the present embodiment will be described with reference to FIGS. 3 (a) to 3 (c) are cross-sectional process diagrams for explaining a method of manufacturing an LED array according to an embodiment of the present invention, and are cross-sectional processes in consideration of the AA cross section shown in FIG. FIG. FIG. 5 is a sectional view taken along line BB of FIG.
[0030]
First, in the present manufacturing method, a semiconductor layer 109 is formed on a semiconductor substrate 110 as shown in FIG. Here, as the semiconductor substrate 110, for example, a high-resistance GaAs substrate is used. The semiconductor layer 109 is formed by, for example, sequentially growing a p-type AlGaAs layer, an active layer, an n-type AlGaAs layer, and an n-type GaAs layer by an epitaxial growth method. Here, the epitaxial growth method is a method of growing a crystal film on a substrate, and includes a VPE (vapor phase epitaxial) method, a CVD (chemical vapor deposition) method, a MOVPE (organic metal vapor phase epitaxial) method, and a MOCVD method. (Organic metal chemical vapor deposition), halide-VPE (halogen chemical vapor epitaxial), MBE (molecular beam epitaxy), MOMBE (organic metal molecular beam epitaxy), GSMBE (gas source molecular beam epitaxy) , CBE (chemical beam epitaxy) method. The thickness of the semiconductor layer 109 is, for example, 5 μm.
[0031]
When forming the semiconductor layer 109 on the semiconductor substrate 110, the semiconductor layers are formed in the order of P-type and N-type. Therefore, in the semiconductor layer 109, the upper layer 109a is N-type and the lower layer 109b is P-type.
[0032]
Next, after forming a diffusion mask (not shown) on the surface of the semiconductor layer 109, a diffusion separation portion and a diffusion conduction portion (both not shown) are opened in the film. The opening can be formed by, for example, photolithography and etching. Next, a diffusion source (not shown) doped with a predetermined impurity is formed on the diffusion mask formed on the semiconductor layer 109. Here, for example, Zn is used as the predetermined impurity. As the diffusion source, for example, a ZnO—SiO ₂ film (for example, 150 Å) can be used. As a film formation method, for example, a sputtering method can be used.
[0033]
Next, an annealing cap film (not shown) is formed on the diffusion source doped with a predetermined impurity. Here, for example, a Si ₃ N ₄ film (for example, 1000 Å) can be used as the annealing cap film. Further, as a method of forming the annealing cap film, for example, a sputtering method can be used.
[0034]
Next, as shown in FIG. 3B, diffusion annealing is performed using a diffusion source doped with a predetermined impurity to diffuse the predetermined impurity into the semiconductor layer 109, and the light emitting element 101 and the p-type diffusion are diffused. An isolation layer 112 and a diffusion conduction layer 113 are formed. Here, the diffusion layer is formed so as to reach the p-type AlGaAs layer 109b under the semiconductor layer 109, and is diffused, for example, by 3 μm. Next, the annealing cap film and the diffusion source are removed, and then the diffusion mask formed on the surface of the semiconductor layer 109 is removed.
[0035]
Next, as shown in FIG. 4, isolation grooves 105 for block isolation are formed in the semiconductor layer 109. The separation groove 105 is formed at a depth reaching the semiconductor substrate 110 as shown in FIG.
[0036]
Next, as shown in FIG. 3C, an insulating film 114 is formed on the semiconductor layer 109, and an opening 117 exposing a part of the light emitting element 101 and an opening exposing a surface of the diffusion conduction layer 113 are formed. The part 118 is formed. Here, the opening can be formed by, for example, photolithography and etching. Note that, as shown in FIG. 5, the insulating film 114 is formed on the semiconductor layer 109 so as to cover the isolation trench 105. Thereby, the semiconductor layer can be physically and electrically separated into each block.
[0037]
Next, as shown in FIG. 3C, a pattern is formed by a lift-off method, and the individual wiring 102, the common wirings 103a and 103b, and the common n-side electrode pad 106a (in the LED array shown in FIG. Simultaneously form the common n-side electrode pad 106b). Although not shown in FIG. 3C, at this time, the connection wiring 130 is also formed at the same time, and in the LED array shown in FIG. 2, another connection wiring 131 is also formed at the same time. .
[0038]
Here, the n-side electrode includes the individual wiring 102 and the common wirings 103a and 103b, and the n-side electrode includes the individual wiring 102 and the common wirings 103a and 103b in a group 108 formed by two or more blocks 104. And is connected to at least one of the two common n-side electrode pads (common n-side electrodes) 106a and 106b formed in the same group 108. The electrode material may be any material that can be ohmic-connected to the semiconductor. For example, an Au laminated film such as Ti (200 Å) / Au (50 Å) / Ni / Ge / Au (1.2 μm) can be used.
[0039]
Next, as shown in FIG. 3C, a pattern is also formed by a lift-off method for forming the p-side electrode pad, and the individual p-side electrode pad 107 (individually) is formed on the diffusion conductive layer 113 through the opening 118. (p-side electrode). The individual p-side electrode pad 107 is ohmically connected to a P-type diffusion conduction layer 113 formed so as to penetrate a p-layer 109b formed as a lower layer of the semiconductor layer 109. That is, the individual p-side electrode pad 107 is connected to the P-type AlGaAs layer formed below the semiconductor layer 109 via the P-type diffusion conduction layer 113 formed on the element surface other than the light-emitting region where the light-emitting element 101 is formed. Is electrically connected to the epi layer composed of Here, the electrode material may be any material that can be ohmic-connected to the semiconductor. For example, an Au alloy film such as Ti (200 Å) / Au (1.2 μm) can be used.
[0040]
Note that the common n-side electrode pads 106a and 106b and the individual p-side electrode pads 107 do not necessarily need to be formed in separate steps, but may be formed simultaneously in the same step. By simultaneously forming in this manner, when performing wire bonding connection with the outside, the N side and the P side can be connected under the same conditions.
[0041]
Next, a sintering process (heat treatment) for ohmic connection between the electrode and the semiconductor layer 109 is performed, and if necessary, the back surface of the semiconductor substrate 110 is polished, and then the light emitting element array 100 shown in FIG. 4 is manufactured.
[0042]
FIG. 6 shows an example of using the light emitting element array. In the figure, common n-side electrode pads 106a and 106b are connected to a power supply line L via switches Q1 and Q2. On the other hand, the individual p-side electrode pads 107a, 107b, 107c, 107d, 107e, 107f are connected to the output terminal T via switches S1, S2, S3, S4, S5, S6. W is an output circuit that sequentially outputs pulses to output terminals P1, P2, P3, P4, P5, and P6 according to input image data, and the output pulses are switches S1, S2, S3, S4, and S5. , S6 are sequentially turned on. The optical print head has a plurality of groups 108, and the length of the print head is determined, for example, according to the axial length of the photosensitive drum. Of the two light emitting elements in each block of the light emitting element array, 101a, 101c, 101e, 101g, 101i, and 101k are used for writing odd lines, and 101b, 101d, 101f, 101h, 101j, and 101m are used for writing even lines. Used for Therefore, as shown in FIG. 7, the switches Q1 and Q2 are controlled so that when one is on, the other is off.
[0043]
It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made based on the gist of the present invention, and these are not excluded from the scope of the present invention.
[0044]
For example, in the embodiment of the present invention, the case where the LED array is used as the light emitting element array has been described. However, the light emitting element is not limited to this, and another element such as a light emitting laser can be used.
[0045]
Further, the material, composition, and the like of the substrate, the electrode, the impurities, and the like are not limited to those of the embodiments, and other materials can be selected.
[0046]
For example, in the above embodiment, a GaAs substrate is used as a semiconductor substrate, but other substrates, for example, a Si substrate or a glass substrate can be used.
[0047]
Further, in the above embodiment, Zn is applied as a doping impurity. However, the present invention is not limited thereto, and various other impurities, for example, an impurity of a group 5 element such as P or As, or an impurity of a group 3 element such as B or Ga may be used. Impurities, and can be applied.
[0048]
【The invention's effect】
As described above, in the light emitting element array according to the present invention, the common wiring 103a connected to the individual wiring 102a and the common wiring 103b connected to the individual wiring 102b are arranged on both sides of the light emitting element row across the block 104. The common n-side electrode pad (common n-side electrode) 106a, 106b is provided on one side of the row of the light emitting elements 101, and the common n-side electrode pad 106a is connected to the common wiring 103a. The common n-side electrode pad 106b is connected to the row of the light emitting elements 101 via the connection wiring 130, and the common n-side electrode pad 106b is arranged on the opposite side to the side on which the common n-side electrode pad 106b is formed. It is connected to the wiring 103b.
[0049]
With this structure, it is possible to prevent the individual wirings 102a and 102b and the common wirings 103a and 103b from being multi-layered wirings, so that it is possible to prevent the manufacturing process from being complicated and to avoid a short circuit between the wirings. Retention can be improved.
[0050]
In addition, since the number of blocks in the group can be appropriately selected, the upper limit of the current flowing through the common wirings 103a and 103b can be adjusted. As a result, the common wirings 103a and 103b can be formed with the minimum wiring width and thickness. Therefore, an inexpensive LED array can be provided.
[0051]
The common n-side electrode pad 106a is connected to the common wiring 103a, and the common n-side electrode pad 106b is connected to the row of the light emitting elements 101 via the connection wiring 130. Are connected to the common wiring 103b arranged on the side opposite to the side where the is formed. Therefore, even if a current sufficient to fully light the light-emitting portion is applied to the common wirings 103a and 103b, the current can be uniformly applied (or voltage applied) to each light-emitting element 101, so that each light-emitting element n Since the light emission intensity can be made uniform and even if the current flowing through the common wirings 103a and 103b increases, the wiring width and thickness of the common wirings 103a and 103b are hardly affected. Can be avoided.
[0052]
In the light emitting element array according to the present invention, the connection wiring 130 is formed on the common n-side electrode pad 106b by another connection wiring 131 provided on the block 104 on which the connection wiring 130 is formed. Of the light emitting elements 101a and 101b included in the block 104, the light emitting element 101b is also connected to the light emitting element 101b connected to the common wiring 103b.
[0053]
With such a configuration, when the distance between the light-emitting elements 101a and 101b is extremely small, and the connection wiring 130 must be narrowed, a current originally flowing only in the connection wiring 130 is originally reduced to the connection wiring 130. Since the wiring 130 can be distributed to the wiring 130 and another connection wiring 131, an overcurrent can be prevented from flowing through the connection wiring 130.
[0054]
Further, since the separation groove 105 is provided in the semiconductor layer 109 provided on the semiconductor substrate 110, the semiconductor layer 109 can be physically separated into each block.
[0055]
If a semiconductor substrate 110 having a sufficiently higher resistance than the semiconductor layer 109 is applied, the semiconductor layer 109 can be physically and electrically separated into blocks.
[0056]
The individual P-side electrode 107 formed in each block is connected to the P-type AlGaAs epitaxial layer 109b formed under the semiconductor layer 109 via the P-type diffusion conduction layer 113 formed on the element surface other than the light emitting region. , It is possible to avoid an adverse effect on the light emitting layer due to an impact at the time of wire bonding.
[0057]
The light emitting element 101 is formed by diffusing a predetermined impurity into the semiconductor layer 109 already formed in the order of P-type and N-type. Therefore, in the formation of the light emitting layer by diffusion involving the two factors of epitaxial growth and diffusion, the final characteristics of the light emitting layer cannot be known until after the diffusion, but in the present embodiment, the light emitting layer has already been formed. Therefore, the stable characteristics of the light emitting layer can be verified in advance.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing an LED array according to an embodiment of the present invention.
FIG. 2 is a plan view schematically showing an LED array according to another embodiment of the present invention.
FIG. 3 is a sectional process view for explaining the method for manufacturing the LED array according to the embodiment of the present invention.
FIG. 4 is a plan view schematically showing an LED array according to an embodiment of the present invention.
FIG. 5 is a sectional view taken along line BB in the schematic plan view shown in FIG. 4;
FIG. 6 is a schematic view showing an example of use of the LED array according to the embodiment of the present invention.
FIG. 7 is a signal waveform diagram for explaining the operation of FIG. 7;
FIG. 8 is a plan view schematically showing a conventional LED array.
[Explanation of symbols]
100: LED array 101: Light emitting element 102: Individual wiring 103a, 103b: Common wiring 106a, 106b: Common n-side electrode pad 107: Individual p-side electrode pad 109: Semiconductor layer 110: Semiconductor substrate 112: Diffusion separation layer 113: Diffusion Conductive layer 114: Insulating layer 130: Connection wiring 131: Other connection wiring

Claims (7)

In a light-emitting element array having two or more blocks obtained by dividing light-emitting elements in a light-emitting element column into a plurality of light-emitting elements, each of the blocks is formed with an individual wiring connected one-to-one to a light-emitting element included in the block. A common wiring connected to the individual wiring is disposed on both sides of the light emitting element row across the block, and one of the blocks is provided with a bonding electrode for connecting the common wiring to the outside. A light-emitting element array, wherein the common wiring and the bonding electrode are connected by a connection wiring formed between light-emitting elements included in any of the blocks. The bonding electrode is provided on one side of the light emitting element row, and is a common wiring disposed on both sides of the light emitting element row across the block, and on a side opposite to the bonding electrode with respect to the light emitting element row. The light emitting element array according to claim 1, wherein the disposed common wiring is connected to the bonding electrode by the connection wiring. Any one of the light emitting elements included in the block in which the connection wiring is formed and the bonding electrode are connected by another connection wiring provided in the block in which the connection wiring is formed. The light-emitting element array according to claim 1, wherein: 4. The light emitting device array according to claim 1, wherein a group is formed for each of a plurality of blocks, and the common wiring is provided separately for each of the groups. 4. The light emitting device array according to claim 1, further comprising a semiconductor layer on which a plurality of light emitting devices are formed, wherein the semiconductor layer is provided with a separation groove for separating the block. . In a light-emitting element array including a semiconductor layer on which a plurality of light-emitting elements are formed and having two or more blocks divided for every two light-emitting elements, a P-type electrode is formed in each of the blocks. A light-emitting element, wherein the electrode is electrically connected to a p-type AlGaAs epilayer formed below the semiconductor layer via a p-type diffusion conduction layer formed on the element surface other than the light-emitting region. array. The light emitting device array according to claim 6, wherein the semiconductor layer is formed on a GaAs substrate, and the semiconductor layers are formed in the order of P-type and N-type.

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