JP2004158094A - Flash memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flash memory device that can stop the sequence during the operation from a writing or erasing command and output the status of that time inside the device. <P>SOLUTION: An analyzing mode command is inputted as the command input 1 before inputting a write or erase command. When this analyzing mode command is inputted, the controller 3 control the command sequence to stop writing or erasing at a desired step. Also, at the same time, the controller 3 controls the selector 11 to output the device status collected by the status collecting circuit 10 as the status output 12. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a flash memory device that performs a write operation or an erase operation according to a command sequence.
[0002]
[Prior art]
Writing and erasing data to and from a flash memory, which is a nonvolatile memory, is performed by injecting or extracting electrons from / to a floating gate disposed in an insulating oxide film of a memory cell. Therefore, for example, in writing data, it is assumed that a memory cell in which electrons have been injected into the floating gate holds logic '0', and a memory cell in which electrons have not been injected holds logic '1'. Things. Therefore, in this case, extracting electrons from the floating gate by erasing data can be said to be equivalent to bringing all the memory cells into the logical "1" state.
[0003]
The structure of the floating gate portion is fine, and the data write characteristics or erase characteristics of each memory cell vary to some extent. Therefore, not all the memory cells can be set to a predetermined value by one writing operation or one erasing operation.
[0004]
Therefore, when a write or erase command is input to the flash memory device, a sequence in which the write or erase operation is repeated until all memory cells have a desired value is automatically generated inside the flash memory device. The control circuit is designed. In this case, the maximum value of the number of repetitions is set in advance, and when this number is reached, the write operation or the erase operation ends even if the state of the memory cell does not reach a desired state.
[0005]
FIG. 6 is a block diagram showing a configuration for performing a write and erase operation of a conventional flash memory device. The command input 1a from the external terminal is stored in the command register 2a. Control unit 103 decodes the command decoder 103 ₁ reads the data of the command register 2a, generates a control signal for controlling a series of operation sequences by the loop counter and the sequence control circuit 103 ₂ (not shown).
[0006]
The address input 4a for specifying the address of the memory cell is input from an external terminal and stored in the address register 5a, and the data input 6a from the external terminal is stored in the data register 7a. The data stored in the data register 7a becomes data to be written to the memory cell array 8a during a write operation.
[0007]
When one write operation or one erase operation is completed, the verification circuit 9a verifies whether the value of the memory cell array 8a matches the value of the data register 7a. The verification result is fed back to the control unit 103, and it is determined whether the writing operation or the erasing operation is completed or further repeated.
[0008]
FIG. 7 is a flowchart showing a sequence of a write operation or an erase operation of the conventional flash memory device by the control unit 103 of FIG. Since the sequence of the writing operation and the erasing operation are the same, the flow is represented by an expression representing both of them in common.
[0009]
At the start of the sequence (step S101), first, a mode designation command for designating a write mode (write mode) or an erase mode (erase mode) is input to the command register 2a (step S102). Next, an address is input (step S103), and data is loaded (step S104). Next, a write start command (write start command) or an erase start command (erase start command) is input to the command register 2a (step S105). Here, the value n of a loop counter for counting the number of repetitions of the subsequent write operation or erase operation is set to 1 (step S106).
[0010]
Thereafter, the writing or erasing operation specified by the command is performed (step S107). When the specified operation is completed, verification is performed by the verification circuit 9a (step S108). If the value of the memory cell array 8a and the value of the data register 7a match (OK), writing or erasing has been performed correctly. Then, a pass signal is output in the normal end processing (step S109), and a series of sequences under the control of the control unit 103 ends (step S113).
[0011]
However, if the value of the memory cell array 8a and the value of the data register 7a do not match (NG) in the verification in step S108, it is checked whether the value n of the loop counter is the set maximum number of repetitions (k) (step S110). If it is less than k (NO), the counter value is advanced by one (step S110), and the operation returns to step S107.
[0012]
Thereafter, the operation in step S107 is repeatedly performed until the verification is OK. However, in step S117, when the number of repetitions n = k (YES), no further command designation operation is performed, and the value of the memory cell becomes the desired value. , A series of sequences under the control of the control unit 103 is ended via the abnormal end process (step S112) (step S113).
[0013]
[Problems to be solved by the invention]
When the abnormal termination process is performed in the above sequence flow, one of the causes may be a failure of a device in the flash memory device or a failure of a circuit operation. However, when trying to pursue the cause of the abnormal termination of the sequence, the conventional sequence flow has the following problems. That is, the sequence operation automatically proceeds from the beginning to the end, and it is not possible to know at which step in the series of operations the abnormality has occurred. Therefore, in order to elucidate the cause of the abnormal termination of the sequence, it is necessary to open the package of the IC constituting the flash memory device and to investigate the internal circuit operation of the IC in detail using, for example, an electron beam tester. Was.
[0014]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a flash memory device capable of detecting an abnormality in the middle of execution of a write or erase operation.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, a flash memory device according to the present invention comprises a memory cell array, writing and erasing means for writing and erasing data to and from this memory cell array, and an externally input command for writing or erasing. Command storage means for storing commands for stopping, resuming, or terminating writing or erasing, and writing or erasing the writing or erasing means for the writing and erasing means, respectively, in accordance with a write command or an erasure command stored in the command storage means. Command sequence generating means for generating a command sequence; command sequence stopping means for stopping execution of the write or erase command sequence in accordance with a stop command stored in the command storage means; A command sequence resuming and terminating means for resuming or terminating the execution of the programming or erasing command sequence that has been stopped in accordance with a resume or termination command stored in the memory means. Further, a status output means for outputting an internal signal of the device as a status to the outside of the device is provided.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0017]
(Embodiment)
FIG. 1 is a block diagram showing a configuration of a flash memory device according to an embodiment of the present invention.
[0018]
Command input 1 from an external terminal is stored in command register 2. Control unit 3 decodes the command decoder 3 ₁ reads the data of the command register 2 generates a control signal for controlling the sequence of operation sequence by the sequence control circuit 3 _2. The sequence control circuit 3 _2, includes a loop counter 3 ₂₁ for counting the number of write and erase.
[0019]
Here, in the flash memory device according to the present embodiment, the analysis mode command and the restart or end (hereinafter referred to as restart / end) are added to the normal write mode command, the write start command, the erase mode command, and the erase start command as new commands. The command has been added. Here, the analysis mode command instructs a temporary stop of the apparatus and an output operation of the internal status.
[0020]
Control unit 3, in response to this additional command, the command decoder 3 ₁ generates a new decoded output, to generate a stop signal at the stop signal generating circuit 3 ₃ it as input, resume / end signal generator generating a resume / end signal in the circuit 3 _4. Also, the status output select signal at the status output select signal generating circuit ₃₅ also generates.
[0021]
An address input 4 for specifying an address of a memory cell is input from an external terminal and stored in an address register 5, and a data input 6 from an external terminal is stored in a data register 7. The data stored in the data register 7 is the data to be written to the memory cell array 8. However, in the case of the erase command, the value of the data register 7 is automatically set to "1" in the flash memory device regardless of the input of data from the external terminal.
[0022]
The verification circuit 9 verifies whether the value of the memory cell array 8 matches the value of the data register 7 after one write operation or one erasure operation is completed. The verification result is fed back to the control unit 3 to determine whether to end or further repeat the writing operation or the erasing operation.
[0023]
The status collection circuit 10 is a circuit that collects information on the operation state of each circuit related to a write or erase operation. As the information to be collected, for example, various flag signals indicating whether each command has been correctly received, whether the address input or data input can be received, whether the circuit has been enabled for writing or erasing, and the like, can be used. is there.
[0024]
The output of the status collection circuit 10 is input to the selector 11 as a status signal indicating a circuit operation state. Information related to the verification by the verification circuit 9 is also input to the selector 11 via the status collection circuit 10 as one of the status signals.
[0025]
The selector 11 is a selector that receives an output of the memory cell array 8 and a status signal as inputs, and selects and outputs one of them. During normal operation, the output of the memory cell array 8 is output, but when a status output select signal is generated, the status signal is output as a status output 12 and transmitted to an external terminal of the IC.
[0026]
FIG. 2 and FIG. 3 are flowcharts showing the sequence of the write operation when the analysis mode command is input in the flash memory device of the present embodiment.
[0027]
After the start of the operation (step S1), first, an analysis mode command is input to the command register 2 (step S2). When this command is input, the control unit 3 outputs a stop signal for stopping the sequence in a predetermined step and a status output select signal for switching the selector 12 so as to output the circuit operation status at that time to an external terminal. Become like
[0028]
Next, when a write mode command is input (step S3), the sequence stops (step S4), and the status at that time is output. The status signals output include a flag signal indicating whether the command register 2 has correctly received the write mode command, a flag signal indicating whether the address register 5 is ready to input an address, and a data register 7 indicating that the data load has been completed. This is a flag signal or the like indicating whether or not a possible state has been reached.
[0029]
If a flag indicating that the circuit is not operating properly is set in these flag signals, it means that an abnormal operation circuit on the flash memory device has been narrowed down. In this case, it is meaningless to proceed with the sequence any further. Therefore, an end command is input from outside (step S5), and after the end of step S6 is determined, the process proceeds to the end process (step S7), and the control unit 3 Is completed (step S24).
[0030]
If the status output output in step S4 is normal, a restart command is input in step S5 to further advance the sequence. At step S6, it is determined that the operation is to be restarted, and the sequence proceeds with address input (step S8) and data loading (step S9). At this point, the sequence is stopped again, and the status at this time is output (step S10).
[0031]
The status shown here is a flag signal indicating whether or not the circuit has become writable. If a flag indicating an operation abnormality is set in this flag signal, it is understood that there is an abnormality in a circuit related to the flag.
[0032]
After seeing the status output, a restart or end command is input (step S11). In step S12, the content of the command in step S11 is determined. If the command is terminated, a series of sequence operations by the control unit 3 is terminated through a termination process (step S7) (step S24).
[0033]
If the determination in step S12 is restarted, the process proceeds to input of a write start command (step S13). Here sets the value n of the loop counter _{3 21} to 1 (step S14), and enters the write operation (step S15).
[0034]
When the write operation is completed, it is verified whether a desired value has been correctly written to the memory cell array 8 (step S16). If the result of the verification is OK, a series of sequence operations by the control unit 3 is completed through a normal end process (Step S17) (Step S24). If the result of the verification is NG, the sequence is terminated at this time. Stop and output the status (step S18). Here the status to be output, the input signal and the validation circuit 9, and the like verification result signal and the loop count (the value n of the loop counter 3 _21).
[0035]
The status is analyzed to determine whether the cause of the sequence operation abnormality is known. If the cause of the abnormality in the sequence operation is known, it is not necessary to continue the sequence any more. However, if the cause of the abnormality in the sequence operation is not known at this point, it is necessary to continue the sequence. According to the necessity, a restart or end command is input (step S19).
[0036]
In step S20, the contents of the command in step S19 are determined. If the command is terminated, a series of sequence operations by the control unit 3 is terminated through a termination process (step S7) (step S24). proceeds, it is determined whether the reached the maximum number of iterations the value n of the loop counter 3 ₂₁ is set (k) (step S21). If n is less than k (NO), n is increased by one (step S22), and the process returns to step S15.
[0037]
Thereafter, the operation from step S15 to step S22 are repeated until the maximum number of iterations the value n of the loop counter 3 ₂₁ is set (k). Reaching the maximum number of iterations the value n of the loop counter _{3 21} is set (k), that is, the n = k (YES) at step S21, the sequence proceeds to step S23, are the abnormal end process, the control unit The series of sequence operations by No. 3 ends (step S24).
[0038]
4 and 5 are flowcharts showing a sequence of an erasing operation when an analysis mode command is input to the flash memory according to the present embodiment.
[0039]
The flow of the sequence of the erase operation in the present embodiment is not much different from the sequence of the write operation. Therefore, here, steps different from the sequence of the write operation according to the flows of FIGS. 2 and 3 will be described, and the same steps will be denoted by the same reference numerals and detailed description thereof will be omitted.
[0040]
When an erase mode command is input to the command register 2 in step S33, the sequence stops in step S4 and a status is output. The status output at this time indicates whether the command register 2 has correctly received the erase mode command. There are a flag signal, a flag signal indicating whether or not the address register 5 is ready to input an address, a flag signal indicating whether or not a signal instructing erasure to a memory cell is ready to be output, and the like.
[0041]
Since data is erased from the memory cell array 8 in units of blocks, a block address for designating a block from which data is to be erased is input in step S38. Also, all the values of the data register 7 are automatically set to "1" in the flash memory device (step S39).
[0042]
The status output in step S10 is a flag signal indicating whether or not the circuit has become erasable.
[0043]
Erase start command is input (step S43), sets the value n of the loop counter _{3 21} to 1 (step S14), and enters the erase operation (step S45).
[0044]
After the erase operation, verification is performed (step S16), and if the result is NG, the sequence is stopped (step S18). Status output at this step S18, the input signal and the validation circuit 9, and the like verification result signal and the loop count (the value n of the loop counter 3 _21).
[0045]
According to the above-described embodiment, the sequence can be stopped during the write or erase operation, and the internal signal of the flash memory device, that is, the status at that time can be output to the outside of the flash memory device. Therefore, it is possible to know at which step of the write or erase command operation an error has occurred, and to easily estimate which circuit of the flash memory device causes the abnormal end of the write or erase command operation. . Therefore, the cause of the occurrence of the abnormality in the writing or erasing operation of the flash memory device can be easily clarified.
[0046]
【The invention's effect】
According to the present invention, by using the command sequence using the analysis mode command, it is possible to output the circuit operation state inside the flash memory device during the write or erase operation to the outside of the flash memory device.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a flash memory device according to an embodiment of the present invention.
FIG. 2 is a flowchart showing a first stage of an example of a write operation sequence when an analysis mode command is input in the flash memory device according to the embodiment of the present invention.
FIG. 3 is a flowchart showing a second stage of an example of a write operation sequence when the analysis mode command is input in the flash memory device according to the embodiment of the present invention.
FIG. 4 is a flowchart showing a first stage of an example of a sequence of an erase operation when an analysis mode command is input in the flash memory device according to the embodiment of the present invention.
FIG. 5 is a flowchart showing a second stage of an example of a sequence of an erase operation when an analysis mode command is input in the flash memory device according to the embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of a conventional flash memory device.
FIG. 7 is a flowchart showing a sequence of a write operation or an erase operation of the conventional flash memory device.
[Explanation of symbols]
1,1a command input 2,2a command register 3,103 controller ₃ 1, 103 ₁ command decoder ₃ 2, 103 ₂ sequence control circuit _{3 21} loop counter _{3 3} stop signal generating circuit _{3 4} Resume / end signal generating circuit 4, 4a Address input 5, 5a Address register 6, 6a Data input 7, 7a Data register 8, 8a Memory cell array 9, 9a Verification circuit 10 Status collection circuit 11 Selector 12 Status output

Claims (4)

A memory cell array;
Writing and erasing means for writing and erasing data to and from the memory cell array;
Command storage means for storing a command for writing or erasing input from the outside and a command for stopping, resuming or terminating writing or erasing,
Command sequence generating means for generating a write or erase command sequence for the write and erase means, respectively, according to a write command or an erase command stored in the command storage means;
Command sequence stopping means for stopping execution of the write or erase command sequence in accordance with a stop command stored in the command storage means; and a write or write stop which has been stopped in accordance with a restart or end command stored in the command storage means. Alternatively, a flash memory device including a command sequence restarting and terminating means for restarting or terminating the execution of the erase command sequence,
The device further comprises:
A flash memory device comprising status output means for outputting an internal signal of the device as a status to the outside of the device. 2. The flash memory device according to claim 1, wherein said status output means includes a selector for selecting and outputting one of said status and said memory cell array output. 3. The flash memory device according to claim 2, wherein the selector selects and outputs the status when the execution of the write or erase command sequence is stopped. 4. The flash memory device according to claim 1, wherein the status is a flag signal indicating an operation result of a predetermined circuit inside the device.

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