JP2004158074A - Method for rewriting data in nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for rewriting data in a nonvolatile semiconductor memory, which can raise the number of available rewriting (endurance lifetime) by a new technique. <P>SOLUTION: Injection/emission of electrons to a floating gate electrode from an buried impurities diffused area formed on a surface section of a silicon substrate is performed through a tunnel oxide film. As a shape of a voltage pulse impressed in writing and erasing data, the voltage is raised steeply in the first periods tre1 and trw1 to tunneling starting voltages Vtne and Vtnw at starting time, and in the second periods tre2 and trw2, the voltage is elevated gently to the subsequent final rewriting voltage Vpp. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data rewriting method for a nonvolatile semiconductor memory.
[0002]
[Prior art]
An EEPROM is an electrically rewritable device. This device creates a state where data becomes "1" and "0" by injection / emission of electrons through a tunnel film. Specifically, a state where data becomes "1" or "0" is created by tunneling electrons through a thin insulating film of about 10 nm called a tunnel film between the BN layer (buried impurity diffusion region) and the floating gate.
[0003]
Injecting and emitting these electrons are referred to as erasing and writing, respectively, in the EEPROM. It is desirable in terms of memory characteristics that the number of times of erasing and writing (endurance life) is large.
[0004]
However, the tunnel film is damaged by the tunneling that occurs at the time of writing / erasing, and eventually causes the tunnel film to be destroyed.
It is a well-known fact that the lifetime of a tunnel film is determined by the amount of electric charge passed through it. The amount of charge passing through to this destruction is called a destructive charge Qbd. It is known that the endurance life of an EEPROM corresponds to the amount of destructive charge Qbd because electrons pass through the tunnel film to rewrite data as described above.
[0005]
As shown in FIG. 11, it is known that the breakdown charge amount Qbd decreases as the electric field strength Eox when a tunnel current flows increases. FIG. 11 in the present application is a reference to FIG. 8 in “Umeda, Transactions of the Institute of Electronics, Information and Communication Engineers vol.j80-C-II No. 2, p. 65-72, 1997”.
[0006]
As a method of suppressing the electric field at the time of rewriting, Patent Documents 1 and 2 propose a method of extending the time (rise time tr, trw) until reaching the final rewriting voltage Vpp at the time of writing or erasing. FIG. 12 shows a rewriting pulse waveform using such a method.
[0007]
However, in this pulse waveform, the final rewrite voltage Vpp fluctuates depending on the temperature or the like, and depending on circuit accuracy, when the final rewrite voltage Vpp is low, times te and tw in which the final rewrite voltage Vpp becomes constant may be required. At this time, if the rise times tr and trw are long, the constant voltage application times te and tw become short, so that sufficient write threshold voltage Vtw and erase threshold voltage Vte cannot be obtained, and a malfunction occurs during reading. is there. In addition, if an attempt is made to achieve a predetermined threshold voltage for writing and a threshold voltage for erasing within the total rewriting time Tew (about 10 ms) required under normal use conditions, the upper limits of the rise times tr and trw are limited. .
[0008]
[Patent Document 1]
JP-A-61-289497 [Patent Document 2]
Japanese Patent Application Laid-Open No. 61-239498
[Problems to be solved by the invention]
The present invention has been made under such a background, and an object of the present invention is to provide a data rewriting method for a nonvolatile semiconductor memory that can improve the number of rewrites (endurance life) by a novel method. is there.
[0010]
[Means for Solving the Problems]
According to the first aspect of the present invention, as a shape of the voltage pulse applied when performing at least one of data writing and erasing, the voltage is sharply increased during the first period up to the tunneling start voltage at the time of startup. The voltage is gradually increased during the second period up to the final rewrite voltage thereafter. That is, in the electrically rewritable nonvolatile semiconductor memory, the voltage waveform at the time of rewriting is controlled, and the voltage from the time when the tunneling starts to the time when the tunneling starts to the floating gate electrode until the final rewriting voltage is reached is controlled. Reduce the rate (reduce the rate of voltage rise). Thereby, the intensity of the electric field applied to the tunnel film at the time of tunneling can be reduced, and the number of rewritable times (endurance life) can be improved.
[0011]
According to the second aspect, the voltage is increased at a constant gradient of a linear function in the second period, or the time differential value is gradually increased in the second period. The voltage may be increased so as to increase, or a plurality of different voltage increasing characteristics which are continuous within the second period as described in claim 4. The plurality of voltage rising characteristics in the period may have different slopes in a linear function.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
(First Embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
[0013]
In this embodiment, the present invention is embodied in an EEPROM. FIG. 1 is a longitudinal sectional view of a memory cell portion in an EEPROM. The memory cell includes a memory cell transistor having a floating gate and a selection transistor.
[0014]
An N ⁺ -type source region 2, an N ⁺ -type region 3, and an N ⁺ -type drain region 4 are formed in a surface layer portion of a P-type single-crystal silicon substrate 1 as a semiconductor substrate so as to be separated from each other. The N ⁺ type region 3 extends over the memory cell transistor portion and the selection transistor portion, and serves as a drain region in the memory cell transistor portion and a source region in the selection transistor portion.
[0015]
On the other hand, in the memory cell transistor portion, a floating gate electrode (floating gate electrode) 7 is arranged on P-type single crystal silicon substrate 1 with a gate oxide film 5 interposed therebetween. The gate oxide film 5 is locally thinned to about 10 nm on the drain region, so that the floating gate electrode 7 is arranged via the tunnel oxide film (tunnel insulating film) 6. On the floating gate electrode 7, a control gate electrode (control gate electrode) 9 is arranged via a silicon oxide film 8 as a gate interlayer insulating film.
[0016]
In the select transistor section, a select gate electrode 11 is formed on the substrate 1 between the drain region 4 and the source region 3 via a silicon oxide film (gate oxide film) 10. Then, the drain of the selection transistor is connected to the bit line BL, and the gate is connected to the word line WL.
[0017]
FIG. 2 shows a cell array and its peripheral circuits.
2, a large number of memory cells 100 are provided vertically and horizontally to form a cell array. The word lines WL0, WL1, WL2,... Of each cell are connected to the row decoder 15. The bit lines BL0, BL1,... Of each cell are connected to the column decoder 16. The write circuit 17 applies a predetermined voltage to the word lines WL0, WL1, WL2,. Write circuit 18 applies a predetermined voltage to bit lines BL0, BL1,... Via switching circuit 19 and column decoder 16. Further, the writing circuit 18 applies a predetermined voltage to a desired control gate electrode via the switching circuit 19. By applying these voltages, a data rewriting operation is performed as follows.
[0018]
When erasing data, a high voltage Vpp (specifically, 18 volts) is applied to the select gate electrode 11 of the select transistor in FIG. 1 and the drain region 4 is set to the ground potential. High voltage Vpp (specifically, 18 volts) is applied to control gate electrode 9. Then, the selection transistor is turned on, and electrons are injected from the drain to the floating gate through the tunnel oxide film 6 between the floating gate and the drain in the memory cell transistor. Thereby, the threshold voltage of the memory cell transistor increases.
[0019]
When writing data, the control gate electrode 9 in the memory cell transistor is set to the ground potential, and the high voltage Vpp (specifically, 18 volts) is applied to the select gate electrode 11 and the drain region 4 in the select transistor. Is applied. Then, the selection transistor is turned on, a high voltage is applied to the drain of the memory cell transistor, and electrons are extracted from the floating gate electrode 7 to the drain. Thus, the threshold voltage of the memory cell transistor decreases.
[0020]
As described above, electrons are injected / emitted from the buried impurity diffusion region (BN layer) 3 formed in the surface layer portion of the silicon substrate 1 as a semiconductor substrate to the floating gate electrode 7 via the tunnel oxide film 6. In a broad sense, electrons are injected / emitted into / from the floating gate electrode 7 via a tunnel oxide film 6 disposed between the silicon substrate 1 and the floating gate electrode 7.
[0021]
Reading is performed as follows. The control gate electrode 9 of the memory cell transistor is set to a high voltage, and the gate (word line) and drain (bit line) of the selection transistor are set to a high voltage. At this time, the presence or absence of the bit line current is determined by the sense amplifier 20 in FIG. When a current flows through the bit line, the bit becomes "1", and when no current flows, it becomes "0".
[0022]
In the present embodiment, the output voltages of the write circuits 17 and 18 in FIG. 2 have a pulse shape as shown in FIG. That is, in FIG. 3, as the shape of the voltage pulse applied when performing data writing and erasing, the first periods trel and trw1 up to the tunneling start voltages Vtne and Vtnw (for example, 9.5 volts) at startup are steep. The voltage is gradually increased during the second period tr2, trw2 until the final rewrite voltage Vpp. More specifically, in the second periods tr2 and trw2, the voltage is increased with a constant gradient of a linear function.
[0023]
This is for the following reason.
As shown in FIG. 4, it is assumed that two capacitors are connected in series between a control gate electrode and a drain region in a memory cell transistor, and that a diode is connected in parallel to a lower capacitor. Then, as shown in FIG. 5, a pulse signal having a rise time to 18 volts of 100 μs, 200 μs, and 1 ms is applied to the control gate electrode. FIG. 6 shows a simulation result of the voltage V2 applied to the lower capacitor (capacitor made of the tunnel oxide film) at this time in FIG.
[0024]
From FIG. 6, the electric field strength at the time of rewriting is analyzed. The electric field strength of the tunnel film (corresponding to the vertical axis in FIG. 6) increases when a pulse voltage rises at the time of writing (or at the time of erasing where electrons are injected) where electrons are extracted from the floating gate. When the current becomes constant, almost no current flows.
[0025]
This means that almost all electrons move when the rewriting pulse rises as shown in FIG. 7, and that the electric field intensity at this time affects the endurance life. Therefore, the key to improving the endurance life is how to suppress the electric field intensity when the tunnel current is flowing. Also, as shown in FIG. 6, it can be seen that the electric field strength (corresponding to the vertical axis in FIG. 6) of the tunnel film becomes lower as the rise time is longer, that is, as the slew rate (slope) is smaller.
[0026]
By the way, as a general theory, an electric field strength of about 8 MV / cm or more is required for a tunnel current sufficient to shift the threshold voltage Vt of the cell to start flowing. Therefore, even if the rising waveform is sharp, the tunnel current does not flow until the electric field strength reaches this level, so that the damage to the tunnel film is much less than that when the tunnel current flows.
[0027]
Therefore, as shown in FIG. 3, the rising shape of the pulse waveform at the time of rewriting the control gate voltage Vcg, the select transistor drain voltage Vseld, and the select transistor gate voltage Vselg is a rising period (tre2, In trw2), control is performed so that the voltage rises more slowly than the rising period (tre1, trw1) before the voltage at which tunneling occurs. By doing so, damage to the tunnel film can be suppressed, and the endurance life can be improved.
[0028]
In other words, by shortening the rising period (tre1, trw1) before the voltage at which tunneling occurs, the rewriting time can be shortened as compared with the conventional method when the same damage occurs as in the conventional rewriting method (total time). Rewriting time can be shortened). Conversely, if the total rewriting time is constant, the voltage can be increased more slowly.
[0029]
As described above, as the shape of the voltage pulse applied at the time of performing data writing and erasing, the first periods trel and trw1 up to the tunneling start voltages Vtne and Vtnw at the time of rising are sharply increased. In the second period tr2, trw2 up to the final rewrite voltage Vpp, the voltage is gradually increased. That is, in the electrically rewritable EEPROM, the voltage waveform at the time of rewriting is controlled, and the voltage from the start of the tunneling to the final rewriting voltage Vpp from the voltages Vtne and Vtnw until the tunneling starts to the floating gate electrode. Reduced slew rate (reduced voltage rise rate). Thereby, the intensity of the electric field applied to the tunnel film at the time of tunneling can be reduced, and the number of rewritable times (endurance life) can be improved.
[0030]
That is, when electrons pass through the tunnel film at the time of writing / erasing, in order to suppress the electric field intensity applied to the tunnel film as much as possible during the limited rise time, particularly, the rising of the rewriting pulse through which the electrons pass through the tunnel film. By controlling the rising waveform at the time, the endurance life can be improved.
[0031]
Although the shape of the voltage pulse applied when performing data writing and erasing is defined, the shape of the voltage pulse applied when performing data writing or erasing may be defined as described above. That is, in a broad sense, the shape of the voltage pulse applied when performing at least one of data writing and erasing may be defined as the shape described above.
(Second embodiment)
Next, a second embodiment will be described focusing on differences from the first embodiment.
[0032]
Instead of FIG. 3, in the present embodiment, the waveform at the time of rewriting shown in FIG. 8 is used.
In FIG. 3, the voltage is increased at a constant gradient of a linear function. However, in FIG. 8, the voltage increase rate is initially small in the second periods tr2 and trw2, and is gradually increased thereafter. That is, as shown in FIG. 9, the voltage is increased so that the time differential value (ΔV / Δt) gradually increases. As described above, the rising waveforms of the control gate voltage Vcg for controlling the electric field strength of the tunnel film and the drain voltage Vsel of the selection transistor are reduced at the beginning of the tunneling, and gradually increased thereafter.
[0033]
As a result, the voltage (electric field applied to the tunnel film) applied to the tunnel film at the time of rewriting increases near the middle of the rising period (see FIG. 8), but the electric field strength near the middle can be reduced.
[0034]
In FIG. 8, the select transistor gate voltage Vselg for determining whether rewriting is necessary is not made to have a waveform such as the control gate voltage Vcg or the select transistor drain voltage Vseld. This may be the same.
(Third embodiment)
Next, a third embodiment will be described focusing on differences from the first embodiment.
[0035]
Instead of FIG. 3, in the present embodiment, the waveform at the time of rewriting shown in FIG. 10 is used. In FIG. 3, the voltage is increased at a constant gradient of a linear function. However, in FIG. 10, the voltage has three different voltage rising characteristics that are continuous in the second periods tr2 and trw2 (a plurality of different voltage rising characteristics are continuous). It has a voltage rise characteristic). More specifically, three voltage rising characteristics (characteristics in the periods ta, tb, and tc) in the second periods tr2 and trw2 have different slopes in a linear function.
[0036]
More specifically, as the rising waveforms of the control gate voltage Vcg and the select transistor drain voltage Vseld, the second periods tr2 and trw2 are divided into three periods ta, tb and tc, the first period ta being sharp and the next period tb being steep. Is made gradual, and sharp during the last period tc. That is, the slew rate (rising speed) is reduced during the period tb during the rising of the final rewrite voltage Vpp, and is increased during the rising start period ta and the ending period tc.
[0037]
Thereby, the electric field intensity applied to the tunnel film during the rise of the final rewrite voltage Vpp can be further suppressed as compared with FIG. Also, in FIG. 10, similar control to the select transistor gate voltage Vselg is not necessarily required as in the second embodiment.
[0038]
In each of the embodiments described above, the example of the EEPROM is shown, but the invention may be applied to a flash memory.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of an EEPROM according to an embodiment.
FIG. 2 is a diagram showing an electrical configuration of a cell array and peripheral circuits.
FIG. 3 is a diagram showing a pulse waveform according to the first embodiment.
FIG. 4 is an equivalent circuit between a substrate and a control gate.
FIG. 5 is a waveform chart applied to a control gate.
FIG. 6 is a diagram showing the time dependence of the voltage applied to the tunnel film.
FIG. 7 is a diagram illustrating movement of electrons.
FIG. 8 is a diagram showing a pulse waveform according to the second embodiment.
FIG. 9 is a diagram for explaining waveforms.
FIG. 10 is a diagram showing a pulse waveform according to the third embodiment.
FIG. 11 is a diagram showing a relationship between an electric field intensity and a breakdown charge amount.
FIG. 12 is a diagram showing a pulse waveform for explaining a conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... P type single crystal silicon substrate, 2 ... Source region, 3 ... N ⁺ type region, 4 ... Drain region, 5 ... Silicon oxide film, 6 ... Tunnel oxide film, 7 ... Floating gate electrode, 8 ... Gate interlayer insulating film (Silicon oxide film), 9: control gate electrode, 10: silicon oxide film, 11: select gate electrode.

Claims (5)

In a nonvolatile semiconductor memory for injecting / emitting electrons to / from a floating gate electrode (7) via a tunnel insulating film (6) disposed between a semiconductor substrate (1) and a floating gate electrode (7),
As a shape of a voltage pulse applied when at least one of data writing and erasing is performed, the voltage is sharply increased in a first period (tre1, trw1) until a tunneling start voltage at the time of startup, and thereafter, the voltage is increased. A data rewriting method for a nonvolatile semiconductor memory, wherein the voltage is gradually increased in a second period (tre2, trw2) until a final rewriting voltage. 2. The data rewriting method according to claim 1, wherein in the second period (tre2, trw2), the voltage is increased at a constant gradient of a linear function. 2. The method according to claim 1, wherein the voltage is increased in the second period (tre2, trw2) so that the time differential value gradually increases. 2. The data rewriting method for a nonvolatile semiconductor memory according to claim 1, wherein the method has a plurality of different voltage rising characteristics that are continuous in the second period (tre2, trw2). 5. The data rewriting method according to claim 4, wherein the plurality of voltage rising characteristics in the second period (tre2, trw2) have different slopes in a linear function.

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