JP2004153053A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of contamination from the edge of a wafer in the manufacturing process of a semiconductor integrated circuit device. <P>SOLUTION: A thin film TF1 is deposited on the wafer 1. After patterning the thin film TF1 by etching with a photoresist film as a mask, the uneven thin film TF1 which is easily stripped from the wafer 1 at the edge of the wafer 1 is removed by grinding, dry etching or wet etching using a plurality of grinding drums, e.g. Thus, the thin film TF1 is prevented from being stripped out of the edge of the wafer 1 to be the contamination and stuck to the wafer 1 again. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology that is effective when applied to a manufacturing process of a semiconductor integrated circuit device including processing of a semiconductor wafer.
[0002]
[Prior art]
For example, the yield of a semiconductor integrated circuit device such as a DRAM (Dynamic Random Access Memory) is greatly affected by foreign substances adhering to a semiconductor wafer (hereinafter simply referred to as a wafer) used for manufacturing the semiconductor integrated circuit device. In particular, the foreign matter is often generated from the edge of the wafer. In order to prevent such foreign matter from being generated from the edge of the wafer, a thin film is formed on the wafer and, during a process of forming a wiring pattern and the like, the thin film remaining on the edge of the main surface (element formation surface) of the wafer is removed. There is a means for removing by etching or polishing (for example, see Patent Documents 1 and 2).
[0003]
In order to prevent the organic film (including the photoresist film) applied on the wafer from peeling off at the edge of the wafer and forming foreign matter, for example, when the positioning member and the wafer come into contact with each other, , There is a means for removing the organic film using a solvent or the like (for example, see Patent Document 3, Patent Document 4, Patent Document 5, and Patent Document 6).
[0004]
[Patent Document 1]
JP 2000-68273 A
[0005]
[Patent Document 2]
JP-A-2002-110593
[0006]
[Patent Document 3]
JP-A-8-195370
[0007]
[Patent Document 4]
JP-A-9-106980
[0008]
[Patent Document 5]
JP-A-10-275772
[0009]
[Patent Document 6]
JP 2001-196291 A
[0010]
[Problems to be solved by the invention]
The present inventors are studying a technique for preventing the generation of foreign matter from the edge of a wafer. In the meantime, the present inventors have studied factors that cause foreign matter to be generated from the edge of the wafer.
[0011]
One of the factors that cause foreign matter to be generated from the edge of the wafer is, for example, peeling of the thin film at the edge of the wafer. For example, when wiring is formed from the thin film, a thin film is deposited on a wafer, a photoresist film patterned by photolithography is formed on the thin film, and etching is performed using the photoresist film as a mask. When various processes are performed with the photoresist film left on the edge of the wafer, for example, a transfer robot used to transfer the wafer comes into contact with the photoresist film at the edge of the wafer, and the contact causes There is a problem that the photoresist film is shaved and the shaved photoresist film itself becomes a factor of foreign matter.
[0012]
Then, after applying a photoresist film on the main surface of the wafer, the wafer is rotated, and an organic solvent is sprayed on the wafer from the back side of the wafer, so that the organic solvent is not applied to the main surface (element formation surface) of the wafer. In the meantime, a method of dissolving and removing only the photoresist film on the edge of the wafer with an organic solvent can be considered. However, since the organic solvent is sprayed from the back surface side of the wafer, the photoresist film viewed from the main surface side of the wafer has an intricate contour after the removal processing. When the thin film is etched using the photoresist film having the intricate contour as a mask, the thin film is etched at the edge of the wafer in a pattern having the intricate contour, and the thin film remaining near the edge of the wafer after etching is removed from the wafer. There is a problem that the shape is easily peeled.
[0013]
In addition, the edge of the wafer is a portion that is likely to come into contact with various manufacturing devices or the like during the manufacturing process of the semiconductor integrated circuit device, and is, for example, a portion that comes into contact with the transfer robot as described above. Also, in a post-cleaning process at the time of CMP (Chemical Mechanical Polishing), when the rotation of the wafer is performed by a rotating roller, the edge of the wafer is repeatedly pressed against the roller, so that the thin film formed at the edge of the wafer is There is a problem that it becomes shaved foreign matter.
[0014]
When a wafer is placed on a stage in a film forming apparatus and a thin film is formed on the main surface of the wafer using, for example, a single-wafer processing type film forming apparatus, the thin film is formed from the main surface to the edge of the wafer. Is formed, but the thin film is not formed on the back surface of the wafer. Therefore, when the adhesiveness between the thin film and the wafer is not good, there is a problem that the thin film peels off from the edge of the wafer and becomes foreign matter. In the single-wafer processing process, there are many processes in which a film is not formed on the back surface except for an unavoidable film formation. In this case, the terminal end of the thin film is located at the edge of the wafer, and the problem of foreign matter generation due to peeling is remarkable. Become.
[0015]
An object of the present invention is to provide a technique capable of preventing generation of foreign matter from an edge of a wafer in a manufacturing process of a semiconductor integrated circuit device.
[0016]
Another object of the present invention is to provide a technique suitable for preventing generation of foreign matter from an edge of a wafer in a single wafer processing process.
[0017]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0018]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0019]
That is, the present invention provides a step of forming a single-layer or laminated first thin film on a semiconductor wafer, and forming irregularities on the surface of the first thin film at the edge of the semiconductor wafer with respect to the semiconductor wafer. Performing a first process, and removing the first thin film at the edge of the semiconductor wafer.
[0020]
The present invention also includes a step of forming a single-layer or laminated first thin film on a semiconductor wafer by single-wafer processing, and a step of removing the first thin film at an edge of the semiconductor wafer.
[0021]
The present invention also provides a step of forming a single-layer or laminated first thin film on a semiconductor wafer, and forming an unevenness on the surface of the first thin film at an edge of the semiconductor wafer with respect to the semiconductor wafer. Performing a first process, removing the first thin film at the edge of the semiconductor wafer, forming a single-layer or stacked second thin film on the semiconductor wafer including the edge, Forming a third thin film on the second thin film, wherein the second thin film has relatively better adhesion with the semiconductor wafer than the third thin film, and the third thin film has a good adhesion. This is to select a thin film to be formed.
[0022]
The present invention also provides a step of forming a single-layer or laminated first thin film on a semiconductor wafer, and forming an unevenness on the surface of the first thin film at an edge of the semiconductor wafer with respect to the semiconductor wafer. Performing a first process, polishing the first thin film including the irregularities at the edge of the semiconductor wafer, and leaving the first thin film having a first thickness at the edge of the semiconductor wafer. Forming a third thin film on one thin film.
[0023]
The present invention also provides a step of forming a single-layer or laminated first thin film on a semiconductor wafer, a step of forming a masking layer covering a main surface and an edge of the semiconductor wafer on the first thin film, Patterning a masking layer so as to remain on the edge of the semiconductor wafer; and etching the first thin film using the masking layer as a mask.
[0024]
The present invention also provides a step of forming a single-layer or laminated first thin film on a semiconductor wafer, a step of forming a masking layer on the first thin film, and removing the masking layer at an edge of the semiconductor wafer. Performing the step of: patterning the masking layer; and etching the first thin film using the masking layer as a mask.
[0025]
The present invention also provides a step of forming a single-layer or laminated first thin film on a semiconductor wafer, and performing a first treatment on the semiconductor wafer, and then forming a first film on the first thin film at an edge of the semiconductor wafer. Inspecting the presence or absence of the occurrence of the first defect, and if the first defect is detected, performing the first processing on the semiconductor wafer and then performing the first processing on the semiconductor wafer. Is added.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Before describing the present invention in detail, the meanings of terms in the present application will be described as follows.
[0027]
The element formation surface is a main surface of the wafer, on which a device pattern corresponding to a plurality of chip regions is formed by a photolithography technique.
[0028]
The edge of the wafer refers to a region at an outer peripheral portion of the wafer that is angled with respect to the flat surface of the main surface and the back surface of the wafer.
[0029]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0030]
(Embodiment 1)
The semiconductor integrated circuit device according to the first embodiment has, for example, an n-channel MISFET, a p-channel MISFET, and wirings electrically connected thereto on the main surface of a wafer.
[0031]
1 to 3 are main-portion cross-sectional views of a wafer during a manufacturing process of the semiconductor integrated circuit device according to the first embodiment.
[0032]
The wafer 1 according to the first embodiment shown in FIG. 1 has a diameter of, for example, about 300 mm, and has a chip forming region having a flat surface and edges formed at an angle with respect to the main surface and the flat surface on the back surface. And On such a main surface of the wafer 1, a thin film (first thin film) TF1 is deposited by a single-wafer processing CVD method or a sputtering method. When depositing the thin film TF1 by single-wafer processing, for example, the wafer 1 is placed on a stage in a film forming apparatus, and the wafer 1 is held on the stage by electrostatically attracting the back surface of the wafer 1 to the stage. The film forming process is performed while performing. Therefore, the thin film TF1 is formed from the main surface of the wafer 1 to the edge, and is not formed on the back surface of the wafer 1. In the first embodiment, description will be given by taking as an example a case where the thin film TF1 is a single-layer film of a silicon oxide film or an interlayer insulating film formed of a stacked film of a silicon oxide film and a silicon nitride film.
[0033]
Next, a photoresist film (masking layer) is applied on the thin film TF1. When various processes are performed while the photoresist film is left on the edge of the wafer 1, for example, a transfer robot used to transfer the wafer 1 comes into contact with the photoresist film at the edge of the wafer 1, The contact removes the photoresist film, and the removed photoresist film becomes a foreign substance. When such foreign matter adheres to, for example, a conductive film forming a wiring, there is a possibility that a failure such as a short circuit or an opening may occur in the wiring. Therefore, for example, by rotating the wafer 1 with the main surface facing upward and spraying the organic solvent onto the wafer 1 from the back surface of the wafer 1, the photoresist on the edge of the wafer 1 is prevented while preventing the organic solvent from being applied to the main surface. Only the film is removed by dissolving it with an organic solvent. Here, since the organic solvent is sprayed from the back surface side of the wafer 1, after the photoresist film at the edge of the wafer 1 is removed, the photoresist film viewed from the main surface side of the wafer 1 has a complicated contour line. Will have. When such a photoresist film is patterned by a photolithography technique and the thin film TF1 is patterned by etching (first processing) using the patterned photoresist film as a mask, the thin film TF1 at the edge of the wafer 1 is peeled off from the wafer 1. It becomes a thin film TF1A having an uneven shape that is easy to be formed (see FIG. 2). What is formed on the thin film TF1 by this patterning is, for example, a hole or a groove for forming a wiring.
[0034]
Next, as shown in FIG. 3, the uneven thin film TF1A at the edge of the wafer 1 is removed. If the subsequent steps are continued in a state where the uneven thin film TF1A is left, the thin film TF1A peels off and adheres again to the wafer 1, thereby lowering the yield of the semiconductor integrated circuit device of the first embodiment. However, such a problem can be prevented by removing the uneven thin film TF1A at the edge of the wafer 1 as in the first embodiment. In the step of removing the thin film TF1A at the edge of the wafer 1, the surface S at the end of the thin film TF1 has an angle of about 5 ° to 75 ° with respect to the main surface (element formation surface) of the wafer 1 after the removing step. So that it sticks. Thereby, when another thin film is deposited on the wafer 1 in a later step, it is possible to prevent the coverage of the thin film from decreasing from the surface S to the surface of the wafer 1.
[0035]
The step of removing the uneven thin film TF1A can be performed by, for example, polishing using a plurality of polishing drums, and three polishing drums (first polishing means) DRM1 to DRM3 as shown in FIG. The case where it is used can be exemplified. By using a plurality of polishing drums, it is easy to polish the entire area of the edge of the wafer 1, and the time required for polishing can be reduced. Each of the polishing drums DRM1 to DRM3 has a soft polishing pad wound around its outer periphery, and performs polishing by supplying a slurry such as colloidal silica, cerium oxide, or alumina oxide to the polishing surface during polishing.
[0036]
5 to 7 are cross-sectional views taken along line AA (see FIG. 4), line BB (see FIG. 4), and line CC (see FIG. 4), respectively.
[0037]
The shape of the edge of the wafer 1 is, for example, a so-called full-round type in which the edge has an arc shape, or a so-called flat tip type in which the edge of the edge is flat. In the first embodiment, the angles θ1 to θ3 at which the polishing drums DRM1 to DRM3 contact the wafer 1 can be appropriately set according to the shape of the edge of the wafer 1. Further, the angles θ1 to θ3 can be appropriately set according to the shape of the uneven thin film TF1A to be removed. That is, by using the polishing drums DRM1 to DRM3 of the first embodiment, it is possible to remove the uneven thin film TF1A over the entire edge shape of various wafers 1.
[0038]
In addition, the polishing drums DRM1 to DRM3 can change the polishing rate by appropriately setting the number, the number of rotations, and the pressure in contact with the wafer 1. That is, the optimum polishing speed of the polishing drums DRM1 to DRM3 can be set according to the edge shape of the wafer 1 described above according to the specification of the wafer 1 and the shape of the uneven thin film TF1A. For example, as shown in FIG. 8, when the thin film TF1 is relatively formed only on the main surface (element formation surface) side of the wafer 1, the uneven thin film TF1A at the edge of the wafer 1 1 exists on the main surface (element formation surface) side. Therefore, it can be exemplified that θ1 = 150 °, θ2 = 120 °, and θ3 = 60 °. At this time, if the thin film to be removed can be removed only by the polishing drums DRM1 and DRM2, the polishing drum DRM3 can be omitted. In addition, the polishing may be performed by four or more polishing drums by adding another polishing drum to the three polishing drums DRM1 to DRM3. Also in this case, the angle at which each polishing drum comes into contact with the wafer 1, the rotation speed of each polishing drum, and the pressure at which each polishing drum comes into contact with the wafer 1 are affected by the shape of the edge of the wafer 1 and the shape of the uneven thin film TF1A. It is the same that it can be set accordingly.
[0039]
On the other hand, as shown in FIG. 9, when the thin film TF1 is formed from the main surface (element formation surface) to the vicinity of the back surface of the wafer 1, the uneven thin film TF1A is present over the entire edge of the wafer 1. Will be. Therefore, it can be exemplified that θ1 = 135 °, θ2 = 90 °, and θ3 = 45 °. By setting the angles θ1 to θ3 in this manner, it is possible to remove the thin film TF1A at the edge of the wafer 1 in a short time.
[0040]
Instead of using the polishing drums DRM1 to DRM3, removal of the uneven thin film TF1A at the edge of the wafer 1 by polishing using polishing pads (first polishing means) PAD1 to PAD3 as shown in FIGS. May be performed. FIG. 11A and FIG. 11B are cross-sectional views taken along lines DD and EE in FIG. 10, respectively. The polishing pads PAD1 to PAD3 each have a soft polishing pad wound on the surface in contact with the wafer 1, and the polishing is performed by supplying a slurry such as colloidal silica, cerium oxide, or alumina oxide to the polishing surface during polishing. Do.
[0041]
As shown in FIG. 11A, the polishing pad PAD1 relatively polishes the lower surface (back surface) of the edge of the wafer 1, and the polishing pad PAD2 relatively polishes the upper surface (element forming surface) of the edge of the wafer 1. Polished. Also, as shown in FIG. 11B, the polishing pad PAD3 relatively polishes the center of the edge of the wafer 1. During the polishing, the thin film TF1 can be removed over the entire edge of the wafer 1 by rotating the wafer 1 at a high speed. Further, during polishing, the polishing pads PAD1 to PAD3 are reciprocated while being in contact with the wafer 1, so that it is possible to prevent only a specific portion of the polishing surface of the polishing pads PAD1 to PAD3 from being worn away. .
[0042]
In the first embodiment, the method of removing the uneven thin film TF1A at the edge of the wafer 1 using the polishing drums DRM1 to DRM3 or the polishing pads PAD1 to PAD3 has been described. The thin film TF1A may be removed by a dry etching method or a wet etching method instead of the pads PAD1 to PAD3.
[0043]
In the above first embodiment, the case where the thin film TF1A is easily etched at the edge of the wafer 1 when the thin film TF1 is etched using the photoresist film as a mask has been described. An uneven thin film TF1A may occur at the edge of the wafer 1. For example, when there is a step of carrying the robot 1 (first processing) after the deposition of the thin film TF1, the wafer 1 is held (chucking) at the edge. That is, the wafer 1 comes into contact with the transfer robot at the edge of the wafer 1, and there is a concern that the uneven thin film TF <b> 1 </ b> A easily peels off at the edge of the wafer 1. Further, during the transfer of the wafer 1, the edge of the wafer 1 is a portion that is likely to come into contact with various manufacturing apparatuses and the like, and thus the uneven thin film TF1A that is easily peeled off at the edge of the wafer 1 due to the contact during the transfer occurs. It is also a concern. Further, when the surface of the thin film TF1 is flattened (first processing) by the CMP (Chemical Mechanical Polishing) method after the deposition of the thin film TF1, the wafer 1 is prevented from coming off the carrier head in the CMP apparatus during the CMP. And the edge of the wafer 1 comes into contact. Further, when the rotation of the wafer in the post-cleaning step at the time of the CMP is performed by the rotating roller, the edge of the wafer repeatedly comes into pressure contact with the roller. Due to this contact, there is a concern that an uneven thin film TF1A that is easily peeled off at the edge of the wafer 1 is generated.
[0044]
Therefore, even after the step in which the edge of the wafer 1 makes mechanical contact as described above, the uneven thin film TF1A at the edge of the wafer 1 is similarly removed, whereby the thin film TF1A peels off and the wafer 1 It is possible to prevent the yield of the semiconductor integrated circuit device according to the first embodiment from being reduced due to reattachment to the semiconductor device.
[0045]
In the above-described embodiment, the case where the thin film TF1 is an interlayer insulating film has been described as an example. However, even when the thin film TF1 is a metal film serving as a wiring material, the thin film TF1 is Therefore, there is a concern that the thin film TF1A may be easily peeled from the thin film TF1A. Therefore, even when the thin film TF1 is a metal film serving as a wiring material, the unevenness of the thin film TF1A at the edge of the wafer 1 is similarly removed, so that the thin film TF1A peels off and adheres to the wafer 1 again. Thus, it is possible to prevent the yield of the semiconductor integrated circuit device according to the first embodiment from lowering.
[0046]
(Embodiment 2)
Next, a manufacturing process of the semiconductor integrated circuit device according to the second embodiment will be described.
[0047]
Also in the second embodiment, the step of depositing the thin film TF1 (see FIGS. 1 to 3) on the main surface of the wafer 1 (see FIGS. This is the same as in the first embodiment.
[0048]
As shown in FIG. 12, when the boundary end KKT of the thin film TF1 is located at the edge of the wafer 1 in a round state, the wafer 1 makes mechanical contact at the edge in a later step. At this time, there is a concern that the thin film TF1 may be separated from the boundary end KKT. Therefore, in the second embodiment, before applying a photoresist film on the thin film TF1, by the same steps and means as those described with reference to FIGS. 3 to 11 in the first embodiment, The thin film TF1 at the edge of the wafer 1 is removed. This can prevent the thin film TF1 from peeling off from the boundary end KKT even when the wafer 1 makes mechanical contact at the edge in a later step. As a result, it is possible to prevent the yield of the semiconductor integrated circuit device according to the first embodiment from lowering due to the foreign matter generated from the edge of the wafer 1 due to the peeling of the thin film TF1 adhering to the wafer 1.
[0049]
Further, even when the thin film TF1 is etched using the same photoresist film as the photoresist film described in the first embodiment as a mask, the uneven thin film TF1A (see FIG. 2) which is easily peeled off at the edge of the wafer 1 is formed. This can be prevented. That is, it is possible to prevent the thin film TF1A from being peeled off from the edge of the wafer 1 as described in the first embodiment.
[0050]
According to the second embodiment as described above, the same effect as in the first embodiment can be obtained. Further, by applying the second embodiment, especially when the thin film TF1 is made of a material (for example, W (tungsten)) having low adhesion between the thin film TF1 and the wafer 1 and easily peeling from the edge of the wafer 1 An effective effect can be obtained.
[0051]
(Embodiment 3)
Next, a manufacturing process of the semiconductor integrated circuit device according to the third embodiment will be described.
[0052]
The manufacturing process of the semiconductor integrated circuit device according to the third embodiment is the same as the process described in the first embodiment with reference to FIGS.
[0053]
In the case where the thin film TF1 is, for example, a single-layer film of a silicon oxide film or an interlayer insulating film composed of a stacked film of a silicon oxide film and a silicon nitride film, the steps described in Embodiment 1 with reference to FIG. After that, a conductive film for filling the hole or groove for forming a wiring formed in the thin film TF1 is deposited on the wafer 1 by a sputtering method or a CVD method. If the conductive film is, for example, a W film or an Al (aluminum) film serving as a main conductive layer of a wiring (including a barrier metal film if a lower layer is required), a lower layer is formed. Since the adhesion of the conductive film to the wafer 1 is not good, there is a concern that the conductive film may be peeled off from the edge of the wafer 1. Therefore, there is a concern that the yield of the semiconductor integrated circuit device according to the first embodiment may be reduced due to the peeled-off conductive film adhering to the wafer 1 as foreign matter.
[0054]
Therefore, as shown in FIG. 13, in the third embodiment, after removing the thin film TF1 at the edge of the wafer 1, a conductive film such as a W film or an Al film serving as a main conductive layer of the wiring is replaced with the wafer 1. Before being deposited on the thin film, a thin film (second thin film) TF2A having good adhesion to the wafer 1 and good adhesion to the conductive film as compared with the conductive film is edge-formed by a CVD method or the like. Is deposited on the wafer 1 containing Here, a silicon oxide film deposited by a CVD method can be exemplified as the thin film TF2A.
[0055]
Subsequently, as shown in FIG. 14, a photoresist film (second masking layer) RESI1 is applied on the wafer 1 by a spin coating method. When the photoresist film RESI1 is applied, the edge portion of the wafer 1 is sufficiently covered with the photoresist film RESI1, for example, by adjusting the rotation speed at which the wafer 1 is rotated. Next, the photoresist film RESI1 applied to the back surface of the wafer 1 is removed, for example, by spraying an organic solvent onto the back surface of the wafer 1 while rotating the wafer 1. At this time, the organic solvent is prevented from reaching the edge of the wafer 1 by adjusting the jetting strength of the organic solvent and the rotation speed at which the wafer 1 is rotated. Thereby, the photoresist film RESI1 is left at the edge of the wafer 1. When the wafer 1 is placed on a stage in an etching apparatus, for example, the back surface comes into contact with the stage. Therefore, when the photoresist film RESI1 remains on the back surface of the wafer 1, the photoresist film RESI1 is peeled off from the back surface of the wafer 1 and remains on the stage, and becomes a foreign substance on the wafer 1 or another wafer. There is a concern that the adhesion may contaminate the wafer 1 or another wafer. Therefore, such a problem can be prevented beforehand by removing the photoresist film RESI1 applied to the back surface of the wafer 1 in advance.
[0056]
Next, as shown in FIG. 15, the photoresist film RESI1 is patterned by photolithography. At this time, patterning is performed so that the photoresist film RESI1 remains sufficiently at the edge of the wafer 1 (so that the photoresist film RESI1 covers the edge of the wafer 1).
[0057]
Next, as shown in FIG. 16, by etching the thin films TF2A and TF1 using the patterned photoresist film RESI1 as a mask, a groove portion for wiring formation (including a hole reaching a lower wiring or element) MZ. To form At this time, since the thin film TF2A is sufficiently covered with the photoresist film RESI1 at the edge of the wafer 1, the thin film TF2A at the edge of the wafer 1 after the etching process has an uneven shape that is easily peeled from the wafer 1. It can be prevented from becoming a thin film. That is, in the subsequent process, the problem that the yield of the semiconductor integrated circuit device of the third embodiment is reduced due to the thin film TF2A peeling off from the edge of the wafer 1 and attaching again to the wafer 1 is prevented. be able to.
[0058]
Next, as shown in FIG. 17, after removing the photoresist film RESI1, as shown in FIG. 18, a conductive film (third thin film) made of a W film or an Al film or the like filling the trench MZ on the thin film TF2A. Deposit TF2. When the conductive film TF2 is an Al film, the groove MZ is a hole reaching the underlying wiring or element. At this time, on the edge of the wafer 1, a thin film TF2A is formed below the conductive film TF2. As described above, the thin film TF2A has better adhesion to the wafer 1 and better adhesion to the conductive film TF2 than the conductive film TF2. Therefore, it is possible to prevent the conductive film TF2 made of a W film, an Al film, or the like that is easily peeled from the wafer 1 from being peeled off at the edge of the wafer 1. As a result, it is possible to prevent the yield of the semiconductor integrated circuit device according to the third embodiment from being reduced due to the peeled-off conductive film TF2 becoming a foreign substance and adhering to wafer 1.
[0059]
Thereafter, when the conductive film TF2 is a W film, the conductive film TF2 on the thin film TF2A is removed by an etch-back method or a CMP method, and a wiring is formed by leaving the conductive film TF2 in the groove MZ. The semiconductor integrated circuit device according to the third embodiment is manufactured. In the case where the conductive film TF2 is an Al film, a wiring is formed by patterning the conductive film TF2 by etching using a photoresist film patterned by photolithography as a mask. Third, a semiconductor integrated circuit device is manufactured.
[0060]
According to the third embodiment described above, the same effects as those of the first and second embodiments can be obtained.
[0061]
(Embodiment 4)
Next, a manufacturing process of the semiconductor integrated circuit device according to the fourth embodiment will be described.
[0062]
The manufacturing process of the semiconductor integrated circuit device according to the fourth embodiment is the same as the process described in the first embodiment with reference to FIGS. Further, also in the fourth embodiment, description will be given by taking as an example a case where the thin film TF1 is a single-layer film of a silicon oxide film or an interlayer insulating film composed of a stacked film of a silicon oxide film and a silicon nitride film.
[0063]
Thereafter, the uneven thin film TF1A at the edge of the wafer 1 (see FIG. 19) is polished to form a smooth thin film TF1B covering the edge of the wafer 1 (see FIG. 20). The polishing of the thin film TF1A can be performed using, for example, the polishing drums DRM1 to DRM3 (see FIGS. 4 to 7) described in the first embodiment.
[0064]
Subsequently, the thin film TF1 is etched by using the photoresist film patterned by the photolithography technique as a mask, so that the thin film TF1 includes a groove portion for forming a wiring (a hole reaching a lower wiring or an element or the like (not shown)). ) Is formed.
[0065]
After removing the photoresist film, as shown in FIG. 21, a conductive film TF2 made of a W film or an Al film or the like filling the trench is deposited on the thin film TF2A. When the conductive film TF2 is an Al film, the groove becomes a hole reaching a lower wiring or element.
[0066]
At this time, at the edge of the wafer 1, the thin film TF1B is formed below the conductive film TF2. As described in the third embodiment, the thin film TF1B is a silicon oxide film that has better adhesiveness to the wafer 1 and better adhesiveness to the conductive film TF2 than the conductive film TF2. is there. Therefore, it is possible to prevent the conductive film TF2 made of a W film, an Al film, or the like that is easily peeled from the wafer 1 from being peeled off at the edge of the wafer 1. As a result, it is possible to prevent the yield of the semiconductor integrated circuit device according to the fourth embodiment from being reduced due to the peeled conductive film TF2 becoming a foreign substance and adhering to the wafer 1.
[0067]
Thereafter, the semiconductor integrated circuit device according to the fourth embodiment is manufactured through the steps after the steps described in the third embodiment with reference to FIG.
[0068]
According to the above-described fourth embodiment, the same effects as those of the first to third embodiments can be obtained.
[0069]
(Embodiment 5)
Next, a manufacturing process of the semiconductor integrated circuit device according to the fifth embodiment will be described.
[0070]
Also in the fifth embodiment, the step of depositing the thin film TF1 (see FIGS. 1 to 3) on the main surface of the wafer 1 (see FIGS. This is the same as in the first embodiment. Further, in the fifth embodiment, similarly to the first embodiment, the case where the thin film TF1 is a single-layer film of a silicon oxide film or an interlayer insulating film composed of a stacked film of a silicon oxide film and a silicon nitride film is described. The description will be given as an example.
[0071]
After the formation of the thin film TF1, a photoresist film (second masking layer) RESI1 is applied on the wafer 1 as shown in FIG. Subsequently, while the wafer 1 is being rotated, for example, an organic solvent is sprayed onto the photoresist film RESI1 at the edge of the wafer 1 by the nozzle NZL from the main surface (element formation surface) side of the wafer 1. At this time, the area where the organic solvent is sprayed is set to a range of about 0.5 mm to 1.5 mm from the outer peripheral end toward the center from the outer peripheral end, and is set to be substantially constant over the entire outer periphery of the wafer 1. The organic solvent is sprayed. The edge of the wafer 1 is completely included in the region where the organic solvent is sprayed. Since the wafer 1 is rotated during the injection of the organic solvent, it is possible to prevent the injected organic solvent from flowing toward the center of the wafer 1 on which the chips to be formed are formed.
[0072]
The photoresist film RESI1 on the edge of the wafer 1 can be removed by the injection of the organic solvent as described above (see FIG. 23). After the photoresist film RESI1 at the edge of the wafer 1 is removed by the injection of the organic solvent, the photoresist film RESI1 viewed from the main surface side of the wafer 1 has a smooth contour line without intrusion. become.
[0073]
Next, as shown in FIG. 24, the photoresist film RESI1 is patterned by a photolithography technique. Subsequently, as shown in FIG. 25, the thin film TF1 is patterned by etching using the photoresist film RESI1 as a mask. As described above, since the photoresist film RESI1 viewed from the main surface side of the wafer 1 has a smooth contour line without intrusion, the thin film TF1 at the edge of the wafer 1 is removed after the etching process. It is possible to prevent an uneven thin film which is easily peeled from the thin film 1. That is, in the subsequent process, the problem that the yield of the semiconductor integrated circuit device of the fifth embodiment is reduced due to the thin film TF1 peeling from the edge of the wafer 1 and attaching to the wafer 1 again is prevented. be able to. If the etching is performed by dry etching, the thin film TF1 may be left behind at the edge of the wafer 1 as it approaches the rear surface of the wafer 1. By performing such a process, it is possible to prevent defects such as the remaining etch of the thin film TF1.
[0074]
As described above, in the fifth embodiment, the example in which the photoresist film RESI1 at the edge of the wafer 1 is removed by spraying the organic solvent has been described. However, only the photoresist film RESI1 at the edge of the wafer 1 is exposed. Means for removing the photoresist film RESI1 at the edge of the wafer 1 by so-called peripheral exposure processing and development processing may be used. Even in the case of using the peripheral exposure processing and the development processing, the range to be exposed may be, for example, about 0.5 mm to 1.5 mm from the outer peripheral edge of the wafer 1 toward the center.
[0075]
Subsequently, as shown in FIG. 26, after the photoresist film RESI1 on the thin film TF1 is removed, the steps following the steps described with reference to FIG. 5 are manufactured.
[0076]
By the way, the manufacturing process of the semiconductor integrated circuit device according to the fifth embodiment described with reference to FIGS. 22 to 26 is applied to the process described with reference to FIGS. 14 to 17 in the third embodiment. Is also good. According to the experiment performed by the present inventors, even when the steps described with reference to FIGS. 22 to 26 are applied to the steps described with reference to FIGS. In this step, the conductive film TF2 (see FIG. 18) formed on the wafer 1 was prevented from peeling off at the edge of the wafer 1. That is, even when the manufacturing process of the fifth embodiment is applied to the third embodiment, the yield of the semiconductor integrated circuit device due to the thin film TF2A peeling off from the edge of the wafer 1 and attaching again to the wafer 1 Can be prevented.
[0077]
According to the fifth embodiment as described above, the same effects as those of the first to fourth embodiments can be obtained.
[0078]
(Embodiment 6)
Next, a manufacturing process of the semiconductor integrated circuit device according to the sixth embodiment will be described. In the sixth embodiment, for example, the present invention is applied to a method of manufacturing a semiconductor integrated circuit device in which an n-channel MISFET (Metal Insulator Semiconductor Effect Transistor) is formed in a p-type well of a semiconductor substrate (wafer). . The manufacturing process of the semiconductor integrated circuit device according to the sixth embodiment will be described along steps P1 to P11 in the flowchart shown in FIG.
[0079]
28 and 29 are cross-sectional views of main parts of a wafer (semiconductor substrate) 1 according to the sixth embodiment. 29 shows the vicinity of the edge of the wafer 1 in particular, and FIG. 28 shows the vicinity of the main surface (element formation surface) of the wafer 1 in an enlarged manner.
[0080]
On the main surface of the wafer 1, an element isolation groove is formed by embedding a silicon oxide film 8 in the groove 6. An n-channel MISFET Qn is formed in a p-type well 9 formed by ion-implanting an impurity (for example, B (boron)) having a p-type conductivity into the wafer 1.
[0081]
The n-channel type MISFET Qn has a gate electrode 11 formed on the main surface of the wafer 1 via a gate oxide film 10 and n-type semiconductor regions 15 (source, drain) formed on both sides of the gate electrode 11. The cap insulating film 12 and the sidewall spacers 14 are formed on the upper surface and side surfaces of the gate electrode 11.
[0082]
Gate oxide film 10 is formed of a silicon oxide film having a thickness of several nm, and can be formed by, for example, a thermal oxidation method or a thermal CVD method.
[0083]
The gate electrode 11 may be made of, for example, a low-resistance polycrystalline silicon film, and a metal film such as a silicide layer or W may be formed thereover to reduce the resistance.
[0084]
The n-type semiconductor region 15 functions as a source / drain region of the n-channel type MISFET Qn. For example, an impurity having an n-type conductivity such as P (phosphorus) or P (arsenic) is introduced at a high concentration. It is formed by this.
[0085]
On top of the gate electrode 11 and the n-type semiconductor region 15, WSi _x , MoSi _x , TiSi _x , TaSi _x Or CoSi _x For example, a high melting point metal silicide film may be laminated.
[0086]
The cap insulating film 12 and the sidewall spacer 14 can be, for example, a silicon oxide film or a silicon nitride film. When a silicon nitride film is used, the cap insulating film 12 and the sidewall spacer 14 made of the silicon nitride film are used. Using the mask as a mask, a connection hole can be formed in a self-aligned manner in an interlayer insulating film described later.
[0087]
Note that a low-concentration n-type semiconductor region is formed before the sidewall spacers 14 are formed, and a high-concentration n-type semiconductor region is formed after the sidewall spacers 14 are formed, so that a source having an LDD (Lightly Doped Drain) structure is formed. , And a drain region.
[0088]
After the completion of the n-channel type MISFET Qn, for example, a silicon oxide film is deposited on the wafer 1 by a CVD method to form an interlayer insulating film (first thin film) 16 (step P1). Subsequently, after the surface of the interlayer insulating film 16 is flattened by polishing (first processing) by a CMP method (step P2), the surface of the interlayer insulating film 16 in the flat chip formation region on the main surface of the wafer 1 is formed. An inspection is performed to determine whether or not a so-called killer defect such as a foreign substance or a minute scratch is present, and whether or not the interlayer insulating film 16 is an irregular thin film (first defect) easily peeled at the edge of the wafer 1. An inspection is performed (step P3). At this time, as shown in FIG. 29, a bright field inspection (first inspection step) in which a flat chip formation area (bright field area) on the main surface of the wafer 1 is illuminated using bright field illumination (coaxial incident illumination). In addition, killer defects on the surface of the interlayer insulating film 16 can be effectively detected. On the other hand, the dark-field inspection (second inspection step) in which the edge (dark-field region) of the wafer 1 is illuminated using the dark-field illumination has the effect that the interlayer insulating film 16 is formed into an uneven thin film that is easily peeled. Can be detected. In FIG. 29, members other than the wafer 1 and the interlayer insulating film 16 are not shown for easy understanding of the positional relationship between members and regions. If the inspection in the process P3 detects that the interlayer insulating film 16 is formed into a concave and convex thin film at the edge of the wafer 1, the semiconductor integrated circuit device according to the sixth embodiment is manufactured. In the step, after the step of flattening the surface of the interlayer insulating film 16 in the step P2, a step of removing the interlayer insulating film 16 at the edge of the wafer 1 is added. The step of removing the interlayer insulating film 16 at the edge of the wafer 1 may be performed by, for example, polishing using the polishing drums DRM1 to DRM3 described in the first embodiment with reference to FIGS. 4 to 7, dry etching, or wet etching. Can be done by By adding such a step of removing the interlayer insulating film 16 at the edge of the wafer 1, it is possible to prevent the interlayer insulating film 16 from remaining at the edge of the wafer 1. That is, in the later cleaning step, the yield of the semiconductor integrated circuit device according to the sixth embodiment is reduced because the interlayer insulating film 16 is separated from the edge of the wafer 1 and adheres to the wafer 1. Can be prevented.
[0089]
Next, as shown in FIG. 30, the interlayer insulating film 16 on the n-type semiconductor region 15 on the main surface of the wafer 1 is etched by using a photoresist film (not shown) patterned by photolithography as a mask. The connection hole 17 is opened (step P4).
[0090]
Subsequently, by the same means as in the step P3, an inspection is performed to determine whether or not the interlayer insulating film 16 is formed into an uneven thin film that is easily peeled off at the edge of the wafer 1 (step P5). Also in this step P5, as in the case of the above-described step P3, when it is detected that the interlayer insulating film 16 is formed into a concave and convex thin film at the edge of the wafer 1, the present embodiment is preferred. In the manufacturing process of the semiconductor integrated circuit device of No. 6, a step of removing the interlayer insulating film 16 at the edge of the wafer 1 is added after the step of etching the interlayer insulating film 16 in Step P4.
[0091]
Next, as shown in FIG. 31, a barrier conductor film 18A such as titanium nitride is deposited on the wafer 1 by sputtering, and a conductive film 18B such as tungsten is deposited on the barrier conductor film 18A by CVD. (Step P6).
[0092]
Here, before forming the connection hole 17, the barrier conductor film 18A, and the conductive film 18B, a step of depositing the thin film TF2A described on the third embodiment with reference to FIG. You may go. As described in the third embodiment, the thin film TF2A has better adhesion to the wafer 1 than the barrier conductor film 18A and the conductive film 18B, and the thin film TF2A has a better adhesion to the barrier conductor film 18A and the conductive film 18B. Is a silicon oxide film having good adhesiveness, it is possible to prevent the barrier conductor film 18A and the conductive film 18B from peeling off at the edge of the wafer 1. That is, it is possible to prevent the yield of the semiconductor integrated circuit device according to the sixth embodiment from being reduced due to the peeled barrier conductor film 18A and conductive film 18B adhering to the wafer 1. Further, instead of performing the step of depositing the thin film TF2A on the wafer 1 including the edge, as described with reference to FIGS. 19 and 20 in the fourth embodiment, the interlayer insulating film 16 on the edge of the wafer 1 Means may be used in which only the uneven portion is polished to smooth the surface of the interlayer insulating film 16 at the edge of the wafer 1.
[0093]
Next, as shown in FIG. 32, the barrier conductive film 18A and the conductive film 18B on the interlayer insulating film 16 are removed by, for example, a CMP method, and the barrier conductive film 18A and the conductive film 18B are left in the connection holes 17. Thus, the plug 18 including the barrier conductor film 18A and the conductive film 18B is formed (Step P7).
[0094]
Subsequently, by the same means as in the above-described step P3, an inspection is performed to determine whether or not the barrier conductor film 18A and the conductive film 18B are easily peeled off at the edge of the wafer 1 (the barrier conductor film 18A and the An inspection for confirming the adhesion to the base is performed (step P8). Also in this step P8, as in the case of the above-described step P3, when it is detected that the barrier conductor film 18A and the conductive film 18B are easily peeled off at the edge of the wafer 1, the present embodiment is performed. In the manufacturing process of the semiconductor integrated circuit device according to the sixth embodiment, a step of removing the barrier conductor film 18A and the conductive film 18B at the edge of the wafer 1 after the step P7 is added.
[0095]
Next, as shown in FIG. 33, a conductive film (first thin film) 20 is formed by sequentially depositing a Ti (titanium) film, an Al alloy film, and a titanium nitride film from the lower layer on the wafer 1 (step). P9).
[0096]
Subsequently, an inspection is performed to determine whether or not the conductive film 20 is easily peeled (including a state where the conductive film 20 is peeled) (Step P10). Also in this process P10, similarly to the case of the above-described process P3, when it is detected that the conductive film 20 is easily peeled off at the edge of the wafer 1, the semiconductor of the sixth embodiment is detected. In the manufacturing process of the integrated circuit device, a step of removing the conductive film 20 at the edge of the wafer 1 after the step P9 is added.
[0097]
Next, as shown in FIG. 34, the conductive film 20 is etched using the photoresist film patterned by the photolithography technique as a mask to form the wiring 21 made of the conductive film 20. Is manufactured (process P11). Note that wiring may be formed in a further multilayer by repeating the steps shown in FIGS.
[0098]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is.
[0099]
For example, in the third embodiment, the case is described where the conductive film embedded in the groove (including the hole) formed in the thin film made of the silicon oxide film contains W or Al as a main component. Even when the conductive film to be buried contains Cu (copper) as a main component, the process of the third embodiment can be similarly applied.
[0100]
Further, in the above-described embodiment, the case where the number of the polishing drums for polishing the edge of the wafer is three is exemplified, but three or more polishing drums may be used.
[0101]
Further, in the above-described embodiment, the case where the edge of the wafer is polished using the polishing drum has been described as an example. However, the grinding wheel (second polishing means) in which the contour of the edge of the wafer is modeled, or an organic resin is used. Polishing may be performed using a polishing tape manufactured by embedding the slurry.
[0102]
Further, in the above-described embodiment, a method of manufacturing a semiconductor integrated circuit device in which an nMIS is formed in a p-type well is illustrated. However, the present invention is applied to a method of manufacturing a semiconductor integrated circuit device in which a pMIS is formed in an n-type well. Is also good.
[0103]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
(1) Since the thin film (first thin film) formed on the edge of the semiconductor wafer is removed, it is possible to prevent the thin film from peeling off from the edge of the semiconductor wafer and becoming a foreign substance.
(2) When patterning a thin film (first thin film) formed on a semiconductor wafer using a photoresist film (masking layer) as a mask, the thin film is sufficiently covered with the photoresist film at the edge of the semiconductor wafer. Therefore, it is possible to prevent the thin film on the edge of the semiconductor wafer from being easily peeled off after patterning.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;
3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2;
FIG. 4 is a plan view illustrating a step of polishing a wafer edge using a polishing drum.
FIG. 5 is a cross-sectional view of a principal part explaining an angle at which one of the polishing drums shown in FIG. 4 contacts an edge of a wafer.
6 is a cross-sectional view of a principal part explaining an angle at which one of the polishing drums shown in FIG. 4 contacts an edge of a wafer.
7 is a cross-sectional view of a principal part explaining an angle at which one of the polishing drums shown in FIG. 4 contacts an edge of a wafer.
FIG. 8 is a cross-sectional view of a main part for explaining a difference in a film formation state of a thin film formed on a wafer.
FIG. 9 is a cross-sectional view of a principal part for explaining a difference in a film formation state of a thin film formed on a wafer.
FIG. 10 is a plan view illustrating a polishing step of a wafer edge using a polishing pad.
FIGS. 11A and 11B are cross-sectional views illustrating a polishing process of an edge of a wafer using a polishing pad, respectively.
FIG. 12 is an essential part cross sectional view of the semiconductor integrated circuit device of Second Embodiment of the present invention during a manufacturing step;
FIG. 13 is a fragmentary cross-sectional view for explaining the method of manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;
14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 13;
15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 14;
16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 15;
17 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 16;
18 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 17;
FIG. 19 is a fragmentary cross-sectional view for explaining the method of manufacturing the semiconductor integrated circuit device according to the fourth embodiment of the present invention;
20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19;
21 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 20;
FIG. 22 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.
23 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 22;
FIG. 24 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 23;
FIG. 25 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 24;
26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 25;
FIG. 27 is a flowchart illustrating a main part of a manufacturing process of the semiconductor integrated circuit device according to the sixth embodiment of the present invention;
FIG. 28 is a fragmentary cross-sectional view for explaining the method of manufacturing the semiconductor integrated circuit device according to the sixth embodiment of the present invention;
FIG. 29 is an essential part cross sectional view for explaining the method of manufacturing the semiconductor integrated circuit device of the sixth embodiment of the present invention;
30 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 28;
FIG. 31 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 30;
32 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 31;
FIG. 33 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 32;
FIG. 34 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 33;
[Explanation of symbols]
1 wafer
2 Silicon oxide film
3 Silicon nitride film
5 Photoresist film
6 grooves
8 Silicon oxide film
9 p-type well
10 Gate oxide film
11 Gate electrode
12 Cap insulating film
14 Sidewall spacer
15 n-type semiconductor region (source, drain)
16 Interlayer insulation film (first thin film)
17 Connection hole
18 plug
18A Barrier conductor film
18B conductive film
20 conductive film (first thin film)
MZ groove
DRM1 to DRM3 polishing drum (first polishing means)
KKT border edge
NZL nozzle
P1 to P10 process
PAD1 to PAD3 Polishing pad (first polishing means)
Qn n-channel type MISFET
RESI1 photoresist film (second masking layer)
S side
TF1 thin film (first thin film)
TF1A, TF1B thin film
TF2 conductive film (third thin film)
TF2A thin film (second thin film)

Claims (30)

(A) forming a single-layer or laminated first thin film on a semiconductor wafer;
(B) performing a first treatment on the semiconductor wafer such that irregularities are formed on the surface of the first thin film at the edge of the semiconductor wafer;
(C) removing the first thin film at an edge of the semiconductor wafer;
A method for manufacturing a semiconductor integrated circuit device, comprising: 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first processing includes:
(B1) polishing and flattening the surface of the first thin film;
(B2) forming a patterned masking layer on the first thin film, and etching the first thin film using the masking layer as a mask;
(B3) holding the semiconductor wafer by mechanical means in the presence of the first thin film at the edge of the semiconductor wafer;
A method for manufacturing a semiconductor integrated circuit device, comprising: 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said step (c) comprises selecting one of a first polishing unit using a slurry, a second polishing unit using a grindstone, a dry etching unit, and a wet etching unit. A method for manufacturing a semiconductor integrated circuit device, wherein the method is performed using at least one of the above methods. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step (a) is performed by single-wafer processing. (A) forming a single-layer or laminated first thin film on a semiconductor wafer by single-wafer processing;
(B) removing the first thin film at an edge of the semiconductor wafer;
A method for manufacturing a semiconductor integrated circuit device, comprising: 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein said first thin film is an insulating film containing silicon. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the step (b) comprises selecting one of a first polishing unit using a slurry, a second polishing unit using a grindstone, a dry etching unit, and a wet etching unit. A method for manufacturing a semiconductor integrated circuit device, wherein the method is performed using at least one of the above methods. (A) forming a single-layer or laminated first thin film on a semiconductor wafer;
(B) performing a first treatment on the semiconductor wafer such that irregularities are formed on the surface of the first thin film at the edge of the semiconductor wafer;
(C) removing the first thin film at an edge of the semiconductor wafer;
(D) after the step (c), forming a single-layer or laminated second thin film on the semiconductor wafer including the edge;
(E) forming a third thin film on the second thin film;
Wherein the second thin film is selected from a thin film having better adhesion to the semiconductor wafer than the third thin film and to which the third thin film adheres well. Device manufacturing method. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the first processing includes:
(B1) polishing and flattening the surface of the first thin film;
(B2) forming a patterned masking layer on the first thin film, and etching the first thin film using the masking layer as a mask;
(B3) holding the semiconductor wafer by mechanical means in the presence of the first thin film at the edge of the semiconductor wafer;
A method for manufacturing a semiconductor integrated circuit device, comprising: The method for manufacturing a semiconductor integrated circuit device according to claim 8,
The step (c) is performed by using at least one selected from a first polishing unit using a slurry, a second polishing unit using a grindstone, a dry etching unit, and a wet etching unit. A method for manufacturing a semiconductor integrated circuit device. The method for manufacturing a semiconductor integrated circuit device according to claim 8,
The method of manufacturing a semiconductor integrated circuit device, wherein the step (a) is performed by single-wafer processing. The method for manufacturing a semiconductor integrated circuit device according to claim 8,
The method for manufacturing a semiconductor integrated circuit device, wherein the second thin film is an insulating film containing silicon. The method for manufacturing a semiconductor integrated circuit device according to claim 8,
The step (d) includes:
(D1) forming a second masking layer covering the main surface and the edge of the semiconductor wafer on the second thin film;
(D2) patterning the second masking layer so as to remain on the edge of the semiconductor wafer;
(D3) a step of etching the second thin film using the second masking layer as a mask;
A method for manufacturing a semiconductor integrated circuit device, comprising: The method for manufacturing a semiconductor integrated circuit device according to claim 8,
The step (d) includes:
(D1) forming a second masking layer on the second thin film;
(D2) removing the second masking layer at an edge of the semiconductor wafer;
(D3) a step of patterning the second masking layer;
(D4) etching the second thin film using the second masking layer as a mask;
A method for manufacturing a semiconductor integrated circuit device, comprising: 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein, in the step (d2), after the second masking layer at the edge of the semiconductor wafer is subjected to an exposure process, the second masking layer is subjected to a development process to perform a development process. Removing the second masking layer, or while rotating the semiconductor wafer with the main surface facing upward, from the main surface side of the semiconductor wafer to the second masking layer at the edge of the semiconductor wafer. A method of manufacturing a semiconductor integrated circuit device, comprising: injecting an organic solvent to remove the second masking layer at an edge of the semiconductor wafer. (A) forming a single-layer or laminated first thin film on a semiconductor wafer;
(B) performing a first treatment on the semiconductor wafer such that irregularities are formed on the surface of the first thin film at the edge of the semiconductor wafer;
(C) polishing the first thin film including the irregularities at the edge of the semiconductor wafer, leaving the first thin film having a first thickness at the edge of the semiconductor wafer;
(D) after the step (c), forming a third thin film on the first thin film;
A method for manufacturing a semiconductor integrated circuit device, comprising: 17. The method for manufacturing a semiconductor integrated circuit device according to claim 16, wherein the first processing includes:
(B1) polishing and flattening the surface of the first thin film;
(B2) forming a patterned masking layer on the first thin film, and etching the first thin film using the masking layer as a mask;
(B3) holding the semiconductor wafer by mechanical means in the presence of the first thin film at the edge of the semiconductor wafer;
A method for manufacturing a semiconductor integrated circuit device, comprising: 17. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the step (c) uses at least one selected from a first polishing unit using a slurry and a second polishing unit using a grindstone. A method of manufacturing a semiconductor integrated circuit device. 17. The method for manufacturing a semiconductor integrated circuit device according to claim 16, wherein the step (a) is performed by single-wafer processing. (A) forming a single-layer or laminated first thin film on a semiconductor wafer;
(B) forming a masking layer covering the main surface and the edge of the semiconductor wafer on the first thin film;
(C) patterning the masking layer so as to remain on an edge of the semiconductor wafer;
(D) etching the first thin film using the masking layer as a mask;
A method for manufacturing a semiconductor integrated circuit device, comprising: 21. The method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein the step (a) is performed by single-wafer processing. (A) forming a single-layer or laminated first thin film on a semiconductor wafer;
(B) forming a masking layer on the first thin film;
(C) removing the masking layer at an edge of the semiconductor wafer;
(D) patterning the masking layer;
(E) etching the first thin film using the masking layer as a mask;
A method for manufacturing a semiconductor integrated circuit device, comprising: 23. The method of manufacturing a semiconductor integrated circuit device according to claim 22, wherein the step (c) comprises:
(C1) performing an exposure process on the masking layer at the edge of the semiconductor wafer, and then performing a developing process to remove the masking layer at the edge of the semiconductor wafer;
(C2) an organic solvent is sprayed from the main surface side of the semiconductor wafer to the masking layer at the edge of the semiconductor wafer while the semiconductor wafer is held and rotated with the main surface facing upward, Removing the masking layer at the edge,
A method for manufacturing a semiconductor integrated circuit device, comprising: 23. The method of manufacturing a semiconductor integrated circuit device according to claim 22, wherein the step (a) is performed by single-wafer processing. (A) forming a single-layer or laminated first thin film on a semiconductor wafer;
(B) performing a first process on the semiconductor wafer;
(C) after the step (b), inspecting the first thin film at the edge of the semiconductor wafer for occurrence of a first defect;
A step of removing the first thin film at the edge of the semiconductor wafer after the step (b) when the first defect is detected. Method. 26. The method for manufacturing a semiconductor integrated circuit device according to claim 25, wherein the first problem is at least one of irregularities generated on a surface of the first thin film and peeling of the first thin film from a base. Of manufacturing a semiconductor integrated circuit device. 26. The method of manufacturing a semiconductor integrated circuit device according to claim 25, wherein the step (c) uses a first inspection step of inspecting a flat region on a main surface of the semiconductor wafer using bright field illumination, and a dark field illumination. And a second inspection step of inspecting the edge of the semiconductor wafer. 26. The method of manufacturing a semiconductor integrated circuit device according to claim 25, wherein the first processing includes:
(B1) polishing and flattening the surface of the first thin film;
(B2) forming a patterned masking layer on the first thin film, and etching the first thin film using the masking layer as a mask;
(B3) holding the semiconductor wafer by mechanical means in the presence of the first thin film at the edge of the semiconductor wafer;
A method for manufacturing a semiconductor integrated circuit device, comprising: 26. The method of manufacturing a semiconductor integrated circuit device according to claim 25, wherein the step of removing the first thin film at the edge of the semiconductor wafer includes a first polishing unit using a slurry, a second polishing unit using a grindstone, and dry etching. A method of manufacturing a semiconductor integrated circuit device, wherein the method is performed by using at least one selected from a unit and a wet etching unit. 26. The method of manufacturing a semiconductor integrated circuit device according to claim 25, wherein the step (a) is performed by single-wafer processing.

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