JP2004145957A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of performing failure analysis to improve the yield by efficiently outputting the data within a program circuit. <P>SOLUTION: This device is provided with a memory cell array in which a plurality of normal memory cells are arranged in a matrix. The memory cell array includes a plurality of spare memory cells which replace the failure memory cells of the plurality of normal memory cells in predetermined units, and has: a program circuit for storing failure addresses to specify the predetermined units including the failure memory cells in a nonvolatile manner; a redundancy control section having the function of determining coincidence comparison between an input address and a failure address and designed to control accesses to a plurality of spare memory cells on the basis of the result of the coincidence comparison in a normal mode; and a test output circuit for outputting the result of the coincidence comparison in a test mode. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundant configuration for repairing a defective memory cell.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the capacity and integration of semiconductor memory devices have been increasingly advanced. A semiconductor memory device having a high degree of integration includes a spare memory cell, and even if a defect occurs in some of the memory cells in the manufacturing stage, the defective memory cell in which the defect has occurred is replaced with the spare memory cell and repaired. It is common. By performing such redundant replacement, the yield is improved. (For example, see Patent Document 1).
[0003]
In order to perform redundant replacement, it is necessary to store the address of a defective memory cell (hereinafter, simply referred to as a defective address) in a nonvolatile manner using a program element. Typically, a fuse element is used as a program element. Some of the fuse elements are called electric blow fuses or antifuses. Generally, a fuse element is cut using a laser beam or the like.
[0004]
FIG. 14 is a block diagram showing a configuration of a conventional semiconductor memory device 106 having a redundant replacement configuration.
[0005]
Referring to FIG. 14, a semiconductor memory device 106 includes a memory cell array 10 having a plurality of memory cells arranged in a matrix, an address terminal 21 receiving an address signal ADD, a row decoder 11, and a column decoder 13 Read / write control circuit 12, and data terminal 22 for transmitting / receiving data signal DT to / from read / write control circuit 12.
[0006]
The memory cell array 10 has normal memory cells MC arranged in (n + 1) rows × (m + 1) columns (n, m: natural numbers) and memory cells arranged in (p + 1) rows and (p + 1) columns (p: natural numbers). Spare memory cell SMC for replacing and relieving a defective memory cell. In the following, a memory cell row and a memory cell column formed by normal memory cells MC are also referred to as a “normal memory cell row” and a “normal memory cell column”, respectively. Also referred to as "spare rows" and "spare columns".
[0007]
In the following, a row address indicating a memory cell row in which a defective memory cell exists (hereinafter, also referred to as a defective row) is also referred to as a row defective address. Similarly, a column address indicating a memory cell column in which a defective memory cell exists (hereinafter, also referred to as a defective column) is also referred to as a column defective address.
[0008]
Word lines WL0 to WLn are arranged corresponding to normal memory cell rows, respectively. Spare word lines SWL0-SWLp are arranged corresponding to the respective spare rows. Bit lines BL0 to BLm are arranged corresponding to the normal memory cell columns, respectively. Spare bit lines SBL0 to SBLp are arranged corresponding to the respective spare columns.
[0009]
In the following, when each of a word line, a bit line, a spare bit line, and a spare word line is collectively expressed, the word line, the bit line, the spare bit line, and the spare word line will be represented by reference numerals WL, BL, SBL, and SWL. , Bit lines, spare bit lines and spare word lines are denoted by subscripts and denoted as WL1, BL1, SBL1 and SWL1.
[0010]
Row decoder 11 performs row selection in memory cell array 10 according to row address RA indicated by address signal ADD. Column decoder 13 performs column selection in memory cell array 10 according to column address CA indicated by address signal ADD. In the following, a memory cell designated as a target of data reading or data writing by row address RA and column address CA is also referred to as “selected memory cell”.
[0011]
At the time of data reading, read / write control circuit 12 reads data from a selected memory cell according to a voltage / current of a bit line of a selected memory cell column (hereinafter, also referred to as a selected column) corresponding to the selected memory cell. A group of circuits for outputting to the data terminal 22 and a group of circuits for writing input data to the data terminal 22 to the selected memory cell by controlling the voltage and current of the bit line in the selected column at the time of writing data are generally described. It is the notation.
[0012]
Next, a redundant configuration of the semiconductor storage device 106 will be described.
The semiconductor memory device 106 further includes a row program circuit 14 and a redundancy control circuit 19.
[0013]
The row program circuit 14 can store the defective addresses of the rows obtained by the wafer test or the like by the number of the spare word lines SWL, that is, (p + 1). The defective address of a row is represented by (h + 1) (h: natural number) bits. For example, when h = 7, the number of word lines WL is 256. Therefore, when a defective address of one row is stored in row program circuit 14, for example, a defective address of an 8-bit row is replaced by eight fuses (not shown) provided inside address row program circuit 14. Is stored depending on whether or not is disconnected. When storing the defective addresses of (p + 1) rows, the defective addresses of the rows are stored in (p + 1) sets of fuses (not shown), with a set of eight fuses as one set.
[0014]
The row program circuit 14 outputs the defective address of the row stored by the (p + 1) sets of fuse groups to the redundancy control circuit 19 as a defective address RAPG <0: p>.
[0015]
Here, RAPG <0: p> is a general expression of (h + 1) -bit RAPG <0> to RAPG <p>. Hereinafter, in the present specification, the same notation is used when a plurality of signals constituting the same signal are collectively shown. Further, the binary high voltage state (power supply voltage Vcc) and low voltage state (ground voltage Vss) of the signal and the signal line are referred to as “H level”, “1”, “L level” and “0”, respectively. Name.
[0016]
In a normal operation, the redundancy control circuit 19 selects a defective row as a data read or data write target by comparing the row address RA with each of the defective addresses of a plurality of rows stored in the row program circuit 14. It is determined whether it has been performed.
[0017]
FIG. 15 is a circuit diagram showing a configuration of the redundancy control circuit 19.
Referring to FIG. 15, redundancy control circuit 19 includes comparison circuits 31.0 to 31.3 provided corresponding to defective addresses RAPG <0> to RAPG <p> input from row program circuit 14, respectively. p, an OR circuit 32, and an inverter 33. Comparison circuits 31.0 to 31. For each of p, (h + 1) -bit row address RA composed of row address bits RAB <0: h> (RAB <0> to RAB <h>, h: natural number) is input. In addition, the comparison circuits 31.0 to 31. The defective addresses RAPG <0> to RAPG <p> from the row program circuit 14 are input to each of p. Each of defective addresses RAPG <0> to RAPG <p> has (h + 1) bits, similarly to row address RA.
[0018]
Comparison circuits 31.0 to 31. p sets the spare enable signals RSPE <0> to RSPE <p> to the H or L level, respectively, based on the comparison result between the row address RA and the defective addresses RAPG <0> to RAPG <p>.
[0019]
In the following, the comparison circuits 31.0 to 31. p, the defective addresses RAPG <0> to RAPG <p> and the spare enable signals RSPE <0> to RSPE <p> are also collectively referred to as a comparison circuit 31, a defective address RAPG and a spare enable signal RSPE.
[0020]
Each comparison circuit 31 sets the corresponding spare enable signal RSPE to the H level when the row address RA matches the corresponding defective address RAPG. For example, comparison circuit 31.0 sets spare enable signal RSPE <0> to H level when row address RA matches defective address RAPG <0>.
[0021]
OR circuit 32 includes comparison circuits 31.0 to 31. and outputs signals obtained by performing a logical sum operation on the spare enable signals RSPE <0> to RSPE <p> output from p. Inverter 33 outputs the inverted level of the output signal from OR circuit 32 as normal enable signal RNE.
[0022]
Referring to FIG. 14 again, row decoder 11 receives normal enable signal RNE and spare enable signal RSPE <0: p> from redundancy control circuit 19. The row decoder 11 selects the word line WL corresponding to the row address RA when the row address RA does not match the defective address RAPG in the row program circuit 14 and the normal enable signal RNE becomes H level. On the other hand, when the row address RA matches the defective address RAPG in the row program circuit 14 and the normal enable signal RNE goes low, the row decoder 11 inhibits access to the word line WL corresponding to the row address RA. , Spare word line SWL corresponding to spare enable signal RSPE is set to the selected state (H level). For example, when spare enable signal RSPE <0> is at H level, word line WL0 is selected.
[0023]
The semiconductor memory device 106 further includes a column program circuit 16 and a redundancy control circuit 19a.
[0024]
Similarly to the row program circuit 14, the column program circuit 16 can store the defective addresses of the columns obtained by the wafer test or the like by the number of (p + 1) spare bit lines. Column program circuit 16 is configured similarly to row program circuit 14, and stores defective address CAPG <0: p>. The defective address CAPG <0: p> read from the column address circuit 16 is input to the redundancy control circuit 19a.
[0025]
The column address CA has (p + 1) bits composed of column address bits CAB <0: h> (CAB <0> to CAB <p>, p: natural number). Each of defective addresses CAPG <0> to CAPG <p> has (h + 1) bits, similarly to column address CA.
[0026]
Hereinafter, defective addresses CAPG <0> to CAPG <p> are collectively referred to as defective addresses CAPG.
[0027]
Redundancy control circuit 19a has a configuration similar to that of redundancy control circuit 19 shown in FIG. 15, and receives a column address CA and a defective address CAPG <0: p>, and receives a normal enable signal CNE indicating a result of comparison between the two. And a spare enable signal CSPE <0: p>. In other words, in the configuration of FIG. 15, if row address RA is replaced by column address CA and defective address RAPG <0: p> is replaced by defective address CAPG <0: p>, normal enable signal RNE and spare enable signal RSPE <0 : P>, a normal enable signal CNE and a spare enable signal CSPE <0: p> can be obtained. Therefore, during normal operation, the redundancy control circuit 19a determines whether or not a defective row has been selected as a data read or data write target.
[0028]
Hereinafter, spare enable signals CSPE <0: p> are also collectively referred to as spare enable signals CSPE.
[0029]
Column decoder 13 receives normal enable signal CNE and spare enable signal CSPE <0: p> from redundancy control circuit 19a. When the column address CA does not match the defective address CAPG in the column program circuit 16 and the normal enable signal CNE becomes H level, the column decoder 13 selects the bit line BL corresponding to the column address CA. When the column address CA matches the defective address CAPG in the column program circuit 16 and the normal enable signal CNE goes to L level, the column decoder 13 inhibits access to the bit line BL corresponding to the column address CA. , Spare bit line SBL corresponding to spare enable signal CSPE is set to the selected state (H level). For example, when spare enable signal CSPE <0> is at H level, spare bit line SBL0 is selected.
[0030]
Next, the replacement relief operation in the semiconductor memory device 106 will be described.
First, the data read operation will be described. When the row address RA matches the defective address RAPG and the column address CA does not match the defective address CAPG, the redundancy control circuit 19 sends the row decoder 11 an L level normal enable signal RNE and a spare enable signal RSPE. And instructs access to a spare word line corresponding to the spare enable signal RSPE, and instructs to stop access to the word line WL corresponding to the row address RA.
[0031]
On the other hand, the column address CA is input to the column decoder 13, and the bit line BL corresponding to the column address CA is selected.
[0032]
Thereby, when row address RA is input to row decoder 11, the spare memory cell corresponding to the selected spare word line and selected bit line BL in place of the memory cell row indicated by row address RA Data is output from data terminal 22 by read / write control circuit 12.
[0033]
Next, when the row address RA does not match the defective address RAPG and the column address CA matches the defective address CAPG, the redundancy control circuit 19a sends the L level normal enable signal CNE and the spare enable to the column decoder 13. A signal CSPE is output to instruct access to a spare bit line corresponding to spare enable signal CSPE and to stop access to bit line BL corresponding to column address CA.
[0034]
On the other hand, the row address RA is input to the row decoder 11, and the word line WL corresponding to the row address RA is selected. Further, when column address CA is input to column decoder 13, the spare cell line corresponding to the selected spare bit line BL and selected word line WL is replaced with the memory cell column indicated by column address CA. Data is output from data terminal 22 by read / write control circuit 12.
[0035]
Next, when the row address RA and the defective address RAPG match the column address CA and the defective address CAPG, respectively, the row decoder selects the spare word line SWL corresponding to the defective address RAPG, and the column decoder selects the defective address. The spare bit line SBL corresponding to the CAPG is selected.
[0036]
Thus, a spare memory cell corresponding to a spare word line WL selected in place of the memory cell row indicated by loum address RA and a spare bit line BL selected in place of the memory cell column indicated by column address CA Are output from the data terminal 22 by the read / write control circuit 12.
[0037]
In replacement replacement at the time of data write operation, a spare memory cell is selected and data from the data terminal 22 is stored in the selected spare memo cell by the read / write control circuit 12, as in the data read operation. Detailed description of the operation is similar to that of the data read operation, and will not be repeated.
[0038]
As described above, a semiconductor memory device having a redundant replacement configuration can rescue a semiconductor memory device including a defective memory cell generated in a manufacturing process by replacing a defective memory cell with a spare memory cell. Can be improved.
[0039]
[Patent Document 1]
JP 2001-35187 A (page 3-5, FIG. 1)
[0040]
[Problems to be solved by the invention]
Generally, in a semiconductor memory device, defective memory cells are generated with a probability of several percent in a manufacturing process. Therefore, the address of the defective memory cell is stored by cutting the fuse in the program circuit. However, it is necessary to check whether the redundant replacement circuit in the semiconductor memory device operates normally in a subsequent test in a wafer state.
[0041]
Therefore, by analyzing where a memory cell in a semiconductor memory device is likely to be defective, for example, if a memory cell at the same position is defective every time, a circuit design error can be ascertained. Further, if it can be analyzed that the probability that the memory cell at the same position is defective is high, for example, the probability that a defective memory cell is generated can be reduced by changing the transistor used in the memory cell to one having a large margin. Can be.
[0042]
Further, in the operation test of the semiconductor memory device after the fuse is cut, the defective memory may be determined to be defective because the fuse storing the defective address is not cut properly. Therefore, by analyzing whether or not the fuse has been cut normally, if it is possible to analyze, for example, that only the fuse in the same place has a high probability of not being cut normally, the energy of the laser for cutting the fuse element is adjusted. By doing so, the probability of surely cutting the desired fuse element is also improved. That is, a semiconductor memory device determined to be defective due to a defect on the program circuit side can also be repaired.
[0043]
As described above, by outputting the defective address stored in the program circuit and analyzing the data, the yield of the semiconductor memory device can be further improved. Hereinafter, outputting data in the program circuit and analyzing the data is also referred to as failure analysis.
[0044]
As an example for outputting a defective address stored in the program circuit, a configuration in which a shift register is provided in association with the program circuit can be considered.
[0045]
FIG. 16 is a configuration diagram of the shift register 61 for outputting a defective address stored in the program circuit. Note that the shift register in FIG. 14 has a configuration for outputting 8-bit data as an example. FIG. 14 also shows a program circuit 24 that can store an 8-bit defective address and an output terminal 23 that outputs data from the shift register for the sake of explanation.
[0046]
Referring to FIG. 16, shift register 61 includes flip-flops 62.0 to 62.7 each connected in series. In the following, flip-flops 62.0 to 62.7 are collectively referred to as flip-flop 62.
[0047]
In each flip-flop 62, an 8-bit defective address stored in the program circuit 24 is stored bit by bit. When reading the data in the shift register 61, if the clock control signal CTR is externally input to the shift register, the data stored in each flip-flop 62 is serially output from the output terminal 23.
[0048]
As described above, if a shift register is provided in association with a program circuit, it is possible to output a defective address in the program circuit. However, as the number of defective addresses that can be stored in the program circuit increases, the number of shift registers must also increase accordingly. For this reason, there is a problem that the degree of integration of the circuit of the semiconductor memory device is reduced.
[0049]
Further, it is necessary to further provide a data pin for outputting data of the shift register. Therefore, a configuration in which data in a program circuit is output using a shift register is not very suitable for a semiconductor memory device that needs to have a slightly higher degree of integration. Furthermore, in the above configuration, it is necessary to separately create a program for controlling the shift register.
[0050]
On the other hand, as another problem, in a semiconductor memory device having a conventional redundant replacement configuration, whether a desired fuse is cut correctly is determined by an operation test for relieving defects after cutting of the fuse. The determination was difficult only depending on whether or not the substitution was made.
[0051]
In particular, it has been difficult to determine which fuse group stores a plurality of defective addresses stored in the program circuit. Therefore, it has been difficult to analyze a failure in a program circuit for storing a failure address.
[0052]
Further, in a conventional semiconductor memory device having a redundant replacement configuration, a defective memory cell cannot be accessed because a redundant replacement circuit operates after a fuse is blown. Therefore, it has been difficult to analyze the position of the defective memory cell on the actual memory after the fuse is cut.
[0053]
The present invention has been made to solve the above problems, and an object of the present invention is to improve the yield by efficiently outputting data in a program circuit with a small circuit change. It is an object of the present invention to provide a semiconductor memory device capable of performing a failure analysis.
[0054]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention is a semiconductor memory device having a normal mode and a test mode as operation modes, and includes a memory cell array in which a plurality of normal memory cells are arranged in a matrix, and the memory cell array includes a plurality of normal memory cells. A plurality of spare memory cells that replace defective memory cells of the memory cells in predetermined units,
A program circuit for nonvolatilely storing a defective address that specifies a predetermined unit including a defective memory cell; and a function of determining a match comparison between an input address and a defective address, and based on a result of the match comparison in a normal mode. It further includes a redundancy control unit for controlling access to the plurality of spare memory cells, and a test output circuit for outputting a result of the match comparison in the test mode.
[0055]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.
[0056]
[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device 101 according to the first embodiment. The semiconductor memory device 101 has a function of outputting a defective address stored in the row program circuit 14.
[0057]
Referring to FIG. 1, semiconductor memory device 101 is different from conventional semiconductor memory device 106 of FIG. 14 in further including selector 18 and in including redundant control circuit 19c instead of redundant control circuit 19. Are different.
[0058]
The semiconductor memory device 101 is further different from the semiconductor memory device 106 in that the signal RPD is input to the selector 18 from the redundancy control circuit 19c and that the test mode signal TM is input to the selector 18. . Other configurations are the same as those of semiconductor memory device 106 shown in FIG. 14, and thus detailed description will not be repeated. Note that the memory cell array 10 has a configuration in which memory cells are arranged in 256 rows × 256 columns as an example. In the following, it is assumed that when test mode signal TM is at the H level, the semiconductor memory device is in the test mode.
[0059]
Further, the application of the present invention is not limited to the type of memory cell, but is applied to the entire semiconductor memory device having a redundant configuration in which a defective memory cell is replaced and replaced by a spare memory cell having the same configuration. Is possible. That is, as the normal memory cell MC and the spare memory cell SMC shown in FIG. 1, the DRAM (Dynamic Random Access Memory) cell, the SRAM (Static Random Access Memory) cell, the MRAM (Magnetic Random Access ROM), and the MRAM (Magnetic Random Access Memory) Various types of cells, such as an electrically erasable programmable read only memory (flash memory) cell, are collectively shown.
[0060]
When the test mode signal TM is at the H level, the selector 18 electrically couples the redundancy control circuit 19c and the data terminal 22, and enables the signal RPD from the redundancy control circuit 19c to be output from the data terminal 22. On the other hand, when test mode signal TM is at L level, read / write control circuit 12 and data terminal 22 are electrically coupled, and read / write control circuit 12 and data terminal 22 receive data signal DT. Transfer is possible. The selector 18 operates as a test output circuit that outputs the signal RPD when the test mode signal TM is at the H level, that is, in the test mode.
[0061]
FIG. 2 is a circuit diagram showing a configuration of the redundancy control circuit 19c according to the first embodiment.
Referring to FIG. 2, redundancy control circuit 19c is different from redundancy control circuit 19 shown in FIG. 15 in that a signal path for guiding output signal RPD from OR circuit 32 to selector 18 is newly provided. Are different. Other configurations are the same as those of redundancy control circuit 19, and therefore detailed description will not be repeated.
[0062]
The redundancy control circuit 19c sets the corresponding spare enable signal RSPE to the H level when the row address RA matches the defective address RAPG stored in the row program circuit 14, similarly to the redundancy control circuit 19. In this case, the output signal RPD of the OR circuit 32 is set to the H level.
[0063]
Next, an output operation of the defective address RAPG stored in the row program circuit 14 in the semiconductor memory device 101 will be described with reference to FIGS. As an example, assume that “140” and “180” of “0” to “255” indicated by the row address are stored in the row program circuit 14 as defective addresses of the row.
[0064]
First, the test mode signal TM is set to the H level. As a result, the signal RPD is output from the selector 18. Next, the column address CA is fixed to, for example, “0”, and the row address RA is sequentially input to the redundancy control circuit 19a from “0” to “255”. When the row address RA becomes “140” and “180”, an H-level signal RPD is output to the data terminal 22. At other times, the signal RPD is at the L level. As a result, the defective address stored in the row program circuit 14 can be easily known.
[0065]
FIG. 3 is a conceptual diagram visually showing a position of a defective address in association with a memory cell array. In the following, a diagram visually indicating the position of a defective address in association with a memory cell array is also referred to as a fail bit map. In the fail bit map, the vertical axis corresponds to the word lines WL0 to WLn, and the horizontal axis corresponds to the bit lines BL0 to BLm. In the following, it is assumed that normal data (L level data) is output in a white portion on a fail bit map, and defective data (H level data) is shown in a black or hatched region on a fail bit map. Is output.
[0066]
Hatched areas B and C and D and E of the fail bit map are diagrams showing examples of defective addresses stored in the row program circuit 14 and the column program circuit 16, respectively. Note that the area painted black indicates the actual position of the defective memory cell. As an example, when the defective addresses of the rows stored in the row program circuit 14 are “140” and “180”, they are indicated as hatched areas B and C on the fail bit map, respectively.
[0067]
Therefore, by using the fail bit map, the distribution of defective addresses can be visually recognized, and failure analysis can be easily performed.
[0068]
Next, an operation of determining whether or not a desired defective address is stored in row program circuit 14 in semiconductor memory device 101 will be described with reference to FIGS. 1 and 2 again.
[0069]
First, the test mode signal TM is set to the H level. Next, the defective address RA of the row obtained by the wafer test is input to the redundancy control circuit 19c. At this time, when the defective address RA of the row matches the defective address RAPG stored in the row program circuit 14, that is, if the fuse group corresponding to the defective address of the row is correctly cut, the data terminal 22 , H level signal RPD is output.
[0070]
On the other hand, when the defective address RA of the row does not match the defective address RAPG stored in the row program circuit 14, the data terminal 22 outputs an L-level signal RPD. Since the signal RPD which is supposed to be at the H level is output as the L level, the defective address is not correctly stored in the row program circuit 14, that is, the fuse group corresponding to the defective address RA of the row is correctly blown. It can be recognized that it has not been done.
[0071]
Note that the replacement repair operation in the data write operation and the data read operation in semiconductor memory device 101 is the same as that in semiconductor memory device 106 if test mode signal TM is set to L level, and therefore detailed description will not be repeated. .
[0072]
As described above, in the semiconductor memory device 101 according to the first embodiment, the fuse is correctly cut in the row program circuit by the 1-bit signal RPD that can be output from the data terminal 22 used during the normal operation, and the defective address becomes normal. Can be detected. That is, data in the program circuit can be efficiently output with a slight circuit change, and failure analysis can be performed for the purpose of improving the yield of the semiconductor memory device.
[0073]
[Modification of First Embodiment]
FIG. 4 is a block diagram showing a configuration of a semiconductor memory device 102 according to a modification of the first embodiment. The semiconductor memory device 102 has a function of outputting a defective address stored in the column program circuit 16.
[0074]
Referring to FIG. 4, a semiconductor memory device 102 is different from semiconductor memory device 101 shown in FIG. 1 in that a redundancy control circuit 19 is provided instead of redundancy control circuit 19c, and a semiconductor memory device 102 is provided instead of redundancy control circuit 19a. The difference is that a redundant control circuit 19d is provided.
[0075]
The semiconductor memory device 102 is further different from the semiconductor memory device 101 in that the signal CPD is input to the selector 18 from the redundancy control circuit 19d. Other configurations are the same as those of semiconductor memory device 101 shown in FIG. 1, and thus detailed description will not be repeated. It is assumed that the memory cell array 10 has a configuration in which memory cells are arranged in 256 rows × 256 columns as an example, similarly to the semiconductor memory device 101.
[0076]
The redundancy control circuit 19d has a configuration and a function similar to those of the redundancy control circuit 19c. Redundancy control circuit 19d has a configuration similar to that of redundancy control circuit 19c shown in FIG. 2, and receives a column address CA and a defective address CAPG <0: p>, and receives a normal enable signal CNE indicating a result of comparison between the two. , And a spare enable signal CSPE <0: p> and a signal CPD. That is, in the configuration of FIG. 2, if the row address RA is replaced with the column address CA and the defective address RAPG <0: p> is replaced with the defective address CAPG <0: p>, the normal enable signal RNE and the spare enable signal RSPE <0 : P> and signal RPD in place of normal enable signal CNE, spare enable signal CSPE <0: p>, and signal CPD. Therefore, the redundancy control circuit 19d determines whether or not a defective column has been selected as a data read or data write target.
[0077]
Similarly to the redundancy control circuit 19c, the redundancy control circuit 19d sets the corresponding spare enable signal CSPE to the H level when the column address CA matches the defective address CAPG stored in the column program circuit 16. In this case, the output signal CPD of the OR circuit 32 is set to the H level.
[0078]
Next, an output operation of the defective address CAPG stored in the column program circuit 16 in the semiconductor memory device 102 will be described with reference to FIG. As an example, it is assumed that “120” and “200” of “0” to “255” indicated by the column address are stored in the column program circuit 16 as the column defective address.
[0079]
First, the test mode signal TM is set to the H level. As a result, the selector 18 outputs the signal CPD. Next, the row address RA is fixed to, for example, "0", and the column address CA is sequentially input from "0" to "255" to the redundancy control circuit 19d. When the column address CA becomes “120” and “200”, the H-level signal CPD is output to the data terminal 22. At other times, the signal CPD is at the L level. As a result, the defective address stored in the column program circuit 16 can be easily known.
[0080]
Referring to FIG. 3 again, defective addresses “120” and “200” of the column are shown as hatched areas D and E on the fail bit map.
[0081]
Therefore, similarly to the first embodiment, by using the fail bit map, the distribution of defective addresses can be visually recognized, and failure analysis can be easily performed.
[0082]
In semiconductor memory device 102, the operation of determining whether or not a desired defective address is stored in column program circuit 16 is the same as that of semiconductor memory device 101, and therefore detailed description will not be repeated.
[0083]
The operation of replacement and remedy at the time of data write operation and data read operation in semiconductor memory device 102 is the same as that of semiconductor memory device 106 if test mode signal TM is set to L level, and therefore detailed description will not be repeated.
[0084]
As described above, the semiconductor memory device 102 according to the modification of the first embodiment uses a 1-bit signal RPD that can be output from the data terminal 22 used in the normal operation to operate the column program circuit in the same manner as in the first embodiment. It can be detected whether the fuse is correctly blown and the defective address is stored normally. That is, data in the program circuit can be efficiently output with a slight circuit change, and failure analysis can be performed for the purpose of improving the yield of the semiconductor memory device.
[0085]
[Embodiment 2]
FIG. 5 is a block diagram showing a configuration of a semiconductor memory device 103 according to the second embodiment. The semiconductor memory device 103 has a function of outputting a defective address stored in the row program circuit 14 and the column program circuit 16.
[0086]
Referring to FIG. 5, semiconductor memory device 103 is different from semiconductor memory device 102 in FIG. 4 in that redundant control circuit 15 is provided instead of redundant control circuit 19, and inverter 36 and AND circuit 37 are further provided. The point is different.
[0087]
Inverter 36 outputs a signal obtained by inverting the level of test mode signal TM to redundancy control circuit 15. The AND circuit 37 outputs the result of the logical operation of the signal CPD from the redundancy control circuit 19d and the test mode signal TM to the selector 18.
[0088]
The selector 18 does not directly receive the test mode signal TM, but receives the output of the AND circuit 37. That is, when the output signal of the AND circuit 37 is at the H level, the selector 18 electrically connects the redundancy control circuit 19d and the data terminal 22 and can output the signal CPD from the redundancy control circuit 19d from the data terminal 22. And On the other hand, when the output signal of AND circuit 37 is at L level, read / write control circuit 12 and data terminal 22 are electrically coupled, and data signal is applied between read / write control circuit 12 and data terminal 22. DT can be exchanged. Other configurations are the same as those of semiconductor memory device 102 shown in FIG. 4, and thus detailed description will not be repeated. Note that the memory cell array 10 has a configuration in which memory cells are arranged in 256 rows × 256 columns as an example, similarly to the semiconductor memory device 102.
[0089]
FIG. 6 is a circuit diagram showing a configuration of the redundancy control circuit according to the second embodiment.
Referring to FIG. 6, redundancy control circuit 15 includes AND circuits 34.0-34.34 corresponding to comparison circuits 31, respectively, as compared with redundancy control circuit 19c of FIG. The difference is that p is further included.
[0090]
Redundancy control circuit 15 outputs a signal / TM of an inverted level of test mode signal TM to AND circuits 34.0 to 34. p, and that the output signals of the respective comparison circuits 31 are comparison signals CP <0> to CP <p> instead of the spare enable signals RSPE <0> to RSPE <p>. Is even different. The other configuration is similar to that of redundancy control circuit 19c, and thus detailed description will not be repeated.
[0091]
In the following, AND circuits 34.0 to 34. p and the comparison signals CP <0> to CP <p> are also collectively referred to as an AND circuit 34 and a comparison signal CP.
[0092]
AND circuits 34.0 to 34. p is a value of the comparison circuits 31.0 to 31. The spare enable signals RSPE <0> to RSPE <p>, which are obtained by performing logical operations on the comparison signals CP <0> to CP <p> output from P and the test mode signal TM, are output.
[0093]
In redundant control circuit 15, for example, when test mode signal TM is at L level, all spare enable signals RSPE are all set at L level. Therefore, access to the corresponding spare word line SWL becomes impossible. When test mode signal TM is at H level and comparison signal CP <0> output from comparison circuit 31.0 is at H level, spare enable signal RSPE <0> is set to H level. That is, when test mode signal TM is at H level and row address RA matches defective address RAPG, redundancy control circuit 15 sets spare enable signal RSPE and signal RPD corresponding to defective address RAGP to H level. I do.
[0094]
Next, the output operation of the defective address stored in the row program circuit 14 and the column program circuit 16 in the semiconductor memory device 103 will be described with reference to FIGS. As an example, assume that “140” and “180” of “0” to “255” indicated by the row address are stored in the row program circuit 14 as defective addresses of the row. Further, it is assumed that “120” and “200” of “0” to “255” indicated by the column address are stored in the column program circuit 16 as the defective address of the column.
[0095]
First, the test mode signal TM is set to the H level. As a result, all the output signals RSPE <0: p> of the redundancy control circuit 15 become L level, and access to the spare word line SWL corresponding to the signal RSPE <0: p> becomes impossible.
[0096]
Next, the row address RA is fixed at "0", and the column address CA is sequentially input from "0" to "255" to the redundancy control circuit 19d. When the column address CA at the data terminal 22 becomes “120” and “200”, the signal CPD goes to H level. Accordingly, the output of the AND circuit 37 also becomes H level, and the selector 18 outputs an H level signal CPD.
[0097]
Next, "1" is added to the row address RA and fixed, and only the column address CA is sequentially input from "0" to "255" to the redundancy control circuit 19d. The same operation as above is repeated for row addresses RA "2" to "255". As a result, even if the row address RA becomes "140" and "180", access to the spare word line SWL cannot be performed. Therefore, semiconductor memory device 103 is also inaccessible to the normal memory cell and the spare memory cell, and either L or H signal DT is output from selector 18 as indefinite data. When the above data is output as a fail bit map, a diagram as shown in FIG. 7 is obtained.
[0098]
FIG. 7 is a conceptual diagram visually showing positions of defective addresses according to the second embodiment in association with memory cell arrays.
[0099]
Referring to FIG. 7, defective addresses "140" and "180" of a row are shown as areas B and C on the fail bit map, respectively. In the areas B and C, since the indefinite data which is unknown at either the H level or the L level is output, the white and black portions indicating the L and H levels are randomly displayed in the areas B and C, respectively.
[0100]
On the other hand, the defective addresses “120” and “200” of the column are shown as hatched areas D and E on the fail bit map. Therefore, by using the fail bitmap, the position of the defective address in the row and the column can be visually recognized, and the defect analysis can be easily performed.
[0101]
Next, an operation of determining whether or not a desired defective address is stored in row program circuit 14 and column program circuit 16 in semiconductor memory device 103 will be described with reference to FIGS. 5 and 6 again.
[0102]
First, L-level data is written to all normal memory cells. Next, the test mode signal TM is set to the H level. Then, the defective address CA of the column obtained by the wafer test is input to the redundancy control circuit 19d. At this time, if the defective address of the column matches the defective address CAPG stored in the column program circuit 14, an H-level signal CPD is output from the data terminal 22.
[0103]
On the other hand, when the defective address CA of the column does not match the defective address CAPG stored in the column program circuit 14, the data terminal 22 outputs an L-level signal RPD. Since the signal CPD which is supposed to be at the H level is output as the L level, the defective address is not correctly stored in the column program circuit 16, that is, the fuse group corresponding to the column defective address CA is correctly cut. It can be recognized that it has not been done.
[0104]
Next, the defective address RA of the row obtained by the wafer test is input to the redundancy control circuit 15, and the column address is sequentially input from "0" to "255" to the redundancy control circuit 19d. At this time, if the defective address RA of the row matches the defective address RAPG stored in the row program circuit 14, either the H or L level data is output from the data terminal 22 irregularly.
[0105]
When the defective address of the row and the defective address RAPG stored in the row program circuit 16 do not match, the L level signal RPD is output from the data terminal 22 because L level data is stored in each memory cell. Are output continuously. Originally, if either the H or L level data is output irregularly from the data terminal 22 but the L level signal is continuously output, the defective address is correctly stored in the row program circuit 16. That is, it can be recognized that the fuse group corresponding to the defective address RA of the row is not blown correctly.
[0106]
Note that the replacement relief operation at the time of data write operation and data read operation in semiconductor memory device 103 is the same as that of semiconductor memory device 106 if test mode signal TM is set to L level, and therefore detailed description will not be repeated. .
[0107]
As described above, the semiconductor memory device 103 according to the second embodiment is different from the first embodiment or the modification of the first embodiment in that a row and column program circuit is used instead of either a row or a column program circuit. In both cases, it is possible to detect whether or not the fuse is correctly blown and the defective address is normally stored. That is, with a slight circuit change, not only the row program circuit but also the data in the column program circuit can be efficiently output, and the failure analysis can be performed for the purpose of improving the yield of the semiconductor memory device.
[0108]
[Embodiment 3]
FIG. 8 is a block diagram showing a configuration of a semiconductor memory device 104 according to the third embodiment. The semiconductor memory device 104 has a function of specifying in which fuse group the defective address stored in the row program circuit 14 is stored.
[0109]
Referring to FIG. 8, semiconductor memory device 104 is different from semiconductor memory device 101 of FIG. 1 in that a redundant control circuit 40 is provided instead of redundant control circuit 19c. Other configurations are the same as those of semiconductor memory device 101 shown in FIG. 1, and thus detailed description will not be repeated. It is assumed that the memory cell array 10 has a configuration in which memory cells are arranged in 256 rows × 256 columns as an example, similarly to the semiconductor memory device 101. It is also assumed that column address CA is composed of eight bits CA <7: 0>. For example, when the column address CA is “14” of “0” to “255” indicated by the column address, the decimal number “14” is “00001110” when represented by a binary number. Therefore, the least significant bits CA <0> = 0, CA <1> = 1, CA <2> = 1, CA <3> = 1, CA <4> = 0, CA <5> = 0, CA <6 > = 0 and the most significant bit CA <7> = 0.
[0110]
FIG. 9 is an example of a circuit diagram showing the configuration of the redundancy control circuit 40.
Referring to FIG. 9, redundancy control circuit 40 includes AND circuits 35.0 to 35.3 corresponding to comparison circuits 31, respectively, as compared with redundancy control circuit 19 in FIG. , OR circuit 38.
[0111]
AND circuits 35.0-35.3 have spare enable signals RSPE <0> -RSPE <3> from each comparison circuit 31 and inversion of least significant bits CA <0> through CA <3> of column address CA. Signals / CA <0> to / CA <3> are input, respectively. The output signals of the AND circuits 35.0 to 35.3 are input to the OR circuit 38. Other configurations are the same as those of redundancy control circuit 19, and therefore detailed description will not be repeated.
[0112]
AND circuits 35.0-35.3 output signals / CA <0>-/ CA <corresponding to spare enable signals RSPE <0> -RSPE <3> and spare enable signals RSPE <0> -RSPE <3>, respectively. 3> is output. Hereinafter, the AND circuits 35.0 to 35.3 are collectively referred to as an AND circuit 35. Note that the configuration of the redundancy control circuit 40 is an example, and the number of the comparison circuit 31 and the AND circuit 35 may be four or more as long as the number is smaller than the number of bits of the column address CA.
[0113]
Next, an operation of outputting a defective address in the row program circuit 14 in the semiconductor memory device 104 will be described with reference to FIGS. As an example, the row program circuit 14 stores four defective addresses of rows, “20”, “40”, “70” and “100” of “0” to “255” indicated by the row address. Suppose you have been. It is assumed that row program circuit 14 includes fuse groups 0 to 3 (not shown). In general, defective addresses of rows are not always stored in ascending order for the fuse groups 0 to 3. However, here, for simplicity of explanation, as an example, defective addresses “20”, “40”, “70” and “100” of the rows are respectively corresponding to the fuse groups 0, 1, 2 and 3. Is stored. It is also assumed that defective addresses “20”, “40”, “70” and “100” of the row correspond to defective addresses RAPG <0> to RAPG <3>, respectively.
[0114]
First, the test mode signal TM is set to the H level. Next, the row address RA is fixed to “0”, and only the column address CA is input to the redundancy control circuit 19 in order from “0” to “255”.
[0115]
Next, "1" is added to the row address RA and fixed, and only the column address CA is input to the redundancy control circuit 19 in order from "0" to "255". The same operation as above is repeated for row addresses RA "2" to "255".
[0116]
As a result, when the row address RA becomes "20", the row address RA is fixed and only the column address CA "0" to "255" are sequentially input to the redundancy control circuit 19, so that the decimal number "0" The least significant bit CA <0> of the column address expressing "255" to "255" in binary is switched in the order of "0, 1", that is, L and H levels. Therefore, when defective address RAPG <0> representing defective address 20 of the row is input to comparison circuit 31.0, spare enable signal RSPE <0> attains H level. AND circuit 35.0 supplies an H level spare enable signal RSPE <0> and an inverted signal of CA <0> that switches in the order of L and H levels until column address CA changes from “0” to “255”. Is entered. Therefore, the output signal of AND circuit 35.0 alternates between H and L levels. As a result, the output signal RPD of the OR circuit 38 also switches alternately between the H and L levels, and the output terminal 22 outputs an alternate signal between the H and L levels.
[0117]
Next, when the row address RA changes to “40” and the column address CA changes from “0” to “255”, CA <1> becomes “0, 0, 1, 1”, that is, “L, L, H”. , H "level as one cycle. Therefore, the signal RPD switches with the “H, H, L, L” level as one cycle in the same operation as in CA <0>.
[0118]
Similarly, when the row address RA is “70”, CA <2> is “0, 0, 0, 0, 1, 1, 1, 1”, that is, “L, L, L, L, H, H”. , H, H "level as one cycle. Therefore, the signal RPD switches the “H, H, H, H, L, L, L, L” level as one cycle.
[0119]
Similarly, when the row address is “100”, CA <3> switches eight consecutive “0” s, that is, L level, and eight consecutive “1” s, that is, H level, as one cycle. Therefore, the signal RPD switches eight consecutive L levels to eight consecutive L levels as one cycle.
[0120]
FIG. 10 is a conceptual diagram visually showing positions of defective addresses according to the third embodiment in association with a part of the memory cell array.
[0121]
Referring to FIG. 10, defective addresses "20", "40", "70", and "100" of a row are shown as areas O, P, Q, and R on a fail bitmap, respectively. The area S indicates one of the defective addresses of the row in the row program circuit output in the configuration of the semiconductor memory device 101, for example. That is, the area S is the same as the one in which the H level is output in the row direction, similarly to the area C of the fail bit map in FIG.
[0122]
By associating the patterns of the regions O, P, Q, and R shown in the fail bit map with the fuse groups 0 to 3 in which the defective addresses are respectively stored, the defective addresses in a plurality of rows can be respectively specified. Thus, it is possible to specify which row of the defective address corresponds to which fuse group in the row program circuit 14 on the fail bit map.
[0123]
For example, when the pattern shown in the area O is displayed on the fail bit map, the defective addresses are associated with those stored in the fuse group 0. When "20" is stored in the fuse group 0 as the defective address of the row, the same pattern as that of the area O is displayed at the position of WL20 on the fail bit map. Therefore, it is understood that the defective address “20” of the row is stored in the fuse group 0.
[0124]
In the present embodiment, the fuse group corresponding to the row program circuit 14 corresponding to the defective addresses of a plurality of rows is specified. However, in the semiconductor memory device 102, the redundancy control circuit 19d is used instead of the redundancy control circuit 19d. 40, and if the input signals to the AND circuits 35.0 to 35.3 are / RA <0> to / RA <3>, the fuse address in the column program circuit can be similarly determined as the column defective address. Can be specified.
[0125]
Next, an operation of determining whether or not a desired defective address is stored in row program circuit 14 in semiconductor memory device 104 will be described with reference to FIGS. 8 and 9 again.
[0126]
First, the test mode signal TM is set to the H level. Then, the defective address RA of the row obtained by the wafer test is input to the redundancy control circuit 40. Then, the defective address RA of the row is fixed, and only the column address CA is input to the redundancy control circuit 19 in order from 0 to 255. If the defective address RA of the row matches the defective address RAPG stored in the row program circuit 14, the data terminal 22 outputs a signal RPD of a predetermined cycle of H and L levels.
[0127]
When the defective address of the row does not match the defective address RAPG stored in the row program circuit 16, the data terminal 22 continuously outputs the signal RPD of the L level. Originally, when a continuous L-level signal RPD is output from the data terminal 22 instead of the signal RPD in which the H and L levels change in a predetermined cycle, the defective address is not correctly stored in the row program circuit 14, ie, It can be recognized that the desired fuse is not blown correctly.
[0128]
Further, by associating a plurality of signals RPD having patterns of different periods of H and L levels with a plurality of fuse groups storing defective addresses, the fuse group corresponding to the input defective address can be correctly determined. It can be determined whether the connection has been disconnected.
[0129]
Note that the replacement repair operation in the data write operation and the data read operation in semiconductor memory device 104 is the same as that in semiconductor memory device 106 if test mode signal TM is set to L level, and therefore detailed description will not be repeated. .
[0130]
As described above, the semiconductor memory device 104 according to the third embodiment can specify a fuse group corresponding to a defective address, in addition to the effects of the semiconductor memory device 101 of the first embodiment. Therefore, the failure analysis in the program circuit can be performed more efficiently, and the yield of the semiconductor memory device can be further improved.
[0131]
[Embodiment 4]
FIG. 11 is a block diagram showing a configuration of a semiconductor memory device 105 according to the fourth embodiment. The semiconductor memory device 105 has a function of deactivating the redundancy control circuit.
[0132]
Referring to FIG. 11, semiconductor memory device 105 is different from conventional semiconductor memory device 106 of FIG. 14 in that redundant storage circuit 15b is provided instead of redundant control circuit 19, and semiconductor memory device 105 is replaced with redundant control circuit 19a. The difference is that a redundant control circuit 15c is provided and that inverters 41 and 42 are further provided. Inverters 41 and 42 output a signal of an inverted level of test mode signal TM.
[0133]
The semiconductor memory device 105 is further different from the semiconductor memory device 106 in that a signal having an inverted level of the test mode signal TM is input to the redundancy control circuits 15b and 15c. Other configurations are the same as those of semiconductor memory device 106 shown in FIG. 14, and thus detailed description will not be repeated. Note that the memory cell array 10 has a configuration in which memory cells are arranged in 256 rows × 256 columns, for example, as in the semiconductor memory device 106.
[0134]
FIG. 12 is a circuit diagram showing a configuration of a redundancy control circuit 15b according to the fourth embodiment.
[0135]
12, redundancy control circuit 15b is different from redundancy control circuit 15 of FIG. 6 in that NAND control circuit 39 is provided instead of inverter 33.
[0136]
The redundancy control circuit 15b is different from the redundancy control circuit 15 in that the NAND circuit 39 receives the output signal of the OR circuit 32 and the signal / TM at an inverted level of the test mode signal TM. Is not output to the selector 18. Other configurations are the same as those of redundancy control circuit 15, and therefore detailed description will not be repeated.
[0137]
In the redundancy control circuit 15b, in the test mode, since the signal / TM of the inverted level of the test mode signal TM of the H level is input to the NAND circuit 39, the normal enable signal RNE is always at the H level. Therefore, the defective word line is replaced with a spare word line and can be accessed, which cannot be accessed originally. Further, in the redundancy control circuit 15b, in the normal mode, the signal / TM at the inverted level of the L-level test mode signal TM is input to the NAND circuit 39, so that the normal enable signal RNE is supplied to the row address RA and the defective address RAPG <0; when p> coincides, it becomes L level.
[0138]
Referring to FIG. 11 again, redundancy control circuit 15c has the same function as redundancy control circuit 15b. The redundancy control circuit 15c is different from the redundancy control circuit 15b in that the column address CA is input instead of the row address RA, and the defective address CAPG <0: p> is used instead of the defective address RAPG <0: p>. Is input, a normal enable signal CNE is output instead of the normal enable signal RNE, and a spare enable signal CSPE <0: p> is output instead of the spare enable signal RSPE <0: p>. Are different. Therefore, in response to column address CA and defective address CAPG <0: p>, normal enable signal CNE and spare enable signal CSPE <0: p> indicating the result of comparison between the two are output.
[0139]
In the test mode, the signal / TM at the inverted level of the test mode signal TM at the H level is input to the redundancy control circuit 15c. The line becomes accessible.
[0140]
Next, the operation of semiconductor memory device 105 when redundancy control circuits 15b and 15c are inactivated will be described.
[0141]
When test mode signal TM is set at H level, spare enable signals RSPE and CSPE in redundancy control circuits 15b and 15c are always at L level, and semiconductor memory device 105 cannot perform the redundancy replacement operation. That is, the semiconductor memory device 105 can be virtually returned to the state before the fuse is cut.
[0142]
Then, the row address RA is fixed at "0", and the column address CA is sequentially input from "0" to "255" to the redundancy control circuit 15c.
[0143]
Next, the row address RA is fixed by adding "1", and the column address CA is sequentially input to the redundancy control circuit 15c from "0" to "255". The same operation as above is repeated for row addresses RA "2" to "255".
[0144]
Thus, an actual defective memory cell in the memory cell array 10 corresponding to the row address RA and the column address CA can be specified.
[0145]
FIG. 13 is a conceptual diagram visually showing positions of defective addresses according to the fourth embodiment in association with a part of the memory cell array.
[0146]
Referring to FIG. 13, the position of the defective memory cell in memory cell array 10 can be determined even after the fuse is blown, based on the state of black distribution in the fail bit map.
[0147]
Note that the replacement and relief operation at the time of data write operation and data read operation in semiconductor memory device 105 is the same as that of semiconductor memory device 106 if test mode signal TM is set to L level, and therefore detailed description will not be repeated. .
[0148]
As described above, semiconductor memory device 105 according to the fourth embodiment has a configuration in which the redundancy control circuit can be deactivated and virtually returned to the state before the fuse is cut. Thus, an actual defective memory cell in the memory cell array can be specified. Therefore, failure analysis is possible even after the fuse is cut.
[0149]
The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0150]
【The invention's effect】
A redundancy control unit having a function of determining a match between an input address and a defective address stored in the program circuit, and controlling access to a plurality of spare memory cells based on a result of the match comparison in a normal mode; By outputting the result of the match comparison in the test mode, data in the program circuit can be efficiently output, and a failure analysis can be performed for the purpose of improving the yield of the semiconductor memory device.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment.
FIG. 2 is a circuit diagram showing a configuration of a redundancy control circuit according to the first embodiment.
FIG. 3 is a conceptual diagram visually showing a position of a defective address in association with a memory cell array.
FIG. 4 is a block diagram showing a configuration of a semiconductor memory device according to a modification of the first embodiment.
FIG. 5 is a block diagram showing a configuration of a semiconductor memory device according to a second embodiment.
FIG. 6 is a circuit diagram showing a configuration of a redundancy control circuit according to a second embodiment.
FIG. 7 is a conceptual diagram visually showing positions of defective addresses according to a second embodiment in association with a memory cell array.
FIG. 8 is a block diagram showing a configuration of a semiconductor memory device according to a third embodiment.
FIG. 9 is an example of a circuit diagram showing a configuration of a redundancy control circuit.
FIG. 10 is a conceptual diagram visually showing a position of a defective address according to a third embodiment in association with a part of a memory cell array.
FIG. 11 is a block diagram showing a configuration of a semiconductor memory device according to a fourth embodiment.
FIG. 12 is a circuit diagram showing a configuration of a redundancy control circuit according to a fourth embodiment.
FIG. 13 is a conceptual diagram visually showing a position of a defective address according to a fourth embodiment in association with a part of a memory cell array.
FIG. 14 is a block diagram showing a configuration of a conventional semiconductor memory device having a redundant replacement configuration.
FIG. 15 is a circuit diagram showing a configuration of a redundancy control circuit.
FIG. 16 is a configuration diagram of a shift register for outputting a defective address stored in a program circuit.
[Explanation of symbols]
10 memory cell array, 11 row decoder, 12 read / write control circuit, 13 column decoder, 14 row program circuit, 18 selector, 15, 15b, 15c, 19, 19a, 19c, 19d, 40 redundancy control circuit, 21 address terminals , 22 data terminals, 33, 36, 41, 42 inverters, 34, 35, 37 AND circuits, 32, 38 OR circuits, 39 NAND circuits, 101, 102, 103, 104, 105 semiconductor memory devices.

Claims (11)

A semiconductor memory device having a normal mode and a test mode as operation modes,
A memory cell array in which a plurality of normal memory cells are arranged in a matrix,
The memory cell array includes a plurality of spare memory cells for replacing a defective memory cell among the plurality of normal memory cells for each predetermined unit,
A program circuit for nonvolatilely storing a defective address specifying the predetermined unit including the defective memory cell;
A redundancy control unit having a function of determining a match comparison between an input address and the defective address, and controlling access to the plurality of spare memory cells based on a result of the match comparison in the normal mode;
A semiconductor memory device further comprising: a test output circuit that outputs the result of the match comparison in the test mode. A read / write control circuit for performing data read and data write on the memory cell array;
A data terminal capable of exchanging data with an external device,
2. The semiconductor memory device according to claim 1, wherein said test output circuit includes a selector circuit for selectively connecting said read / write control circuit and said redundancy control unit to said data terminal according to said operation mode. The data terminal outputs the result of the match comparison from the redundancy control unit in the test mode, and inputs and outputs data written to the memory cell array and data read from the memory cell array in the normal mode. The semiconductor memory device according to claim 2. The program circuit stores at least one of the defective addresses;
The redundancy control unit includes:
At least one address comparing circuit provided corresponding to each of the at least one defective address and performing a match comparison between the corresponding defective address and the input address;
A detection circuit that outputs a result of the match comparison in accordance with an output from each of the at least one address comparison circuit;
2. The semiconductor memory device according to claim 1, wherein said plurality of spare memory cells are accessed according to outputs from each of said at least one address comparison circuit. The redundancy control unit, in the normal mode, when the input address and the defective address match, instructs suspension of access to the plurality of normal memory cells, and controls access to the plurality of spare memory cells. 2. The semiconductor memory device according to claim 1, wherein said instruction is issued. The input address includes first and second addresses;
The defective address includes first and second program addresses indicated by the first and second addresses, respectively.
The redundancy control unit includes:
A first redundancy control circuit that performs a match comparison between the first address and the first program address;
A second redundancy control circuit that performs a match comparison between the second address and the second program address,
The semiconductor memory device further includes a read circuit that executes data read for a memory cell selected by the first and second addresses among the plurality of normal memory cells and the plurality of spare memory cells,
A selector circuit for selectively outputting outputs of the read circuit and the second redundancy control circuit in the test mode according to a result of the coincidence comparison in the first redundancy control circuit; The semiconductor memory device according to claim 1, comprising: 2. The redundancy control unit according to claim 1, further comprising an access prohibition circuit for prohibiting access to the plurality of spare memory cells in the test mode regardless of a result of the match comparison from the test output circuit. Semiconductor storage device. In the test mode, the first redundancy control circuit instructs to suspend access to the plurality of spare memory cells regardless of a result of the comparison between the first address and the first program address. While instructing access to the plurality of normal memory cells,
The second redundancy control circuit instructs, when in the test mode, a match between the second address and the second program address is detected, to stop accessing the plurality of normal memory cells. 7. The semiconductor memory device according to claim 6, wherein an instruction is given to access to said plurality of spare memory cells. In the test mode, the first redundancy control circuit instructs to suspend access to the plurality of spare memory cells regardless of a result of the comparison between the first address and the first program address. While instructing access to the plurality of normal memory cells,
The second redundancy control circuit instructs, in the test mode, to halt access to the plurality of spare memory cells regardless of a result of the match comparison between the second address and the second program address. 7. The semiconductor memory device according to claim 6, further comprising: instructing access to said plurality of normal memory cells. The input address includes first and second addresses;
The defective address includes first and second program addresses indicated by the first and second addresses, respectively.
The first and second addresses are composed of a plurality of bits,
The program circuit includes a plurality of program element groups each storing a plurality of the first program addresses,
The redundancy control unit includes:
A plurality of address comparison circuits provided corresponding to the plurality of program element groups, respectively, for performing a match comparison between the corresponding first program address and the first address;
A plurality of logic operation circuits provided corresponding to the plurality of address comparison circuits, respectively.
The plurality of logical operation circuits each receive a different one of the plurality of bits forming the second address,
Each of the plurality of logical operation circuits outputs, as test data, a logical operation result of an output from the corresponding address comparison circuit and a corresponding one of the plurality of bits,
2. The semiconductor memory device according to claim 1, wherein in the test mode, the second address is sequentially updated such that the different bits change at different known cycles. Each of the plurality of logical operation circuits fixes the test data at a constant level when the corresponding first program address and the first address do not match, and sets the corresponding first program address and 11. The semiconductor memory device according to claim 10, wherein when the first address matches, the test data is set according to the corresponding one bit.

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