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JP2004032362A - Gain limiting circuit - Google Patents

Gain limiting circuit Download PDF

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Publication number
JP2004032362A
JP2004032362A JP2002185755A JP2002185755A JP2004032362A JP 2004032362 A JP2004032362 A JP 2004032362A JP 2002185755 A JP2002185755 A JP 2002185755A JP 2002185755 A JP2002185755 A JP 2002185755A JP 2004032362 A JP2004032362 A JP 2004032362A
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JP
Japan
Prior art keywords
signal
output
amplitude
output signal
gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP2002185755A
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Japanese (ja)
Inventor
Hisahito Watanabe
央人 渡邊
Takeyuki Takayama
強之 高山
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2002185755A priority Critical patent/JP2004032362A/en
Publication of JP2004032362A publication Critical patent/JP2004032362A/en
Withdrawn legal-status Critical Current

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  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

【課題】従来の利得制限回路を用いた場合,クリップ回路により信号が制限されると波形を著しくひずませることとなり,特に音声データを取り扱う場合,その信号の歪が高調波として出力され聴感を悪化させてしまう。
【解決手段】遅延素子3と,遅延素子3の出力信号の振幅を検出するレベル検出器4と,遅延素子3の出力信号にレベル検出器4の出力信号に応じた増幅度を持たせて出力させる増幅器6と,入力信号と増幅器6の出力の加(減)算した結果を遅延素子3に出力する加(減)算器2を備え、出力信号の利得制限を行う入力信号の振幅が大きくなるほど利得を下げて増幅することで,信号の振幅を抑え,クリップすることを防ぐ。
【選択図】 図1
When a signal is limited by a clipping circuit, a waveform is significantly distorted when a conventional gain limiting circuit is used. In particular, when audio data is handled, distortion of the signal is output as a higher harmonic wave, thereby deteriorating audibility. Let me do it.
A delay element, a level detector for detecting the amplitude of an output signal of the delay element, and an output signal of the delay element having an amplification degree corresponding to the output signal of the level detector are output. And an adder (subtractor) 2 for outputting the result of addition (subtraction) of the input signal and the output of the amplifier 6 to the delay element 3. The amplitude of the input signal for limiting the gain of the output signal is large. By reducing the gain as much as possible and amplifying the signal, the amplitude of the signal is suppressed and clipping is prevented.
[Selection diagram] Fig. 1

Description

【0001】
【発明の属する技術分野】
本発明は,ディジタルオーディオ装置などに利用し,出力信号の過大出力を自動的に抑制するディジタル信号処理によるオーディオ信号の利得制限回路に関する。
【0002】
【従来の技術】
図3において,従来の利得制限回路を示す。入力端子1からの入力信号を遅延素子3によりフィルタリングを行い特定の帯域信号を抽出し,得られた信号を増幅器7により増幅し,クリップ回路9により出力端子8で許容されている最大値以上,最小値以下が出力されないように信号振幅を制限する。
【0003】
図4は図3で得られる入力信号振幅と出力信号振幅の関係を示す図である。入力信号がある一定レベルまでは増幅されているが,出力信号が許容されている最大値,または最小値に達するとそれ以上振幅が大きくならないので一定振幅を得ることとなる。
【0004】
【発明が解決しようとする課題】
しかしながら,上記従来の利得制限回路を用いた場合,クリップ回路9により信号が制限されると波形を著しくひずませることとなり,特に音声データを取り扱う場合,その信号の歪が高調波として出力され聴感を悪化させてしまう。
【0005】
本発明は、上記課題を解決するために,入力信号の振幅が大きくなるほど利得を下げて増幅することで,信号の振幅を抑え,クリップすることを防ぐ利得制限回路を提供することを目的とする。
【0006】
【課題を解決するための手段】
本発明は,遅延素子と,前記遅延素子の出力信号の振幅を検出する検出器と,前記遅延素子の出力信号に前記検出器の出力信号に応じた増幅度を持たせて出力させる増幅器と,入力信号と前記増幅器の出力の加(減)算した結果を前記遅延素子に出力する加(減)算器を備え,出力信号の利得を制限する構成である。
【0007】
本発明は上記した構成によって,入力信号の過大入力に対しても滑らかな利得制限特性を以って増幅効果を得ることができる。
【0008】
【発明の実施の形態】
図1は本発明の一実施の形態に係る利得制限回路の構成を示すブロック図である。図1において、遅延素子3,増幅器7は図3に示したものと同じである。更に,加算器2,レベル検出器4,制御回路5,増幅器6により,利得制限のための帰還回路が構成される。
【0009】
以上のように構成された本実施の形態の動作を以下に説明する。
【0010】
まず,入力端子1より入力された信号は,加(減)算器2で増幅器6により生成された帰還信号と演算され,その演算結果が遅延素子3に入力される。ここで遅延素子3は,フィルタなどの帯域制限回路であり,その出力は増幅器7により増幅され出力端子8より出力される一方,レベル検出器4により遅延素子3の出力振幅を検出し,その検出結果より制御回路5で増幅器6の増幅度を決定する。
【0011】
ここで,制御回路5は入力に対して定数を乗算させるのみで出力させても,利得制限の特性を得ることができる。増幅器6では、遅延素子3の出力信号を増幅し,加(減)算器2で入力端子1より入力された信号との演算結果を再び遅延素子3に入力させ帰還をかける。
【0012】
このような構成により,入力端子1より過大信号が入力した時でも,その振幅レベルが大きいほど負帰還が多くかかるので、遅延素子3での出力振幅は抑えられ,負帰還の強さを制御回路5で適切に設定すれば,増幅器7で信号を増幅しても出力端子8の出力許容範囲を超えないようにすることができる。
【0013】
図2は,本実施の形態において,制御回路5に閾値設定を持たせた場合の入力端子1と出力端子8での信号の振幅特性図であり,破線で示されている特性は増幅器7のみで得られる特性,実線は本実施の形態の特性である。以下に本実施の形態の動作を説明する。
【0014】
まず、制御回路5にて,設定された閾値とレベル検出回路4で得られた振幅値を比較し,振幅値のほうが小さい時,つまり,入力端子1より入力される信号が小さい時は,制御回路5より増幅器6の増幅度をゼロとして帰還信号の生成を行わない。
【0015】
このことにより,加(減)算器2で信号の振幅を減ずることなく遅延素子3を経由して増幅器7で増幅される。また制御回路5にて設定された閾値よりレベル検出器4で得られた振幅値の方が大きい場合,制御回路5で増幅器6の増幅度を設定することで帰還信号を生成し,加(減)算器2に入力することで帰還をかける。
【0016】
つまり,制御回路5に閾値設定を持たせた場合,入力端子1からの信号振幅により利得制限を行うか,行わないかの決定をさせることができ,信号振幅が小さい場合は十分な増幅が行われ,大きくなると利得制限を行い、出力振幅を抑えることができる。ここで制御回路5は,レベル検出器4の出力に対して,演算を行う演算器や,対応した係数を出力するテーブルなどでも構成が可能である。
【0017】
またレベル検出器4において,検出した信号の振幅値が大きくなるときには検出器の出力信号を素早く変化させ,検出した信号の振幅値が小さくなるときには検出器の出力信号をゆっくり変化させる回路,例えば検波回路を用いれば,この変化に合わせて増幅器6の増幅度を制御回路5により変化させることで,入力端子1に過大な信号が入力されても素早く帰還がかかり利得を制御することができる。
【0018】
逆に入力端子1の信号振幅が急に小さくなるような場合,ゆっくり帰還を弱めることで,制限されていたゲインを徐々に復帰させることで滑らに振幅を変化させることができる。
【0019】
尚、前記遅延素子としてローパスフィルタを用いることで,入力信号の低域成分の過大入力に対しても出力信号のクリップを防ぎ,滑らかな波形を出力することができる。
【0020】
【発明の効果】
以上のように本発明は,遅延素子の出力に,その信号振幅レベルを検出し決定された増幅度を持たせた信号を遅延素子の入力部に負帰還させることにより遅延素子の出力で得られる振幅を制限させ増幅させることで,出力端子で許容されている振幅範囲内で滑らかな利得制限特性を以って増幅効果を得ることができる。また,クリップ回路のような高周波歪は発生しないので,特に音声信号の利得制限回路として有用である。
【図面の簡単な説明】
【図1】本発明の一実施の形態に係る利得制限回路の構成を示すブロック図
【図2】本実施の形態の利得制限回路の振幅特性図
【図3】従来の利得制限回路の構成を示すブロック図
【図4】従来の利得制限回路の振幅特性図
【符号の説明】
1 入力端子
2 加(減)算器
3 遅延素子
4 レベル検出器
5 制御回路
6 増幅器
7 増幅器
8 出力端子
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a gain limiting circuit for an audio signal by digital signal processing which is used in a digital audio device or the like and automatically suppresses an excessive output of an output signal.
[0002]
[Prior art]
FIG. 3 shows a conventional gain limiting circuit. The input signal from the input terminal 1 is filtered by the delay element 3 to extract a specific band signal, the obtained signal is amplified by the amplifier 7, and the clipping circuit 9 exceeds the maximum value allowed at the output terminal 8, The signal amplitude is limited so that a value less than the minimum value is not output.
[0003]
FIG. 4 is a diagram showing the relationship between the input signal amplitude and the output signal amplitude obtained in FIG. Although the input signal is amplified to a certain level, the amplitude does not increase further when the output signal reaches the maximum value or the minimum value allowed, so that a constant amplitude is obtained.
[0004]
[Problems to be solved by the invention]
However, when the above-described conventional gain limiting circuit is used, if the signal is limited by the clipping circuit 9, the waveform is significantly distorted. In particular, when audio data is handled, the distortion of the signal is output as harmonics, and the audibility is reduced. Will make it worse.
[0005]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a gain limiting circuit that suppresses signal amplitude and prevents clipping by lowering and amplifying the gain as the amplitude of the input signal increases, in order to solve the above problem. .
[0006]
[Means for Solving the Problems]
The present invention provides a delay element, a detector for detecting an amplitude of an output signal of the delay element, an amplifier for causing the output signal of the delay element to have an amplification degree corresponding to the output signal of the detector, and outputting the amplified signal. An adder / subtractor that outputs the result of addition (subtraction) of the input signal and the output of the amplifier to the delay element is provided to limit the gain of the output signal.
[0007]
According to the present invention, with the above-described configuration, an amplification effect can be obtained with a smooth gain limiting characteristic even for an excessive input of an input signal.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing a configuration of a gain limiting circuit according to one embodiment of the present invention. 1, the delay element 3 and the amplifier 7 are the same as those shown in FIG. Further, the adder 2, the level detector 4, the control circuit 5, and the amplifier 6 constitute a feedback circuit for limiting the gain.
[0009]
The operation of the present embodiment configured as described above will be described below.
[0010]
First, the signal input from the input terminal 1 is operated by the adder (subtractor) 2 with the feedback signal generated by the amplifier 6, and the operation result is input to the delay element 3. Here, the delay element 3 is a band limiting circuit such as a filter, the output of which is amplified by an amplifier 7 and output from an output terminal 8, while the level detector 4 detects the output amplitude of the delay element 3 and detects the output amplitude. Based on the result, the control circuit 5 determines the degree of amplification of the amplifier 6.
[0011]
Here, the gain limiting characteristic can be obtained even if the control circuit 5 outputs the signal only by multiplying the input by a constant. The amplifier 6 amplifies the output signal of the delay element 3, and the adder (subtractor) 2 again inputs the operation result with the signal input from the input terminal 1 to the delay element 3 to apply feedback.
[0012]
With this configuration, even when an excessive signal is input from the input terminal 1, the negative feedback increases as the amplitude level increases, so that the output amplitude at the delay element 3 is suppressed, and the strength of the negative feedback is controlled by the control circuit. If the setting is appropriately made in step 5, even if the signal is amplified by the amplifier 7, the output allowable range of the output terminal 8 can be prevented from being exceeded.
[0013]
FIG. 2 is a diagram showing the amplitude characteristics of the signals at the input terminal 1 and the output terminal 8 when the control circuit 5 has a threshold setting in the present embodiment. , And the solid line is the characteristic of the present embodiment. The operation of the present embodiment will be described below.
[0014]
First, the control circuit 5 compares the set threshold value with the amplitude value obtained by the level detection circuit 4, and when the amplitude value is smaller, that is, when the signal input from the input terminal 1 is smaller, the control circuit 5 The circuit 5 sets the amplification degree of the amplifier 6 to zero and does not generate a feedback signal.
[0015]
As a result, the signal is amplified by the amplifier 7 via the delay element 3 without reducing the amplitude of the signal by the adder / subtractor 2. When the amplitude value obtained by the level detector 4 is larger than the threshold value set by the control circuit 5, a feedback signal is generated by setting the amplification degree of the amplifier 6 by the control circuit 5, and a feedback signal is generated. ) Feedback is applied to the input to the arithmetic unit 2.
[0016]
In other words, when the control circuit 5 is provided with a threshold setting, it is possible to determine whether to perform gain limitation or not based on the signal amplitude from the input terminal 1. When the signal amplitude is small, sufficient amplification is performed. However, when it becomes large, the gain is limited and the output amplitude can be suppressed. Here, the control circuit 5 can be configured with an arithmetic unit that performs an operation on the output of the level detector 4, a table that outputs the corresponding coefficient, and the like.
[0017]
Also, in the level detector 4, a circuit that changes the output signal of the detector quickly when the amplitude value of the detected signal increases, and changes the output signal of the detector slowly when the amplitude value of the detected signal decreases, for example, detection. If a circuit is used, by changing the amplification degree of the amplifier 6 by the control circuit 5 in accordance with this change, even if an excessive signal is input to the input terminal 1, feedback is quickly performed and the gain can be controlled.
[0018]
On the other hand, when the signal amplitude at the input terminal 1 suddenly decreases, the amplitude can be smoothly changed by gradually reducing the feedback by gradually weakening the feedback.
[0019]
By using a low-pass filter as the delay element, clipping of the output signal can be prevented even for an excessive input of a low-frequency component of the input signal, and a smooth waveform can be output.
[0020]
【The invention's effect】
As described above, the present invention can be obtained at the output of the delay element by negatively feeding back the signal having the determined amplification degree by detecting the signal amplitude level of the output of the delay element to the input section of the delay element. By limiting and amplifying the amplitude, an amplification effect can be obtained with a smooth gain limiting characteristic within the amplitude range allowed at the output terminal. Further, since high-frequency distortion unlike a clipping circuit does not occur, it is particularly useful as a gain limiting circuit for audio signals.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a gain limiting circuit according to an embodiment of the present invention; FIG. 2 is an amplitude characteristic diagram of the gain limiting circuit of the present embodiment; FIG. FIG. 4 is an amplitude characteristic diagram of a conventional gain limiting circuit.
Reference Signs List 1 input terminal 2 adder (subtractor) 3 delay element 4 level detector 5 control circuit 6 amplifier 7 amplifier 8 output terminal

Claims (5)

遅延素子と,前記遅延素子の出力信号の振幅を検出する検出器と,前記遅延素子の出力信号に前記検出器の出力信号に応じた増幅度を持たせて出力させる増幅器と,入力信号と前記増幅器の出力の加(減)算した結果を前記遅延素子に出力する加(減)算器を備え、出力信号の利得制限を行うことを特徴とする利得制限回路。A delay element, a detector for detecting an amplitude of an output signal of the delay element, an amplifier for outputting the output signal of the delay element with an amplification degree corresponding to the output signal of the detector, and an input signal; A gain limiting circuit, comprising: an adder / subtractor that outputs a result of addition / subtraction of an output of an amplifier to the delay element, and limits a gain of an output signal. 前記遅延素子としてローパスフィルタを用いることで,入力信号の低域成分の過大入力に対しても出力信号のクリップを防ぎ,滑らかな波形を出力することを特徴とする請求項1記載の利得制限回路。2. The gain limiting circuit according to claim 1, wherein the use of a low-pass filter as the delay element prevents clipping of the output signal even for an excessive input of a low-frequency component of the input signal and outputs a smooth waveform. . 前記検出器において,検出した振幅値が設定値以下では前記増幅器の増幅度をゼロとする信号を,設定値以上では前記増幅器に前記検出器出力に応じた増幅度を持たせる信号を出力することで,設定値により入力信号の振幅に応じて出力信号の利得特性を変化させることを特徴とする請求項1記載の利得制限回路。The detector outputs a signal that makes the amplification of the amplifier zero when the detected amplitude value is equal to or less than a set value, and outputs a signal that causes the amplifier to have an amplification corresponding to the detector output when the detected amplitude value is equal to or more than the set value. 2. The gain limiting circuit according to claim 1, wherein the gain characteristic of the output signal is changed according to the amplitude of the input signal according to the set value. 前記検出器において,検出した信号の振幅値が大きくなるときには検出器の出力信号を素早く変化させ,検出した信号の振幅値が小さくなるときには検出器の出力信号をゆっくり変化させることで,過大な入力信号に対して出力信号のゲインを素早く抑え,過大入力信号後の出力信号のゲインを復帰をゆっくりと変化させることで滑らかな波形を出力できることを特徴とする請求項1記載の利得制限回路。In the detector, when the amplitude value of the detected signal is large, the output signal of the detector is changed quickly, and when the amplitude value of the detected signal is small, the output signal of the detector is changed slowly, so that an excessive input 2. The gain limiting circuit according to claim 1, wherein a smooth waveform can be output by quickly suppressing the gain of the output signal with respect to the signal and slowly changing the return of the gain of the output signal after the excessive input signal. フィルタ回路と,前記フィルタ回路の出力信号の振幅を検出する検出器と,前記フィルタ回路の出力信号に前記検出器で検出した振幅に応じた増幅度を持たせて出力させる増幅器と,入力信号と前記増幅器の出力の加(減)算した結果を前記フィルタ回路に出力する加(減)算器を備えたことを特徴とする利得制限回路。A filter circuit, a detector for detecting an amplitude of an output signal of the filter circuit, an amplifier for outputting an output signal of the filter circuit with an amplification degree corresponding to the amplitude detected by the detector, and an input signal. A gain limiting circuit comprising an adder (subtractor) for outputting a result of addition (subtraction) of the output of the amplifier to the filter circuit.
JP2002185755A 2002-06-26 2002-06-26 Gain limiting circuit Withdrawn JP2004032362A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007089029A (en) * 2005-09-26 2007-04-05 Nippon Hoso Kyokai <Nhk> Acoustic signal compression apparatus and acoustic signal compression program
JP2014175838A (en) * 2013-03-08 2014-09-22 Pioneer Electronic Corp Acoustic device, method for controlling acoustic device, and program
CN113113042A (en) * 2021-04-09 2021-07-13 广州慧睿思通科技股份有限公司 Audio signal processing method, device, equipment and storage medium

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007089029A (en) * 2005-09-26 2007-04-05 Nippon Hoso Kyokai <Nhk> Acoustic signal compression apparatus and acoustic signal compression program
JP2014175838A (en) * 2013-03-08 2014-09-22 Pioneer Electronic Corp Acoustic device, method for controlling acoustic device, and program
CN113113042A (en) * 2021-04-09 2021-07-13 广州慧睿思通科技股份有限公司 Audio signal processing method, device, equipment and storage medium

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