JP2004030362A - Load module generation method, load module generation program, and load module generation device - Google Patents

Abstract

[PROBLEMS] Even if a plurality of partial programs for reading and writing the same data are assigned to a plurality of processors sharing a main memory and executed, respectively, between a cache memory and a main memory of each processor or between cache memories. To generate a program load module in which the cache coherency is automatically maintained.
A compiler specifies data shared by a plurality of partial programs and adds predetermined identification information (a prefix such as "__shr_") to the data, and the identification information is added when the linker combines the programs. Only the extracted data is extracted to form a shared data area. This area is located in the area specified as non-cacheable in the memory space when the program is executed, so the shared data is not copied to the cache memory, and the only value in main memory is always referred to・ It will be updated.
[Selection diagram] Fig. 4

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a load module generation method, a load module generation program, and a load module generation device that are configured by a plurality of partial programs, and each of the partial programs generates a load module of a program executed by a plurality of processors.
[0002]
[Prior art]
2. Description of the Related Art In a computer system, a cache mechanism may be provided between a processor and a main memory in order to improve processing performance by utilizing locality of reference at the time of program execution.
[0003]
This cache mechanism has a cache memory which has a smaller capacity than the main memory but is readable and writable at high speed, and reads and writes the cache memory or the main memory in response to a read / write request from the processor. At this time, in order to utilize the locality of reference, the contents (values) of the memory area of the main memory once read and written are copied to the cache memory. With respect to the copied memory area, it is only necessary to read and write the data in the cache memory instead of the main memory, and the processing speed is increased.
[0004]
By the way, in recent computer systems, there is an example in which a plurality of processors are mounted and the processing capacity is improved by allocating each partial program in the program to these processors. Such a technique is called “shared-memory multiprocessors”. Also, in this shared memory type multiprocessor system, providing a cache mechanism for each processor as shown in FIG. 10 is effective in improving the processing performance.
[0005]
However, in the above method, since a plurality of cache memories are provided, the values of the memory area specified by the same address may not match between each cache memory and the main memory. This means that a read from an arbitrary processor to an arbitrary memory area in the main memory does not always return the latest value held in the area, and the "cache coherence problem" (cache coherence problem). problem).
[0006]
In the prior art, this problem is usually solved in hardware by a physical mechanism called a "cache coherency mechanism". This is based on a cache consistency protocol that monitors the position of data read and written by a plurality of partial programs (hereinafter collectively referred to as “shared data”) and prevents old data before updating from being cached. Based on this, it guarantees the coherency of the cache.
[0007]
FIG. 11 is an explanatory diagram showing an example of a memory map in the case where cache coherency is ensured by the cache coherency mechanism. In the figure, a text area 1100 is an area for holding a sequence of instructions of a program, and a data area 1101 is an area for holding data (whether or not it is shared data) read / written from the program.
[0008]
Each of these two areas is a cache target area, that is, an area that may be copied to the cache memory. Therefore, the shared data may be copied to the cache memories of a plurality of processors while executing the partial program sharing the data, but the cache coherency mechanism described above causes the value of each cache memory to be copied. (And the value of the main memory) are always controlled to match.
[0009]
[Problems to be solved by the invention]
However, in such a hardware method, there is a problem that the circuit size of the processor becomes large because the cache coherence mechanism itself is complicated.
[0010]
In the past, the shared memory multiprocessor method was mainly used for high-end products, so this point was not a problem.However, in the future, multiple processors will be used in general-purpose printers, digital cameras, digital televisions, etc. Considering that the processor is installed, it is necessary to avoid the processor from becoming large / heavy or increasing the product price just to guarantee the coherency of the cache.
[0011]
The present invention solves the above-mentioned problem of the prior art by software, so that even if a plurality of partial programs sharing the same data are respectively executed by separate processors, cache coherency is automatically maintained. It is an object to provide a load module generation method, a load module generation program, and a load module generation device capable of generating a load module.
[0012]
[Means for Solving the Problems]
In order to solve the above-described problem and achieve the object, a load module generation method, a load module generation program, or a load module generation device according to the present invention is configured by a plurality of partial programs, and each of the partial programs is executed by a plurality of processors. In a load module generation method for generating a load module of a program to be executed, it is determined whether or not each data included in the program is data read and written by at least two of the plurality of partial programs. It is determined to add predetermined identification information to the data determined to be such data, and to combine the data with the identification information added thereto and arrange the data in the non-cache target area in the memory space. The method is characterized in that a region is formed.
[0013]
Further, a load module generation method according to the present invention is characterized in that a predetermined prefix is added to the shared data as the identification information.
[0014]
The load module generation method according to the present invention is characterized in that information for designating a section to which the shared data belongs is added as the identification information.
[0015]
In addition, a load module generation method, a load module generation program, or a load module generation device according to the present invention includes a plurality of partial programs, and each of the partial programs generates a load module of a program that is executed by a plurality of processors. In the load module generation method, it is determined whether individual data included in the program is data read and written by at least two of the plurality of partial programs, and the data is determined to be such data. A cache invalidation operation is added to the determined data.
[0016]
Further, the load module generation method according to the present invention is characterized in that, as the cache invalidation operation, immediately before a read instruction for the shared data, an invalidate instruction for a cache of the data is inserted.
[0017]
When the load module generated by these inventions is executed, data shared by a plurality of partial programs is not copied to the cache memory of the processor in the first place, or is copied but erased at the time of reading. The value of the main memory will be referenced and updated.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of a load module generation method, a load module generation program, and a load module generation device according to the present invention will be described in detail with reference to the accompanying drawings.
[0019]
As described above, in the prior art, the data consistency between the cache memory and the main storage or between the cache memories is guaranteed by using hardware called a cache coherency mechanism. The policy is to solve the cache coherency problem exclusively with software. It may be said that the cache coherency is not the processor executing the program but the program executed by the processor.
[0020]
The following two methods have been proposed in theory as solutions to this policy (cf. Shimmer, Cart "UNIX (R) Kernel Internal Analysis-Cache and Multiprocessor Management", SoftBank Corp.).
[0021]
(1) A method in which shared data in a program is not cached in the first place, that is, a value in a main memory is always read and written to prevent a situation in which copies of the shared data are scattered at a plurality of locations. Hereinafter, it is referred to as “uncached shared data method”.
[0022]
Some processors having an MMU (Memory Management Unit) can designate an arbitrary area in a memory space as an area not copied to a cache memory. For example, in SPARC, an arbitrary area can be excluded from the cache by turning off the C bit (cacheable bit) of the page table entry of the MMU.
[0023]
This function is mainly provided because it is not necessary to provide an I / O space separately from the memory space, and when a part of the memory space is used as the I / O space, the relevant area must be excluded from the cache target. Is what is being done. For the I / O, if a cache is present, a problem such as the inability to read / write the latest value occurs. Therefore, it is reasonable to set the cache not to be used even if the processing speed is sacrificed.
[0024]
If this function is diverted to provide a non-cacheable area in the memory space of the processor and the shared data is arranged exclusively in this area, the non-shared data, that is, the Therefore, only data unique to the partial program being executed is stored, and since there is no cache for shared data, the value in the main memory is always read and written.
[0025]
FIG. 1 is an explanatory diagram showing an example of a memory map in a case where coherency of a cache is guaranteed by an uncached shared data method. In the drawing, a text area 100 is an area for holding a sequence of instructions of a program, and a data area 101 is an area for holding, in particular, non-shared data among data read / written from the program. Each of these two areas is a cache target area, that is, an area that may be copied to the cache memory.
[0026]
On the other hand, the shared data area 102 is an area for holding, in particular, shared data among data read and written from the program. This area is a non-cacheable area, that is, an area that is not likely to be copied to the cache memory.
[0027]
Embodiments 1 and 2 described below are intended to guarantee the coherency of the cache by using the “uncached shared data method”. More specifically, on the premise of the above, the present invention relates to a procedure of how to form each of the above-mentioned regions arranged at different locations in the memory space when a program load module is generated.
[0028]
(2) Both shared data and non-shared data are cached without distinction, but for shared data, the value in the main memory is always read by invalidating the data in the cache memory immediately before reading. A method that ignores the upper cache. Hereinafter, it is referred to as a “selective cache invalidation operation method”. Selective is that the cache is not invalidated for non-shared data.
[0029]
The cache mechanism has a write-through cache in which the value of the main memory is simultaneously updated with the value of the cache memory just by executing a store instruction.To reflect the update in the cache memory to the main memory, There are two types, a write-back cache in which a flush instruction must be executed again after a store instruction. The procedure of the above-mentioned "invalidation operation" differs depending on the type of the cache mechanism.
[0030]
That is, in the case of the write-through type, since the latest value is always held in the main memory, executing the invalidate instruction before reading the shared data allows the cache memory to remain in its own cache memory. You only need to delete that copy. On the other hand, in the case of the write-back type, first, the flash instruction is executed to update the value in the main memory with the value in the cache memory, that is, the value in the main memory is updated to the latest value, and then the This is a two-stage configuration in which the cache is erased and the value in the main memory is read by the validate instruction.
[0031]
FIG. 2 is an explanatory diagram illustrating an example of a memory map in a case where cache coherency is ensured by a selective cache invalidation operation method. In the figure, a text area 200 is an area for holding a sequence of instructions of a program, a data area 201 is an area for holding, in particular, non-shared data among data read and written from the program, and a shared data area 202 is an area for holding shared data. These three areas are all cache target areas.
[0032]
The third embodiment described below intends to guarantee the coherency of the cache by this “selective cache invalidation operation method”. More specifically, shared data is specified in advance when a program load module is generated, and a cache invalidation operation is performed immediately before a load instruction of the data, that is, an invalidate instruction and a write-back instruction in a write-through cache. This is related to the procedure of inserting a flash instruction + invalidate instruction in the cache.
[0033]
(Embodiment 1)
FIG. 3 is a block diagram illustrating an example of a hardware configuration of the load module generation device according to the first embodiment of the present invention.
[0034]
In the figure, first, a CPU 301 controls the entire apparatus. The ROM 302 stores a boot program and the like. The RAM 303 is used as a work area of the CPU 301. The HDD 304 controls reading / writing of data from / to the HD 305 under the control of the CPU 301. The HD 305 stores data written under the control of the HDD 304.
[0035]
The FDD 306 controls reading / writing of data from / to the FD 307 under the control of the CPU 301. The FDD 307 stores the data written under the control of the FDD 306 and causes the magnetic head of the FDD 306 to read the stored data. As the removable recording medium, in addition to the FD 307, a CD-ROM, a CD-R, a CD-RW, an MO, a DVD (Digital Versatile Disk), a memory card, and the like can be considered.
[0036]
The display 308 is, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like, and displays various data such as a document and an image, in addition to a cursor and a window. The network I / F 309 is connected to the LAN via the Ethernet (R) cable 310 and controls transmission and reception of data between the LAN and the inside of the apparatus.
[0037]
The keyboard 311 includes keys for inputting characters, numerical values, various instructions, and the like, and performs input of data into the apparatus. It may be a touch panel type input pad or a numeric keypad. The mouse 312 is used to move a cursor, select a range, and the like. A trackball, a joystick, a cross key, a jog dial, or the like may be used as long as the pointing device has a similar function. Note that the above components are connected by a bus or a cable 300.
[0038]
Next, FIG. 4 is a block diagram functionally showing the configuration of the load module generation device according to the first embodiment of the present invention. The CPU 301 reads out the programs stored in the HD 305 and the FD 307 shown in FIG. 3, specifically, the three programs of the compiler, the assembler, and the linker into the RAM 303 and executes the programs. This is achieved by doing
[0039]
In the figure, reference numerals 400 to 404 denote compilers, 405 to 407 denote assemblers, and 408 to 412 denote functional units realized by linkers. The function of each functional unit will be described with reference to a flowchart described immediately below.
[0040]
Next, FIG. 5 is a flowchart illustrating a procedure of a load module generation process in the load module generation device according to the first embodiment of the present invention.
[0041]
In the above device, a compiler is first activated, and a first analyzer 400 implemented by the compiler reads a source description of a specified program, performs lexical analysis and syntax analysis, and converts the program into an internal representation of the compiler. Conversion is performed (step S501).
[0042]
Next, the shared data determination unit 401 scans the internal representation of the compiler to determine whether individual data included therein is shared data between partial programs. At this time, an identifier to that effect is added to the data determined to be shared data (step S502).
[0043]
Next, the shared data identification information adding unit 402 scans the internal expression of the compiler and searches for the data to which the identifier has been added in step S502. Then, a predetermined prefix is added to the head of the data name as identification information of the searched shared data (step S503). Note that the prefix may be a character string “__shr_” or the like.
[0044]
Next, the instruction sequence generation unit 403 generates an instruction sequence for realizing the operation of the program based on the internal expression of the compiler, and adds the instruction sequence to the internal information of the compiler (step S504).
[0045]
Next, the assembly description output unit 404 outputs the assembly description of the program based on the internal expression of the compiler and the added instruction sequence (step S505). Thus, the conversion process from the source description to the assembly description by the compiler is completed.
[0046]
Next, in the above apparatus, an assembler is started, and the second analysis unit 405 implemented by the assembler reads the assembly description output from the assembly description output unit 404 of the compiler in step S505, performs lexical analysis, and performs the lexical analysis. It is converted to an internal representation (step S506).
[0047]
Next, the binary code generation unit 406 generates a binary code (including an instruction code) based on the internal representation of the assembler, and adds the code to the internal information of the assembler (step S507).
[0048]
Next, the object output unit 407 outputs an object of the program based on the internal expression of the assembler and the added binary code (step S508). Thus, the conversion process from the assembly description to the object code by the assembler is completed.
[0049]
Next, in the above apparatus, a linker is activated, and the object reading unit 408 realized by the linker reads the object output from the object output unit 407 of the assembler in step S508 as an internal representation of the linker (step S509).
[0050]
Next, the shared data area forming unit 409 searches for data having identification information indicating that the data is shared data (such as “__shr_” described above) in the internal representation of the linker. Then, an area (shared data area 102 shown in FIG. 1) composed only of these shared data is formed and added as an internal expression of the linker (step S510).
[0051]
Next, the memory space construction unit 410 forms, in the internal representation of the linker, an area composed of only the remaining unshared data (data area 101) and an area composed of only the instruction sequence (text area 100). It is added as an internal expression (step S511).
[0052]
Next, the address resolution unit 411 resolves the addresses of the memory areas of the text area 100, the data area 101, and the shared data area 102 in the internal representation of the linker (step S512).
[0053]
Next, the load module output unit 412 outputs the load module of the program based on the internal representation of the linker (step S513). Thus, the linking of the object code by the linker is completed, and the process of converting the program from the source to the load module is completed.
[0054]
According to the first embodiment described above, identification information (specifically, a prefix such as “__shr_”) is attached to data shared by a plurality of partial programs, and at the time of linking, only this shared data is first used. Is extracted to form a shared data area 102, then a data area 101 is formed by the remaining unshared data, and a text area 100 is formed by the remaining instruction sequence.
[0055]
As described above, since the shared data and the non-shared data are previously grouped in different areas when the load module is generated, the shared data, that is, the shared data area 102 is cached in the non-cache target area, and the non-shared data, that is, the data area 101 is cached, during execution. By arranging the shared data in the target area, it is possible to prevent the shared data from being distributed to the cache memories of the respective processors, thereby maintaining the coherency of the cache.
[0056]
(Embodiment 2)
By the way, in the first embodiment described above, the shared data marked in advance is so-called separated before the construction of the memory space by the linker. However, this is not the case with the prior art linker. This is because there is no idea of separately combining shared data. That is, since the data is simply combined in the order described in the source, unless only the shared data is first separated in step S510, an area in which the shared data and the non-shared data are mixed in the subsequent step S511. This is because it is formed.
[0057]
However, the linker according to the related art also has a function of collecting data in the same section into one block and arranging each block in a different memory area. Therefore, if a shared data portion is designated as section A and a non-shared data portion is designated as section B using a section designation pseudo instruction of an assembler as in the second embodiment described below, Within the framework of memory space construction processing by the technology linker, shared data and non-shared data can be combined into separate blocks.
[0058]
The hardware configuration of the load module generation device according to the second embodiment is the same as that of the first embodiment shown in FIG. FIG. 6 is a block diagram functionally showing the configuration of the load module generation device according to the second embodiment of the present invention, and FIG. 7 is a flowchart showing the procedure of a load module generation process in the device. The difference from the first embodiment is that FIG. 6 does not have a functional unit corresponding to the shared data area forming unit 409 shown in FIG. 4, and accordingly, FIG. 7 shows a step S510 shown in FIG. There is no corresponding processing.
[0059]
Further, while the shared data identification information adding unit 402 according to the first embodiment adds a predetermined prefix to the shared data in step S503, the shared data identification information adding unit 602 according to the second embodiment performs the processing in step S703. A section specification pseudo instruction, for example, one line such as ".sect" SHARED DATA "" is inserted immediately before the shared data.
[0060]
Then, in step S710, the memory space construction unit 609 according to the second embodiment collects only data belonging to the “SHARED DATA” section to form a shared data area 102, and collects data in the remaining sections collectively as a data area 101 and an instruction sequence. Collectively, text area 100 is used.
[0061]
According to the second embodiment, since the shared data and the non-shared data are separated in advance by the assembler section specification pseudo instruction, the former is set to the non-cache target area and the latter is set to the cache target area when executing the program. With each arrangement, the shared data is prevented from being distributed to the cache memories of the respective processors, thereby maintaining cache coherency.
[0062]
(Embodiment 3)
The first and second embodiments are based on the premise that an area not to be cached is provided in the memory space of the processor and the shared data is arranged in the area. Therefore, the shared data is not copied to the cache memory in the first place. However, as in the third embodiment described below, the shared data is set to be cached, and the existing cache is invalidated when the data is read. Then, control may be performed so that data is always read to the main memory.
[0063]
The hardware configuration of the load module generation device according to the third embodiment is the same as that of the first embodiment shown in FIG. FIG. 8 is a block diagram functionally showing the configuration of the load module generation device according to the third embodiment of the present invention, and FIG. 9 is a flowchart showing the procedure of a load module generation process in the device. The difference from the first embodiment is that FIG. 8 does not include a function unit corresponding to the shared data area forming unit 409 shown in FIG. 4, and accordingly, FIG. 9 shows a step S510 shown in FIG. There is no corresponding processing.
[0064]
Also, in FIG. 8, a cache invalidation operation adding unit 802 is provided instead of the shared data identification information adding unit 402 shown in FIG. 4, and accordingly, in step S903 in FIG. Instead, the cache invalidation operation adding unit 802 performs the cache invalidation operation addition processing.
[0065]
The addition of the cache invalidation operation is, specifically, immediately before a load instruction for shared data, in the case of a write-through cache, the cache of the data in the cache memory (strictly speaking, a cache block including the cache). ) Is inserted, and in the case of a write-back cache, the flash instruction and the invalidate instruction are inserted.
[0066]
According to the third embodiment, the shared data is cached similarly to the non-shared data, but the copy of the shared data stored in the cache memory of each processor is practically not used.
[0067]
In other words, when reading non-shared data, the processor reads the copy if there is a copy in the cache memory.However, when reading shared data, the processor executes an invalidate instruction immediately before that to execute the copy. Is erased, so that the user skips the cache memory and always goes to the main memory to see the main body of the data. As a result, all processors read and write the same address on the main memory for the shared data, and the cache consistency is maintained.
[0068]
Note that the load module generation method according to the present embodiment is realized by executing a prepared program (compiler, assembler, and linker) on various computers such as a personal computer and a workstation. Is recorded on various computer-readable recording media such as HD, FD, CD-ROM, MO, and DVD, and can be distributed via the recording media or distributed via a network such as the Internet. It is.
[0069]
(Supplementary Note 1) In a load module generation method configured to generate a load module of a program including a plurality of partial programs, each of the partial programs being respectively executed by a plurality of processors,
Individual data included in the program, a shared data determination step of determining whether or not data read and written by at least two of the plurality of partial programs,
An identification information adding step of adding predetermined identification information to data determined to be data read and written by at least two partial programs in the shared data determination step;
A shared data area forming step of combining data to which predetermined identification information has been added in the identification information adding step to form an area to be arranged in a non-cache target area in a memory space;
A load module generation method, comprising:
[0070]
(Supplementary Note 2) In the identification information adding step, a predetermined prefix is added as identification information to data determined to be data read / written by at least two partial programs in the shared data determination step. 3. The load module generation method according to claim 1, wherein
[0071]
(Supplementary Note 3) In the identification information adding step, information specifying the section to which the section belongs is added to the data determined to be data read / written by at least two partial programs in the shared data determination step. 3. The load module generation method according to claim 1, wherein
[0072]
(Supplementary Note 4) In a load module generation method configured to generate a load module of a program including a plurality of partial programs, each of the partial programs being respectively executed by a plurality of processors,
Individual data included in the program, a shared data determination step of determining whether or not data read and written by at least two of the plurality of partial programs,
A cache invalidation operation adding step of adding a cache invalidation operation to data determined to be data read and written by at least two partial programs in the shared data determination step,
A load module generation method, comprising:
[0073]
(Supplementary Note 5) In the cache invalidation operation adding step, immediately before a read instruction for data determined to be data read / written by at least two partial programs in the shared data determination step, the cache invalidation of the data is performed. 5. The load module generation method according to claim 4, wherein a date instruction is inserted.
[0074]
(Supplementary Note 6) In a load module generation program configured to generate a load module of a program configured by a plurality of partial programs, each of the partial programs being respectively executed by a plurality of processors,
A shared data determination step of determining whether individual data included in the program is data read and written by at least two of the plurality of partial programs,
An identification information adding step of adding predetermined identification information to data determined to be data read and written by at least two partial programs in the shared data determination step;
A shared data area forming step of combining data to which predetermined identification information has been added in the identification information adding step to form an area to be arranged in a non-cache target area in the memory space;
A load module generation program for causing a computer to execute the program.
[0075]
(Supplementary Note 7) In the identification information adding step, a predetermined prefix is added as identification information to data determined to be data read / written by at least two partial programs in the shared data determination step. 7. The load module generation program according to claim 6, wherein
[0076]
(Supplementary Note 8) In the identification information adding step, information specifying a section to which the section belongs is added as identification information to the data determined to be data read and written by at least two partial programs in the shared data determination step. 7. The load module generation program according to claim 6, wherein:
[0077]
(Supplementary Note 9) In a load module generation program configured to generate a load module of a program that is configured by a plurality of partial programs and each of the partial programs is respectively executed by a plurality of processors,
A shared data determination step of determining whether individual data included in the program is data read and written by at least two of the plurality of partial programs,
A cache invalidation operation adding step of adding a cache invalidation operation to data determined to be data read and written by at least two partial programs in the shared data determination step,
A load module generation program for causing a computer to execute the program.
[0078]
(Supplementary Note 10) In the cache invalidation operation adding step, immediately before a read instruction for data determined to be data read / written by at least two partial programs in the shared data determination step, the cache invalidation of the data is performed. 10. The load module generation program according to supplementary note 9, wherein a date instruction is inserted.
[0079]
(Supplementary Note 11) In a load module generation device configured by a plurality of partial programs, wherein each of the partial programs generates a load module of a program executed by a plurality of processors,
Individual data included in the program, shared data determination means to determine whether or not data read and written by at least two of the plurality of partial programs,
Identification information adding means for adding predetermined identification information to data determined to be data read and written by at least two partial programs by the shared data determination means,
A shared data area forming means for combining data to which predetermined identification information has been added by the identification information adding means to form an area to be arranged in a non-cache target area in a memory space;
A load module generation device comprising:
[0080]
(Supplementary Note 12) The identification information adding means adds a predetermined prefix as identification information to the data determined by the shared data determination means to be data read / written by at least two partial programs. 12. The load module generation device according to attachment 11, wherein
[0081]
(Supplementary Note 13) The identification information adding means adds, as identification information, information specifying a section to which the data belongs to the data determined to be data read / written by at least two partial programs by the shared data determination means. 13. The load module generation device according to claim 11, wherein
[0082]
(Supplementary Note 14) In a load module generation device configured to generate a load module of a program configured by a plurality of partial programs, each of the partial programs being respectively executed by a plurality of processors,
Individual data included in the program, shared data determination means to determine whether or not data read and written by at least two of the plurality of partial programs,
A cache invalidation operation adding unit that adds a cache invalidation operation to data determined to be data read and written by at least two partial programs by the shared data determination unit;
A load module generation device comprising:
[0083]
(Supplementary Note 15) The cache invalidation operation adding unit, immediately before a read command for data determined to be data read / written by at least two partial programs by the shared data determining unit, performs an inversion of a cache of the data. 15. The load module generation device according to appendix 14, wherein a date command is inserted.
[0084]
【The invention's effect】
As described above, when the load module generated according to the present invention is executed, data shared by a plurality of partial programs is not copied to the cache memory of the processor in the first place, or is copied but erased when read. As a result, the value of the main memory is always referred to and updated, so that even if a plurality of partial programs sharing the same data are executed by different processors, the coherency of the cache is automatically maintained. It is possible to obtain a load module generation method, a load module generation program, and a load module generation device capable of generating a load module to be generated.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing an example of a memory map in a case where cache coherency is ensured by an uncached shared data method.
FIG. 2 is an explanatory diagram showing an example of a memory map in a case where cache coherency is ensured by a selective cache invalidation operation method;
FIG. 3 is a block diagram illustrating an example of a hardware configuration of the load module generation device according to the first embodiment of the present invention;
FIG. 4 is a block diagram functionally showing a configuration of the load module generation device according to the first embodiment of the present invention;
FIG. 5 is a flowchart illustrating a procedure of a load module generation process in the load module generation device according to the first embodiment of the present invention;
FIG. 6 is a block diagram functionally illustrating a configuration of a load module generation device according to a second embodiment of the present invention;
FIG. 7 is a flowchart illustrating a procedure of a load module generation process in the load module generation device according to the second embodiment of the present invention;
FIG. 8 is a block diagram functionally illustrating a configuration of a load module generation device according to a third embodiment of the present invention;
FIG. 9 is a flowchart illustrating a procedure of a load module generation process in the load module generation device according to the third embodiment of the present invention;
FIG. 10 is an explanatory diagram schematically showing a configuration of a shared memory multiprocessor system having a cache mechanism.
FIG. 11 is an explanatory diagram showing an example of a memory map in a case where cache coherency is ensured by a conventional cache coherency mechanism.
[Explanation of symbols]
300 bus or cable
301 CPU
302 ROM
303 RAM
304 HDD
305 HD
306 FDD
307 FD
308 display
309 Network I / F
310 Ethernet cable
311 keyboard
312 mouse
400, 600, 800 First analysis unit
401, 601, 801 shared data determination unit
402, 602 shared data identification information adding unit
403, 603, 803 Instruction sequence generator
404, 604, 804 Assembly description output unit
405, 605, 805 Second analysis unit
406,606,806 Binary code generator
407, 607, 807 Object output unit
408, 608, 808 Object reading unit
409 Shared data area forming unit
410,609,809 Memory space construction unit
411,610,810 Address resolution unit
412, 611, 811 load module output unit
802 Cache invalidation operation addition unit

Claims (9)

A load module generation method configured by a plurality of partial programs, wherein each of the partial programs generates a load module of a program executed by a plurality of processors,
Individual data included in the program, a shared data determination step of determining whether or not data read and written by at least two of the plurality of partial programs,
An identification information adding step of adding predetermined identification information to data determined to be data read and written by at least two partial programs in the shared data determination step;
A shared data area forming step of combining data to which predetermined identification information has been added in the identification information adding step to form an area to be arranged in a non-cache target area in a memory space;
A load module generation method, comprising: 2. The identification information adding step, wherein a predetermined prefix is added as identification information to data determined to be data read / written by at least two partial programs in the shared data determination step. The load module generation method according to 1. In the identification information adding step, information specifying a section to which the section belongs is added as identification information to data determined to be data read / written by at least two partial programs in the shared data determination step. The load module generation method according to claim 1, wherein A load module generation method configured by a plurality of partial programs, wherein each of the partial programs generates a load module of a program executed by a plurality of processors,
Individual data included in the program, a shared data determination step of determining whether or not data read and written by at least two of the plurality of partial programs,
A cache invalidation operation adding step of adding a cache invalidation operation to data determined to be data read and written by at least two partial programs in the shared data determination step,
A load module generation method, comprising: In the cache invalidation operation adding step, an invalidate instruction of a cache of the data is inserted immediately before a read instruction for data determined to be data read / written by at least two partial programs in the shared data determination step. The load module generation method according to claim 4, wherein A load module generation program configured by a plurality of partial programs, wherein each of the partial programs generates a load module of a program executed by a plurality of processors,
Individual data included in the program, a shared data determination step of determining whether or not data read and written by at least two of the plurality of partial programs,
An identification information adding step of adding predetermined identification information to data determined to be data read and written by at least two partial programs in the shared data determination step;
A shared data area forming step of combining data to which predetermined identification information has been added in the identification information adding step to form an area to be arranged in a non-cache target area in a memory space;
A load module generation program for causing a computer to execute the program. A load module generation program configured by a plurality of partial programs, wherein each of the partial programs generates a load module of a program executed by a plurality of processors,
Individual data included in the program, a shared data determination step of determining whether or not data read and written by at least two of the plurality of partial programs,
A cache invalidation operation adding step of adding a cache invalidation operation to data determined to be data read and written by at least two partial programs in the shared data determination step,
A load module generation program for causing a computer to execute the program. A load module generation device configured by a plurality of partial programs, wherein each of the partial programs generates a load module of a program executed by a plurality of processors,
Individual data included in the program, shared data determination means to determine whether or not data read and written by at least two of the plurality of partial programs,
Identification information adding means for adding predetermined identification information to data determined to be data read and written by at least two partial programs by the shared data determination means,
A shared data area forming means for combining data to which predetermined identification information has been added by the identification information adding means to form an area to be arranged in a non-cache target area in a memory space;
A load module generation device comprising: A load module generation device configured by a plurality of partial programs, wherein each of the partial programs generates a load module of a program executed by a plurality of processors,
Individual data included in the program, shared data determination means to determine whether or not data read and written by at least two of the plurality of partial programs,
A cache invalidation operation adding unit that adds a cache invalidation operation to data determined to be data read and written by at least two partial programs by the shared data determination unit;
A load module generation device comprising:

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