JP2004029851A - Driving method of image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To drive a display device such as an AC type PDP to reduce the withstand voltage of an address data driver and to simplify a power supply, suppress generation of noise at the fall of a sustain discharge pulse, and maintain a stable sustain discharge period. The purpose is to guarantee discharge.
SOLUTION: A first and a second electrode are arranged on a first substrate, a third electrode is arranged on a second substrate facing the first substrate, and the first or the second electrode and the third electrode are arranged on the second substrate. In the case where writing is performed on the display cell selected by the first and second electrodes, the first voltage supply means 4 for supplying a half of a predetermined voltage required for the sustain discharge to the first electrode, A second voltage supply means for supplying a half of the predetermined voltage to the second electrode; and a potential for selecting the second electrode in the address period has a voltage equivalent to that in the sustain discharge period. Then, a voltage having a polarity opposite to the voltage of the second electrode and equivalent to the voltage during the sustain discharge period is applied to the first electrode.
[Selection diagram] Fig. 1

Description

The present invention relates to a technique for driving an image display panel to display display data on an image display panel formed by a set of display cells, which are display elements having a memory function, and more particularly to an AC (AC) type. The present invention relates to an image display device and a driving method of the image display device for realizing cost reduction and improvement of reliability in a plasma display panel.

An image display device using the above-mentioned AC type plasma display panel, that is, an AC type plasma display device (usually abbreviated as an AC type PDP) has a pulse voltage waveform alternately applied to two sustain discharge electrodes. Is applied to maintain the discharge and display light emission. One discharge ends in 1 μs (microsecond, 1 microsecond corresponds to 10 ⁻⁶ seconds) to several μs after pulse application. Ions, which are positive charges generated by the discharge, accumulate on the surface of the insulating layer on the electrode to which a negative voltage is applied, and similarly, electrons, which are negative charges, on the electrode to which a positive voltage is applied. It is accumulated on the surface of the insulating layer.

Therefore, first, a wall charge is generated by discharging with a high voltage (writing voltage) pulse (writing pulse), and then a lower voltage (sustaining discharge pulse) pulse (sustain discharge pulse and sustain pulse) having a different polarity than the previous one is used. Is applied, the previously accumulated wall charges are overlapped with the sustain discharge voltage, the voltage to the discharge space becomes large, and the discharge by light emission is started exceeding the threshold of the discharge voltage. In other words, the display cell that has once performed the write discharge to generate the wall charge has a feature that the discharge is continued by alternately applying the sustain discharge pulse in the opposite polarity. This is called a memory effect or memory drive. The AC PDP uses the memory effect to realize display on a plasma display panel.

The AC-type PDP has a two-electrode type that performs selective discharge (address discharge) and sustain discharge with two electrodes including a first electrode and a second electrode, and performs an address discharge using a third electrode. There is a three-electrode type. In particular, in a color display PDP that performs multi-tone display, a phosphor in a display cell is excited by ultraviolet rays generated by discharge, and the phosphor is bombarded by ions that are positive charges generated simultaneously by discharge. Has the disadvantage of being very weak. In the above-mentioned two-electrode type, since the phosphor directly hits the ions, the life of the phosphor may be shortened. In order to avoid this, a three-electrode type structure using surface discharge is generally used in a PDP for color display.

Further, in this type of three-electrode surface discharge type structure, a third electrode is formed on a substrate on which a first electrode and a second electrode for performing sustain discharge are arranged, and another substrate facing the other electrode is used. In some cases, a third electrode is formed. Further, even when the above three types of electrodes are formed on the same substrate, there are cases where a third electrode is arranged on two electrodes for performing sustain discharge, and cases where a third electrode is arranged thereunder. is there. Furthermore, there are a case where visible light emitted from the phosphor is viewed through the phosphor (transmission type) and a case where reflected light from the phosphor is viewed (reflection type).

On the other hand, a display cell that performs discharge (also called a discharge cell) has a spatial connection with an adjacent display cell cut off by a barrier (also called a rib or a barrier). Further, such barriers are provided on all sides to surround the discharge cells and each discharge cell is completely sealed. On the other hand, the barrier is provided only in one direction, and between the electrodes on the non-barrier side. In some cases, the spatial coupling between adjacent display cells is cut off by optimizing the gap (that is, the distance between the electrodes).

で は The present specification is directed to an image display device using an image display panel having a structure in which a third electrode is formed on an opposite substrate different from a substrate on which two electrodes for performing sustain discharge are arranged. Further, in this specification, the barrier is formed only in the vertical direction (that is, the direction orthogonal to the first electrode and the second electrode and parallel to the third electrode), and the first electrode and the second electrode The configuration of a conventional image display device will be described based on an example of a reflective three-electrode surface discharge AC type PDP in which a part of a sustain electrode (also referred to as a sustain electrode) formed of a transparent electrode is formed of a transparent electrode. It shall be.

FIGS. 12 to 14 are views showing the structure of a general reflection type three-electrode surface discharge / AC type PDP. More specifically, FIG. 12 is a plan view showing a schematic structure of an image display panel including a plasma display panel in a general reflection type three-electrode surface discharge / AC type PDP, and FIG. FIG. 14 is a cross-sectional view (vertical direction) showing a schematic structure along an address electrode of one display cell (shaded portion in FIG. 12) in an image display panel in a surface discharge AC type PDP, and FIG. FIG. 3 is a cross-sectional view (horizontal direction) showing a schematic structure along a sustain electrode of a three-electrode surface discharge AC type PDP.

In FIG. 12, reference numeral 2 denotes an image display panel made up of, for example, a plasma display panel. Further, reference numeral 14 denotes a first electrode formed of, for example, a common X sustain electrode, and reference numeral 15 denotes, for example, Y scan electrodes Y1, Y2,... Corresponding to N (N is an arbitrary positive integer) display lines, respectively. , YN. The first electrode 14 and the second electrode 15 are arranged in parallel with each other. Further, reference numeral 16 denotes a third electrode composed of a plurality of address electrodes A1, A2,..., AM for, for example, M bits (N is an arbitrary positive integer). Here, M × N display cells 22 are formed at intersections between a pair of X sustain electrodes and Y scan electrodes and one address electrode. Reference numeral 23 denotes a barrier that partitions the display cell 22.

Further, as shown in FIG. 13, the image display panel 2 (FIG. 12) includes two glass substrates including a front glass substrate 24 as a first substrate and a rear glass substrate 25 as a second substrate. ing. The first substrate (front glass substrate 24) includes a sustain electrode including a first electrode 14 and a second electrode 15 which are parallel to each other. These sustain electrodes are composed of a bus electrode constituting a main part of the first electrode 14 and the second electrode 15 and a transparent electrode 17 serving as a base of the bus electrode. Since this transparent electrode 17 has a role of transmitting the reflected light from the phosphor 28, it is formed of ITO (a transparent conductive film mainly containing indium oxide).

On the other hand, the bus electrode needs to be formed of a low-resistance material in order to prevent a voltage drop (voltage drop) due to electrode resistance. To satisfy such requirements, the bus electrode is usually formed of chromium (Cr) or copper (Cu). Further, this bus electrode is covered with a dielectric layer 26 of glass or the like, and a magnesium oxide (MgO) film is formed as a protective film 27 on the discharge surface of the discharge space S. Furthermore, a third electrode (address electrode) 16 is formed on the second substrate facing the first substrate so as to be orthogonal to the sustain electrode.

Further, as shown in FIG. 14, a barrier 23 is formed between adjacent address electrodes. Phosphors 28 having red, green and blue emission characteristics are formed between these barriers 23 so as to cover the address electrodes. Here, two glass substrates are assembled so that the ridge of the barrier 23 and the surface of the MgO film are in close contact with each other.
FIG. 15 is a block diagram showing a configuration of a peripheral circuit for driving a general three-electrode surface discharge / AC PDP.

In the image display panel 2 in the three-electrode surface discharge / AC type PDP shown in FIG. 15, for example, a plasma display panel, as described above, the first electrode 14 including the common X sustain electrode and the like, and the Y scan A pair of second electrodes 15 composed of electrodes Y1, Y2, Y3,..., YN, etc., is arranged in parallel for each display line. Further, the third electrode 16 composed of the address electrodes A1, A2, A3,..., AM and the like is placed at a position facing the pair of the first and second electrodes 14, 15 and at the first and second electrodes 14 and 15. , 15 so as to form a plurality of display cells 22 in a planar matrix at the intersections between the pair of the first and second electrodes 14 and 15 and the third electrode 16. You.

Further, in FIG. 15, the configuration of a plurality of types of drivers (drive circuit units) for driving the display cells 22 in the plasma display panel and peripheral circuits including a control circuit unit for controlling these drivers will be described. It shall be.
15, the address data driver 60 for driving the address electrodes A1, A2, A3,..., AM for each display line for the purpose of address discharge of the display cell, and the sustain discharge of the display cell 22 are performed. For the purpose, an X common driver 40 for performing common sustain discharge driving (that is, sustain driving) for the X sustain electrode X is provided. Further, in the address period in which the selective write discharge is performed, data scanning (scanning) is sequentially performed on the data for one display line set by the address data driver 60 for the Y scan electrodes Y1 to YN (for example, N = 480). A Y common driver 50 that performs sustain driving when a sustain discharge period (that is, a sustain period) occurs is provided. Further, a Y scan driver 55 is connected to the Y common driver 50. The Y scan driver 55 applies a sustain discharge pulse to its own power supply itself by the Y common driver 50 to perform common sustain driving for the Y scan electrodes Y1 to YN.

Further, in FIG. 15, a control circuit unit 31 for controlling all the operations of the AC type PDP including the address data driver 60, the X common driver 40, the Y common driver 50, the Y scan driver 55, and the plasma display panel is provided. Have been. The main parts of the control circuit unit 31 are a display data control unit 32 for controlling display data by address discharge of the plurality of display cells 22, and a timing for driving the display cells 22 in the plasma display panel by the various drivers described above. And a panel drive control unit 34 for controlling the

Here, the address electrodes A1, A2, A3,..., AM are connected one by one (1 bit) to the address data driver 60, and the address data driver 60 applies an address pulse at the time of address discharge. Further, the Y scan electrodes Y1 to YN are individually applied to the Y scan driver 55. The Y scan driver 55 is connected to the Y common driver 50, and a scan pulse at the time of address discharge is generated from the Y scan driver 55. Further, the sustain discharge pulse and the like are generated from the Y common driver 50 and applied to the Y scan electrodes Y1 to YN via the Y scan driver 55. On the other hand, the X sustain electrodes X are commonly connected and taken out over the entire surface of the plasma display panel. The X common driver 40 generates a write pulse, a sustain discharge pulse, and the like. The circuits of these drivers are controlled by the control circuit unit 31. The control circuit 31 is controlled by a dot clock CLOCK, a vertical synchronizing signal VSYNC, a horizontal synchronizing signal HSYNC, and display data DATA input from outside the AC PDP.

To explain in more detail, the display data control unit 32 in the control circuit unit 31 has a frame memory unit 33. The display data DATA for color display input from the outside is rearranged into data for driving the AC type PDP based on the dot clock CLOCK, and the rearranged data is temporarily stored in the frame memory unit 33. After being stored, it is sequentially transferred to the address data driver 60 as a control signal for address discharge control (that is, an M-bit display data signal) during the address period.

On the other hand, the panel drive control section 34 in the control circuit section 31 drives the Y scan driver 55 based on various signals such as an externally input dot clock CLOCK, vertical synchronization signal VSYNC, and horizontal synchronization signal HSYNC. And a common driver control unit 36 for controlling the X common driver 40 and the Y common driver 50.

FIG. 16 is a driving waveform diagram for explaining a conventional image display panel driving method using an address period / sustain discharge period separated type / write address system and using a full erase discharge during a reset period. FIG. 16 exemplifies a drive waveform in one sub-frame (sub-field) period in the conventional “address period / sustain discharge period separated type / write address system”.

In the example of FIG. 16, one subframe is divided into a reset period, an address period, and a sustain discharge period (ie, a sustain period). In the first part of the reset period, first, the potentials of all the Y scan electrodes Y1 to YN are set to the level of 0 V (GND level), and at the same time, the voltage Vs + Vw (for example, about 330 V) is applied to the X sustain electrode X. ) Is applied (for example, a pulse width of about 10 μs). By applying this full-surface write pulse, discharge is performed in all display cells of all display lines regardless of the previous display state. At this time, each potential of the address electrodes A1, A2, A3,..., AM has a voltage (Vaw) of about 100V.

(4) In the rest of the reset period, the potentials of the X sustain electrode and the address electrode are at the level of 0 V, and the voltage of the wall charges exceeds the discharge start voltage in all the display cells, and discharge is started. In this discharge, since there is no potential difference between the electrodes, no wall charge is formed, and the space charge is self-neutralized to terminate the discharge. Such a phenomenon is generally called a self-erasing discharge. Due to this self-erasing discharge, the state of all display cells in the plasma display panel becomes a uniform state without wall charges. During the reset period, all display cells have the same operation regardless of the lighting state of the previous subframe, and the next address discharge (write discharge) can be performed stably.

Next, in the address period, in order to perform an on / off (ON / OFF) operation of the display cell according to the display data, an address discharge is performed by a line sequential method. In this address period, first, a scan pulse having a voltage of -VY (for example, about 150 V) is applied to the Y scan electrode, and a display cell that causes a sustain discharge, that is, a display cell to be lit, in the address electrode is first applied. An address pulse having a voltage of Va (for example, about 50 V) is selectively applied to the corresponding address electrode, and a discharge occurs between the address electrode of the display cell to be turned on and the Y scan electrode. Next, this discharge is used as priming (seeding) to shift to discharge between the X sustain electrode (the potential of the X sustain electrode has a voltage VX of about 50 V, for example) and the Y scan electrode. As a result, an amount of wall charges capable of sustaining discharge is accumulated on a surface such as an MgO film on the X sustain electrode and the Y scan electrode corresponding to the selected cell on the selected display line.

Hereinafter, the same operation is sequentially performed on the other display lines, and new display data is written on all the display lines.
Thereafter, in the sustain discharge period, a sustain discharge pulse composed of a voltage Vs (for example, about 180 V) is alternately applied to the X sustain electrode and the Y scan electrode to perform a sustain discharge, and image display of one sub-frame is performed. Done. In the “address period / sustain discharge period separated type / write address method”, the brightness of the lighted display cell is determined by the length of the sustain discharge period, that is, the number of sustain discharge pulses.

FIG. 17 is a diagram showing a state in which a plurality of subframes are formed in the address period / sustain discharge period separation type / write address system of FIG. However, here, as an example of the multi-gradation display, a driving method of the plasma display panel in the case of performing the gradation display for 256 gradations is illustrated.
In the example of FIG. 17, one frame is divided into eight subframes SF1, SF2, SF3, SF4,.

In each of the subframes SF1, SF2, SF3, SF4,... SF8, the reset period in which the full-area write discharge is performed and the address period in which the selective write discharge is performed along the address line have the same length. Will be. On the other hand, the length of the sustain discharge period has a ratio of 1: 2: 4: 8: 16: 32: 64: 128. Therefore, by selecting and combining the subframes in which the display cells should be turned on, it is possible to display the difference in the luminance of 256 steps (2 ⁸ = 256) from 0 to 255.

Further, an example of the actual time distribution is as follows. When the rewriting frequency of the screen on the plasma display panel is 60 Hz (Hertz), the length of one frame is 1/60 second, that is, 16.6 ms (millisecond, 1 millisecond is equivalent to 10 ^-3 second). ).
Assuming that the number of sustain discharge cycles (that is, sustain cycles) in one frame is 510, the number of sustain discharge cycles in each subframe is 2 in subframe SF1, 4 in subframe SF2, and 4 in subframe SF3. The subframe SF4 has 16 cycles, the subframe SF5 has 32 cycles, the subframe SF6 has 64 cycles, the subframe SF7 has 128 cycles, and the subframe SF8 has 256 cycles. Assuming that the sustain discharge cycle time is 8 μs, the total in one frame is 4.08 ms. Therefore, eight reset periods and address periods are allocated in the remaining approximately 12 ms. In this case, the reset period of each subframe is 50 μs. Further, since the time required for an address cycle corresponding to scanning per display line is 3 μs, if a plasma display panel having 480 display lines in the vertical direction is used for a multi-tone color display, 1.times. A time of 44 ms (3 × 480) is required.

As described above, in the conventional image display panel driving method of a general AC type PDP or the like, when the address period ends and the sustain discharge period starts, the X sustain electrode (first electrode) and the Y scan electrode (second electrode) The sustain discharge pulse is applied alternately to the sustain electrode, and the sustain discharge is performed. In this case, the potential of the address electrode is, for example, about の of the voltage Vs of the sustain discharge pulse, or the entire-area write discharge. It is set to a value substantially equal to the voltage Vaw of the potential of the address electrode at the time, and is fixed to a constant value.

The potential of the address electrode during the sustain discharge period must be such that the sustain discharge can be performed stably in the selected cell in which the address discharge has been performed, and on the other hand, the non-selected cell in which the address discharge has not been performed. In this case, the potential must not cause a discharge while the sustain discharge pulse is repeatedly applied. That is, when a sustain discharge pulse is applied to the X sustain electrode and the Y scan electrode, it is necessary to make the potential difference between the voltage of the sustain discharge pulse Vs and the voltage of the address electrode less than the discharge start voltage.

(4) If such a necessary condition is not satisfied, there is a possibility that discharge is started even in a display cell in which selection is not performed in the address period. On the other hand, a display cell which needs to perform an address discharge in the address period and maintain the sustain discharge is required to stably perform the sustain discharge by the wall charges accumulated in the address period. Due to the address discharge, negative (-) wall charges are accumulated on the address electrode side and the X sustain electrode, and positive (+) wall charges are accumulated on the Y scan electrode side. However, in this case, in the first part of the sustain discharge, there is a possibility that the discharge is performed even between the Y scan electrode and the address electrode. For this reason, the discharge between the Y scan electrode and the address electrode precedes, and the intended sustain discharge between the X sustain electrode and the Y scan electrode may not be performed. Therefore, there is an optimum value for the potential of the address electrode even in the selected cell to be turned on.

The above phenomenon occurs because the discharge starting voltage between the Y scan electrode and the address electrode performing the opposing discharge is much lower than the discharge starting voltage between the X sustain electrode and the Y scan electrode performing the surface discharge. This is caused by the general characteristics of a three-electrode surface-discharge AC-type PDP disposed on a substrate facing the side where discharge is performed.
From this point of view, in the conventional driving method, the potential of the address electrode during the sustain discharge period is set to a value of about の of the voltage Vs of the sustain discharge pulse (or the voltage of the potential of the address electrode at the time of the full write discharge) Vaw). When the potential of this value is maintained, the possibility that charged particles such as generated ions and electrons fly to the address electrode side during the sustain discharge is minimized, and these charged particles are accumulated as wall charges. Is also reduced. In order to reduce the number of power supplies added to the address data driver, the potential of the address electrode during the sustain discharge period is set to be close to a value of about 1/2 of the voltage Vs of the sustain discharge pulse (for example, about 90 V). It is also conceivable to set the voltage to a value approximately equal to the voltage Vaw (for example, about 100 V) at the time of the entire write discharge (reset period).

In this case, in the reset period, by performing a full-area writing discharge and a full-area erasing discharge, wall charges accumulated on the surface of the MgO film or the like on the X sustain electrode side and the Y scan electrode side are positively removed to clear the cell. However, the address electrode side is relatively unlikely to be in a clear state. As a result, the uniformity of the address discharge may be lost. Therefore, it is necessary to set the potential of the address electrode to 0 V during the sustain discharge period so that the wall charges are hardly accumulated.

Originally, an address data driver is a circuit for selecting a display cell during an address period, and a voltage of about 0 V and a voltage of Va (for example, about 50 V), which are potentials for distinguishing selection and non-selection of a display cell from each other. It suffices if binary output is possible. Further, the withstand voltage of the address data driver may satisfy Va (50 V).
However, in the conventional driving method, it is absolutely necessary to maintain the potential of the address electrode at a value of about 1/2 of the voltage Vs of the sustain discharge pulse during the sustain discharge period for the above-described reason. Therefore, as a first problem, it is necessary to make the withstand voltage of the address data driver 90 V or more (about の of the voltage Vs of the sustain discharge pulse) or more, which leads to cost reduction by lowering the withstand voltage of the address data driver. There is a risk of hindrance. Incidentally, the lower the withstand voltage of the address data driver, the simpler the manufacturing process and the like for the integration into an integrated circuit, and the lower the price of the driver.

Further, according to Japanese Patent Application Laid-Open No. 59-94328, etc., as a voltage to be applied when performing a sustain discharge, a half of the voltage of the sustain discharge pulse is applied to the two sustain electrodes in a positive polarity and a negative polarity, respectively. At the same timing to perform sustain discharge. However, in this case, the voltage of the pulse applied to the sustain electrode when performing the address discharge has a value different from the voltage applied when performing the sustain discharge. And the cost of the address data driver may increase.

Furthermore, according to the configuration of the conventional peripheral circuit, when the sustain discharge pulse is terminated, the voltage sharply falls from the voltage Vs (about 180 V) to 0 V, so that a large current flows instantaneously and noise occurs. Therefore, as a third problem, this kind of noise may enter another circuit or be radiated to another circuit as an unnecessary radio wave, thereby causing a malfunction or failure.

On the other hand, a case where the potential of the address electrode during the sustain discharge period is fixed to, for example, a value substantially equal to the voltage Vaw of the potential of the address electrode at the time of full write discharge will be considered.
Also in this case, the potential of the address electrode during the sustain discharge period must be a potential at which the sustain discharge can be stably performed in the selected cell where the address discharge has been performed, and on the other hand, the address discharge is not performed. In the unselected cells, the potential must be set so as not to cause a discharge when the sustain discharge pulse is repeatedly applied.

Here, the phenomenon that the sustain discharge is attenuated by abnormal discharge of the address electrode, the X sustain electrode (first electrode), and the Y scan electrode (second electrode) will be described.
A sustain discharge pulse is applied to the X sustain electrode and the Y scan electrode during the sustain discharge period. When the respective sustain discharge pulses are switched, that is, when the potentials of both the X sustain electrode and the Y scan electrode become 0V. When the potential of the address electrode during the sustain discharge period has the value of the voltage Vaw, for the plasma display panel having a characteristic of a low discharge potential, between the address electrode and the X sustain electrode, and between the address electrode and the Y electrode. An abnormal discharge is caused between the scan electrode and the scan electrode. Due to the occurrence of such abnormal discharge, as a fourth problem, stable sustain discharge is not guaranteed, and there is a possibility that stable operation characteristics of an AC type PDP or the like may be hindered.
JP-A-59-94328

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and when driving an AC-type PDP plasma display panel or the like, it is possible to realize a low withstand voltage of an address data driver and a simplification of a power supply configuration, and a sustain discharge pulse. It is a first object of the present invention to provide an image display device capable of suppressing occurrence of noise at the time of falling of the image, and a driving method of the image display device.

Further, the present invention prevents abnormal discharge from occurring between the address electrode and the first electrode and between the address electrode and the second electrode during the sustain discharge period, and achieves a stable sustain discharge. It is a second object of the present invention to provide a driving method of an image display device which can guarantee the driving method.

FIG. 1 is a block diagram showing the principle configuration of the present invention. However, here, the drive circuit unit and the image display panel 2 related to the present invention in the image display device 1 will be mainly shown. Further, here, one display cell 22 of the plurality of display cells is shown in an enlarged manner. Hereinafter, the same components as those described above will be denoted by the same reference numerals.

As shown in FIG. 1, the image display device of the present invention arranges the first electrode 14 and the second electrode 15 on the first substrate in parallel for each display line, A third electrode 16 is disposed on a second substrate opposite to the first substrate so as to be orthogonal to the first and second electrodes 14 and 15, and any one of the first electrode 14 and the second electrode 15 is provided. One, an address period for executing writing to the display cell 22 in the image display panel 2 selected by the third electrode 16, and the first and second electrodes 14, 14 based on the information written by the writing. 15 is intended for an image display device having a sustain discharge period for performing a sustain discharge and performing a light emitting display.

Further, in order to achieve the first object, as shown in FIG. 1, the image display device of the present invention applies a predetermined voltage required for the sustain discharge to the first electrode 14 during the sustain discharge period. On the other hand, a first voltage supply means 4 for supplying a voltage of approximately 1/2 of the predetermined voltage, and a second voltage supply means for supplying a voltage of approximately 1/2 of the predetermined voltage having a different polarity to the second electrode 15. And a voltage supply means 5.
Further, in the image display device of the present invention, in the address period, the potential for selecting the second electrode 15 has substantially the same voltage as the voltage supplied during the sustain discharge period. A voltage having a polarity opposite to that of the applied voltage and substantially the same as the voltage supplied during the sustain discharge period is applied to the first electrode 14.

Preferably, in the image display device of the present invention, the potential applied during the address period and for selecting the second electrode 15 comprises a voltage pulse having a negative polarity with respect to 0 V, and the potential of the first electrode 14 Consists of a voltage pulse that is positive with respect to 0V.
More preferably, in the image display device of the present invention, the selection potential of the third electrode 16 applied during the address period has a positive polarity with respect to 0 V and is approximately の of a predetermined voltage required for sustain discharge. With voltage.

More preferably, in the image display device of the present invention, the first voltage supply means 4 and the second voltage supply means 5 operate during a sustain discharge period when a predetermined applied voltage required for the sustain discharge is removed. A switching means for sustaining voltage release; and a switching means for sustaining discharge for supplying a current required to execute the sustaining discharge to the first electrode 14 or the second electrode 15. It is composed of elements having high impedance with respect to.

More preferably, in the image display device of the present invention, the element having a high impedance includes a field-effect transistor having a high resistance in a conductive state.
More preferably, in the image display device of the present invention, the high impedance element is realized by inserting a resistor in the output stage of the field effect transistor.

More preferably, in the image display device of the present invention, when resetting all the display cells by the entire writing discharge and the entire self-erasing discharge, the voltage applied to the third electrode 16 has a positive polarity with respect to 0V. The voltage is approximately one half of the predetermined voltage required for the sustain discharge, and all of the first, second and third electrodes 14, 15 and 16 have a positive polarity with respect to 0V and are required for the sustain discharge. The entire self-erasing discharge is performed by setting the voltage to approximately half the predetermined voltage.

On the other hand, in order to achieve the first object, in the driving method of the image display device of the present invention, the first electrode and the second electrode are arranged on the first substrate in parallel for each display line. A third electrode is disposed on the first substrate or a second substrate facing the first substrate so as to be orthogonal to the first and second electrodes, and the first electrode or the second electrode , An address period during which writing is performed on the display cell in the image display panel selected by the third electrode, and first and second electrodes based on the information written by the writing. To drive an image display device having a sustain discharge period for performing light emission display.

Further, in the driving method of the image display device of the present invention, during the sustain discharge period, a voltage that is approximately １ ／ of the predetermined voltage is applied to the first electrode as a predetermined voltage required for the sustain discharge, Sustain discharge is performed by applying approximately ほ ぼ voltages having different polarities to the second electrode.
Further, in the address period, the potential for selecting the second electrode has substantially the same voltage as the voltage applied in the sustain discharge period, and has a polarity opposite to that of the voltage applied to the second electrode. A voltage substantially equal to the voltage applied during the sustain discharge period is applied to the first electrode.

Preferably, in the method for driving an image display device according to the present invention, the potential applied during the address period and selecting the second electrode comprises a voltage pulse having a negative polarity with respect to 0 V, and The potential consists of a voltage pulse that is positive with respect to 0V.
Still preferably, in the method for driving an image display device according to the present invention, the selection potential of the third electrode applied during the address period is positive with respect to 0 V, and is approximately one of a predetermined voltage required for sustain discharge. / 2 voltage.

Further, in order to achieve the above second object, in the driving method of the image display device according to the present invention, in the sustain discharge period, the voltage is alternately applied between the first and second electrodes to execute the sustain discharge. When both of the applied voltage pulses are switched, the potential of the third electrode is reduced from a constant voltage.
More preferably, in order to achieve the second object, in the driving method of the image display device of the present invention, during the sustain discharge period, the potential of the third electrode is once reduced from a constant voltage to approximately 0 V, Thereafter, when the potential of the third electrode is raised to the original constant voltage, the potential of the third electrode is raised by the capacitance between the first and second electrodes and the third electrode.

Still preferably, in order to achieve the second object, in the method of driving an image display device of the present invention, the third electrode is driven only when the first voltage pulse for sustain discharge is applied. By means, the potential of the third electrode is set to a predetermined voltage.

According to the image display device or the method of driving the image display device of the present invention for achieving the first object, first, the voltage required for the sustain discharge is alternately changed by １ ／ with a different polarity. , X sustain electrodes and the like, and a second electrode such as a Y scan electrode. Therefore, it is possible to minimize the adverse effect on the sustain discharge of the address electrodes and the like, and to lower the withstand voltage of the address data driver. Further, since the selection potential of the Y scan electrode and the like and the potential at the time of sustain discharge are the same, the type of power supply can be reduced, and the configuration of the power supply circuit can be simplified.

Further, according to the image display device or the method of driving the image display device of the present invention, secondly, the address pulse applied to the address electrode or the like during the address period has a positive polarity with respect to 0 V, and the Y scan electrode Since the scan pulse applied to the gate electrode has a negative polarity with respect to 0 V, it is possible to minimize the impact of ions on the phosphor on the address electrode side during the selective write discharge.

Further, according to the image display device or the method of driving the image display device of the present invention, thirdly, the address pulse is positive with respect to 0 V and has the same voltage as the sustain discharge pulse. Therefore, the configuration of the power supply circuit can be simplified.
Furthermore, according to the image display device of the present invention, fourthly, when the potential of the sustain discharge pulse is set to 0 V, since a high-impedance element is used, a large current does not flow and other circuits can be used. Since the intrusion of noise and the emission of noise are suppressed, malfunctions and failures can be prevented.

Fifth, according to the image display device of the present invention, in the reset period, all display cells can be reset by self-erasing discharge over the entire surface by using a switching element having a sufficiently low impedance. Good reset operation is possible.
According to the method of driving the image display device of the present invention to achieve the second object, first, the first electrode such as the X sustain electrode during the sustain discharge period, and the Y scan electrode In order to prevent abnormal discharge between the second electrode and the third electrode such as the address electrode, the address electrode is not applied when the sustain discharge pulse is applied to the X sustain electrode and the Y scan electrode. It is necessary to drive up to the voltage of Vaw. Therefore, only when the first sustain discharge pulse (sustain discharge pulse of the Y scan electrode) is applied, the circuit is driven to the voltage Vaw using the circuit on the address electrode side. Thereafter, only when the sustain discharge pulse applied to the X sustain electrode and the Y scan electrode is switched, that is, when both the X sustain electrode and the Y scan electrode are at 0 V, the drive waveform of the address electrode is changed from the level of the voltage Vaw to 0 V, for example. By driving such a voltage pulse waveform as to lower the level of the selected cell, a stable sustain discharge can be performed on the selected cell in the address period.

{However, when realizing the above-mentioned pulse-like drive waveform, it is necessary to raise the voltage from 0V to the original voltage Vaw again. When the driver function of the drive circuit unit, which is a conventional driving method, is used, the same number of times of driving as the sustain discharge pulse during the sustain discharge period is required, which causes a disadvantage that more driving power is consumed than before. Therefore, according to the method for driving an image display panel of the present invention for achieving the second object, secondly, the X sustain electrode and the Y scan electrode can be used without using the driver function of the drive circuit section. Since the voltage of the address electrode is automatically raised by utilizing the capacitance existing between the address electrode and the address electrode, it is possible to realize a stable sustain discharge while suppressing the driving power of the circuit.

In other words, according to the image display device of the present invention, first, the voltage required for the sustain discharge is alternately changed by ２ at a different polarity, and the first electrode such as the X sustain electrode and the Y scan electrode Is applied to the second electrode. Therefore, it is possible to minimize the adverse effect on the sustain discharge of the address electrodes and the like, and to use a low withstand voltage address data driver. Furthermore, since the selection potential of the Y scan electrode and the like and the potential at the time of the sustain discharge are the same, the type of power supply can be reduced, and the configuration of the power supply circuit can be simplified. Can be provided.

Further, according to the image display device of the present invention, secondly, the address pulse applied to the address electrode or the like during the address period has a positive polarity with respect to 0 V, and the scan pulse applied to the Y scan electrode or the like has a voltage of 0 V Therefore, ion impact on the phosphor on the address electrode side during selective write discharge can be minimized.
Furthermore, according to the image display device of the present invention, thirdly, since the address pulse has a positive polarity with respect to 0 V and has the same voltage as the sustain discharge pulse, the configuration of the power supply circuit is simplified. Can be achieved.

Furthermore, according to the image display device of the present invention, fourthly, when the potential of the sustain discharge pulse is set to 0 V, since a high-impedance element is used, a large current does not flow and other circuits can be used. It is possible to prevent malfunctions and failures caused by the intrusion of noise of the above.
Fifth, according to the image display device of the present invention, during the reset period, all display cells can be reset by self-erasing discharge over the entire surface by using a switching element having sufficiently low impedance. And a stable reset operation can be performed.

On the other hand, according to the driving method of the image display device of the present invention, firstly, the voltage required for the sustain discharge is alternately changed by ず つ with the first electrode such as the X sustain electrode and the Y scan. The voltage is applied to a second electrode such as an electrode. Therefore, it is possible to minimize the adverse effect on the sustain discharge of the address electrodes and the like, and to lower the withstand voltage of the address data driver.

Further, according to the driving method of the image display device of the present invention, secondly, the address pulse applied to the address electrode or the like during the address period has a positive polarity with respect to 0 V, and the scan pulse applied to the Y scan electrode or the like. Since the pulse has a negative polarity with respect to 0 V, the quality of the image display panel can be prevented from deteriorating due to ion impact on the phosphor on the address electrode side during the selective write discharge.

Furthermore, according to the method of driving the image display device of the present invention, thirdly, the address pulse has a positive polarity with respect to 0 V and has the same voltage as the sustain discharge pulse. The configuration and control method are simplified.
Furthermore, according to the driving method of the image display device of the present invention, fourthly, when the sustain discharge pulse applied to the X sustain electrode and the Y scan electrode is switched, that is, when both the X sustain electrode and the Y scan electrode are at 0V. Only in such a case, by applying a voltage pulse as a drive waveform of the address electrode from the level of the voltage Vaw to, for example, the level of 0 V, stable sustain discharge can be performed on the selected cell in the address period. As a result, the operation characteristics of the image display panel can be improved.

Fifth, according to the driving method of the image display device of the present invention, the capacitance existing between the X sustain electrode and the Y scan electrode and the address electrode without using the driver function of the drive circuit unit is reduced. Since the voltage of the address electrode is raised by utilizing the voltage, a stable sustain discharge can be realized while suppressing an increase in the driving power of the circuit.
Further, according to the driving method of the image display device of the present invention, sixthly, only when the first sustain discharge pulse is applied, the circuit is driven to a constant voltage (Vaw voltage) using the circuit on the address electrode side. As a result, the discharge potential among the address electrode, the X sustain electrode, and the Y scan electrode during the sustain discharge period can be stabilized.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS.
In each of the following embodiments, it is assumed that an AC type PDP as an image display device has a structure as shown in FIGS. 12, 13, and 14, for example. Further, the peripheral circuit for operating the AC type PDP is substantially the same as the configuration shown in FIG. 15 described above.

FIG. 2 is a timing chart showing a drive waveform of a voltage pulse applied to an electrode during one subframe in the first embodiment of the present invention.
In the timing chart of FIG. 2 showing the driving method of the image display device according to the first embodiment of the present invention, the value of Vs, which is the voltage of the sustain discharge pulse applied during the sustain discharge period, is set to a positive value. Voltage is applied from the X sustain electrode and the Y scan electrode with positive and negative polarities (+1/2 Vs, -1/2 Vs), and the sustain discharge is repeated while changing the polarity. At this time, the potential of the address electrode is kept at 0V. On the other hand, in the reset period, a negative voltage pulse of -1/2 Vs is applied to the Y scan electrode, and a positive voltage pulse of 1/2 Vs + Vw is applied to the X sustain electrode. By doing so, the entire surface write operation is performed.

Next, by returning both the X sustain electrode and the Y scan electrode to 0 V at the same time, a self-erasing discharge occurs on the entire surface, and all the display cells have no wall charges. Also at this time, the potential of the address electrode is kept at 0V. Further, in the address period, a scan pulse consisting of a negative voltage of -1/2 Vs is applied to the Y scan electrode, and at the same time, an address pulse consisting of a voltage of Va is applied to the address electrode. , An address discharge is performed. Such a series of operations is executed from the first display line to the last display line. At this time, the potential of the X sustain electrode is maintained at a positive voltage of +1/2 Vs.

FIG. 3 is a circuit diagram (part 1) showing a configuration of a drive circuit unit of the image display device according to the first embodiment of the present invention, and FIG. 4 is a drive circuit of the image display device according to the first embodiment of the present invention. FIG. 9 is a circuit diagram (part 2) illustrating a configuration of a unit. However, here, the configuration of a switching element (switching means) such as a field-effect transistor (generally abbreviated as FET) and a diode of the drive circuit unit will be mainly illustrated.

3 and 4, an address data driver 60 for driving the address electrodes A1, A2, A3,..., AM constituting the third electrode 16 applies an address pulse of voltage Va to the address electrodes during the address period. And a second field effect transistor T2 that maintains the potential of the address electrode at approximately 0 V (GND level) during the sustain discharge period. Further, diodes D1 and D2 are connected in parallel and with opposite polarities to these field effect transistors T1 and T2.

Further, the X common driver 40 for driving the X sustain electrode X forming the first electrode 14 changes the value of substantially の of the voltage Vs, which is the voltage of the sustain discharge pulse applied during the sustain discharge period, to: Each of them includes a thirteenth field-effect transistor T13 and a fourteenth field-effect transistor T14, each of which is a switching element that supplies a positive polarity and a negative polarity (+ ／ Vs, − ／ Vs) to the X sustain electrode X. Furthermore, diodes D13 and D14 are connected in parallel and with opposite polarities to these field effect transistors T13 and T14. The field effect transistors T13 and T14 have a function as the first voltage supply unit 4.

Further, the X common driver 40 includes a fifteenth field effect transistor T15, which is a switching element that supplies a voltage pulse for writing having a voltage of Vw to the X sustain electrode X via a capacitor 41, and a sixteenth field transistor. Field effect transistor T16. Furthermore, diodes D15 and D16 are connected in parallel and with opposite polarities to these field effect transistors T15 and T16. These diodes are usually built into the FET.

Further, an eleventh field effect transistor T11 comprising a switching element for returning the potential of the X sustain electrode X from + 1 / 2Vs to 0V, and a switching element for returning the potential of the X sustain electrode X from -1 / 2Vs to 0V And a twelfth field-effect transistor T12. Further, diodes D11 and D12 are connected in parallel and with opposite polarities to the field effect transistors T11 and T12 for releasing the sustain voltage. These field-effect transistors T11 and T12 are composed of elements having a relatively high resistance in the ON state (conductive state).

Further, in FIG. 3, the Y common driver 50 for driving the Y scan electrodes Y1, Y2, Y3,..., YN constituting the second electrode 15 is supplied with a voltage of a sustain discharge pulse applied during the sustain discharge period. A third field-effect transistor T3, which is a switching element that supplies a substantially half value of Vs to the Y scan electrode with negative polarity and positive polarity (− ／ Vs, + ／ Vs), respectively, and , A fourth field effect transistor T4. Further, diodes D3 and D4 are connected to these field effect transistors T3 and T4 in parallel and with opposite polarities. The field effect transistors T3 and T4 have a function as the second voltage supply unit 5.

Further, a diode D30 is connected between the third field-effect transistor T3 and a power supply for supplying a voltage of +1/2 Vs, and a diode D30 is provided between the fourth field-effect transistor T4 and a power supply for supplying a voltage of -1/2 Vs. The diode D30 is connected between them.
Further, a field effect transistor T5 comprising a fifth switching element for lowering the potential of the Y scan electrode from + 1 / 2Vs to 0V, and a switching element for raising the potential of the Y scan electrode from -1 / 2Vs to 0V. A sixth field effect transistor T6 is provided. Further, diodes D5 and D6 are connected in parallel and with opposite polarities to the field effect transistors T5 and T6 for releasing the sustain voltage. These field effect transistors T5 and T6 are composed of elements having a relatively high resistance in the ON state.

Further, in the address period, a seventh field-effect transistor T7, which is a switching element for supplying a 0V non-selection signal SD to the Y scan driver 55, and a -1 / 2Vs selection signal SU to the Y scan driver 55 And an eighth field-effect transistor T8 comprising a switching element. Further, diodes D7 and D8 are connected in parallel and with opposite polarities to these field effect transistors T7 and T8. Further, a diode D70 is connected in series with the seventh field-effect transistor T7.

Further, in FIG. 3, the Y scan driver 55 includes a ninth field effect transistor T9 including a switching element for driving a non-selected cell and a tenth field effect transistor including a switching element for driving a selected cell. T10. Further, diodes D9 and D10 are connected in parallel and with opposite polarities to these field effect transistors T9 and T10.

In the drive circuit section of the embodiment shown in FIGS. 3 and 4, a switching element for returning the potential of the X sustain electrode and the Y scan electrode from -1/2 Vs or +1/2 Vs to 0 V is required. However, since it is not necessary to supply a gas discharge current to these switching elements, an increase in the number of switching elements hardly causes a problem.

FIG. 5 is a timing chart for explaining the operation of the drive circuit unit according to the first embodiment of the present invention.
In FIG. 5, during the entire writing during the reset period, the third field effect transistor T3 on the Y common driver side connected to the Y scan electrode is turned on. Further, when the third field-effect transistor T3 is turned on, the corresponding signal is pulled down to -1/2 Vs via the diode in the Y-scan driver. Further, the thirteenth field-effect transistor T13 and the fifteenth field-effect transistor T15 on the X common driver side, which are connected to the X sustain electrode, are turned on, and a voltage pulse of 1/2 Vs + Vw is applied to the X sustain electrode. Is applied. After the end of the voltage pulse, the sixth field effect transistor T6 is turned on to raise the potential of the Y scan electrode to 0 V, and at the same time, the twelfth field effect transistor T12 is turned on and the X sustain electrode is turned off. The potential is reduced to 0V.

In the address period, the seventh field-effect transistor T7 and the eighth field-effect transistor 8 on the Y common driver side are each turned on, and the non-selection potential is on the non-selection signal SD side of the Y scan driver. While applying 0 V, a selection potential of -1/2 Vs is applied to the selection signal SU of the Y scan driver. Further, the ninth field effect transistor 9 in the Y scan driver is turned on when not selected, and the tenth field effect transistor T10 is turned on when selected, whereby scan pulses are sequentially applied to the Y scan electrodes. At this time, since the X sustain electrode is kept at + Ｖ Vs, the thirteenth field effect transistor T13 keeps on. The address data driver performs an on / off operation of the first field-effect transistor T1 and the second field-effect transistor T2 according to selection / non-selection.

During the sustain discharge period, the field effect transistors T3 to T6 on the Y common driver side and the field effect transistors T11 to T14 on the X common driver side repeat on / off operations, and the sustain discharge pulse is applied to the X sustain electrode and the Y scan electrode. Is applied. The field effect transistors through which current flows due to the discharge during the sustain discharge are T3, T4, T13, and T14.

FIG. 6 is a circuit diagram (part 1) showing a configuration of a drive circuit unit of an image display device according to a second embodiment of the present invention, and FIG. 7 is a drive circuit of the image display device according to the second embodiment of the present invention. FIG. 9 is a circuit diagram (part 2) illustrating a configuration of a unit. Here, however, as in the case of the above-described first embodiment (FIGS. 3 and 4), the configuration of a switching element (switching means) such as a field-effect transistor and a diode of the drive circuit unit is mainly illustrated. It shall be.

The configuration of the second embodiment of the present invention is substantially the same as the configuration of the second embodiment described above, except that the resistances 51, 52, 42 and 43 is different from that of the above-described second embodiment.
In the second embodiment shown in FIGS. 6 and 7, the impedance of the switching means including the switching element is further increased by inserting a resistor in the output stage of the field effect transistor for releasing the sustain voltage. With such a configuration, particularly, the fall of the sustain discharge pulse can be stably performed.

FIG. 8 is a timing chart for explaining the operation of the drive circuit unit according to the second embodiment of the present invention.
The timing chart shown in FIG. 8 is substantially the same as the timing chart (FIG. 5) in the case of the above-described second embodiment. However, in FIG. 8, when the voltage of the sustain discharge pulse applied to the X sustain electrode and the Y scan electrode is returned to 0 V, the field effect transistors T5, T6, T11 and T12 are inserted by inserting the resistors 51, 52, 42 and 43. The current flowing through each is limited. Therefore, it is possible to suppress a large current from flowing due to a gradual fall of the sustain discharge pulse, so that it is possible to prevent generation of noise due to the large current. On the other hand, in the reset period, by operating the field effect transistors T13 and T15 having a relatively low on-resistance, the entire self-erasing discharge can be efficiently performed in a state where a large current can flow.

FIG. 9 is a timing chart showing a drive waveform of a voltage pulse applied to an electrode during one subframe in the third embodiment of the present invention.
The third embodiment shows an example based on a conventional addressing / sustain-discharge-period / write addressing method which is a conventional driving method. In the timing chart of FIG. 9, a period of one subframe of a voltage pulse applied to each electrode is divided into a reset period, an address period, and a sustain discharge period.

In the reset period, for the purpose of initializing all display cells, a voltage pulse composed of a voltage of positive polarity Vs + Vw is applied to the X sustain electrode, thereby performing the entire write operation. Next, by returning the potential of the X sustain electrode to 0 V, a self-erasing discharge is performed on the entire surface.
Further, in the address period, the discharge between the address electrode and the Y scan electrode is executed by a line sequential scanning method for the selected cell corresponding to the display data, and the wall charge of the selected cell is set.

Then, during the sustain discharge period, a sustain discharge pulse consisting of a voltage of Vs (for example, 180 V) is alternately applied to the X sustain electrode and the Y scan electrode, and the sustain discharge is applied to the selected cell on which the wall charges have been set. Done. That is, in this case, by using a driver having the same configuration as that of the related art, the entire writing operation, the entire self-erasing discharge, the address discharge, and the sustain discharge are performed.

Further, in FIG. 9, when the above-described sustain discharge period is started, the circuit on the address electrode side is used only when the first sustain discharge pulse (that is, the sustain discharge pulse of the Y scan electrode) is applied. The voltage is raised to the potential Vaw so as to stabilize the discharge potential among three electrodes including the X sustain electrode, the Y scan electrode, and the address electrode.

Thereafter, as the drive waveform of the address electrode during the above-described sustain discharge period, when the sustain discharge pulses of the X sustain electrode and the Y scan electrode are switched (when the sustain discharge pulse is not output), the voltage Vaw level is reduced to 0V. By applying such a pulse waveform, a stable sustain discharge of the selected cell during the address period can be performed.

FIG. 10 is a diagram showing a configuration of an address electrode unit related to the third embodiment of the present invention, and FIG. 11 is a timing chart for explaining the operation of the address electrode unit of the third embodiment of the present invention. is there. Here, the address electrode unit refers to a component including the address data driver 60 and the image display panel 2 having the address electrodes connected to the address data driver 60.

In FIG. 10, an address data driver 60 for driving an address electrode forming the third electrode 16 includes a switching element for supplying a voltage pulse of voltage Vaw to the address electrode in the initial part of the reset period and the sustain discharge period. And a field effect transistor 62 for holding the potential of the address electrode at 0V. Furthermore, diodes 63 and 64 are connected to these field effect transistors 61 and 62 in parallel and with opposite polarities.

In the address electrode section of FIG. 10, in order to realize supply of a pulse-like drive waveform to the address electrode, a driving method for raising the voltage from 0 V to the original voltage again without using the driver function of the drive circuit section By utilizing the capacitance (panel capacitor capacitance) between the X sustain electrode and the Y scan electrode and the address electrode, the potential of the address electrode is raised by itself. By executing the driving method using the capacitance existing at the intersection between the electrodes, it is possible to suppress an increase in the driving power of the driving circuit unit.

More specifically, in the third embodiment of the present invention, as shown in FIG. 10, a capacitance C13 between the X sustain electrode and the address electrode, a capacitance C23 between the Y scan electrode and the address electrode, and The potential of the address electrode is automatically raised by utilizing the capacitance C12 between the X sustain electrode and the Y scan electrode. By utilizing these capacitances, the potential can be raised to about 100 V by itself. Further, the potential boosted by these capacitances is forcibly returned to 0 V by a switching element in the address data driver 60.

In other words, as shown in the timing chart of FIG. 11, the field-effect transistors 61 and 62 are controlled based on the high-potential-side FET control signal UP and the low-potential-side FET control signal DOWN input to the address data driver 60. By turning it on, the potential of the address electrode is reduced from the voltage Vaw to the voltage 0V. Thereafter, when the voltage of either the X sustain electrode or the Y scan electrode rises while the field effect transistor in the address data driver is in a high impedance state, the potential of the address electrode is raised to Vaw again by the above-mentioned capacitance. . Such a series of operations makes it possible to apply a pulse-like voltage without using the capability of the drive circuit unit.

FIG. 1 is a block diagram illustrating a principle configuration of the present invention. 6 is a timing chart showing a driving waveform of a voltage pulse applied to an electrode during one subframe in the first embodiment of the present invention. FIG. 2 is a circuit diagram (part 1) illustrating a configuration of a drive circuit unit of the image display device according to the first embodiment of the present invention. FIG. 3 is a circuit diagram (part 2) illustrating a configuration of a drive circuit unit of the image display device according to the first embodiment of the present invention. 5 is a timing chart for explaining an operation of the drive circuit unit according to the first embodiment of the present invention. FIG. 9 is a circuit diagram (part 1) illustrating a configuration of a drive circuit unit of an image display device according to a second embodiment of the present invention. FIG. 8 is a circuit diagram (part 2) illustrating a configuration of a drive circuit unit of an image display device according to a second embodiment of the present invention. 6 is a timing chart for explaining the operation of the drive circuit unit according to the second embodiment of the present invention. 9 is a timing chart showing a driving waveform of a voltage pulse applied to an electrode during one sub-frame in a third embodiment of the present invention. FIG. 11 is a diagram illustrating a configuration of an address electrode unit related to a third embodiment of the present invention. 9 is a timing chart for explaining an operation of an address electrode unit according to a third embodiment of the present invention. FIG. 2 is a plan view showing a schematic structure of a general three-electrode surface discharge / AC type PDP. FIG. 2 is a cross-sectional view showing a schematic structure along an address electrode of a general three-electrode surface discharge / AC type PDP. FIG. 2 is a cross-sectional view showing a schematic structure along a sustain electrode of a general three-electrode surface discharge / AC PDP. FIG. 3 is a block diagram showing a configuration of a peripheral circuit for driving a general three-electrode surface discharge / AC PDP. FIG. 9 is a drive waveform diagram for explaining a conventional image display panel driving method using an address period / sustain discharge period separated type / write address system and using a full erase discharge in a reset period. FIG. 17 is a diagram showing a state in which a plurality of subframes are formed in the address period / sustain discharge period separation type / write address system of FIG. 16.

Explanation of reference numerals

REFERENCE SIGNS LIST 1 image display device 2 image display panel 4 first voltage supply means 5 second voltage supply means 14 first electrode 15 second electrode 16 third electrode 22 display cell 31 Control circuit unit 32 Display data control unit 33 Frame memory unit 34 Panel drive control unit 35 Scan driver control unit 36 Common driver control unit 40 X common driver 50 Y common driver 55 Y scan driver 60 Address Data drivers T1 to T16: Field effect transistors

Claims (3)

A first electrode and a second electrode are arranged in parallel on a first substrate for each display line, and a third electrode is provided on the first substrate or on a second substrate opposed to the first substrate. An address period in which display cells are turned on / off in accordance with display data, and a sustain discharge for performing light-emitting display between the first and second electrodes are arranged so as to intersect the first and second electrodes. A driving method of the image display device including a period,
In the sustain discharge period, when both voltage pulses alternately applied between the first and second electrodes for performing the sustain discharge are switched, the potential of the third electrode is reduced from a constant voltage. A method for driving an image display device, comprising: In the sustain discharge period, when the potential of the third electrode is temporarily reduced from a constant voltage to substantially a reference potential, and then the potential of the third electrode is increased to the original constant voltage, the first and second potentials are reduced. 2. The method according to claim 1, wherein the potential of the third electrode is raised by an electrostatic capacitance between the electrode and the third electrode. 3. The driving method for an image display device according to claim 2, wherein the potential of the third electrode is set to a predetermined voltage by means for driving the third electrode only when the first sustain discharge voltage pulse is applied.

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