JP2004022624A - Method for manufacturing solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress dark current and noise, to improve image quality, and to enhance productivity and yield by combining a process of making a transfer transistor, which reads out a signal charge from PD to FD at a unit pixel, as an embedded transistor with a process excellent in reproducibility of an opening pattern of the PD. <P>SOLUTION: P-type dopant ions are implanted in a poly-silicon film 62 which is used for a gate electrode of a transistor at an FD region and a P-type transistor of a peripheral circuit, while N-type dopant ions are implanted at an N-type transistor region immediately after the production of the film in order to induce polarity of the gate electrode. Then an insulation film 63, which masks ions implanted in a diffusion layer and the N-region of the PD, is formed on the silicon film 62. Patterning of the gate electrode is carried out by the self-aligning mask of this insulation film 63. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a solid-state imaging device in which a pixel array unit and a peripheral circuit unit are mounted on one semiconductor chip such as a CMOS image sensor.
[0002]
[Prior art]
3A and 3B are diagrams illustrating an example of a unit pixel in a CMOS image sensor. FIG. 3A is an equivalent circuit diagram in the unit pixel, FIG. 3B is a cross-sectional view illustrating an element structure, and FIG. FIG. 4 shows a potential diagram of a transfer gate for reading out signal charges from a photodiode.
In FIG. 3A, a photodiode (hereinafter, referred to as PD) generates and accumulates electrons corresponding to the amount of received light by photoelectric conversion, and a transfer transistor Tg converts the photoelectrically converted electrons accumulated in the PD into floating diffusion. Unit (hereinafter, referred to as an FD unit).
[0003]
The transfer selection transistor Ty supplies a row selection pulse from a vertical (V) scanner (not shown) to the transfer transistor Tg.
The amplifying transistor Ta detects a potential change of the FD portion due to photoelectric conversion electrons read by the transfer transistor Tg and outputs it as an electric signal. The read transistor Tx outputs an m-th horizontal (H) read signal. Then, the output of the amplification transistor Ta is output as a current signal to an IV (current-voltage) conversion circuit (not shown).
The reset transistor Tr resets the potential of the FD section to the power supply voltage VDD based on the (m-1) th reset signal.
[0004]
In FIG. 3B, the PD includes a P + region (hole separation region) 10 on the surface of the semiconductor substrate and an N− region (photoelectron storage region) 11 thereunder, and the FD portion serves as a drain of the transfer transistor Tg. It is formed from the N + region 12.
Then, a channel region 13 of the transfer transistor Tg is formed between the PD and the FD portion, and a gate electrode 15 is formed thereover via an insulating film 14.
In such a configuration, carriers transferred from the PD by the transfer transistor Tg are electrons (e−), the transfer transistor Tg is an N-channel transistor, the gate electrode 15 of the transfer transistor Tg has N-type polarity, and the channel is Formed on the substrate surface.
Note that such a transfer transistor Tg is not limited to the pixel structure shown in the figure, but is common to various CMOS image sensors.
[0005]
Then, if there is an interface state on the substrate surface below the gate of the transfer transistor Tg, as shown in FIG. 3C, a dark current is generated from under the gate of the transfer transistor Tg during transfer or accumulation. This dark current is added to the image signal as a noise signal and degrades the image quality.
Therefore, as shown in FIG. 4, a method in which a P-type gate electrode 25 is used for an N-channel transfer transistor Tg and an N-type layer 26 is formed on the substrate surface under the gate, that is, a method in which a buried channel transistor is used Has been proposed.
In such a buried channel transistor, the channel 27 through which the current flows is formed at a potential minimum slightly inside the semiconductor surface, and is not affected by the interface state on the surface. Noise due to dark current under the gate can be reduced.
[0006]
In forming the N-region 11 of the PD for storing photoelectric conversion electrons, it is necessary to mask the transfer gate during ion implantation so that an N-type dopant is not implanted into the transfer gate.
Therefore, for example, as shown in FIG. 5A, in order to cover the transfer gate electrode 15 with the resist 31 newly patterned after the gate processing and to open the PD region, it is necessary to pattern the resist with zero misalignment. This is not possible in reality.
Therefore, for example, as shown in FIG. 5B, it is necessary to use a method of pattern-forming a resist 33 for forming an N-region of a PD so as to overlap a resist 32 for gate processing.
[0007]
[Problems to be solved by the invention]
By the way, in the LSIs of the 0.18 μm generation or later, the gate electrode of the N-channel transistor is usually made N-type, and the gate electrode of the P-channel transistor is made P-type.
In such a configuration, since the polarity of the gate electrode and the diffusion layer is the same, the gate electrode and the diffusion layer are simultaneously ion-implanted, and the shortage is additionally implanted into the gate electrode, thereby separately forming the gate polarity. .
However, in the above-described buried channel transfer transistor, since the polarities of the diffusion layer and the gate electrode are different, the P + type gate electrode cannot be formed by the process of simultaneously ion-implanting the diffusion layer and the gate electrode as described above.
That is, since ions of the N-type diffusion layer are also implanted into the P + -type gate electrode, it is necessary to additionally perform ion implantation to cancel the ion, and the number of steps (PR + ion implantation) increases.
[0008]
Further, when forming the N-region of the PD, a so-called double resist technique (a resist of the first layer is not removed, but a second layer of resist is applied and patterned) is used. When the resist pattern is reproduced, the first-layer resist is also removed, so that the first-layer pattern becomes unreproducible, the PD cannot be effectively formed, and the risk of manufacturing failure increases.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a solid-state imaging device capable of achieving both a process of forming a buried channel transistor and a process of forming a photoelectric conversion region having excellent pattern reproducibility.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a pixel array unit in which a plurality of unit pixels for capturing an image of a subject are arranged by a photoelectric conversion unit that generates a signal charge corresponding to an amount of received light, and controlling and controlling the pixel array unit. A transistor forming step of separately forming various transistors included in a peripheral circuit portion that performs signal processing of an imaging signal into an N-type gate transistor and a P-type gate transistor; and in the transistor forming step, a gate electrode of the transistor is formed. N-type or P-type ion implantation is performed after the formation of a silicon film to be formed, and the polarity of the gate electrode is selectively formed. After the ion implantation step, the diffusion layer of the transistor and the photoelectric conversion of the pixel array portion are formed. An insulating film for masking the ion implantation into the charge storage region of the conversion means is formed on the silicon film, and the gate electrode is patterned. And having a Ningu gate electrode forming step.
[0011]
In the method for manufacturing a solid-state imaging device according to the present invention, in a transistor forming step of forming a unit pixel or a peripheral circuit portion, N-type or P-type ion implantation is performed after formation of a silicon film to be a gate electrode, and the polarity of the gate electrode is After that, an insulating film was formed on the silicon film to mask the diffusion layer of the transistor and the ion implantation into the charge storage region of the photoelectric conversion means, and the gate electrode was patterned. The process of forming a channel transistor and the process of forming a photoelectric conversion region with excellent pattern reproducibility can be compatible.
Therefore, generation of dark current in the image array portion and noise on the image can be suppressed by the buried channel type transistor, and image quality can be improved, and the efficiency of the manufacturing process, the yield, and the imaging characteristics can be improved. It becomes possible.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
In this embodiment, in a transistor forming process of a CMOS image sensor, N-type or P-type ion implantation is performed immediately after formation of a silicon film to be a gate electrode of a MOS transistor, and the polarity of the gate electrode is separately formed. Thereafter, an insulating film for masking the ion implantation for forming the N− region of the PD and the diffusion layer is formed on the silicon film, and the gate electrode is patterned.
This process makes it possible to achieve both the process of forming the N-type transfer transistor having the P-type gate and the process of forming the N-region of the reproducible PD.
The CMOS image sensor includes an image array unit in which unit pixels are arranged in a two-dimensional array on one semiconductor chip, and a peripheral circuit unit that drives the image array unit and performs signal processing of an imaging signal. As the structure of the unit pixel, for example, the structure shown in FIG. 3 can be applied.
[0013]
1 and 2 are cross-sectional views showing steps of a method of manufacturing a CMOS image sensor according to an embodiment of the present invention. The left side of the figure shows the steps of manufacturing a buried-channel transfer transistor, and the right side shows other steps. Of the transistor shown in FIG.
First, after an element isolation region (not shown) is formed in the N-type silicon substrate 40 by a commonly used method, ion implantation necessary for forming a transistor in a pixel region and a transistor in a peripheral circuit portion is performed.
In FIG. 1A, a P− type layer 41 is formed in a deep region (> 0.3 μm) of the silicon substrate 40 in the pixel region, and the silicon substrate and the P− layer are formed below the FD and the transfer transistor Tg. A P-type layer 42 is also formed between the mold layers 41.
In the peripheral circuit region, a P-type well region 51 is provided in an N-type transistor region, and an ion implantation layer 52 for adjusting a threshold voltage Vth is provided on an upper surface thereof.
Further, an N-type well region 53 is provided in the P-type transistor region, and an ion implantation layer 54 for adjusting the threshold voltage Vth is provided on the upper surface thereof.
In the surface region of the substrate 40 corresponding to the formation region of the transfer transistor Tg, an N-type layer 43 having the opposite polarity to the channel and the gate electrode is formed.
[0014]
Then, in FIG. 1B, after forming a gate insulating film 61 on the silicon substrate 40, a polysilicon film 62 serving as a gate electrode is formed. This is deposited to a thickness of 200 nm by, for example, a CVD (chemical vapor deposition) method.
Next, in FIG. 1 (C), a boron ion B + as a P-type dopant is applied to the polysilicon film 62 of the P-type transistor in the FD region and the peripheral circuit portion under the condition of 5 KeV, 3.00E + 15 / cm 2, for example. Perform injection.
Further, phosphorus ions P + as an N-type dopant are ion-implanted into the polysilicon film 62 in the N-type transistor region in the peripheral circuit section, for example, under the conditions of 15 KeV and 4E14 / cm 2.
Thereafter, in order to activate those impurities, annealing is performed at 800 ° C. for 60 minutes in an N 2 atmosphere, for example.
[0015]
Next, in FIG. 2D, a silicon oxide film (SiO 2) 63 is deposited on the polysilicon film 62 to a thickness of, for example, 250 nm by a CVD method. The silicon oxide film 63 serves as an insulating film for masking ion implantation into the diffusion layer of the transistor and the charge storage region of the PD.
Thereafter, the polysilicon film 62 and the silicon oxide film 63 are processed into a predetermined pattern shape by patterning the resist 64 and dry etching.
Next, in FIG. 2 (E), the resist 64 used in the processing of FIG. 2 (D) is removed, a resist pattern in which a PD region is opened by a new resist 65 is formed, and arsenic ions As are, for example, 300 KeV, Ion implantation is performed under the condition of 2.3E12 / cm 2 to form an N− region 71 of the PD.
At this time, since the insulating film (silicon oxide film) 63 is present, the transfer gate is masked in a self-aligned manner.
[0016]
Next, in FIG. 2 (F), boron fluoride ions BF2 are ion-implanted on the substrate surface in a region included in the N- region 71 of the PD under conditions of, for example, 50 KeV and 1E13 / cm2, and the P + The layer 72 is formed. Thereafter, a source-drain diffusion layer 73 and an upper layer structure (not shown) of the transistor are formed by a commonly used method, and are used as pixels of a CMOS image sensor.
Here, the implanted ions of the source / drain diffusion layer remain in the 250 nm insulating film (silicon oxide film 63) and are not implanted in the 200 nm polysilicon film (gate electrode) 62.
[0017]
In the manufacturing method according to the present embodiment as described above, N-type or P-type ion implantation is performed immediately after the formation of the silicon film 62 serving as the gate electrode of the transistor, and the polarity of the gate electrode is separately determined. By forming an insulating film 63 for masking the ion implantation for forming the N- region of the PD on the silicon film 62 and patterning the gate electrode, the following effects can be obtained.
(1) In a pixel structure in which signal charges are transferred from a PD to an FD, by using a buried channel transistor as a transfer transistor, it is possible to reduce dark current generated from below the transfer transistor.
[0018]
(2) Similarly, by using a buried channel transistor as the transfer transistor, noise added to the image signal can be reduced, and the image quality of the output image can be improved.
(3) In addition, the ion implantation of a buried channel transistor can be used as a mask using an insulating film for a gate electrode, and a new process is added to a conventional logic process to form a buried channel transfer transistor. In comparison, it can be realized with fewer steps.
(4) Further, it is not necessary to use the double resist technique for the resist mask for forming the N-region of the PD, and the resist pattern can be easily reproduced.
[0019]
Although the above description has been given of the case where the present invention is applied to a CMOS image sensor having a unit pixel having a five-transistor structure, the present invention can be widely applied to a solid-state imaging device having another pixel structure.
Further, the ion species and the implantation conditions in the above description are merely examples, and it goes without saying that various modifications can be made within the scope of achieving the gist of the present invention.
[0020]
【The invention's effect】
As described above, according to the method of manufacturing a solid-state imaging device of the present invention, N-type or P-type ion implantation is performed after a silicon film serving as a gate electrode is formed in a transistor forming step of forming a unit pixel and a peripheral circuit portion. After forming the polarity of the gate electrode, an insulating film for masking ion implantation into the charge accumulation region of the transistor diffusion layer and the photoelectric conversion means is formed on the silicon film, and the gate electrode is patterned. Thus, the formation process of the buried channel transistor and the formation process of the photoelectric conversion region having excellent pattern reproducibility can be compatible.
Therefore, generation of dark current in the image array portion and noise on the image can be suppressed by the buried channel type transistor, and image quality can be improved, and the efficiency of the manufacturing process, the yield, and the imaging characteristics can be improved. This has the effect that it becomes possible.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing each step of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing each step of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention.
3A and 3B are diagrams illustrating an example of a unit pixel in a CMOS image sensor, wherein FIG. 3A is an equivalent circuit diagram, FIG. 3B is a cross-sectional view, and FIG. 3C is a potential diagram.
4A and 4B are diagrams illustrating an example of a unit pixel in a CMOS image sensor using a buried channel transfer transistor, wherein FIG. 4A is a cross-sectional view and FIG. 4B is a potential diagram.
5 is a cross-sectional view illustrating an example of a resist mask for ion implantation into a PD in the CMOS image sensor illustrated in FIG.
[Explanation of symbols]
40 N-type silicon substrate, 41, 42 P-type layer, 43, 71 N-type layer, 51, 53 P-type well region, 52, 54 ion-implanted layer, 61 Gate insulating film, 62 polysilicon film, 63 silicon oxide film, 64, 65 resist, 72 P + layer.

Claims (6)

A pixel array section in which a plurality of unit pixels for capturing an image of a subject by photoelectric conversion means for generating a signal charge corresponding to the amount of light received, and a peripheral circuit section for controlling the pixel array section and performing signal processing of an imaging signal And a transistor forming step of separately forming the various transistors included in the N-type gate transistor and the P-type gate transistor.
In the transistor forming step,
An ion implantation step of performing N-type or P-type ion implantation after forming a silicon film to be a gate electrode of the transistor, and selectively creating the polarity of the gate electrode;
After the ion implantation step, an insulating film for masking ion implantation into the charge accumulation region of the photoelectric conversion means of the pixel array portion and the diffusion layer of the transistor is formed on the silicon film, and the gate electrode is patterned. A gate electrode forming step;
A method for manufacturing a solid-state imaging device, comprising: 2. The method according to claim 1, wherein in the ion implantation step, an N-type dopant is ion-implanted into the N-type gate region and a P-type dopant is ion-implanted into the P-type gate region. For each unit pixel of the pixel array unit, the photoelectric conversion unit, a charge detection unit that extracts a signal charge of the photoelectric conversion unit, and a buried channel type transfer that transfers a signal charge from the photoelectric conversion unit to the charge detection unit 2. The method according to claim 1, further comprising forming a transistor. 4. The method according to claim 3, wherein the buried channel transfer transistor has a polarity of a channel region and a polarity of a gate electrode opposite to each other. 2. The method according to claim 1, wherein said photoelectric conversion means comprises a photodiode including an upper P + region and a lower N- region. 2. The method according to claim 1, wherein the gate electrode comprises a laminated film of a lower silicon film and an upper insulating film.

Images