JP2004021742A - USB device controller - Google Patents

Abstract

Provided is a USB device controller having a small circuit scale and capable of satisfying a restriction on an inter-packet delay time in the USB standard.
Kind Code: A1 In a USB device controller using an SRAM as an end point FIFO defined by a USB standard, transfer data is stored in a data transfer path between an SRAM 11 functioning as an end point FIFO for in-transfer and a serial interface engine (SIE) 2. [Selection] FIG. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a USB device controller in a data communication system between a plurality of devices.
[0002]
[Prior art]
Japanese Patent Application Laid-Open No. H11-328069 is a related art related to a USB device controller in a data communication system between a plurality of devices. In this publication, a USB interface device having a small circuit scale is provided by using a dual port memory for an end point FIFO.
[0003]
[Problems to be solved by the invention]
Universal Serial Bus (USB) is a serial bus interface standard established for connecting a personal computer (PC) to a plurality of PC peripheral devices and performing data communication. It is characterized by simple connectivity and expandability not found in conventional interface standards, and many PC peripheral devices such as a mouse, keyboard, printer, scanner, and modem have recently become compatible with USB.
[0004]
The USB standard defines four transfer modes: control transfer / bulk transfer / interrupt transfer / isochronous transfer, and the transfer mode and transfer direction can be selected according to the purpose of the peripheral device (USB device). The data transfer direction in USB is defined as out transfer when data is transferred from the host PC to a peripheral device (USB device), and in transfer when data is transferred from the USB device to the host PC. It is specified in the USB specification that the transfer is performed via a buffer called an endpoint provided in a USB device controller on the peripheral device side. Basically, it is necessary to provide the same number of endpoint buffers as the number of transfer modes and transfer directions supported by the USB device.
[0005]
FIG. 1 shows a configuration example of a USB device controller. It is roughly classified into a PHY block 1, an SIE (serial interface engine) block 2, an end point block 3, an internal register block 4, and a user interface block (I / F block) 5.
[0006]
The PHY block 1 is a block for performing serial data transmission / reception with a host PC via a USB cable, serial / parallel mutual conversion, and the like. The SIE block 2 is a block that performs processes related to the USB communication protocol such as packet ID decoding / encoding and CRC generation / detection.
[0007]
The endpoint block 3 is composed of an endpoint FIFO and its peripheral circuits, and is a block that buffers USB transmission / reception data. The internal register block 4 is a block accessed by a device-side CPU such as a printer or another block for controlling the USB controller and checking the state.
[0008]
The user interface block 5 is an interface block for transferring data between a device-side memory such as a printer and an end point FIFO and accessing an internal register.
[0009]
Data transmission / reception between the host PC and the USB device is executed using a packet transmission / reception sequence called a transaction. In the USB specification, a plurality of USB devices can be connected, but there is only one USB device to be transmitted / received in one transaction.
[0010]
The data communication of a plurality of devices can be performed by a plurality of transactions. However, in order to prevent the transactions from overlapping in time, the time interval (inter-packet delay time) between each packet constituting the transaction and the host PC The time interval (timeout time) for determining the establishment is strictly defined in the USB specification.
[0011]
The inter-packet delay time and the timeout time will be described with reference to FIG. According to the USB standard, it is required that the host PC and the device connection operate normally even when connected via up to five hubs, and FIG. 2 shows the most severe case. A transaction in in-transfer is established by normal transmission and reception of three packets as shown below.
[0012]
{Circle around (1)} The host PC issues an IN token packet for requesting data transmission to a specific device (t = t0). The IN token packet contains information on the USB address number of the specific device and the endpoint number of the device.
[0013]
{Circle around (2)} The IN token arrives at the device with a delay of the delay time (Td = t2-t0) between the hub and the USB cable (t = t2). When the transfer data to be transmitted to the endpoint FIFO of the specific device is ready, the device transmits the transfer data to the host PC (t = t4). The time interval (Tipd) between t3 and t4 in the figure is one of the inter-packet delay times. However, if the transfer data is not ready, a NAK packet (not shown in FIG. 2) is transmitted instead of the transfer data, and the transaction is completed with two packets (IN-NAK).
[0014]
{Circle around (3)} Transfer data from the device arrives at the device delayed by the delay time (Td '= t5-t4) between the hub and the USB cable (T = t5). When the host PC normally receives the transfer data, the host PC transmits an ACK packet to the device (t = t8), and notifies the establishment of the transaction. The host transmits an ACK packet when a data packet arrives from a device within a timeout period (Ttout) specified by the USB standard and no error is detected in the received data. The time interval (Tipd ′ = t8−t7) from the completion of data reception by the host to the transmission of ACK is also the inter-packet delay time.
[0015]
If the interval between t3 and t4 exceeds the maximum allowable value of the inter-packet delay time, the interval between t1 and t5 will also be correspondingly longer, and will exceed the timeout time (Ttout). In this case, the host interrupts the transaction without sending an ACK, and issues an IN token packet again after a certain period of time. However, reduce the number of hub stages between the host PC and the device or change the configuration of the endpoint FIFO. Since the same timeout is repeated unless the data is changed, data transfer using the target endpoint becomes impossible.
[0016]
In the case of the USB 2.0 standard, the maximum inter-packet delay in the HS mode is 192 bits, and the timeout is 816 bits. Since the data transfer rate in the HS mode is 480 Mbps, one bit time is about 2.08 ns. These values indicate values on the USB port of the host PC or device.
[0017]
As a standard conforming to the USB 2.0 standard, an interface specification between a PHY block and an SIE block in USB 2.0 is defined as a UTMI (USB Transceiver Macrocell Interface). Parallel data communication is performed between the PHY block and the SIE block, and a specification of a data width of 8 bits / clock frequency of 60 MHz and a specification of a data width of 16 bits / clock frequency of 30 MHz can be selected.
[0018]
In the UTMI specification, the same inter-packet delay time as in the USB 2.0 standard is applied. For example, in the case of a 16-bit / 30-MHz specification, Tipd (up to 192 bit times) in FIG. 2 corresponds to 7 CLK. The UTMI-standard PHY block is divided into a part that operates at a 480 MHz clock on the USB bus side and a part that operates at 30 MHz on the UTMI side, but the UTMI side has a stricter design for the inter-packet delay time constraint.
[0019]
The PHY and the SIE are connected via the UTMI. If the NIE responds to the IN token, the SIE will issue a NAK packet. Therefore, the USB controller must satisfy the restriction (within 7 CLK) on the UTMI. It is relatively easy to design.
[0020]
On the other hand, when transmitting a data packet to the IN token, it is necessary to read data stored in the endpoint FIFO. If the reading time is slow, the restrictions on UTMI may not be satisfied.
[0021]
As the endpoint FIFO, it is common to use a register or a memory cell such as an SRAM. When the endpoint FIFO is configured by a register, the time from the data read request to the output of the first data is relatively short, so that it is easy to design to satisfy the inter-packet delay time constraint, but the circuit scale becomes large. This leads to an increase in cost.
[0022]
On the other hand, when a memory cell such as an SRAM is used, the circuit size is reduced, but the time until the first data is output becomes longer than when a register is used. It is difficult to achieve a satisfactory configuration.
[0023]
In JP-A-11-328069, the circuit scale is reduced by using a dual-port memory as a transmission / reception memory (endpoint FIFO) of a USB device controller. No consideration was given to the issue.
[0024]
An object of the present invention is to provide a USB device controller having a small circuit scale and capable of satisfying a restriction of an inter-packet delay time in the USB standard.
[0025]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 is a USB device controller using an SRAM as an endpoint FIFO defined by the USB standard, and a serial interface engine (SRAM) and an SRAM functioning as an endpoint FIFO for in-transfer. The most important feature is a USB device controller provided with a register for storing transfer data in a data transfer path between SIEs.
[0026]
According to a second aspect of the present invention, in the USB device controller according to the first aspect, the USB device that writes a part of data in the SRAM to the register at an arbitrary timing from a time point when data writing to the SRAM starts to a time point when the writing is completed. Controller is the main feature.
[0027]
According to a third aspect of the present invention, the USB device controller according to the first or second aspect is characterized in that the interface specification between the serial interface engine and the physical layer block is UTMI (USB Transceiver Macrocell Interface).
[0028]
According to a fourth aspect of the present invention, in the USB device controller according to the first aspect, a bit width of the register is the same as a bus width of data transfer between the SRAM functioning as an in-transfer end point FIFO and a serial interface engine. The main feature is a USB device controller.
[0029]
According to a fifth aspect of the present invention, in a USB device controller using an SRAM as an endpoint FIFO defined by the USB standard, a transfer data is transferred to a data transfer path between the SRAM functioning as an out-transfer endpoint FIFO and a USB device side interface. The most important feature is a USB device controller provided with a storage register.
[0030]
According to a sixth aspect of the present invention, in the USB device controller according to the fifth aspect, a part of the data in the SRAM is written to the register when the data writing to the SRAM is completed and there is no error in the data. Controller is the main feature.
[0031]
According to a seventh aspect of the present invention, in the USB device controller according to the fifth aspect, the bit width of the register is the same as the bus width of a data transfer path between the SRAM functioning as the end FIFO for out transfer and the USB device side interface. The main feature is a USB device controller.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 3 is a configuration diagram of the USB device controller according to the first embodiment of the present invention. A feature of the present invention is that when the SRAM 11 is used for the end point FIFO (end point block 3 in FIG. 1) of the USB device controller, the data is transferred on the data bus line between the SIE block 2 and the end transfer end point FIFO (SRAM) 11 , A data storage buffer (prefetch register) 12 composed of a register.
[0033]
FIG. 4 is a configuration diagram of a USB device controller according to the second embodiment of the present invention. A feature of the present invention resides in that a data storage buffer (prefetch register) 12 composed of a register is provided on a data bus line between the I / F block 5 and the out-transfer end point FIFO (SRAM) 13.
[0034]
The configuration and operation of the present invention will be described in the following embodiments.
[Example 1]
Data to be transferred to the host is written to the in-transfer endpoint FIFO via the I / F block 5 in FIG. Since the transfer data is divided into the maximum data packet units defined in the USB standard, the data writing to the endpoint FIFO is also performed in the maximum data packet unit.
[0035]
For example, in the case of bulk-in transfer, the maximum data packet in the HS mode is 512 bytes, and the maximum data packet in the FS mode is 64 bytes. Since it is necessary to transfer a large amount of data at a high speed in bulk transfer, the FIFO is generally of a double buffer configuration.
[0036]
For example, using a dual port SRAM of 1024 bytes and having a configuration of two 512 bytes is advantageous in terms of circuit size reduction. In the case of the FS operation, it can be used as a 64-byte two-sided buffer by setting the SRAM peripheral circuit.
[0037]
In the IN transfer configuration according to the present invention, a part of the data in the SRAM (the amount corresponding to the register capacity) is transferred to the prefetch register at an arbitrary timing from the start of the data writing to the time when the data in the SRAM is validated. However, until both data writing to the SRAM and data transfer to the prefetch register are completed, the SIE responds to the IN token with a NAK packet.
[0038]
In response to the IN token after the data transfer to the look-ahead register is completed, the SIE generates a data packet in which a packet ID and CRC data for detecting a data error are added to the transfer data and responds. Are sequentially read from those stored in the look-ahead register, so that data packet transmission can be started at a timing that satisfies the inter-packet delay time constraint.
[0039]
The data transfer from the SRAM to the prefetch register is performed every time the SIE starts data packet transmission and the prefetch register becomes available. In this case, the data output time from the SRAM is longer than the output time at the start of reading. Because of the short length, data transfer following the data transfer from the prefetch register to the SIE is possible, and transmission of a data packet satisfying the USB standard (inter-packet delay time and continuity of the data packet) becomes possible.
[0040]
The parallel number and the number of stages of the FFs (flip-flops) constituting the look-ahead register can be appropriately set so as to satisfy the inter-packet delay time constraint according to the data output time of the SRAM used and the configuration of the SIE block. By making the data bus width the same as that between the SIE and the SRAM, the configuration of the SRAM peripheral circuit including the prefetch register and the SIE block can be simplified.
[0041]
For example, when 16 bits / 30 MHz of the UTMI specification is selected, the number of parallel FFs may be set to 16 (2 bytes). Regarding the number of stages, it is usually possible to satisfy the inter-packet delay time constraint with about three stages. In this case, the look-ahead register capacity is 6 bytes. The register capacity may be set as appropriate, but setting it larger than necessary undesirably increases the circuit scale.
[0042]
The above is the invention relating to the USB inter-packet delay time constraint in the in-transfer, but the same configuration can be used for reading data from the out-transfer endpoint FIFO to the USB device side.
[0043]
[Example 2]
In the out transfer, the host PC successively transmits an OUT token and a DATA token to a specific device. The SIE of the specific device decodes the USB address number and the endpoint number included in the OUT token, and responds as follows according to the state of the target endpoint FIFO.
[0044]
a) When there is no space for the maximum number of packet data in the SRAM, the SIE transmits a NAK packet to notify the host PC that data could not be received.
[0045]
b) If it is determined that the SRAM has free space for the maximum number of packet data and the received data has no error, the SIE transmits an ACK packet to notify the host PC that the data has been successfully received. Notice.
[0046]
c) If any error is detected in the received data, or if the transaction itself does not satisfy the protocol of the USB standard, the SIE does not transmit the NAK packet / ACK packet.
[0047]
In cases a) and c) above, the host PC will send the same data using another transaction. When the data b) is normally received, the data is transferred to the USB device side main memory or the like via the I / F block 5 shown in FIG. This data transfer is performed by DMA transfer or PIO transfer. In the case of PIO transfer, the first data output at the time of accessing the SRAM may be a problem.
[0048]
In the case of PIO transfer, a method of accessing an SRAM by designating an end point FIFO using an address of an internal register in FIG. 1 is generally used. In the I / F block, general-purpose buses such as a CPU bus / ATAPI / PCI bus are used. In read access on these general-purpose buses, a timeout time similar to the USB standard is determined. .
[0049]
More specifically, the time from when the I / F starts a read access request to the out-transfer endpoint FIFO to when the read data from the endpoint FIFO is output to the I / F is determined. . When the SRAM is used for the endpoint FIFO, the time from when the read request arrives at the SRAM until the data is output is longer than that of the register, so that the data transfer on the I / F cannot be established due to the timeout. There is. In particular, when the end point FIFO is assigned to the internal register, the restriction becomes more severe by the time required for address decoding.
[0050]
In the second embodiment, as described above with reference to FIG. 4, when the SRAM is used for the out-transfer endpoint FIFO, the data bus line between the I / F block 5 and the out-transfer endpoint FIFO (SRAM) 13 is used. A data storage buffer (look-ahead register) 12 composed of a register is provided.
[0051]
When the out-transfer SRAM is receiving data via the SIE, the access right to the SRAM is on the SIE side. When one packet of data is stored in the SRAM and it is confirmed that there is no error in the data, the data in the SRAM is determined and the access right to the SRAM is transferred to the I / F side.
[0052]
Thereafter, data transfer from the SRAM to the prefetch register is performed. Generally, an interrupt to the device-side CPU is used for a data transfer request by PIO transfer, and an interrupt is generated when data transfer to the prefetch register is completed.
[0053]
The device-side CPU performs read access to the out-transfer SRAM via the I / F after confirming that there is data to be read in the out-transfer SRAM by an interrupt request. Since a part of the read data is already stored in the prefetch register, it is possible to output the data within a time that satisfies the time-out time restriction of the general-purpose bus used for the I / F.
[0054]
As in the case of the first embodiment, the parallel number and the number of stages of the FFs (flip-flops) constituting the look-ahead register satisfy the time-out time constraint depending on the data output time of the SRAM used and the configuration of the I / F block. However, the configuration of the SRAM peripheral circuit including the look-ahead register and the configuration of the I / F block can be simplified by making the number of parallels the same as the data bus width between the I / F block and the SRAM.
[0055]
For example, when the PCI specification is 32 bits / 33 MHz, the number of parallel FFs may be 32 (4 bytes). Regarding the number of stages, it is usually possible to satisfy the timeout time about two stages, and in this case, the look-ahead register capacity is 8 bytes. Although the register capacity may be set as appropriate, setting it larger than necessary undesirably increases the circuit scale.
[0056]
As a difference from the first embodiment, the data transfer to the prefetch register needs to be performed after data of one packet is stored in the SRAM and it can be confirmed that there is no error in the data (after data is determined). The reason is that, in the case where the transfer is performed before the data is determined, if an error is finally detected, the circuit and the control procedure become complicated by the amount of means for erasing the data in the look-ahead register. .
[0057]
【The invention's effect】
As described above, according to the present invention, a transfer data storage register (look-ahead register) is provided in a data transfer path between an SRAM functioning as an in-transfer endpoint FIFO and a serial interface engine (SIE), and the SRAM is provided in the SRAM. A USB device controller that satisfies an inter-packet time constraint from reception of an IN token packet to transmission of a data packet specified by the USB standard and the UTMI standard by transferring a part of the stored transfer data to a look-ahead register in advance. Can be realized.
[0058]
In this case, the circuit scale can be reduced by using an SRAM for the end point FIFO and setting a minimum register size for the prefetch register to satisfy the time constraint. 4).
[0059]
According to the present invention, a transfer data storage register (prefetch register) is provided on a data transfer path between the SRAM functioning as an out-transfer endpoint FIFO and the USB device-side interface, and one of the transfer data stored in the SRAM is provided. By transferring the section in advance to the look-ahead register, a USB device controller that satisfies the timeout time restriction of the general-purpose bus standard used for the USB device-side interface can be realized.
[0060]
In this case, the circuit scale can be reduced by using an SRAM for the end point FIFO and setting a minimum register size necessary to satisfy the time constraint for the prefetch register. 7).
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram of a USB device controller.
FIG. 2 is an explanatory diagram regarding an inter-packet delay time and a timeout time in the case of in-transfer.
FIG. 3 is a configuration diagram of a USB device controller according to the first embodiment of the present invention.
FIG. 4 is a configuration diagram of a USB device controller according to a second embodiment of the present invention.
[Explanation of symbols]
2 SIE block 11 In-transfer endpoint FIFO (SRAM)
12 Data storage buffer (prefetch register)

Claims (7)

In a USB device controller using an SRAM as an end point FIFO defined in the USB standard, a transfer data storage register is provided on a data transfer path between the SRAM functioning as an end point FIFO for in-transfer and a serial interface engine. Characteristic USB device controller. 2. The USB device controller according to claim 1, wherein a part of the data in the SRAM is written to the register at an arbitrary timing from a point in time when data writing to the SRAM starts to a point in time when the writing is completed. 3. The USB device controller according to claim 1, wherein an interface specification between the serial interface engine and the physical layer block is UTMI. 2. The USB device controller according to claim 1, wherein a bit width of the register is the same as a bus width of data transfer between the SRAM functioning as an in-transfer endpoint FIFO and a serial interface engine. . In a USB device controller using an SRAM as an end point FIFO specified by the USB standard, a transfer data storage register is provided in a data transfer path between the SRAM functioning as an end FIFO for out transfer and a USB device side interface. A USB device controller, characterized in that: 6. The USB device controller according to claim 5, wherein a part of the data in the SRAM is written to the register when it is confirmed that the writing of the data to the SRAM is completed and there is no error in the data. 6. The USB device controller according to claim 5, wherein a bit width of the register is the same as a bus width of a data transfer path between an SRAM functioning as an end FIFO for out transfer and a USB device side interface. Device controller.

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