JP2004014704A - Laser diode drive circuit - Google Patents

Abstract

An object of the present invention is to provide a laser diode driving circuit capable of reducing a leakage current between a drain and a source even under a deep gate bias condition.
A current source FET of a differential pair FET constituting a driving circuit of a laser diode is connected in series with each other, and a gate bias potential for the serially connected FET is appropriately applied by resistance division. I decided. For this reason, the voltage applied between the drain and the source of the current source FET is divided by the two FETs arranged in series, and the voltage applied to one FET is equal to the voltage applied to the current source FET having the conventional configuration. Lower than This makes it possible to provide a laser diode drive circuit that can reduce the drain-source leakage current even under the condition that the gate bias is deep.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a laser diode driving circuit, and more particularly, to a laser diode driving circuit capable of reducing a drain-source leakage current.
[0002]
[Prior art]
The laser diode (LD) is normally driven by two types of modulation currents, ie, a modulation current for turning on / off the LD in response to a signal, and a bias current which is a minimum current required for operating the LD in the laser mode. Current is needed.
[0003]
FIG. 7 is a diagram for explaining an example of a general circuit of a conventional LD drive device. In this circuit diagram, a modulation current is switched in response to a modulation signal input via a modulation current control terminal. A differential amplifier circuit for performing the above operation is shown.
[0004]
The IC 70 provided in this LD driving device includes differential transistor pairs Q1 and Q2 to which signals are complementarily input. The differential transistor pair Q1, Q2 is an enhancement-type or depletion-type FET. An LD is connected to the transistor Q1, and the transistor Q2 has a resistance value substantially equal to the equivalent resistance of the LD connected to the transistor Q1. An external resistor R1 is connected.
[0005]
The differential transistor pair Q1, Q2 is connected to a current source transistor Q4, which is a common source. The source of the current source transistor Q4 is connected in the forward direction connected diode D1, to its gate, the voltage _{V M} is applied to the modulation current control terminal 72 from IC70 external APC (Auto Power Control) circuit 71 Signal input for modulation current control is performed.
[0006]
Here, the diode D1, the gate of the transistor Q4 in which OFF the current source transistor Q4 - a level shifter diodes for transfer money source voltage V _GS negative. Also, R2 in the figure, when the modulation current control terminal 72 is opened, a resistor for causing OFF the current source transistor Q4 a voltage V _M as V _SS.
[0007]
In the circuit shown in FIG. 7, when the signal input In is High, the transistor Q1 is turned on and the transistor Q2 is turned off, so that the constant current set by the current source transistor Q4 mainly flows through the transistor Q1. It will flow to LD. On the other hand, when the signal input In is Low, the inverted input / In becomes High, so that the transistor Q2 is turned on and the transistor Q1 is turned off. As a result, no current flows through the LD. By such switching of the current path, modulation of the LD corresponding to the signal input is performed.
[0008]
Note that the bias current is supplied by the transistor Q5. The bias current does not depend on the signal input, and a constant current is supplied to the LD even when the transistor Q1 is off.
[0009]
The APC circuit 71 is used to prevent the operation of the LD from deviating from its original setting due to a change over time, and to correct fluctuations in the light emission intensity of the LD due to the ambient temperature. Specifically, a part (several percent or less) of the light emitted from the LD is received and amplified by a photodiode (PD) disposed on the rear surface of the LD (the light extraction surface is the front surface), and the average is averaged. A value is obtained, and the gate bias applied to the current source transistor Q4 is controlled so that the difference between the average value and the predetermined value is made zero.
[0010]
For example, in order to obtain a predetermined luminous intensity in a state where the ambient temperature of the LD rises, or at the end of the life of the LD, the luminous efficiency of the LD is lower than the original luminous efficiency, the current should be higher than the current that should normally flow A large amount of current needs to flow to the LD. When such a situation becomes extreme, there is a possibility that the LD itself may be destroyed by a current flowing through the LD. Therefore, the LD drive circuit is required to have a function of turning off the gate bias applied to the current source transistor Q4 to cut off the current flowing through the LD so that such an overcurrent does not occur and destroy the LD itself. . In particular, the threshold current of a recent LD is several mA, and in order to completely control ON / OFF of light emission of this LD, a leak current generated in a control circuit of an ON / OFF control signal is suppressed to 1 mA or less. Is required.
[0011]
[Problems to be solved by the invention]
However, when a conventional FET is used as a current source of an LD drive circuit with an APC function, a leak current occurs between the drain and source of the FET even if the FET is turned off by a control signal input from the outside. Therefore, there is a problem that the operation of the FET is not completely turned off.
[0012]
Conventionally, a method of shortening the gate length has been generally adopted in order to improve the performance (high-speed operation) of the FET. Is about 0.2 to 0.3 μm, and the gate length of the FET for the purpose of integration is about 0.3 to 0.7 μm. However, shortening the gate length of the FET results in impairing the static characteristics of the FET, resulting in an increase in leak current and a decrease in breakdown voltage.
[0013]
Figure 8 is a gate length of a typical drain of 0.5μm of FET - a diagram for explaining the _I DS _{-V DS} characteristics of the source voltage _{(V DS)} - source current _{(I DS)} and the drain . Gate - even if the gate bias V _GS applied between the source deep (direction does not flow I _DS), I _DS increases according slide into increasing the V _DS, so called leakage current comes to increase.
[0014]
Therefore, when an FET having such characteristics is used as a switching element of an LD drive circuit, the LD exhibits stable characteristics in a state where the FET is turned on and a current flows through the LD. In the LD, a situation similar to the case where the FET is not turned off apparently occurs due to a leak current generated in the FET. As a result, there is a problem in that it is difficult to sufficiently secure the function required for the LD drive circuit, namely, "to completely control ON / OFF of the light emission of the LD".
[0015]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a laser diode driving circuit capable of reducing a drain-source leakage current even under a condition where a gate bias is deep. It is in.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a laser diode driving circuit that outputs an optical signal according to a modulation signal, and receives a first signal. A differential pair transistor, a voltage dividing circuit for dividing a second signal by resistance division, and a first current source circuit of the differential pair transistor, wherein the first signals are complementary to each other. Two complementary signals are input to respective control terminals of the transistors constituting the differential pair transistor, and one anode of the differential pair transistor is connected to the laser diode. The first current source circuit includes a first transistor connected to a common cathode of the differential pair transistors, and a second transistor of the same polarity connected in series to the first transistor. And a control terminal of the first transistor and the control terminal of the second transistor. The divided second signal is input to each of the control terminals of the first transistor and the second transistor. 2, the voltage between the anode and the cathode of the second transistor is reduced, so that the current flowing through the first current source circuit becomes substantially zero. The current output to the laser diode is substantially cut off.
[0017]
According to a second aspect of the present invention, in the laser diode driving circuit according to the first aspect, the divided second signal input to a control terminal of the first transistor is connected to the laser diode. Is a light output control signal for keeping the light output of the light emitting device constant.
[0018]
Further, the invention according to claim 3 is the laser diode drive circuit according to claim 1 or 2, further comprising a second current source circuit and a voltage level control diode, wherein a cathode of the second transistor is provided. The second current source circuit is connected to the anode of the voltage level control diode, and the cathode potential of the second transistor is biased to a predetermined value.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
FIG. 1 is a circuit diagram illustrating an embodiment of a laser diode drive circuit according to the present invention. The circuit shown in this figure is commonly used for a modulation signal generation circuit and a bias signal generation circuit in FIG. 2 to be described later. Here, a description will be given assuming that the circuit shown in this figure is a modulation signal generation circuit.
[0021]
This circuit is similar to the conventional circuit shown in FIG. 7 in the configuration of the differential pair transistors Q1 and Q2 provided in the IC 10 and how the LD is connected to the differential pair transistors Q1 and Q2. The point that the current source is composed of two transistors Q4 and Q5 connected in series with each other, and a new resistor R3 is added to divide the input signal from the APC circuit 11 and input the divided voltage to the gate of the transistor Q5. Is different.
[0022]
The transistor Q4 has a drain connected to a common source of the differential pair transistors Q1 and Q2, a source connected to the drain of the transistor Q5, and a gate connected to an APC circuit 11 provided outside the IC 10. signal input for modulation current control voltage V _M is applied is made in modulated current control terminal 12 from.
[0023]
The resistance values of the resistors R2 'and R3 are obtained by applying an appropriate voltage to the modulation current control terminal 12 by the APC circuit 11 under the condition that the sum of these resistance values (= R2' + R3) becomes equal to R2. The gate-source potential (V _GS ) of the transistor Q5 is determined to be about 0.5 V when the LD is turned on.
[0024]
The source of the transistor Q5 is connected to the potential setting diode Q3 and the second current source 13. With the second current source 13 and the diode Q3, the source of the transistor Q5 can always be offset to about 0.6 to 0.7 V, and the potential applied from the APC circuit 11 to the modulation current control terminal 12 is reduced. it is possible to turn OFF the transistor Q5 when it becomes approximately equal to V _SS. The current value set by the first current source constituted by the transistors Q4 and Q5 depends on the type of LD, but is about several tens mA.
[0025]
The gate width ( _WGQ5 ) of the transistor Q5 is determined so that the current I _LD flowing through the _LD has a desired current value. In order to reduce the leakage current between the drain and the source of the transistor Q5, it is advantageous to set the _WGQ5 as narrow as possible. In order to obtain a necessary drain-source current value at this time, in this circuit, V _GS is set to be high.
[0026]
Assuming a supply voltage V _SS to be a common value -5.0V in this circuit, the source potential of the transistor Q5, so that the source is self-biased by a second current source 13 and the diode D1 (V _(SS + 0.7) V, which is clamped to about -4.3V.
[0027]
In general, the current _{I DS} flowing through the FET is given approximately by ^{_{g m · (V GS -V th}} ) 2 · W G. Here, _{g m} the _{transconductance, V GS} is the gate - source _{voltage, V th} be the threshold voltage of the FET and,, _{W G} is the gate width. That is, when the gate-source voltage V _GS is equal to or higher than the threshold voltage _Vth of the FET, a current starts flowing through the FET, and the current value is equal to the difference between the gate-source voltage V _GS and the threshold voltage _{Vth of the} FET. Shows a relationship proportional to the power.
[0028]
As it is apparent from this relation, if setting a higher V _GS, it is possible to narrow the gate width W _G capable of supplying a predetermined current to the FET. Thus, in the circuit of the present invention sets the _{V GS} for example 0.4~0.5V with. Assuming that V _GS is 0.5 V, the gate potential of the transistor Q5 is higher than the source potential by 0.5 V, and a value of about −3.8 V is obtained. Therefore, the resistors R2 ′ and R3 are set to have this gate potential. Adjust the voltage division ratio of the resistor.
[0029]
Further, when the APC control the input level around the value (-3.5 V) was increased by about 1.5V from the _{V SS} from the APC circuit 11, the resistance division ratio of the resistors R2' and R3, R3 / What is necessary is just to set so as to satisfy (R2 ′ + R3) = (0.7 + 0.5) /1.5 (= 4/5). In this case, since almost no current flows through the gate of the FET, for example, R2 ′ can be set to 0.3 kΩ and R3 can be set to 1.2 kΩ.
[0030]
The gate width _{W GQ5} transistor Q5 may be set as desired current value _{I DS} is obtained, in which case the gate bias of about + 0.5V can be, for example, 700 .mu.m. The gate width _WGQ5 depends on a current value, a threshold voltage, characteristics, and the like to be taken out from the FET, and is not limited to about 700 μm.
[0031]
When the IC 10 is configured as described above, the drain potential of the transistor Q5 is lower than the gate input potential of the transistor Q4. If the characteristics of the transistor Q4 are the same as the characteristics of the transistor Q5, the drain potential of the transistor Q5 is -3.5V-0.5V = -4.0V, depending on the APC control signal, and the drain-source The voltage between them is about 0.3V.
[0032]
On the other hand, in the case of the conventional circuit configuration as shown in FIG. 7, assuming that the transistor Q4 in FIG. 7 has the same characteristics as the transistor Q5 in FIG. 1, the drain potential of the transistor Q4 is smaller than the APC input potential. It is obvious that the potential becomes the potential defined by the potential of In or / In having a high potential.
[0033]
Therefore, the drain-source voltage of the transistor Q5 shown in FIG. 1 is greatly reduced as compared with the transistor Q4 shown in FIG. 7, and the drain-source voltage of the transistor Q5 shown in FIG. It becomes possible to set.
[0034]
Note that the drain-source voltage of the transistor Q4 in FIG. 1 is slightly lower than the drain-source voltage of the transistor Q4 in FIG.
[0035]
In the circuit shown in FIG. 1, when the gate potential of the transistor Q4 example V _SS, the gate of the transistor Q5 - between the source while being reverse biased drain of the transistor Q5 - a value of negligible source voltage . This means that the current flowing through the transistors Q4 and Q5 can be made substantially zero by controlling the gate input potential of the transistor Q4, and the leakage current can be significantly reduced. Becomes possible.
[0036]
FIG. 2 is a diagram for explaining an overall view of an LD drive circuit and an example of a conceptual APC circuit of an LD drive device according to the present invention. This LD drive circuit includes a data input buffer amplifier circuit 21 and a clock input buffer. It comprises an amplifier circuit 22, a DF / F circuit 23, a modulation signal generation circuit 24, and a bias signal generation circuit 25.
[0037]
The data input buffer amplifier circuit 21 and the clock input buffer amplifier circuit 22 are FET amplifier circuits of a differential output having a well-known configuration, and these amplifiers are connected between input terminals in order to control a signal having a frequency of 2.5 GHz or more. Matched to 50Ω.
[0038]
The signals output from the data input buffer amplifier circuit 21 and the clock input buffer amplifier circuit 22 are transmitted to the DF / F circuit 23 and retimed to become LD drive modulation signals.
[0039]
The DF / F circuit 23 has an input section corresponding to the data signal D and its inverted signal / D, and the clock signal CLK and its complementary input of the inverted signal / CLK. (Disable: DS) An input section corresponding to a complementary input DS and / DS of the signal is also provided. This DS signal is provided for LD protection and safety standards. When the DS signal becomes true, the potential at point A in the figure is forcibly set to the power supply voltage V _DD , and All current supplied is cut off.
[0040]
FIG. 3 is a detailed circuit diagram of the DF / F circuit, which is composed of a normal master-slave type DF / F circuit. The output section on the slave side is provided with a DS circuit for forcibly setting the output Q from the DF / F circuit and its inverted output / Q to Low and High, respectively.
[0041]
When the DS circuit is provided, when the DS signal becomes true (High) in a state where the transistor Q6 is ON and the transistor Q7 is OFF, the ON / OFF states of the transistor Q6 and the transistor Q7 are inverted, and the transistor Q6 is turned ON. OFF, the transistor Q7 is ON.
[0042]
When the transistor Q7 is turned on in this way, a differential pair transistor composed of the transistors Q8 and Q9 connected to the transistor Q7 comes to function. Since a fixed bias is applied to the gates of these transistors Q8 and Q9 in advance so that the transistor Q8 is turned on and the transistor Q9 is turned off, when the DS true signal is input, the DF / F circuit Are forcibly set so that the Q output of the L is low and the / Q output is high.
[0043]
FIG. 4 is a circuit diagram for explaining the configurations of the output buffer circuit and the modulation driving circuit. The output buffer circuit is a conventional FET differential amplifier circuit, a current source by configuring the current source of the modulation drive circuit in two stages connected in series FET, even if the V _M becomes OFF (approximately 0V) Can be turned off.
[0044]
Further, since the input signal D and DS signals to the inverted signal / D is superimposed, if the DS signal is true when the V _M is normal operation, the D-F / F circuit Becomes low, OUT becomes high, and the LD connected between the OUT terminal and the power supply voltage _VDD can be turned off.
[0045]
FIG. 5 is a circuit diagram for explaining the configuration of the LD bias current control circuit. The magnitude of the bias current is controlled by the V _bias signal. Since _Vbias is controlled by a circuit having a configuration in which transistors Q4 and Q5 are connected in series, similarly to the above-described modulation drive circuit, by cutting _Vbias and setting it to almost 0 V, the bias current is almost completely reduced. It is possible to shut off.
[0046]
Further, a differential circuit including transistors Q1 and Q2 receiving a DS signal is provided between the drain output of the transistor Q4 and the OUT terminal, and is supplied to the LD even when the DS signal becomes true. Bias current can be cut off. Due to the operation of this differential circuit, when the DS signal becomes true, the current set by the transistors Q4 and Q5 flows exclusively to the transistor Q2, and the current supply to the LD connected to the OUT terminal is cut off. Become.
[0047]
A resistor R _mon for monitoring a potential difference is provided outside the IC circuit, and a potential difference generated between both ends of the resistor R _mon is constantly monitored. When the potential difference exceeds a predetermined potential difference, the DS signal becomes true and the LD signal becomes true. The operation is turned off.
[0048]
V _bias is controlled via an APC circuit. Light intensity observed in PD by (optical coupling between the particular LD and PD) status in the feedback loop may become weaker, but V _bias by feedback control increases, the LD destruction by increase in V _bias In order to avoid this, the DS signal can be made to function by setting the resistance value of the resistor R _mon in advance so that the current value does not reach the LD breakdown current.
[0049]
FIG. 6 is a circuit diagram for explaining the configuration of the APC circuit. Normally, the light emission state of the LD is monitored by detecting a small amount of light (light intensity of 1% or less of the total light intensity) from the back surface of the LD by a PD provided near the back surface of the LD. The monitor signal from the PD is first converted from a current signal to a voltage signal by the first stage I / V converter. At the same time, the cutoff frequency is set to 1 / (2π · R1 · C1) by the capacitor C1 connected in parallel with the feedback resistor R1, and the higher frequency side is cut off to smooth the signal. .
[0050]
When the light emission intensity of the LD increases, the output current of the PD also increases, and as a result, the output of the I / V converter decreases. The decrease in the output of the I / V converter is input to the non-inverting amplifier, where the difference signal from the reference signal is calculated and amplified, and is supplied to the LD drive circuit as a V _bias signal.
[0051]
Since the output signal from the non-inverting amplifier has the same phase as the input signal, when the output of the I / V converter decreases, the output potential of the non-inverting amplifier also decreases. Therefore, the V _bias signal supplied to the LD drive circuit decreases, and the light emission intensity of the LD decreases. In this way, feedback control is realized.
[0052]
In the circuit example shown in FIG. 6, the modulation current is controlled by adjusting and fixing the bias applied to the modulation current control terminal at the beginning of the LD drive, and by constantly applying this bias to the modulation current control terminal.
[0053]
The LD temperature characteristic can be compensated for by using a resistor whose temperature characteristic cancels the LD temperature characteristic as the resistor R2 connected to the fixed bias circuit. That is, since the LD has a temperature characteristic in which the luminous efficiency decreases as the temperature rises, if a resistor having a characteristic in which the resistance value decreases as the temperature rises is used as the resistor R2, the modulation current increases as the temperature rises. the voltage V _M increases to be applied to the control terminal, it is possible to compensate for the temperature characteristics of the LD.
[0054]
Further, a circuit design is made such that the difference signal is monitored as needed, with the maximum emission intensity of the LD emission signal as a high signal and the minimum emission intensity as a low signal, and the same feedback control as the APC circuit used for V _bias is performed. It is also possible to obtain a constant modulated optical signal by this feedback control.
[0055]
In the embodiments described so far, the circuit of the present invention has been described as a driving circuit for a laser diode (LD), but the present invention is not limited to this, and other light emitting elements such as a light emitting diode (LED) It is clear that the circuit is also effective as a circuit for driving.
[0056]
【The invention's effect】
As described above, when one high-speed operation FET is used as a current source as in the conventional circuit configuration, the drain-source voltage _VDS changes according to the modulation input signal. the gate of the FET - the V _DS becomes larger trying to OFF deeply the voltage V _GS between source leakage current increases.
[0057]
Therefore, in the laser diode driving circuit of the present invention, the current source FETs of the differential pair FETs constituting the laser diode driving circuit are connected in series with each other, and furthermore, the gate bias potential with respect to the serially connected FETs Was appropriately applied by resistance division. For this reason, the voltage applied between the drain and the source of the current source FET is divided by the two FETs arranged in series, and the voltage applied to one FET is equal to the voltage applied to the current source FET having the conventional configuration. Lower than This makes it possible to provide a laser diode drive circuit that can reduce the drain-source leakage current even under the condition that the gate bias is deep.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a circuit example of a laser diode driving device according to the present invention.
FIG. 2 is a diagram for explaining an overall view of an LD drive circuit of a laser diode drive device of the present invention and an example of a conceptual APC circuit.
FIG. 3 is a detailed circuit diagram of a DF / F circuit provided in the laser diode driving device of the present invention.
FIG. 4 is a circuit diagram for explaining a configuration of an output buffer circuit and a modulation drive circuit provided in the laser diode drive device of the present invention.
FIG. 5 is a circuit diagram for explaining a configuration of an LD bias current control circuit provided in the laser diode driving device of the present invention.
FIG. 6 is a circuit diagram for explaining a configuration of an APC circuit provided in the laser diode driving device of the present invention.
FIG. 7 is a diagram for explaining a circuit example of a conventional laser diode driving device.
8 is a diagram for gate length is described a typical _I DS _{-V DS} characteristics of the conventional FET of 0.5 [mu] m.
[Explanation of symbols]
10 IC
11 APC circuit 12 Modulation current control terminal Q1, Q2 Differential pair transistor Q3, Q4, Q5 Transistor D1 Diode R1, R2 ', R3 Resistance LD Laser diode

Claims (3)

A laser diode drive circuit that outputs an optical signal according to the modulation signal,
A differential pair transistor receiving an input of the first signal;
A voltage dividing circuit for dividing the second signal by resistance division;
A first current source circuit of the differential pair transistor,
The first signal comprises two signals complementary to each other;
Each of the two complementary signals is input to a control terminal of a transistor constituting the differential pair transistor,
One anode of the differential pair transistor is connected to the laser diode,
The first current source circuit includes a first transistor connected to a common cathode of the differential pair transistor, and a second transistor of the same polarity connected in series to the first transistor. The divided second signal is input to each of the control terminals of the first transistor and the second transistor,
When the second signal is controlled so as to cut off the current flowing through the laser diode, the current flowing through the first current source circuit is reduced by reducing the voltage between the anode and the cathode of the second transistor. Is substantially zero, and the current output from the differential pair transistor to the laser diode is substantially cut off. 2. The device according to claim 1, wherein the divided second signal input to a control terminal of the first transistor is an optical output control signal for keeping an optical output of the laser diode constant. 3. A driving circuit for the laser diode as described in the above. A second current source circuit and a voltage level control diode,
The cathode of the second transistor is connected to the second current source circuit and the anode of the voltage level control diode, and the cathode potential of the second transistor is biased to a predetermined value. The laser diode driving circuit according to claim 1 or 2, wherein:

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