JP2004014748A - Method for manufacturing semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a method of manufacturing a semiconductor device which can form a thin device without modifying equipment and which can form a thin P-type semiconductor layer with high accuracy.
A first conductive type layer is formed on a first semiconductor substrate, and an oxide film is formed on one surface of the first conductive type layer or the second semiconductor substrate formed on the first semiconductor substrate. Bonding a first semiconductor substrate and a second semiconductor substrate via an oxide film, polishing the first semiconductor substrate, forming a gate electrode and an emitter electrode on the first semiconductor substrate, A step of selectively forming a mask on the surface of the semiconductor substrate, a step of sealing the surface of the first semiconductor substrate on the side of the gate electrode and the emitter electrode, and removing the second semiconductor substrate; Removing the encapsulating oxide film, removing the encapsulation, forming a second conductivity type layer on the exposed portion of the first conductivity type layer, and surface of the second conductivity type layer Forming an electrode on the substrate.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for a vertical insulated gate bipolar transistor (IGBT).
[0002]
[Prior art]
Conventionally, an insulated gate bipolar transistor (IGBT) has been known as a semiconductor element for controlling a large current. The IGBT is a device (element) having both high-speed switching characteristics of a field effect transistor (MOSFET) and low impedance characteristics of a bipolar transistor.
[0003]
In recent years, with the development of electric vehicles and the like, motors are driven by electric power from relatively low voltage sources such as batteries and capacitors, and IGBTs are often used in inverters that control the driving of the motor. In such an electric vehicle, for the purpose of improving fuel efficiency and efficiency, reduction of IGBT switching loss, reduction of on-resistance, and the like are desired. Hereinafter, a conventional method of manufacturing an IGBT will be described with reference to FIGS.
[0004]
FIG. 13 is a flowchart showing a conventional IGBT manufacturing process. 14 and 15 are cross-sectional views of a semiconductor substrate in respective steps of a conventional IGBT manufacturing process. The IGBT manufacturing process includes an IGBT substrate forming process (ST100) and a device forming process (ST110).
[0005]
In the IGBT substrate forming step (ST100), first, a relatively low-resistance P ⁺ A mold silicon substrate 100 is prepared (see FIG. 14A). This P ⁺ N with relatively low resistance on the silicon substrate 100 ⁺ The semiconductor buffer layer 101 is epitaxially grown to a thickness of about 5 to 30 μm (see FIG. 14B). This N ⁺ N-type semiconductor buffer layer 101 has a relatively high resistance N ⁻ The type semiconductor layer 102 is epitaxially grown (see FIG. 14C). Thus, an IGBT substrate is obtained.
[0006]
In the device forming step (ST110), first, epitaxially grown N ⁻ A P-type impurity is selectively added to the surface of the P-type semiconductor layer 102 to form a P-type base region 103 (see FIG. 15A). N-type impurities are selectively added to the surface of the P-type base ⁺ A mold emitter region 104 is formed (see FIG. 15B). N ⁺ Emitter region 104 and N ⁻ A surface portion of the P-type base region 103 sandwiched between the semiconductor layers 102 becomes a channel region 105.
[0007]
Next, a gate electrode 107 is formed on each channel region 105 with a gate oxide film 106 interposed therebetween. ⁺ An emitter electrode 108 is formed over a part of the p-type base region 103 and the p-type emitter region 104 (see FIG. 15C). Furthermore, P ⁺ A collector electrode 109 is formed on the back surface of the mold silicon substrate 100 (FIG. 15D). FIG. 16 is a cross-sectional view of the IGBT manufactured by the above manufacturing process.
[0008]
The operation of the IGBT manufactured as described above is shown in FIG. 16 and FIG. _CE And collector current I _CE This will be described with reference to a graph showing a time change of the data.
[0009]
In FIG. 17, the horizontal axis represents time, and the vertical axis represents the collector voltage V _CE And collector current I _CE Is represented. Curve C10 is the collector voltage V _CE Of the collector current I. _CE Of FIG.
[0010]
In the IGBT, a collector voltage is applied between the emitter electrode 108 and the collector electrode 109. In this state, a predetermined gate voltage is applied between the emitter electrode 108 and the gate electrode 107. As a result, a channel is formed in the channel region 105, and electrons are emitted from the emitter electrode 108 to the N channel through the channel. ⁻ Implanted into the mold semiconductor layer 102. In addition, P on the collector side ⁺ Layer and N ⁻ By forward biasing between layers, P ⁺ Holes are injected from the mold silicon substrate 100. The amount of electrons equal to the positive charge of the injected holes is N ⁻ Gathered in the semiconductor layer 102 and N ⁻ The resistance of the type semiconductor layer 102 decreases, and the IGBT is turned on. This transient phenomenon up to the ON state is a gradual decrease in the collector voltage at the time of turn-on seen in the curve C10 of the range R10 in FIG. 17, and a gradual increase in the collector current seen in the curve C11.
[0011]
When the application of the gate voltage is stopped in the ON state in the range R11 in FIG. ⁻ Injection of electrons into the semiconductor layer 102 is eliminated, and P ⁺ Type silicon substrate 100 to N ⁻ The injection of holes into the type semiconductor layer 102 is stopped, and the IGBT is turned off. In this off state, the holes already injected also have their lifetimes and decrease. Further, the IGBT is turned off because the remaining holes disappear by recombination with electrons and flow directly to the P-type base region. This appears as the tail current at the time of turn-off, which is seen in the curve C11 in the range R12 in FIG.
[0012]
The power loss of the IGBT includes switching loss and conduction loss. The switching loss is a loss at the time of turn-on indicated by a range R10 and a loss at the time of turn-off indicated by a range R12 in FIG. Therefore, switching loss can be reduced by shortening the turn-on time and the turn-off time. Further, the conduction loss is a loss in the ON state indicated by a range R11 in FIG. Therefore, conduction loss can be reduced by reducing the on-resistance.
[0013]
In order to shorten the turn-off time, one of the reasons is to reduce lattice defects and the like in order to shorten the lifetime of holes. ⁻ It is considered to be introduced into the type semiconductor layer 102. Another is that the P that constitutes the IGBT ⁺ Composed of a silicon substrate 100 ⁺ It is considered that the thickness of the type semiconductor layer (collector layer) is reduced. ⁻ It is known that the amount of holes entering the type semiconductor layer 102 can be limited, the fall time at the time of turn-off (the time during which a tail current flows, the turn-off time (range R12 in FIG. 17)) can be reduced, and the switching loss can be reduced. I have. Also, in order to realize low on-resistance, N ⁻ It is necessary to reduce the thickness of the IGBT mainly including the semiconductor layer 102.
[0014]
As a method for manufacturing a thin P-type semiconductor layer, an epitaxial growth method or an ion implantation method is used. ⁺ Method of forming a type semiconductor layer, or P ⁺ N on the silicon substrate ⁺ Type semiconductor buffer layer, N ⁻ Type semiconductor layers are sequentially formed, and this N ⁻ After forming a base region, an emitter region, a gate electrode, and an emitter electrode on the ⁺ It is conceivable to grind and polish the mold silicon substrate.
[0015]
[Problems to be solved by the invention]
P by epitaxial growth or ion implantation ⁺ In the method of forming the type semiconductor layer, P ⁺ The thickness of the mold semiconductor layer can be accurately reduced and the thickness can be controlled well. However, in a normal IGBT manufacturing facility, a semiconductor substrate needs to have a thickness of about 500 μm or more, so that a semiconductor having a breakdown voltage of about 500 to 1000 V and a semiconductor thickness of about 50 to 100 μm can be manufactured. There is a problem that it is difficult.
[0016]
Also, P ⁺ N on the silicon substrate ⁺ Type semiconductor buffer layer, N ⁻ Type semiconductor layers are sequentially formed, and N ⁻ After forming a base region, an emitter region, a gate electrode, and an emitter electrode on the ⁺ In the method of grinding and polishing a silicon substrate, P ⁺ It is conceivable to use a silicon substrate having a thickness that can be passed through ordinary IGBT manufacturing equipment as a silicon substrate. However, since this method is performed by machining, ⁺ In order to reduce the thickness of the mold semiconductor layer to several μm, variations in the thickness dimension are large, and it is difficult to secure thickness accuracy, and there is a problem that it is difficult to obtain an IGBT with small characteristic variations.
[0017]
Furthermore, P ⁺ In addition to forming the mold semiconductor layer thinly, if the IGBT is formed thin, for example, 100 μm or less in order to obtain low on-resistance characteristics, problems such as wafer cracking and warpage during heat treatment occur. In addition, many of the generally used manufacturing equipments handle wafers of about 500 μm, and for those having a diameter of 100 μm or less, it is necessary to remodel a portion related to a transfer system and take measures against warpage during heat treatment.
[0018]
Further, in the manufacturing method for forming a thin P-type semiconductor layer as described above, ⁺ Since the P-type impurity is ion-implanted into the type semiconductor layer, there is a problem that the P-type impurity is diffused by a heat treatment in a later step, and the thickness and the variation of the P-type semiconductor layer are increased.
[0019]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described demands and problems effectively, and to form a thin device, particularly an IGBT, without modifying equipment. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of accurately forming a (collector layer).
[0020]
Means and action for solving the problem
A method of manufacturing a semiconductor device according to the present invention is configured as follows to achieve the above object.
[0021]
In a first semiconductor device manufacturing method (corresponding to claim 1), a first semiconductor substrate and a second semiconductor substrate are prepared, and the first semiconductor substrate contains an impurity having a higher concentration than the impurity concentration of the first semiconductor substrate. Forming a first conductivity type layer, and forming an oxide film on at least one surface of the first conductivity type layer formed on the first semiconductor substrate or the second semiconductor substrate, Bonding a semiconductor substrate via an oxide film, polishing the first semiconductor substrate to a predetermined thickness, forming a second conductive type base region and a first conductive type emitter region on the first semiconductor substrate. Forming an emitter electrode and a gate electrode with an insulating film interposed therebetween, selectively forming a mask on the surface of the second semiconductor substrate, and forming a surface of the first semiconductor substrate on the side of the gate electrode and the emitter electrode. Seals and stops the oxide film Removing the second semiconductor substrate, removing the mask and the exposed oxide film, removing the encapsulation, and removing the second conductive substrate on the exposed portion of the first conductivity type layer. The method is characterized by including a step of forming a conductive type layer and a step of forming an electrode on the surface of the second conductive type layer.
[0022]
According to the first method for manufacturing a semiconductor device, a first semiconductor substrate and a second semiconductor substrate are prepared, and the first semiconductor substrate is of a first conductivity type containing an impurity at a higher concentration than the impurity concentration of the first semiconductor substrate. Forming a layer, forming an oxide film on either the first conductivity type layer formed on the first semiconductor substrate or the second semiconductor substrate, and oxidizing the first semiconductor substrate and the second semiconductor substrate. A step of bonding via a film, a step of polishing the first semiconductor substrate to a predetermined thickness, a step of forming a second conductive type base region, a first conductive type emitter region, and an emitter electrode on the first semiconductor substrate. Forming a gate electrode with an insulating film interposed therebetween, selectively forming a mask on the surface of the second semiconductor substrate, sealing the surface of the first semiconductor substrate on the side of the gate electrode and the emitter electrode. The second half using the oxide film as a stop layer. Removing the body substrate, removing the mask and the exposed oxide film, removing the encapsulation, and placing the second conductivity type layer on the exposed portion of the first conductivity type layer. Forming a second semiconductor substrate, and selectively etching the second semiconductor substrate to leave a thick portion on the peripheral edge. Therefore, it is possible to form a thin semiconductor device having a thin layer of the second conductivity type without modifying equipment for manufacturing the emitter and gate electrode surface side, and it is difficult to handle the semiconductor device because the wafer becomes thin. And the problems of cracking and warping can be solved. In addition, since the layer of the second conductivity type is formed in the final step, it is possible to accurately form a thin collector layer having a high impurity concentration without being affected by the heat history accompanying the manufacturing process.
[0023]
In a second method of manufacturing a semiconductor device (corresponding to claim 2), in each of the above-described manufacturing methods, preferably, the second semiconductor device is formed as a step before the step of selectively forming a mask on the surface of the second semiconductor substrate. It is characterized by having a step of polishing the substrate to a predetermined thickness.
[0024]
According to the second method for manufacturing a semiconductor device, the step of polishing the second semiconductor substrate to a predetermined thickness is performed before the step of selectively forming a mask on the surface of the second semiconductor substrate. (2) The thickness of the semiconductor substrate becomes thinner, and the etching time in the etching step after the step of forming a mask can be shortened. Further, the amount of the etching solution for etching can be reduced.
[0025]
In a third method of manufacturing a semiconductor device (corresponding to claim 3), in the first and second manufacturing methods, preferably, the surface of the first semiconductor substrate on which the gate electrode and the emitter electrode are formed is sealed. The method is characterized in that the surface of the first semiconductor substrate on which the gate electrode and the emitter electrode are formed is attached to a glass substrate via a protective material.
[0026]
According to the third method for manufacturing a semiconductor device, the surface of the first semiconductor substrate on which the gate electrode and the emitter electrode are formed is sealed with the surface of the first semiconductor substrate on which the gate electrode and the emitter electrode are formed via the protective material. This is performed by attaching to the glass substrate by etching, so that the surface where the emitter / gate electrode is formed can be protected from a chemical solution when the second semiconductor layer is etched.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[0028]
FIGS. 1 and 2 are flowcharts showing steps of manufacturing an insulated gate bipolar transistor (IGBT) by a method of manufacturing a semiconductor device according to an embodiment of the present invention. The manufacturing process of the IGBT includes an IGBT substrate forming process (ST10), an emitter / gate electrode surface forming process (ST20), and a collector electrode surface forming process (ST30).
[0029]
In the IGBT substrate forming step (ST10), a first semiconductor substrate and a second semiconductor substrate are prepared, and a first conductivity type layer containing an impurity having a higher concentration than the impurity concentration of the first semiconductor substrate is formed on the first semiconductor substrate. (Step of forming a first conductive layer) (ST11), and forming SiO 2 on the surface of the second semiconductor substrate. ₂ A step of forming an oxide film (an oxide film forming step) (ST12); ₂ A substrate bonding step (ST13) of bonding the surface on which the oxide film is formed and a layer of the first conductivity type of the first semiconductor substrate, and a step of polishing the first semiconductor substrate to a predetermined thickness (first semiconductor substrate polishing step) ) (ST14). Note that an oxide film is formed on the second conductivity type layer formed on the first semiconductor substrate or on at least one surface of the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are joined via the oxide film. The process includes the oxide film forming process and the substrate bonding process.
[0030]
The emitter / gate electrode surface side forming step (ST20) includes a step of forming a gate electrode on the first semiconductor substrate via an insulating film (gate electrode forming step) (ST21) and a step of forming a second conductive type base region on the first semiconductor substrate. Forming a base region (ST22), forming a first conductivity type emitter region on the surface of the base region (emitter region forming step) (ST23), and forming an emitter electrode (emitter electrode). Forming step) (ST24).
[0031]
The collector electrode surface side forming step (ST30) includes a step of polishing the second semiconductor substrate to a predetermined thickness (backside polishing step) (ST31) and a step of selectively forming a mask on the surface of the second semiconductor substrate (ST31). Mask forming step) (ST32), a sealing step (ST33) of sealing a surface on the side of the gate electrode and the emitter electrode formed on the first semiconductor substrate, and removing the second semiconductor substrate using the oxide film as a stop layer. A removing step (ST34), a step of removing a mask and an exposed oxide film (mask and oxide film removing step) (ST35), a step of removing sealing (sealing removing step) (ST36), and a second step. A step of forming a conductive type layer (second conductive layer forming step) (ST37) and a step of forming a collector electrode on the surface of the second conductive type layer (collector electrode forming step) (ST38). . The step of sealing the surface of the first semiconductor substrate on the side of the gate electrode and the emitter electrode and partially removing the second semiconductor substrate using the oxide film as a stop layer includes the sealing step and the removing step. Consists of
[0032]
The IGBT substrate forming step (ST10) is performed as follows. FIG. 3 is a cross-sectional view of the semiconductor substrate in each step of the IGBT substrate forming step (ST10). In FIG. 3A, a mirror-finished thickness of 500 μm, a diameter of 5 to 6 inches (127 to 152 mm), a phosphorus concentration of 10 ¹⁴ cm ^-3 N below ⁻ A single-crystal silicon substrate 10 having a thickness of 500 μm and a diameter of 5 to 6 inches (127 to 152 mm) mirror-processed as a second single-crystal silicon substrate 10 and a second semiconductor substrate, having a given impurity concentration and a given conductivity type as a dummy substrate prepare.
[0033]
In the first conductive layer forming step (ST11), in FIG. ⁻ N-type single-crystal silicon substrate 10 ⁻ Concentration higher than the phosphorus concentration of the single-crystal silicon substrate 10, for example, a phosphorus concentration of 10 ¹⁶ -10 ¹⁸ cm ^-3 Of the first conductivity type of N ⁺ Formed silicon layer 12 is formed to a thickness of 5 to 20 μm by an epitaxial growth method.
[0034]
The epitaxial growth method is performed, for example, as follows. N ⁻ The single-crystal silicon substrate 10 is arranged on a susceptor of an epitaxial growth reactor. Next, in a hydrogen atmosphere, ⁻ The single-crystal silicon substrate 10 is heated to 1150 ° C., and then phosphine diluted with hydrogen at a flow rate of 0.2 l / min is supplied in addition to trichlorosilane at a flow rate of 5 l / min and hydrogen at a flow rate of 80 l / min. , Deposited at a growth rate of 2.0 ± 0.1 μm / min for 5 minutes, ⁺ A mold silicon layer is formed.
[0035]
Here, N ⁺ Type silicon layer 12 was deposited by an epitaxial growth method. ⁺ The mold silicon layer 12 may be formed.
[0036]
In the oxide film forming step (ST12), as shown in FIG. 3B, the surface of the single-crystal silicon ₂ An oxide film 14 is formed. In this thermal oxidation, the single-crystal silicon substrate 11 is set on a wafer boat, and the wafer boat is set in a quartz tube in an electric furnace. Next, steam is vaporized in the quartz tube, and at the same time, the temperature of the electric furnace is heated to about 1000 ° C. In this state, hold for about 30 minutes. Thereby, the SiO.sub.3 having a thickness of about 0.3 .mu.m is formed. ₂ An oxide film 14 is formed.
[0037]
Thereafter, in a substrate bonding step (ST13) of bonding the surface on which the oxide film 14 is formed and the first conductivity type layer of the first semiconductor substrate, in FIG. ⁺ Type silicon layer 12 and N ⁻ Substrate consisting of silicon single crystal silicon substrate 10 and SiO ₂ After soaking the silicon substrate on which the oxide film 14 has been formed in pure water, ⁺ Surface on the silicon layer 12 side and SiO ₂ The surface on the oxide film 14 side is bonded. The bonded wafer is heated to 1000 ° C. or higher in an electric furnace. Thereby, the bonded substrate 15 is formed.
[0038]
In the first semiconductor substrate polishing step (ST14), the first semiconductor substrate N of the bonded substrate 15 shown in FIG. ⁻ The single crystal silicon substrate 10 is polished to a predetermined thickness. At this time, in order to secure device characteristics such as ON resistance and breakdown voltage, the first semiconductor substrate N ⁻ The thickness dimension of the single-crystal silicon substrate 10 is determined and polished.
[0039]
In this polishing, for example, a mechano-chemical polishing method is used, and abrasive particles having a particle size of 0.01 to 0.5 μm are dispersed in an alkaline polishing liquid in a colloidal manner using a polisher, and N is applied. ⁻ Polishing the surface of the single crystal silicon substrate 10 ⁻ Of the single-crystal silicon substrate 11 from the surface of the ₂ The thickness up to the interface of the oxide film is set to about 100 μm or less. This N ⁻ The on-voltage is small when the thickness of the type single crystal silicon substrate 10 is small, but if the thickness is too small, the breakdown voltage cannot be maintained. In order to make the breakdown voltage 600V to 1200V, this thickness is appropriate.
[0040]
In the substrate bonding step (ST13), only the single-crystal silicon substrate 11, which is a dummy substrate, is SiO ₂ The oxide film 14 was formed and joined, ₂ Oxide film is N ⁻ N of the single crystal silicon substrate 10 ⁺ Formed on the surface of the type silicon layer 12, ₂ N without forming an oxide film ⁻ The single crystal silicon substrate 10 and the single crystal silicon substrate 11 may be joined. Also, N ⁻ Both the single crystal silicon substrate 10 and the single crystal silicon substrate 11 ₂ An oxide film is formed and SiO ₂ The surfaces on which the oxide films are formed may be joined.
[0041]
The step of forming the emitter / gate electrode side (ST20) is performed as follows. FIGS. 4 and 5 are cross-sectional views of the semiconductor substrate in each step of the emitter / gate electrode surface side forming step (ST20).
[0042]
In the gate electrode forming step (ST21) of forming a gate electrode on the first semiconductor substrate via an insulating film, first, in FIG. ⁻ The surface (polished surface) 16 of the type single crystal silicon substrate is thermally oxidized to form an oxide film 17.
[0043]
In this thermal oxidation, the bonded substrate 15 is set on a wafer boat, and the wafer boat is set in a quartz tube in an electric furnace. Next, water vapor is introduced into the quartz tube, and at the same time, the temperature of the electric furnace is heated to about 900 ° C. In that state, keep it for about 30 minutes. Thus, an oxide film having a thickness of about 0.1 μm is formed.
[0044]
In FIG. 4 (b), polycrystalline silicon as a gate electrode material is deposited, a mask is formed by using a photoresist so that a region other than the gate electrode is formed, and the polycrystalline silicon is etched to form a gate electrode 18 To form
[0045]
In the base region forming step (ST22) of forming the second conductivity type base region on the first semiconductor substrate, in FIG. ⁻ A p-type conductive region of the second conductivity type is formed below oxide film 17 of type single-crystal silicon substrate 10 as base region 19.
[0046]
For example, when the gate electrode 18 is formed on the N ⁻ Boron is implanted from the surface of oxide film 17 of type single crystal silicon substrate 10 by an ion implantation method, and then is annealed and diffused, so that boron concentration becomes 10%. ¹⁸ cm ^-3 The P-type conductive region (base region) 19, which is the above-described second conductive type region, is formed.
[0047]
In this ion implantation, the bonded substrate 15 is placed on a sample stage of an ion implantation apparatus, and an acceleration voltage of 30 to 60 keV, 5 × 10 ¹⁴ cm ^-2 Boron is implanted at the above dose, and then annealing is performed in an annealing furnace at 1000 ° C. for 30 minutes to 1 hour.
[0048]
In the emitter region forming step (ST23) of forming the first conductivity type emitter region on the surface of the base region, the first conductivity type N is formed in a part of the base region 19 in FIG. ⁺ The conductive region of the mold is formed as an emitter region 20.
[0049]
For example, a photoresist is applied so as to have a region for forming an emitter region as an opening, and N is used as a mask. ⁻ Arsenic is implanted from the surface of oxide film 17 of type single crystal silicon substrate 10 by an ion implantation method, and thereafter, annealing is performed so that arsenic concentration becomes 10%. ¹⁸ cm ^-3 As described above, the first conductivity type region of about 0.5 μm in thickness N ⁺ A mold conductive region (emitter region) 20 is formed.
[0050]
In this ion implantation, the bonded substrate 15 is set on a sample stage of an ion implantation apparatus, and an acceleration voltage of 80 to 100 keV, 5 × 10 ¹⁴ cm ^-2 Arsenic is implanted at the above dose, and then annealing is performed in an annealing furnace at 1000 ° C. for 30 minutes to 1 hour.
[0051]
In the emitter electrode forming step (ST24) of forming the emitter electrode, first, in FIG. ⁻ An insulating film is deposited so as to cover oxide film 17 and gate electrode 18 on the single-crystal silicon substrate, thereby forming interlayer insulating film 21. The interlayer insulating film 21 has a high electrical insulating property such as a silicon oxide film or a silicon nitride film deposited by using a chemical vapor deposition method (CVD method) or plasma.
[0052]
Next, in FIG. 5B, the interlayer insulating film 21 and the oxide film 17 are partially removed by dry etching using a mask having an opening in a portion other than the region around the gate electrode. Thereafter, an electrode material such as aluminum is deposited by vapor deposition or the like to form an emitter electrode 22 (FIG. 5C).
[0053]
The collector electrode surface side forming step (ST30) is performed as follows. 6 to 8 are cross-sectional views of the semiconductor substrate in each step of the collector electrode surface side forming step (ST30).
[0054]
In the collector electrode surface side forming step (ST30), first, in the back surface polishing step (ST31), the single crystal silicon substrate 11 is polished to a predetermined thickness (see FIG. 6A). As a result, it is possible to secure a thickness capable of handling equipment and a thickness with a small warpage at the time of heat treatment, to cut off an unnecessary portion, and to reduce an etching time and an etchant in a post-process. At this time, the thickness of the single crystal silicon substrate is 100 μm, and the thickness of the entire bonded substrate is about 200 μm. 6 to 9, the structure on the emitter / gate electrode surface side shown in FIG. 5 is omitted.
[0055]
In a mask forming step (ST32) of selectively forming a CVD film 23 as a mask on the surface of the single-crystal silicon substrate 11, which is the second semiconductor substrate, first, in FIG. 6B, the single-crystal silicon substrate 11 is subjected to CVD (Chemical). The CVD film 23 having a thickness of 3000 Å is formed as a mask (inorganic insulating layer) by Vapor Deposition. Since CVD is performed at a temperature of about 300 ° C., it is possible to prevent the previously formed gate / emitter electrode side structure from being thermally destroyed.
[0056]
Next, in FIG. 6C, the CVD film 23 is patterned with a photoresist. As a result, at least a portion of the CVD film 23 where a chip is to be formed is removed. At this time, a pattern as shown in FIG. 10 is formed. The hatched portion shown in FIG. 10 is a portion where the CVD film 23 remains, and the portion without the hatched portion is a portion where the CVD film 23 is removed. The plurality of squares are device forming portions.
[0057]
A resist 24 is uniformly applied on the CVD film 23 deposited on the single crystal silicon substrate 11 of the bonded substrate 15 by a spin coater or the like. Next, a mask having a portion through which light is removed from the CVD film 23 is allowed to adhere to the resist 24 on the CVD film 23 of the bonded substrate 15 and exposed to light having a wavelength to which the resist 24 reacts. Then, the exposed portion of the resist 24 is melted by dipping in a developing solution to form an opening 25. The developer is washed with a rinse solution. Thereafter, post-baking is performed to remove the developing solution or the rinsing solution present in the resist 24 and increase the adhesiveness between the resist 24 and the CVD film 23.
[0058]
Next, in FIG. 6D, the CVD film 23 in the opening 25 of the resist 24 is etched by reactive ion etching (RIE), and the resist 24 is stripped.
[0059]
In addition, patterns as shown in FIGS. 11 and 12 are also conceivable. In the figure, the hatched portions are portions where the CVD film 23 remains, and the portions without hatched portions are portions where the CVD film 23 is removed. The plurality of squares are device forming portions.
[0060]
Next, in a sealing step (ST33) of sealing the surface on the side of the gate electrode and the emitter electrode formed on the first semiconductor substrate, in FIG. ⁻ The surface having the gate electrode 18 and the emitter electrode 22 formed on the mold single crystal silicon substrate 10 is bonded to a glass substrate 27 by heating on a hot plate via a protective agent (wax) 26. As a result, the surface of the bonded substrate 15 on the side of the gate electrode 18 and the emitter electrode 22 is sealed, and can be protected from an etching chemical used in a later step.
[0061]
After sealing, SiO ₂ In the removing step (ST34) for removing the second semiconductor substrate using the oxide film 14 as a stop layer, the CVD film 23 is used as a mask in FIG. ₂ Using the oxide film 14 as a stop layer, the single crystal silicon substrate 11, which is the second semiconductor substrate, is partially removed by an etchant.
[0062]
Thereafter, the CVD film 23 and the exposed SiO ₂ In the mask for removing the oxide film 14 and the oxide film removing step (ST35), the oxide film 14 is removed by immersion in hydrofluoric acid or the like in FIG.
[0063]
In the sealing removing step (ST36) for removing the sealing, the bonded substrate with glass is heated with a hot plate or the like, and the glass is removed while sliding (see FIG. 7A). The wax is also removed with a chemical.
[0064]
In the step of forming the layer of the second conductivity type (the step of forming the second conductive layer) (ST37), in FIG. ⁺ (B) is implanted into the exposed portions of the mold type silicon layer 12 and then annealed so that the boron concentration becomes 10%. ¹⁸ cm ^-3 As described above, the second conductivity type layer P ⁺ A mold silicon layer 13 is formed.
[0065]
In this ion implantation, the bonded substrate 15 is set on a sample stage of an ion implantation apparatus, and an acceleration voltage of 5 to 60 keV, 1 × 10 ¹⁴ cm ^-2 Boron (B) is implanted at the above dose, and then annealing (heat treatment) is performed in an annealing furnace. The heat treatment is performed at a temperature of, for example, 600 ° C. or less for dissolving Al (electrode) so as not to damage the device.
[0066]
In the collector electrode forming step (ST38) of forming a collector electrode on the surface of the second conductivity type layer, as shown in FIG. ⁺ After removing an oxide film (including a natural oxide film) on the surface of the mold silicon layer 13 with hydrofluoric acid or the like, an electrode material such as aluminum is formed by sputtering or the like. By dicing from the wafer 29 obtained in this manner, chips are formed (see FIG. 8D).
[0067]
In the collector electrode surface side forming step (ST30), the single-crystal silicon substrate 11, which is the second semiconductor substrate of the bonded substrate 15, is polished to a predetermined thickness in the back surface polishing step (ST31). This step may be performed without polishing. In this case, the etching time in the post-process becomes longer and the chemical solution cannot be reduced, but the polishing time can be reduced.
[0068]
In the collector electrode surface side forming step (ST30), the oxide film is removed in the mask and oxide film removing step (ST35), but the oxide film may be left thin as shown in FIG. In this case, the thin oxide film 14a prevents damage due to ion implantation in the subsequent step of forming the second conductive layer (ST37).
[0069]
As described above, the second semiconductor substrate is bonded to the first semiconductor substrate, and the second semiconductor substrate is selectively etched to leave a thick portion at the peripheral edge, so that the wafer becomes thin and handling becomes difficult. And cracking and warping problems can be solved. As a result, a thin device can be formed without modifying the equipment. Also, in this method, P ⁺ Since the type silicon layer is formed in the final step, thermal diffusion of P-type impurities due to heating in the manufacturing process is reduced. That is, a thin collector layer having a high impurity concentration can be accurately formed without being affected by a heat history (a heat profile such as temperature and time of various processes) accompanying the manufacturing process. Thereby, switching loss can be reduced.
[0070]
In the present embodiment, a reverse polarity type in which the polarities of P and N in the process description are reversed may be used.
[0071]
【The invention's effect】
As apparent from the above description, the present invention has the following effects.
[0072]
P ⁺ When forming the semiconductor device to be thin and forming the semiconductor device thin in order to obtain low on-resistance characteristics, the second semiconductor substrate was bonded to the first semiconductor substrate, and the semiconductor device was formed on the first semiconductor substrate. Thereafter, the second semiconductor substrate is selectively etched to form a thin semiconductor device, and a thick portion is left on the peripheral edge of the semiconductor device, so that it becomes difficult to handle the thin wafer, and cracks and warpage are caused. The problem can be solved, and a thin semiconductor device can be manufactured without modifying the equipment. In addition, since the second conductivity type layer is formed in the final step, a thin collector layer having a high impurity concentration can be accurately formed without being affected by the heat history accompanying the manufacturing process.
[0073]
Further, since the second semiconductor substrate is bonded to the first semiconductor substrate and the semiconductor device is formed on the first semiconductor substrate using ordinary equipment, even if the semiconductor device is thin, P ⁺ The thickness accuracy of the mold semiconductor layer can be improved by the ion implantation method, and the controllability of the thickness formation can be improved.
[0074]
In addition to the above effects, a step of polishing the second semiconductor substrate to a predetermined thickness is provided as a step before the step of selectively forming a mask on the surface of the second semiconductor substrate. Therefore, the etching time in the etching step after the step of forming the mask can be reduced. In addition, it is possible to reduce a chemical solution for etching.
[0075]
In addition to the above effects, the sealing of the surface on the gate electrode and emitter electrode side formed on the first semiconductor substrate is performed by sealing the surface on the gate electrode and emitter electrode side formed on the first semiconductor substrate with a protective material interposed therebetween. Therefore, when the second semiconductor layer is etched, the surface on which the emitter / gate electrode is formed can be protected from a chemical solution.
[Brief description of the drawings]
FIG. 1 is a flowchart showing steps of manufacturing an insulated gate bipolar transistor (IGBT) by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a flowchart showing steps of manufacturing an insulated gate bipolar transistor (IGBT) by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the semiconductor substrate in each step of an IGBT substrate forming step.
FIG. 4 is a cross-sectional view of the semiconductor substrate in each step of an emitter / gate electrode surface side forming step.
FIG. 5 is a cross-sectional view of the semiconductor substrate in each step of an emitter / gate electrode surface side forming step.
FIG. 6 is a sectional view of the semiconductor substrate in each step of a collector electrode surface side forming step.
FIG. 7 is a sectional view of the semiconductor substrate in each step of a collector electrode surface side forming step.
FIG. 8 is a cross-sectional view of the semiconductor substrate in each step of a collector electrode surface side forming step.
FIG. 9 is a cross-sectional view of the semiconductor substrate in an oxide film removing step.
FIG. 10 is a mask pattern of a CVD film.
FIG. 11 is a mask pattern of a CVD film.
FIG. 12 is a mask pattern of a CVD film.
FIG. 13 is a flowchart showing a conventional IGBT manufacturing process.
FIG. 14 is a sectional view of the semiconductor substrate in an IGBT substrate forming step.
FIG. 15 is a cross-sectional view of the semiconductor substrate in a device forming step.
FIG. 16 is a cross-sectional view of the IGBT.
FIG. 17: Collector voltage V _CE And collector current I _CE 6 is a graph showing a time change of the graph.
[Explanation of symbols]
10 N ⁻ Type single crystal silicon substrate
11 Single crystal silicon substrate
12 N ⁺ Type silicon layer
13 P ⁺ Type silicon layer
14 SiO ₂ Oxide film
15 Laminated substrate
16 Polished surface
17 Oxide film
18 Gate electrode
19 Base area
20 Emitter area
21 Interlayer insulation film
22 Emitter electrode
23 CVD film
24 Resist
25 opening
26 Protective material (wax)
27 Glass substrate
29 wafers
ST10 IGBT substrate forming process
ST11 First conductive layer forming step
ST12 Oxide film forming step
ST13 Substrate bonding process
ST14 First semiconductor substrate polishing step
ST20 Emitter / gate electrode surface side forming step
ST21 Gate electrode forming step
ST22 Base region forming step
ST23 Emitter region forming step
ST24 Emitter electrode forming step
ST30 Collector electrode surface side forming process
ST31 Backside polishing process
ST32 Mask forming step
ST33 Sealing process
ST34 Removal process
ST35 Mask and oxide film removing step
ST36 Seal removal process
ST37 Second conductive layer forming step
ST38 Collector electrode forming process

Claims (3)

Preparing a first semiconductor substrate and a second semiconductor substrate, and forming a first conductivity type layer containing an impurity at a higher concentration than the impurity concentration of the first semiconductor substrate on the first semiconductor substrate;
An oxide film is formed on at least one surface of the first conductivity type layer formed on the first semiconductor substrate or the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are bonded to each other by the oxide film. Surface bonding via
Polishing the first semiconductor substrate to a predetermined thickness;
Forming a second conductivity type base region, a first conductivity type emitter region, an emitter electrode, and a gate electrode via an insulating film on the first semiconductor substrate;
Selectively forming a mask on the surface of the second semiconductor substrate;
Sealing the surface of the gate electrode and the emitter electrode formed on the first semiconductor substrate, and removing the second semiconductor substrate using the oxide film as a stop layer;
Removing the mask and the exposed oxide film;
Removing the encapsulation;
Forming a layer of the second conductivity type at an exposed portion of the layer of the first conductivity type;
Forming an electrode on the surface of the second conductivity type layer;
A method for manufacturing a semiconductor device, comprising: 2. The semiconductor device according to claim 1, further comprising a step of polishing the second semiconductor substrate to a predetermined thickness as a step before the step of selectively forming the mask on the surface of the second semiconductor substrate. Manufacturing method. The sealing of the surface of the first semiconductor substrate on which the gate electrode and the emitter electrode are formed is performed by attaching the surface of the first semiconductor substrate on which the gate electrode and the emitter electrode are formed to a glass substrate via a protective material. 2. The method for manufacturing a semiconductor device according to claim 1, wherein:

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