JP2004096683A - Current sampling circuit and current output type driving circuit using the same - Google Patents

Abstract

A highly accurate current sampling circuit capable of reducing sampling errors and a current output type driving circuit using the same are provided.
When current is sampled, switches SW1 and SW2 are controlled to be on and a switch SW3 is controlled to be off. The current to be sampled flowing through the node N2 flows to the capacitor C1 via the switches SW1 and SW2, and the charging voltage causes the transistor M1 to conduct. When the transistor M1 conducts, the transistors M1 and M2 operate in a saturation region due to the bias voltage output from the voltage output circuit 1, and the current at the node N2 also flows from the power supply line VDD to the path via the transistors M1, M2 and the switch SW2. Flows. When all the currents flow through this path, the charging of the capacitor C1 ends, and the sampling current is held as the charging voltage of the capacitor C1.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a current sampling circuit that samples an input current and a current output type driving circuit that generates a current corresponding to input data to drive output lines of a plurality of channels. The present invention relates to a current sampling circuit and a current output type driving circuit used for a driving circuit.
[0002]
[Prior art]
As a current sampling circuit that samples and holds an input current, for example, a circuit shown in FIG. 10 is generally used.
The current sampling circuit in FIG. 10 includes a p-type MOS transistor Ma, a capacitor Ca, and switches SWa, SWb, and SWc.
[0003]
The p-type MOS transistor Ma is connected between the power supply line VDD and the node Na. The gate terminal of the p-type MOS transistor Ma is connected to the power supply line VDD via the capacitor Ca, and is connected to the node Na via the switch SWa. Switch SWb is connected between nodes Na and Nb, and switch SWc is connected between nodes Na and Nc.
[0004]
A current to be sampled flows through the node Nb. In the example of FIG. 10, a current source U for flowing a current to be sampled is connected between the node Nb and the reference potential line VSS.
The current sampled by the current sampling circuit flows through the node Nc. In the example of FIG. 10, the load Z is connected between the node Nc and the reference potential line VSS, and the current sampled by the current sampling circuit is output to the load Z.
[0005]
When the current sampling is performed in the current sampling circuit of FIG. 10, the switches SWa and SWb are turned on (hereinafter referred to as an on state), and the switch SWc is opened (hereinafter referred to as an off state) by a control circuit (not shown). Notation) are set respectively. When the current of the current source U flows through the capacitor Ca via the switches SWa and SWb, the charging voltage of the capacitor Ca is applied between the gate and the source of the p-type MOS transistor Ma, and the current flows through the p-type MOS transistor Ma. start. When the drain current of the p-type MOS transistor Ma becomes equal to the current of the current source U, the charging of the capacitor Ca ends, and the drain current is kept constant. As a result, the capacitor Ca is charged with a voltage adjusted so that the drain current of the p-type MOS transistor Ma is equal to the current to be sampled.
[0006]
When the sampled current is held, all the switches SWa to SWc are set to the off state. In this case, since the impedance between the gate terminal of the p-type MOS transistor Ma and the power supply line VDD becomes very large, the electric charge stored in the capacitor Ca is slightly discharged, and the voltage is kept substantially constant. .
[0007]
When the sampled current is output, the switches SWa and SWb are set to the off state and the switch SWc is set to the on state while the capacitor Ca is charged with the above-described voltage. A current corresponding to the gate-source voltage applied by the capacitor Ca, that is, a current substantially equal to the current to be sampled, flows through the p-type MOS transistor Ma, and flows to the load Z via the switch SWc.
[0008]
As described above, according to the current sampling circuit of FIG. 10, the current to be sampled is once converted to the voltage of the capacitor Ca and held, and the held voltage of the capacitor Ca is converted again to the current and output to the load Z. You.
[0009]
[Problems to be solved by the invention]
FIG. 11 shows the drain current Id and the drain of the p-type MOS transistor Ma when the gate-source voltage Vgs is equal to the drain-source voltage Vds and when the gate-source voltage Vgs is kept constant. FIG. 6 is a diagram illustrating a relationship with a source-to-source voltage Vds.
A curve CVa shows a curve when the gate-source voltage Vgs is equal to the drain-source voltage Vds, and a curve CVb shows a curve when the gate-source voltage Vgs is kept constant.
[0010]
When current sampling is performed in the current sampling circuit of FIG. 10, since the switch SWa is turned on, the gate-source voltage Vgs and the drain-source voltage Vds of the p-type MOS transistor Ma become equal, and the drain current Id And the relationship between the drain-source voltage Vds is restricted by the curve CVa. In the curve CVa, the drain current Id shows a change similar to a quadratic equation using the drain-source voltage Vds as a variable. When the drain current Id, that is, the current to be sampled is determined, the drain-source voltage Vds is determined from the relationship of the curve CVa.
[0011]
On the other hand, when the sampled current is output, since the gate-source voltage Vgs is kept constant, the relationship between the drain current Id and the drain-source voltage Vds is restricted by the curve CVb. The operating region of the MOS transistor in the curve CVb includes a non-saturation region where the drain current Id increases with an increase in the drain-source voltage Vds, and a saturation region where the drain current becomes constant irrespective of the increase in the drain-source voltage Vds. Area. When the drain voltage and the gate voltage are equal, the operation region of the MOS transistor becomes a saturation region, and thus the operation point Pa where the curve CVa and the curve CVb intersect is included in the saturation region.
[0012]
Since the drain current Id becomes constant in the saturation region, the voltage of the node Nc is determined according to the impedance of the load Z. For this reason, the voltage of the node Nc at the time of sample current output and the voltage of the node Nb at the time of current sampling are not usually equal. In the current sampling circuit of FIG. 10, since the node Nc and the node Nb are directly connected to the drain of the p-type MOS transistor Ma via the switch SWb and the switch SWc, the difference in the node voltage is the same as the difference between the drain-source voltage Vds. This is a difference, that is, a difference in the operating point of the p-type MOS transistor Ma. For example, as shown in FIG. 11, the operating point Pa at the time of current sampling changes to the operating point Pb at the time of sample current output.
[0013]
When the drain-source voltage Vds changes in the saturation region, the drain current Id actually changes slightly due to the channel length fluctuation effect. For example, as shown in FIG. 11, when the voltage difference ΔV changes in the drain-source voltage Vds between the operating point Pa and the operating point Pb, the drain current Id also changes in the current difference ΔI. This current difference ΔI becomes a current sampling error.
[0014]
Further, when a change occurs in the drain-source voltage Vds, the voltage of the capacitor Ca changes due to a current flowing through a parasitic capacitor existing between the drain and the gate, and the gate-source voltage Vgs changes. A phenomenon occurs in which the current Id changes. Such a change in the drain current Id also causes a current sampling error.
[0015]
As described above, in the current sampling circuit of FIG. 10, the voltage difference between the voltage of the node Nb at the time of current sampling and the voltage of the node Nc at the time of sampling current output is the same as the difference between the drain-source voltage Vds of the p-type MOS transistor Ma. This causes a disadvantage that the error between the current to be sampled and the sampling current increases due to the change.
Also, when the voltage of the node Nc changes due to a change in the impedance of the load Z, the gate-source voltage Vgs of the p-type MOS transistor Ma is directly affected by the influence, and the output sampling current changes. There is a disadvantage of doing it.
[0016]
The present invention has been made in view of such circumstances, and a first object of the present invention is to provide a highly accurate current sampling circuit that can reduce an error between a current to be sampled and a sampled current.
Another object of the present invention is to provide a current output type driving circuit capable of generating a highly accurate output current corresponding to input data.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, a current sampling circuit according to a first aspect of the present invention includes a first insulated gate transistor connected between a power supply line and a first node, and a first insulated gate transistor. A capacitor connected between the gate terminal of the transistor and the power supply line, a first switch connected between the gate terminal of the first insulated gate transistor and the first node, A second insulated gate transistor inserted on a connection line between the gate transistor and the first node, and a first insulated gate transistor and a second insulated gate when at least a predetermined level of current is sampled A voltage that causes the transistor to operate in the saturation region and that varies in accordance with the current to be sampled is a gate of the second insulated gate transistor. A voltage output circuit that outputs the current to the first node, a second switch connected between the second node and the first node through which the current to be sampled flows, a third node through which the sampled current flows, and a first switch. A third switch connected between the first switch and the second switch, and in a first operation mode in which current is sampled, the first switch and the second switch are controlled to be in a conductive state, and the third switch is controlled to be in an open state. In the second operation mode for holding the sampled current, the first switch, the second switch, and the third switch are controlled to be in an open state, and in the third operation mode for outputting the held sampling current, A control circuit that controls the first switch and the second switch to be open and the third switch to be conductive.
[0018]
According to the current sampling circuit according to the first aspect of the present invention, in the first operation mode in which the current of the predetermined level is sampled, the first switch and the second switch are turned on, and the third switch is turned on. The switch is controlled to the open state. Thus, the current to be sampled flowing through the second node flows through the first switch and the second switch to the capacitor, and the capacitor is charged. When this charging voltage is received at the gate terminal, the first insulated gate transistor becomes conductive. In addition, the voltage output from the voltage output circuit to the gate terminal turns on the second insulated gate transistor. Thus, the current to be sampled flows from the power supply line to the second node via the first insulated gate transistor, the second insulated gate transistor, and the second switch. When all the current to be sampled flows through this path, the current flowing through the capacitor is depleted, and the charging of the capacitor ends.
[0019]
At this time, both the first insulated gate transistor and the second insulated gate transistor operate in the saturation region by the voltage of the voltage output circuit output to the gate terminal of the second insulated gate transistor. Therefore, even if a voltage change occurs at the second node, the voltage change is converted into a change in the voltage applied to the second insulated gate transistor, so that the voltage applied to the first insulated gate transistor changes. It is unlikely to occur.
[0020]
Further, when the current to be sampled increases or decreases with respect to the current of the predetermined level, the voltage of the voltage output circuit changes accordingly. Therefore, for example, even after a change in the current, the operation of the first insulated gate transistor and the second insulated gate transistor in the saturation region is maintained.
[0021]
In the second operation mode in which the sampled current is held, the first switch, the second switch, and the third switch are all controlled to be open. In this state, since the impedance between the power supply line and the gate terminal of the first insulated gate transistor increases, the voltage of the capacitor can be easily maintained at a constant level.
[0022]
In the third operation mode in which the held current is output, the first switch and the second switch are controlled to be open and the third switch is controlled to be conductive. The first insulated gate transistor is turned on by the voltage held in the capacitor, and the second insulated gate transistor is turned on by the voltage output to the gate terminal by the voltage output circuit. , A current flows from the power supply line through the first insulated gate transistor, the second insulated gate transistor, and the third switch. The current flowing through the third node is a current determined by the voltage held in the capacitor, and is substantially equal to the current to be sampled.
[0023]
At this time, both the first insulated gate transistor and the second insulated gate transistor operate in the saturation region by the voltage of the voltage output circuit output to the gate terminal of the second insulated gate transistor. Therefore, even if a voltage change occurs at the third node, the voltage change is converted into a change in the voltage applied to the second insulated gate transistor, so that the voltage applied to the first insulated gate transistor changes. It is unlikely to occur.
[0024]
Further, when the current to be sampled increases or decreases with respect to the current of the predetermined level, the voltage of the voltage output circuit changes accordingly. Therefore, for example, even after a change in the current, the operation of the first insulated gate transistor and the second insulated gate transistor in the saturation region is maintained.
[0025]
A current sampling circuit according to a second aspect of the present invention includes a first insulated gate transistor connected between a power supply line and a first node, a gate terminal of the first insulated gate transistor, and a power supply line. Charge or discharge the capacitor according to the voltage difference between the voltage at the gate terminal of the first insulated gate transistor and the voltage at the first node, and according to the input control signal. A capacitor charging / discharging circuit for executing or stopping the leverage charging / discharging operation; a second insulated gate transistor inserted on a connection line between the first insulated gate transistor and the first node; A voltage for operating the first insulated gate transistor and the second insulated gate transistor in a saturation region when current is sampled, A voltage output circuit that outputs a voltage that changes according to the current to be sampled to the gate terminal of the second insulated gate transistor, and is connected between the second node and the first node through which the current to be sampled flows A second switch, a third switch connected between a third node through which the sampled current flows, and the first node, and a third switch connected between the first node and the second node. A second switch, a third switch connected between the first node and the third node, and a second switch in a first operation mode for sampling current, the second switch being in a conductive state. In the second operation mode for controlling the switch No. 3 to open and outputting the control signal for executing the charging and discharging of the capacitor charging / discharging circuit and holding the sampled current, In the third operation mode, the switch and the third switch are controlled to be in an open state, the control signal for stopping charging / discharging of the capacitor charging / discharging circuit is output, and the held sampling current is output. And a control circuit for controlling the third switch to an open state, the third switch to a conductive state, and outputting the control signal for stopping charging and discharging of the capacitor charging and discharging circuit.
[0026]
The voltage output circuit of the current sampling circuit according to the first and second aspects includes a second current mirror circuit that outputs a current corresponding to an input current, a current input terminal of the second current mirror circuit, and a power supply line. And a fourth insulated gate transistor having a gate terminal to which the charging voltage of the capacitor is input, and a current output terminal of the second current mirror circuit and a power supply line, A fifth insulated gate transistor may be provided in which the voltage is varied according to the voltage of the current output terminal, and the variable voltage is output to the gate terminal of the second insulated gate transistor.
[0027]
A current output type driving circuit according to a third aspect of the present invention is a current output type driving circuit that outputs a current of a plurality of channels in accordance with input data, and includes a register array that holds input data, and a constant current. A constant current source to be generated, data held in a register array, and a current generated by the constant current source are input, and a current output type digital-to-digital converter converts the input current into an output current having a level corresponding to the input held data. An analog conversion circuit, and a current output circuit that samples an output current of the current output type digital-analog conversion circuit for each held data and drives an output line of a plurality of channels with the sampled output current value. A first insulated gate transistor connected between the power supply line and the first node, and a gate terminal of the first insulated gate transistor A first switch connected between the gate terminal of the first insulated gate transistor and the first node; a first switch connected between the gate terminal of the first insulated gate transistor and the first node; A second insulated gate transistor inserted on a connection line with the first node and a first insulated gate transistor and a second insulated gate transistor in a saturation region when at least a predetermined level of current is sampled. A voltage output circuit for outputting a voltage to be operated, which varies according to the current to be sampled, to the gate terminal of the second insulated gate transistor; a second node through which the current to be sampled flows; A second switch connected between the first node and a third switch connected between the second node and the first node; In the first operation mode for sampling the current with the third switch obtained, the first switch and the second switch are turned on and the third switch is turned on to hold the sampled current. In the second operation mode, the first switch, the second switch, and the third switch are controlled to be in an open state, and the first switch and the second switch are output in the third operation mode in which the held sampling current is output. And a control circuit for controlling the third switch to an open state and the third switch to a conductive state.
[0028]
A current output type driving circuit according to a fourth aspect of the present invention is a current output type driving circuit which outputs a current of a plurality of channels in accordance with input data, wherein a register array holding input data and a constant current A constant current source to be generated, data held in a register array, and a current generated by the constant current source are input, and a current output type digital-to-digital converter converts the input current into an output current having a level corresponding to the input held data. An analog conversion circuit, and a current output circuit that samples an output current of the current output type digital-analog conversion circuit for each held data and drives an output line of a plurality of channels with the sampled output current value. A first insulated gate transistor connected between the power supply line and the first node, and a gate terminal of the first insulated gate transistor A capacitor connected between the source line and a capacitor connected to the first insulated gate transistor and charged or discharged in accordance with a voltage difference between a gate terminal voltage of the first insulated gate transistor and a voltage of the first node; A charging / discharging circuit for executing or stopping the charging / discharging operation in accordance with the following: a second insulated gate transistor inserted on a connection line between the first insulated gate transistor and the first node; A voltage that causes the first insulated gate transistor and the second insulated gate transistor to operate in a saturation region when a level current is sampled, and that changes according to the current to be sampled, A voltage output circuit that outputs to the gate terminal of the gate transistor, a second node through which a current to be sampled flows, and a first node. A second switch connected between the first node and the second node, a third switch connected between the third node and the first node through which the sampled current flows, and a second switch connected between the first node and the second node. A second switch connected between the first node and a third node connected between the first node and the third node; and a second switch connected between the first node and the third node. In the second operation mode of controlling the switch to be in the conductive state and the third switch to be in the open state, outputting the control signal for executing the charging and discharging of the capacitor charging and discharging circuit, and holding the sampled current, A third operation mode for controlling the first switch and the third switch to open states, outputting the control signal for stopping charging and discharging of the capacitor charging / discharging circuit, and outputting the held sampling current. And a control circuit that controls the second switch to an open state and the third switch to a conductive state, and outputs the control signal for stopping charging and discharging of the capacitor charging and discharging circuit.
[0029]
Further, the current sampling circuit according to the first and second aspects and the voltage output circuit of the current output type driving circuit according to the third and fourth aspects are characterized in that the current at the predetermined level is in the first operation mode. In the case of sampling, a voltage for operating the first insulated gate transistor at the boundary between the saturated region and the unsaturated region may be output to the gate terminal of the second insulated gate transistor.
Further, the first insulated gate transistor and the second insulated gate transistor may be configured such that one or both of a ratio of a gate width or a ratio of a gate length of the first and second insulated gate transistors is the second when the current of the predetermined level is sampled. May be set so that the insulated gate transistor operates at the boundary between the saturated region and the unsaturated region.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Seven embodiments of the present invention will be described with reference to the drawings.
<First embodiment>
FIG. 1 is a circuit diagram illustrating an example of a configuration of a current sampling circuit 100 according to the first embodiment of the present invention.
The current sampling circuit 100 shown in FIG. 1 includes a p-type MOS transistor M1 and a p-type MOS transistor M2, a capacitor C1, switches SW1 to SW3, and a voltage output circuit 1.
The p-type MOS transistor M1 is an embodiment of the first insulated gate transistor of the present invention.
The p-type MOS transistor M2 is an embodiment of the second insulated gate transistor of the present invention.
The switch SW1 is an embodiment of the first switch of the present invention.
The switch SW2 is an embodiment of the second switch of the present invention.
The switch SW3 is an embodiment of the third switch of the present invention.
Capacitor C1 is one embodiment of the capacitor of the present invention.
The voltage output circuit 1 is an embodiment of the voltage output circuit according to the present invention.
[0031]
The p-type MOS transistor M1 is connected between the power supply line VDD and the node N1. The capacitor C1 is connected between the gate terminal of the p-type MOS transistor M1 and the power supply line VDD. The p-type MOS transistor M2 is inserted on a connection line between the p-type MOS transistor M1 and the node N1. That is, the source terminal of the p-type MOS transistor M2 is connected to the drain terminal of the p-type MOS transistor M1, and the drain terminal of the p-type MOS transistor M2 is connected to the node N1.
[0032]
Switch SW1 is connected between the gate terminal of p-type MOS transistor M1 and node N1. The switch SW2 is connected between a node N2 through which a current to be sampled flows and the node N1. Switch SW3 is connected between nodes N3 and N1 through which the sampled current flows.
These switches are configured using, for example, p-type or n-type MOS transistors.
[0033]
The voltage output circuit 1 is a circuit that outputs a bias voltage to the gate terminal of the p-type MOS transistor M2. The bias voltage output from the voltage output circuit 1 changes according to the current to be sampled, and when at least a predetermined level of current is sampled, the p-type MOS transistor M1 and the p-type MOS transistor M2 are set in a saturation region. Adjusted to work. The predetermined level means an arbitrary current level appropriately determined according to an arbitrary current to be sampled.
For example, when the current to be sampled increases from this predetermined level, the gate voltage of p-type MOS transistor M2 is reduced to reference potential line VSS in response to this, and its gate-source voltage Vgs_M2 is increased. Thus, even when the current to be sampled increases, the p-type MOS transistor M2 operates in the saturation region.
Conversely, when the current to be sampled decreases from the predetermined level, the gate voltage of the p-type MOS transistor M2 is raised to the power supply line VDD side accordingly, and the gate-source voltage Vgs_M2 is reduced. This prevents the operation region of the p-type MOS transistor M2 from shifting to the non-saturation region when the current to be sampled decreases.
[0034]
Although not particularly shown in FIG. 1, the current sampling circuit 100 includes a control circuit for controlling the state (ON state or OFF state) of the switches SW1 to SW3.
This control circuit controls the switches SW1 and SW2 to be on and the switch SW3 to be off when sampling the current. When holding the sampled current, all the switches SW1 to SW3 are controlled to be in an off state. When outputting the sampled current, the switches SW1 and SW2 are controlled to be in an off state and the switch SW3 is controlled to be in an on state.
[0035]
As shown in FIG. 1, a current source U for flowing a current to be sampled is connected between the node Nb and the reference potential line VSS. A load Z through which the current sampled by the current sampling circuit 100 flows is connected between the node Nc and the reference potential line VSS.
[0036]
The operation of the current sampling circuit 100 shown in FIG. 1 will be described.
FIG. 2 is a timing chart for explaining the relationship between the state of the switches SW1 to SW3 and each signal in the current sampling circuit 100 of FIG. 2A to 2F sequentially show the states of the switches SW1 to SW, the voltage V_N1 of the node N1, the current I_N1 flowing through the node N1, and the voltage V_C1 of the capacitor C1.
[0037]
In the initial state in the timing chart of FIG. 2, the switches SW1 to SW3 are all off, and the charge of the capacitor C1 is completely discharged.
[0038]
At time T1, when an operation mode for performing current sampling (hereinafter, referred to as a sampling mode) is started, the switches SW1 and SW2 are controlled to be in an on state, and the current I_N1 to be sampled causes the switches SW1 and SW2 to be turned on. Through the capacitor C1. The capacitor C1 is charged by the current I_N1, and the capacitor voltage V_C1 increases with time. Then, when the capacitor voltage V_C1 reaches the threshold voltage of the p-type MOS transistor M1, the p-type MOS transistor M1 is turned on. At this time, since the p-type MOS transistor M2 shifts to the saturation region by the bias voltage output from the voltage output circuit 1, a part of the current I_N1 is transferred from the power supply line VDD to the p-type MOS transistor M1 and the p-type MOS transistor M2. Through the node N1. When the p-type MOS transistor M1 and the p-type MOS transistor M2 operate in the saturation region and the current flowing through these transistors becomes equal to the current I_N1 to be sampled, the current flowing through the capacitor C1 is depleted. Thereafter, the voltage V_C1 of the capacitor C1 is maintained at a constant voltage value Vgs1.
[0039]
At time T2, when the operation mode shifts to the mode for holding the sampling current (hereinafter referred to as the current holding mode), first, the switch SW1 is controlled to the off state, and at the subsequent time T3, the switch SW2 is controlled to the off state. .
If the switch SW2 is turned off earlier than the switch SW1, the charge charged in the capacitor C1 during this period is discharged through the p-type MOS transistor M2, and the voltage of the capacitor C1 fluctuates. Therefore, when the current sampling ends, the switch SW1 is turned off prior to the switch SW2, whereby voltage fluctuation of the capacitor C1 can be prevented.
[0040]
When all of the switches SW1 to SW3 are turned off at the time T3, the impedance between the gate terminal of the p-type MOS transistor M1 and the power supply line VDD becomes very large, so that the electric charge stored in the capacitor C1 becomes almost constant. Will be retained.
[0041]
At time T4, when the operation mode shifts to a mode for outputting the held sampling current (hereinafter, referred to as a current output mode), the switch SW3 is controlled to be turned on. At this time, since the p-type MOS transistor M2 operates in the saturation region by the bias voltage output from the voltage output circuit 1, the drain current Id_M1 of the p-type MOS transistor M1 is supplied via the p-type MOS transistor M2 and the switch SW3. Flow to load Z. The drain current Id_M1 has a current value determined according to the voltage V_C1 of the capacitor C1, that is, a current value substantially equal to the current I_N1 to be sampled.
[0042]
As described above, according to the current sampling circuit 100 of FIG. 1, in the sampling mode, the p-type MOS transistor M1 and the p-type MOS transistor M2 operate in the saturation region, and the capacitor C1 has a voltage corresponding to the current to be sampled. The charged voltage is charged. In the current holding mode, the impedance between the gate terminal of the p-type MOS transistor M1 and the power supply line VDD becomes very large, so that the charge stored in the capacitor C1 is held almost constant. In the current output mode, the p-type MOS transistor M1 and the p-type MOS transistor M2 operate in the saturation region, and the output sampling current is substantially equal to the current value corresponding to the voltage V_C1 of the capacitor C1, that is, the current to be sampled. They have equal current values.
Therefore, even when the voltage of the node N1 is different between the sampling mode and the current output mode, most of these voltage differences are reduced because the p-type MOS transistor M2 operates in the saturation region. Is converted to a voltage difference of the drain-source voltage Vds_M2. Therefore, the drain voltage of the p-type MOS transistor M1 becomes substantially the same in these two operation modes, and the fluctuation of the drain-source voltage Vds_M1 of the p-type MOS transistor M1 becomes very small. In addition, even if the drain-source voltage Vds_M1 fluctuates minutely, the fluctuation of the drain current Id_M1 becomes minute since the p-type MOS transistor M1 operates in the saturation region. That is, the drain current Id_M1 of the p-type MOS transistor M1 is less likely to be affected by the voltage fluctuation of the node N1, and the error between the current to be sampled and the sampled current can be made very small.
[0043]
Further, comparing the current sampling circuit 100 of FIG. 1 with the circuit of FIG. 10, only the p-type MOS transistor M2 and the voltage output circuit 1 are added, and elements such as capacitors that require a large area are added. No need to add. That is, since the current sampling circuit 100 can be realized by a simple circuit, an increase in layout area can be suppressed.
[0044]
<Second embodiment>
Next, a second embodiment will be described.
The current sampling circuit according to the second embodiment has, for example, a configuration similar to that of the current sampling circuit 100 in FIG.
However, the bias voltage output from the voltage output circuit 1 is adjusted to a voltage that causes the p-type MOS transistor M1 to operate at the boundary between the saturation region and the non-saturation region when at least a predetermined level of current is sampled.
[0045]
FIG. 3A is a graph showing the relationship between the drain current Id_M1 and the drain-source voltage Vds_M1 when the gate-source voltage of the p-type MOS transistor M1, that is, the voltage V_C1 of the capacitor C is the voltage value Vgs1. is there.
The operation region of the p-type MOS transistor M1 becomes a saturation region when the drain-source voltage Vds_M1 is larger than the pinch-off voltage Vsat1, and becomes an unsaturated region when it is smaller than this. The drain current Id_M1 in the saturation region has a substantially constant current value Is.
[0046]
In the example of FIG. 3A, the output bias voltage of the voltage output circuit 1 is such that the operating point of the p-type MOS transistor M1 is located in a predetermined vicinity on the saturation region side with respect to the operating point Psat1 of the pinch-off voltage Vsat1. It is adjusted so as to become the operating point P1.
[0047]
The pinch-off voltage Vsat1 can be expressed by, for example, the following equation using the threshold voltage Vth and the gate-source voltage Vgs1 of the p-type MOS transistor M1.
[0048]
(Equation 1)
Vsat1 = Vgs1−Vth (1)
[0049]
The drain-source voltage Vds1 at the operating point P1 is set to a value higher than the pinch-off voltage Vsat1 by a predetermined voltage value ΔVds.
[0050]
(Equation 2)
Vds1 = Vsat1 + ΔVds = Vgs1−Vth + ΔVds (2)
[0051]
The drain-source voltage Vds2 of the p-type MOS transistor M2 is expressed by the following equation using the drain-source voltage Vds1 and the gate-source voltage Vgs1 of the p-type MOS transistor M1.
[0052]
[Equation 3]
Vds2 = Vgs1−Vds1 = Vth−ΔVds (3)
[0053]
Therefore, the output bias of the voltage output circuit 1 is set so that the drain-source voltage Vds2 of the p-type MOS transistor M2 with respect to the sampling current of the current value Is becomes slightly smaller than, for example, the threshold voltage Vth of the p-type MOS transistor M1. By adjusting the voltage, the operating point of the p-type MOS transistor M1 at this sampling current can be set near the operating point at which the p-type MOS transistor M1 pinches off.
[0054]
When the sampling current becomes larger than the current value Is, the gate voltage of the p-type MOS transistor M2 in the voltage output circuit 1 is reduced to the reference potential line VSS side, and the gate-source voltage Vgs_M2 increases. Thereby, even when the sampling current becomes larger than the current value Is, the p-type MOS transistor M2 can be operated at the boundary between the saturated region and the non-saturated region.
Conversely, when the sampling current becomes smaller than the current value Is, the gate voltage of the p-type MOS transistor M2 in the voltage output circuit 1 is raised toward the power supply line VDD, and the gate-source voltage Vgs_M2 decreases. I do. Thereby, when the sampling current becomes smaller than the current value Is, it is possible to prevent the operation region of the p-type MOS transistor M2 from shifting to the non-saturation region.
[0055]
The above is the description regarding the setting of the operating point of the p-type MOS transistor M1. However, in addition to the p-type MOS transistor M1, the operating point of the p-type MOS transistor M2 may be set at the boundary between the saturated region and the non-saturated region. It is possible.
[0056]
FIG. 3B is a graph showing a relationship between the drain current Id_M2 and the drain-source voltage Vds_M2 when the gate-source voltage of the p-type MOS transistor M2 is the voltage value Vgs2.
The operation region of the p-type MOS transistor M2 becomes a saturation region when the drain-source voltage Vds_M2 is larger than the pinch-off voltage Vsat2, and becomes an unsaturated region when it is smaller than the pinch-off voltage Vsat2. The drain current Id_M2 in the saturation region has a substantially constant current value Is.
[0057]
Since the voltage value Vds2 and the current value Is of the equation (3) are already determined, the voltage ratio Vgs2 between the gate and the source of the p-type transistor M2 and the size ratio of the p-type MOS transistor M1 and the p-type MOS transistor M2 are determined. By appropriately determining the (gate width ratio and gate length ratio), the operating point P2 of the p-type MOS transistor M2 can be arranged in a predetermined vicinity of the saturation region side of the pinch-off operating point Psat2.
[0058]
As described above, according to the current sampling circuit according to the second embodiment of the present invention, in the sampling mode and the current output mode, the p-type MOS transistor M1 and the p-type MOS transistor M2 are in the saturation region and the non-saturation region. , The drain-source voltage can be reduced as much as possible. Thereby, the voltage range of the node N1 where the current sampling circuit can operate can be widened. Further, the required power supply voltage can be reduced in the case where the voltage range of the node N1 is the same, so that the voltage of the circuit can be reduced.
[0059]
<Third embodiment>
Next, a third embodiment will be described.
In the third embodiment, the configuration of the voltage output circuit in the first and second embodiments described above is further embodied.
[0060]
FIG. 4 is a circuit diagram illustrating an example of a configuration of a current sampling circuit 100A according to the third embodiment of the present invention.
In the current sampling circuit 100A of FIG. 4, the voltage output circuit 1 in the current sampling circuit 100 of FIG. 1 is replaced with a voltage output circuit 1A. In addition, the current sampling circuit 100A has the same configuration as the current sampling circuit 100.
[0061]
In the example of FIG. 4, the voltage output circuit 1A has a p-type MOS transistor M3 and a current mirror circuit 11.
The p-type MOS transistor M3 is an embodiment of the third insulated gate transistor of the present invention.
The current mirror circuit 11 is an embodiment of the first current mirror circuit of the present invention.
[0062]
The current mirror circuit 11 inputs a current to be sampled, and outputs a current I11 corresponding to the input current.
The p-type MOS transistor M3 is connected between the current output terminal of the current mirror circuit 11 and the power supply line VDD, and the voltage of the gate terminal is connected to this current output terminal. The connection point between the gate terminal of the p-type MOS transistor M3 and the current output terminal of the current mirror circuit 11 is connected to the gate terminal of the p-type MOS transistor M2.
[0063]
The size (channel width, channel length, and the like) of the p-type MOS transistor M3 is set so that the p-type MOS transistor M1 and the p-type MOS transistor M2 operate in the saturation region at least when a current of a predetermined level is sampled. Adjusted. When the size ratio between the p-type MOS transistor M1 and the p-type MOS transistor M2 is adjusted as described in the second embodiment, the p-type MOS transistor M1 and the p-type MOS transistor M2 are adjusted accordingly. The size of the p-type MOS transistor M3 is adjusted so that M2 operates at the boundary between the saturated region and the unsaturated region.
[0064]
According to the current sampling circuit 100A, the current to be sampled is directly input to the current mirror circuit 11 in the voltage output circuit 1A. The output current I11 of the current mirror circuit 11 according to the current to be sampled flows through the p-type MOS transistor M3. Then, the gate voltage of the p-type MOS transistor M3 generated according to the output current I11 is supplied to the gate terminal of the p-type MOS transistor M2 as a bias voltage. As described above, the bias voltage supplied to the gate terminal of the p-type MOS transistor M2 can be changed following the current to be sampled.
[0065]
<Fourth embodiment>
Next, a fourth embodiment will be described.
In the current sampling circuit 100A according to the third embodiment, since the current to be sampled is directly input to the current mirror circuit 11 of the voltage output circuit 1A, the current holding mode and the current output mode are set after the current sampling is completed. If the current to be sampled fluctuates, the output bias voltage of the voltage output circuit 1A fluctuates in accordance with this fluctuation, resulting in a disadvantage that a current sampling error occurs. In the fourth embodiment, such disadvantages of the third embodiment are improved.
[0066]
FIG. 5 is a circuit diagram showing an example of a configuration of a current sampling circuit 100B according to the fourth embodiment of the present invention.
In the current sampling circuit 100B of FIG. 5, the voltage output circuit 1 in the current sampling circuit 100 of FIG. 1 is replaced with a voltage output circuit 1B. In addition, the current sampling circuit 100B has the same configuration as the current sampling circuit 100.
[0067]
The voltage output circuit 1B has a p-type MOS transistor M4 and a p-type MOS transistor M5, and a current mirror circuit 12.
The p-type MOS transistor M4 is an embodiment of the fourth insulated gate transistor of the present invention.
The p-type MOS transistor M5 is an embodiment of the fifth insulated gate transistor of the present invention.
The current mirror circuit 12 is an embodiment of the second current mirror circuit of the present invention.
[0068]
The p-type MOS transistor M4 is connected between the current input terminal of the current mirror circuit 12 and the power supply line VDD, and receives the charging voltage of the capacitor C1 at the gate terminal.
The p-type MOS transistor M5 is connected between the current output terminal of the current mirror circuit 12 and the power supply line VDD, and has a gate terminal connected to the current output terminal. A connection point between the gate terminal of the p-type MOS transistor M5 and the current output terminal of the current mirror circuit 12 is connected to the gate terminal of the p-type MOS transistor M2.
[0069]
The size (channel width, channel length, etc.) of the p-type MOS transistor M4 and the p-type MOS transistor M5 saturates the p-type MOS transistor M1 and the p-type MOS transistor M2 at least when a predetermined level of current is sampled. Adjusted to operate in the area.
When the size ratio between the p-type MOS transistor M1 and the p-type MOS transistor M2 is adjusted as described in the second embodiment, the p-type MOS transistor M1 and the p-type MOS transistor M2 are adjusted accordingly. The sizes of p-type MOS transistor M4 and p-type MOS transistor M5 are adjusted so that M2 operates at the boundary between the saturated region and the non-saturated region.
[0070]
According to the current sampling circuit 100B, in the voltage output circuit 1B, a current corresponding to the charging voltage of the capacitor C1 flows through the p-type MOS transistor M4 and is input to the current mirror circuit 12, and a current I12 corresponding to the current is mirrored in the current mirror circuit 12. It is output from the current output terminal of the circuit 12. A voltage corresponding to the current I12 is generated at the gate terminal of the p-type MOS transistor M5, and is supplied as a bias voltage to the gate terminal of the p-type MOS transistor M2.
As described above, since the bias voltage supplied to the gate terminal of the p-type MOS transistor M2 is generated according to the charging voltage of the capacitor C1, the bias voltage can be changed to follow the current to be sampled.
Further, even if the current to be sampled changes after sampling, the charging voltage of the capacitor C1 is kept almost constant, so that the bias voltage generated accordingly is also kept almost constant. Therefore, an appropriate bias voltage can be generated without being affected by a change in the current of the sampling target after sampling.
[0071]
<Fifth embodiment>
Next, a fifth embodiment will be described.
In the current sampling circuit 100B according to the fourth embodiment, the current flows through the p-type MOS transistor M4 and the p-type MOS transistor M5 in the current holding mode, and thus there is a disadvantage that power is wasted. In the fifth embodiment, such disadvantages in the fourth embodiment are improved.
[0072]
FIG. 6 is a circuit diagram illustrating an example of a configuration of a current sampling circuit 100C according to the fifth embodiment of the present invention.
In the current sampling circuit 100C of FIG. 5, the voltage output circuit 1 in the current sampling circuit 100 of FIG. 1 is replaced with a voltage output circuit 1C. In addition, the current sampling circuit 100C has the same configuration as the current sampling circuit 100.
[0073]
The voltage output circuit 1C has a configuration in which a switch SW4 is inserted on the connection line between the current input terminal of the current mirror circuit 12 of the voltage output circuit 1B and the p-type MOS transistor M4 in FIG.
[0074]
The switch SW4 is controlled by an unillustrated control circuit from an on state to an off state when the current holding mode is started, and from an off state to an on state when the current holding mode is ended.
Therefore, in the current holding mode, the current flowing through the p-type MOS transistor M4 and the p-type MOS transistor M5 is cut off, so that the power wasted by the current flowing through these transistors can be reduced.
[0075]
<Sixth embodiment>
Next, a sixth embodiment of the present invention will be described.
In the current sampling circuits according to the first to fifth embodiments, since the current to be sampled flowing through the node N2 directly supplies the charging current of the capacitor C1, when the current to be sampled is small, the charging of the capacitor C1 is performed. The disadvantage is that it takes a very long time to complete. Further, in the case where the sampling of the small current is performed after the sampling of the large current is performed, there is a disadvantage that the discharge of the charge stored in the capacitor C1 requires a very long time. In the sixth embodiment, such disadvantages of each embodiment are improved.
[0076]
FIG. 7 is a circuit diagram illustrating an example of a configuration of a current sampling circuit 100D according to the sixth embodiment of the present invention.
In the current sampling circuit 100D of FIG. 7, the switch SW1 in the current sampling circuit 100 of FIG. In addition, the current sampling circuit 100D has the same configuration as the current sampling circuit 100.
The operational amplifier 2 is an embodiment of the capacitor charge / discharge circuit of the present invention.
[0077]
The operational amplifier 2 amplifies the differential voltage input between the positive input terminal + and the negative input terminal-, outputs the amplified voltage to the gate terminal of the p-type MOS transistor M1, and feeds it back to the negative input terminal-. Positive input terminal + is connected to node N1.
[0078]
Since the gain of the operational amplifier 2 is very high, the output voltage is negatively fed back to the negative input terminal-, so that the voltage at the negative input terminal-is controlled to be substantially equal to the voltage at the positive input terminal +. That is, the gate voltage of the p-type MOS transistor M1 is controlled to be equal to the voltage of the node N1, and in the process, the voltage V_C1 of the capacitor C1 is charged or discharged by the operational amplifier 2. As described above, the operational amplifier 2 functions as a capacitor charging / discharging circuit that charges or discharges the capacitor C1 according to the voltage difference between the gate terminal of the p-type MOS transistor M1 and the node N1.
[0079]
The operational amplifier 2 charges or discharges the capacitor C1 in a normal state of amplifying the differential voltage of the input terminal or changing the output impedance to a high impedance according to a control signal Sc from a control circuit (not shown). The operation is set to the stopped state. When the operation mode is the sampling mode, the operational amplifier 2 is set to the normal state, and in the other modes, that is, the current holding mode and the current output mode, the operation of charging and discharging the capacitor C1 is set to a stopped state.
[0080]
According to the current sampling circuit 100D having the operational amplifier 2 described above, the current to be sampled does not flow directly to the capacitor C1, but most of the current flows to the series circuit of the p-type MOS transistor M1 and the p-type MOS transistor M2. Therefore, for example, when the sampling mode is started in a state where the capacitor C1 is not charged, the p-type MOS transistor M1 is cut off at the initial time, and the voltage of the node N1 is referenced by the current source U1. It is rapidly lowered to the potential line VSS side. As a result, a large differential voltage is input to the input terminal of the operational amplifier 2, and its output voltage rapidly drops to the reference potential line VSS side, and the capacitor C1 is rapidly charged.
[0081]
On the other hand, if the sampling of a small current is started while the voltage of the capacitor C1 is relatively large, the p-type MOS transistor M1 and the p-type MOS transistor M2 operate in the non-saturation region at the initial time, so that the node N1 Is rapidly pulled up to the power supply line VDD side. As a result, a large differential voltage is input to the input terminal of the operational amplifier 2, and its output voltage rapidly rises toward the power supply line VDD, and the capacitor C1 is rapidly discharged.
[0082]
As described above, when the current is sampled, the capacitor C1 is rapidly charged or discharged by the operational amplifier 2, so that the time required for current sampling can be greatly reduced.
Note that the current sampling circuit 100D in FIG. 7 is obtained by replacing the switch SW1 in the current sampling circuit 100 in FIG. 1 with the operational amplifier 2, but is different from the current sampling circuit according to the second to fifth embodiments described above. Similar effects can be obtained by performing similar substitution.
[0083]
<Seventh embodiment>
Next, a seventh embodiment of the present invention will be described.
FIG. 8 is a block diagram showing an example of a configuration of a current output type driving circuit 200 for an organic EL panel or the like according to the seventh embodiment of the present invention.
The current output type driving circuit 200 includes a writing circuit 30, a reference current source circuit 40, a shift register 50, a register array 60, a current output type digital-analog conversion circuit (hereinafter, referred to as DAC) 80-1, , 80-3, 80-4 and current output circuits 90-1, 90-2, ..., 90-3, 90-4.
The reference current source circuit 40 is one embodiment of the constant current source of the present invention.
The register array 60 is one embodiment of the register array of the present invention.
The DACs 80-1, 80-2, ..., 80-3, 80-4 are one embodiment of the current output type digital-analog conversion circuit of the present invention.
The current output circuits 90-1, 90-2, ..., 90-3, 90-4 are one embodiment of the current output circuit of the present invention.
[0084]
The writing circuit 30 holds the input m-bit image data {Din0, Din1,..., Din (m-1)}, and outputs the held image data to the register array 60.
[0085]
The reference current source circuit 40 generates a reference current to be supplied to the DACs 80-1, 80-2, ..., 80-3, 80-4.
[0086]
The shift register 50 sequentially shifts the flag signal input to the terminal Sin, and supplies the shifted flag signal to the register array 60, so that the image data input from the writing circuit 30 is written to the register array 60. Positions (addresses) are sequentially selected.
[0087]
The register array 60 holds the image data input from the writing circuit 30 at an address selected according to the flag signal supplied from the shift register 50. When the drive signals are held by the current output circuits (90-1 to 90-4), the image data held at predetermined addresses are respectively converted into DACs 80-1, 80-2,..., 80-3, 80-. 4 is output.
[0088]
, 80-3, 80-4 generate current signals corresponding to the image data input from the register array 60, and output the current output circuits 90-1, 90-2,. 90-3 and 90-4.
[0089]
, 90-3, 90-4 are current signals corresponding to image data input from the DACs 80-1, 80-2, ..., 80-3, 80-4. Are sampled and held, and the held current is output to n-channel output terminals IOUT1, IOUT2,..., IOUTn.
[0090]
FIG. 9 is a block diagram illustrating an example of the configuration of the current output circuit 90-1.
The current output circuit 90-1 includes a current signal holding circuit 91 including k current sampling circuits 91-1, 91-2,..., 91-k, and k current sampling circuits 91-1, 91-2,. , 92-k. The transistor array 92 includes transistors 92-1, 92-2,..., 92-k.
Although not shown, the other current output circuits (90-2 to 90-4) have the same configuration.
[0091]
The current sampling circuits described in any of the first to sixth embodiments are applied to the current sampling circuits 91-1, 91-2,..., 91-k.
A current signal DAC_out output from the DAC 80-1 is input to the node N2 of each current sampling circuit as a current to be sampled, and further, a selection signal S_SEL and a control signal S_CONT supplied from a control circuit (not shown) are input. You. The sampled current is output from a node N3 of each current sampling circuit, and is output to output terminals IOUT1, IOUT2,..., IOUTk via transistors 92-1, 92-2,.
[0092]
In the current output type driving circuit 200 having the above-described configuration, when image data is written to the register array 60, m-bit image data {Din0, Din1,..., Din (m−1)} is written into the writing circuit 30. And the flag signal input to the terminal Sin of the shift register 50 is sequentially shifted and supplied to the register array 60. As a result, the image data held in the writing circuit 30 is sequentially written to a series of addresses in the register array 60.
[0093]
When the drive signal is held, the image data written at a predetermined address of the register array 60 is converted into a current signal by the corresponding DAC (80-1 to 80-4), and the current output circuit ( 90-1 to 90-4).
[0094]
With the input of the current signal, the current sampling circuits (91-1 to 91-k) are sequentially selected by a selection signal S_SEL from a control circuit (not shown). The selected current sampling circuit is set to the sampling mode, and the input current signal is sampled for a predetermined time. After the end of the sampling, each internal switch is controlled in accordance with the control signal S_CONT to set the current holding mode.
In this manner, the current signals sequentially input to the current output circuits (90-1 to 90-4) are sequentially held in the internal current sampling circuits (91-1 to 91-k).
[0095]
When the drive signal is output, the transistor array 92 is set in a state where the current sampling circuits (91-1 to 91-k) are set to the current output mode in accordance with a control signal S_CONT from a control circuit (not shown). Are turned on by an output enable signal S_OUT from a control circuit (not shown) that drives each of the transistors (92-1 to 92-k). As a result, the current held in each current sampling circuit (91-1 to 91-k) of the current output circuit (90-1 to 90-4) is transferred to each transistor (92-1 to 92-k) of the transistor array 92. ) Are output to output terminals (I0UT1 to IOUTn).
[0096]
As described above, according to the current output type driving circuit 200 of FIG. 8, the driving current signal output from the DAC is held in the plurality of current sampling circuits, and the held current signals are used to control the plurality of channels. Are simultaneously driven. Therefore, it is possible to simultaneously drive the output lines of a plurality of channels using one DAC, and it is possible to reduce the number of DAC circuits required for the drive circuit. Thus, the circuit scale can be reduced, and the layout area can be reduced.
[0097]
Further, since any one of the current sampling circuits according to the above-described first to sixth embodiments is applied as a circuit for holding a current signal, the current level of the drive signal can be set very accurately. become.
[0098]
Note that the present invention is not limited to the embodiment described above.
The circuit shown as an example in each of the embodiments described above is an example, and can be arbitrarily modified to another circuit having an equivalent function.
[0099]
In the circuits shown as examples in the above embodiments, p-type MOS transistors are mainly used as transistors. However, the present invention is not limited to this. The invention is feasible.
[0100]
【The invention's effect】
According to the present invention, first, in the current sampling circuit, the error between the current to be sampled and the sampled current can be reduced, and the sampling accuracy can be improved.
Second, the current output type driving circuit can generate a high-precision output current according to input data.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating an example of a configuration of a current sampling circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining the relationship between the state of each switch and each signal in the current sampling circuit of FIG. 1;
FIG. 3 is a diagram showing a relationship between a drain current and a drain-source voltage when a gate-source voltage is kept constant in two p-type MOS transistors of the current sampling circuit according to the second embodiment; It is.
FIG. 4 is a circuit diagram illustrating an example of a configuration of a current sampling circuit according to a third embodiment of the present invention.
FIG. 5 is a circuit diagram illustrating an example of a configuration of a current sampling circuit according to a fourth embodiment of the present invention.
FIG. 6 is a circuit diagram illustrating an example of a configuration of a current sampling circuit according to a fifth embodiment of the present invention.
FIG. 7 is a circuit diagram illustrating an example of a configuration of a current sampling circuit according to a sixth embodiment of the present invention.
FIG. 8 is a block diagram showing an example of a configuration of a current output type driving circuit for an organic EL panel or the like according to a seventh embodiment of the present invention.
9 is a block diagram showing an example of a configuration of a current output circuit in the current output type driving circuit of FIG.
FIG. 10 is a circuit diagram of a commonly used current sampling circuit.
FIG. 11 shows the relationship between the drain current and the drain-source voltage of a MOS transistor when the gate-source voltage is equal to the drain-source voltage and when the gate-source voltage is kept constant. FIG.
[Explanation of symbols]
1, 1A, 1B, 1C: voltage output circuit, 2: operational amplifier, 11, 12: current mirror circuit, 30: writing circuit, 40: reference current source circuit, 50: shift register, 60: register array, 80-1 -80-4: DAC, 90-1 to 90-4: Current output circuit, 91: Current signal holding circuit, 92: Transistor array, 91-1 to 91-k, 100, 100A to 100D: Current sampling circuit, M1 M5: p-type MOS transistor, SW1 to SW4: switch, C: capacitor, U: current source, Z: load

Claims (20)

A first insulated gate transistor connected between the power supply line and the first node;
A capacitor connected between the gate terminal of the first insulated gate transistor and the power supply line;
A first switch connected between a gate terminal of the first insulated gate transistor and the first node;
A second insulated gate transistor inserted on a connection line between the first insulated gate transistor and the first node;
A voltage for operating the first insulated gate transistor and the second insulated gate transistor in a saturation region at least when a current of a predetermined level is sampled, and a voltage that changes according to a current to be sampled To a gate terminal of the second insulated gate transistor, a second switch connected between a second node through which the current to be sampled flows and the first node,
A third switch connected between a third node through which the sampled current flows and the first node;
In a first operation mode in which current is sampled, a second operation mode in which the first switch and the second switch are turned on and the third switch is turned on and the sampled current is held In the third operation mode in which the first switch, the second switch, and the third switch are controlled to be open and the held sampling current is output, the first switch and the second switch And a control circuit for controlling the third switch to an open state and the third switch to a conductive state. The voltage output circuit, when the current of the predetermined level is sampled in the first operation mode, a voltage for operating the first insulated gate transistor at a boundary between a saturated region and a non-saturated region; Outputting to the gate terminal of the second insulated gate transistor;
The current sampling circuit according to claim 1. The first insulated gate transistor and the second insulated gate transistor may be configured such that one or both of a gate width ratio and a gate length ratio of the first insulated gate transistor and the second insulated gate transistor are different from each other when the current of the predetermined level is sampled. 2, which is set to operate the insulated gate transistor at the boundary between the saturated region and the unsaturated region.
The current sampling circuit according to claim 2. The voltage output circuit,
A first current mirror circuit that inputs the current to be sampled and outputs a current corresponding to the input current;
The power supply line is connected between the current output terminal of the first current mirror circuit and the power supply line, and the voltage of the gate terminal is changed according to the voltage of the current output terminal. A third insulated gate transistor that outputs to a gate terminal of the gate transistor.
The current sampling circuit according to claim 1. The voltage output circuit outputs a voltage that changes according to a charging voltage of the capacitor to a gate terminal of the second insulated gate transistor.
The current sampling circuit according to claim 1. The voltage output circuit,
A second current mirror circuit that outputs a current corresponding to the input current;
A fourth insulated gate transistor connected between a current input terminal of the second current mirror circuit and the power supply line and having a gate terminal charged with a charging voltage of the capacitor;
The voltage of the gate terminal is connected between the current output terminal of the second current mirror circuit and the power supply line, and the voltage of the gate terminal is changed according to the voltage of the current output terminal. A fifth insulated gate transistor that outputs to the gate terminal of the gate transistor,
A current sampling circuit according to claim 5. The voltage output circuit includes a fourth switch inserted on a connection line between the fourth insulated gate transistor and a current input terminal of the second current mirror circuit,
The control circuit controls the fourth switch from a conductive state to an open state when starting the second operation mode, and sets the fourth switch when ending the second operation mode. Control from an open state to a conductive state,
The current sampling circuit according to claim 6. A first insulated gate transistor connected between the power supply line and the first node;
A capacitor connected between the gate terminal of the first insulated gate transistor and the power supply line;
The capacitor is charged or discharged according to the voltage difference between the voltage at the gate terminal of the first insulated gate transistor and the voltage at the first node, and the charge / discharge operation is performed according to an input control signal. Or a capacitor charge / discharge circuit to stop,
A second insulated gate transistor inserted on a connection line between the first insulated gate transistor and the first node;
A voltage for operating the first insulated gate transistor and the second insulated gate transistor in a saturation region at least when a current of a predetermined level is sampled, and a voltage that changes according to a current to be sampled To a gate terminal of the second insulated gate transistor, a second switch connected between a second node through which the current to be sampled flows and the first node,
A third switch connected between a third node through which the sampled current flows and the first node;
A second switch connected between the first node and the second node; a third switch connected between the first node and the third node; In the first operation mode in which sampling is performed, the second switch is controlled to be in a conductive state, the third switch is controlled to be in an open state, and the control signal for performing charging and discharging of the capacitor charging and discharging circuit is output. In the second operation mode for holding the sampled current, while controlling the second switch and the third switch to be in an open state, outputting the control signal for stopping charging and discharging of the capacitor charging and discharging circuit; In a third operation mode in which the held sampling current is output, the second switch is controlled to be open and the third switch is controlled to be conductive. Current sampling circuit and a control circuit for outputting the control signal for stopping the charging and discharging of the serial capacitor charge and discharge circuit. The voltage output circuit, when the current of the predetermined level is sampled in the first operation mode, a voltage for operating the first insulated gate transistor at a boundary between a saturated region and a non-saturated region; Outputting to the gate terminal of the second insulated gate transistor;
A current sampling circuit according to claim 8. The first insulated gate transistor and the second insulated gate transistor may be configured such that one or both of a gate width ratio and a gate length ratio of the first insulated gate transistor and the second insulated gate transistor are different from each other when the current of the predetermined level is sampled. 2, which is set to operate the insulated gate transistor at the boundary between the saturated region and the unsaturated region.
A current sampling circuit according to claim 9. The voltage output circuit,
A first current mirror circuit that inputs the current to be sampled and outputs a current corresponding to the input current;
The power supply line is connected between the current output terminal of the first current mirror circuit and the power supply line, and the voltage of the gate terminal is changed according to the voltage of the current output terminal. A third insulated gate transistor that outputs to a gate terminal of the gate transistor.
A current sampling circuit according to claim 8. The voltage output circuit outputs a voltage that changes according to a charging voltage of the capacitor to a gate terminal of the second insulated gate transistor.
A current sampling circuit according to claim 8. The voltage output circuit,
A second current mirror circuit that outputs a current corresponding to the input current;
A fourth insulated gate transistor connected between a current input terminal of the second current mirror circuit and the power supply line and having a gate terminal charged with a charging voltage of the capacitor;
The voltage of the gate terminal is connected between the current output terminal of the second current mirror circuit and the power supply line, and the voltage of the gate terminal is changed according to the voltage of the current output terminal. A fifth insulated gate transistor that outputs to the gate terminal of the gate transistor,
The current sampling circuit according to claim 12. The voltage output circuit includes a fourth switch inserted on a connection line between the fourth insulated gate transistor and a current input terminal of the second current mirror circuit,
The control circuit controls the fourth switch from a conductive state to an open state when starting the second operation mode, and sets the fourth switch when ending the second operation mode. Control from an open state to a conductive state,
The current sampling circuit according to claim 13. A current output type driving circuit that outputs a current of a plurality of channels according to input data,
A register array for holding the input data,
A constant current source for generating a constant current;
A current output type digital-analog conversion circuit that inputs the held data of the register array, and the current generated by the constant current source, and converts the input current into an output current having a level corresponding to the input held data;
A current output circuit that samples an output current of the current output type digital-analog conversion circuit for each of the held data and drives a plurality of channels of output lines with the sampled output current value;
The current output circuit,
A first insulated gate transistor connected between the power supply line and the first node;
A capacitor connected between the gate terminal of the first insulated gate transistor and the power supply line;
A first switch connected between a gate terminal of the first insulated gate transistor and the first node;
A second insulated gate transistor inserted on a connection line between the first insulated gate transistor and the first node;
A voltage for operating the first insulated gate transistor and the second insulated gate transistor in a saturation region at least when a current of a predetermined level is sampled, and a voltage that changes according to a current to be sampled To a gate terminal of the second insulated gate transistor, a second switch connected between a second node through which the current to be sampled flows and the first node,
A third switch connected between a third node through which the sampled current flows and the first node;
In a first operation mode in which current is sampled, a second operation mode in which the first switch and the second switch are turned on and the third switch is turned on and the sampled current is held In the third operation mode in which the first switch, the second switch, and the third switch are controlled to be open and the held sampling current is output, the first switch and the second switch And a control circuit for controlling the third switch to an open state and the third switch to a conductive state.
Current output type drive circuit. The voltage output circuit, when the current of the predetermined level is sampled in the first operation mode, a voltage for operating the first insulated gate transistor at a boundary between a saturated region and a non-saturated region; Outputting to the gate terminal of the second insulated gate transistor;
A current output type driving circuit according to claim 15. The first insulated gate transistor and the second insulated gate transistor may be configured such that one or both of a gate width ratio and a gate length ratio of the first insulated gate transistor and the second insulated gate transistor are different from each other when the current of the predetermined level is sampled. 2, which is set to operate the insulated gate transistor at the boundary between the saturated region and the unsaturated region.
A current output type driving circuit according to claim 16. A current output type driving circuit that outputs a current of a plurality of channels according to input data,
A register array for holding the input data,
A constant current source for generating a constant current;
A current output type digital-analog conversion circuit that inputs the held data of the register array, and the current generated by the constant current source, and converts the input current into an output current having a level corresponding to the input held data;
A current output circuit that samples an output current of the current output type digital-analog conversion circuit for each of the held data and drives a plurality of channels of output lines with the sampled output current value;
The current output circuit,
A first insulated gate transistor connected between the power supply line and the first node;
A capacitor connected between the gate terminal of the first insulated gate transistor and the power supply line;
The capacitor is charged or discharged according to the voltage difference between the voltage at the gate terminal of the first insulated gate transistor and the voltage at the first node, and the charge / discharge operation is performed according to an input control signal. Or a capacitor charge / discharge circuit to stop,
A second insulated gate transistor inserted on a connection line between the first insulated gate transistor and the first node;
A voltage for operating the first insulated gate transistor and the second insulated gate transistor in a saturation region at least when a current of a predetermined level is sampled, and a voltage that changes according to a current to be sampled To a gate terminal of the second insulated gate transistor, a second switch connected between a second node through which the current to be sampled flows and the first node,
A third switch connected between a third node through which the sampled current flows and the first node;
A second switch connected between the first node and the second node; a third switch connected between the first node and the third node; In the first operation mode in which sampling is performed, the second switch is controlled to be in a conductive state, the third switch is controlled to be in an open state, and the control signal for performing charging and discharging of the capacitor charging and discharging circuit is output. In the second operation mode for holding the sampled current, while controlling the second switch and the third switch to be in an open state, outputting the control signal for stopping charging and discharging of the capacitor charging and discharging circuit; In a third operation mode in which the held sampling current is output, the second switch is controlled to be open and the third switch is controlled to be conductive. Stopping the discharge of the serial capacitor charging and discharging circuit and a control circuit for outputting the control signal,
Current output type drive circuit. The voltage output circuit, when the current of the predetermined level is sampled in the first operation mode, a voltage for operating the first insulated gate transistor at a boundary between a saturated region and a non-saturated region; Outputting to the gate terminal of the second insulated gate transistor;
A current output type driving circuit according to claim 18. The first insulated gate transistor and the second insulated gate transistor may be configured such that one or both of a gate width ratio and a gate length ratio of the first insulated gate transistor and the second insulated gate transistor are different from each other when the current of the predetermined level is sampled. 2, which is set to operate the insulated gate transistor at the boundary between the saturated region and the unsaturated region.
A current output type driving circuit according to claim 19.

Images