JP2004091221A - Silicon single crystal, epitaxial wafer and their manufacturing processes - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon single crystal which yields an epitaxial wafer which has no epitaxial defect and shows a good in-plane uniformity concerning oxygen precipitation density and an excellent IG (intrinsic gettering) effect, the epitaxial wafer and their manufacturing processes. <P>SOLUTION: The epitaxial defect is drastically suppressed without employing any means which results in productivity deterioration such as a reduced pull-up speed of the single crystal, by quenching the pulled single crystal at 1,100-900°C, i.e. at a cooling rate of ≥3.0°C/min within the temperature range and reducing a size of a Crown-in oxygen precipitation nucleus. <P>COPYRIGHT: (C)2004,JPO

Description

【００４５】
【発明の効果】
この発明によると、シリコン単結晶の育成に際して引上げ速度を速くでき、単結晶製造の生産性を低下させることがなく、また育成時の熱履歴を最適化することで、ウェーハ化した後に目的のエピタキシャル欠陥の個数が低減され、酸素析出物密度の面内均一性が良好でかつ高いゲッタリング能力を付与でき、さらに安定的に抵抗率が０．００８〜０．０２５Ω・ｃｍのｐ／ｐ^＋エピタキシャルウェーハを提供できる。
【図面の簡単な説明】
【図１】ＣＺ法による途中過程の引き上げ速度を変更した際のエピタキシャル欠陥密度と引き上げ速度変更開始時の温度との関係を示すグラフである。
【図２】シリコン単結晶の育成装置の概略構成示す説明図である。
【図３】図２の熱シールド材に冷却手段を組み込む構成を示す説明図である。
【符号の説明】
１　ルツボ
１ａ　石英製容器
１ｂ　黒鉛製容器
２　加熱ヒータ
３　融液
４　引き上げ軸
５　種結晶
６　単結晶
７　熱シールド材
８　冷却筒[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a silicon single crystal used for a semiconductor integrated circuit device and an improvement of an epitaxial wafer obtained from the single crystal, and a specific cooling method for pulling and growing a single crystal having a resistivity of 0.008 to 0.025 Ω · cm. Silicon single crystal and epitaxial wafer capable of providing an epitaxial wafer without occurrence of epitaxial defects, good in-plane uniformity of oxygen precipitate density, and excellent in IG (Intrinsic gettering) effect, and their production. About the method.
[0002]
[Prior art]
2. Description of the Related Art High integration of silicon semiconductor devices has been remarkably progressing, and higher quality silicon wafers themselves as substrates for forming devices have been more strictly required. In other words, as circuit patterns become increasingly finer with higher integration, crystal defects such as dislocations that cause an increase in leakage current and a reduction in carrier lifetime in the device active region where devices on the wafer are formed, Reduction and removal of metallic impurities are more strictly required than ever.
[0003]
From such a demand, an epitaxial wafer in which an epitaxial layer substantially free of crystal defects is grown on the wafer has been developed and is often used for manufacturing highly integrated devices. As a wafer on which the epitaxial layer is grown, a p ⁺ silicon wafer doped with boron at a high concentration is generally used.
[0004]
The reason that the p ⁺ wafer is adopted as the epitaxial wafer is that the so-called latch-up phenomenon in which stray charges generated when the device operates causes an unintended parasitic transistor to operate, as a device design reason, is called p ^+. This can be prevented by using a wafer, and device design may be facilitated. Further, when a capacitor having a trench structure is used, there is an advantage that the case where the depletion layer spreads at the time of voltage application around the trench is p ⁺ can be prevented. A wafer obtained by growing an epitaxial layer on such a p ⁺ wafer is referred to as a p / p ⁺ epitaxial wafer.
[0005]
[Problems to be solved by the invention]
In general, it is known that a low-resistivity wafer to which boron is added at a high concentration hardly generates epitaxial defects even if an epitaxial layer is formed on the surface. In recent years, however, it has been found that epitaxial defects frequently occur when an epitaxial layer is formed on a p ⁺ wafer doped with boron in a resistivity range of 0.008 to 0.025 Ωcm.
[0006]
The present inventors have investigated the cause, and found that in a p ⁺ wafer having a resistivity in the range of 0.008 to 0.025 Ωcm, a crystal region having more than 1 × 10 ² oxidation-induced stacking faults / cm ² is present. It was found that epitaxial defects occurred in the region where the oxidation-induced stacking faults exist.
[0007]
In order to avoid epitaxial defects, it is conceivable to change the resistance value. However, by forming an epitaxial layer having a high resistance value on the surface of a wafer having a low resistance value of 0.008 to 0.025 Ω · cm, a high-speed transistor is formed. And the separation between pn junction elements can be made effective, so that reduction of epitaxial defects is strongly required for a silicon single crystal wafer having the above resistivity range.
[0008]
Further, although the occurrence of the oxidation-induced stacking faults can be reduced by lowering the oxygen concentration in the wafer, the lowering of the oxygen in the wafer causes a decrease in the amount of acid precipitates formed inside the wafer, resulting in 1G (Intrinsic gettering). ) Capability will be reduced. In consideration of the gettering ability, the oxygen concentration in the wafer must be at least 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) or more.
[0009]
When trying to manufacture ap ⁺ wafer having a resistivity in the range of 0.008 to 0.025 Ωcm in the oxygen concentration range, the inventors inevitably have 1 × 10 ² oxidation-induced stacking faults / cm ² . It has been found that there is a problem that a crystal region exceeding the absolute value is always included in the wafer and the above-described epitaxial defect is caused.
[0010]
The present invention solves the above-described problems in the p / p ⁺ epitaxial wafer found by the inventors, has no epitaxial defects, has good in-plane uniformity of oxygen precipitate density, and has an excellent 1G effect. It is an object of the present invention to provide a silicon single crystal, an epitaxial wafer, and a method for producing an epitaxial wafer.
[0011]
[Means for Solving the Problems]
The inventors focused on the relationship between the thermal history received during the growth of a silicon single crystal and the defect for the purpose of preventing the occurrence of epitaxial defects, and differed in the thermal history obtained by variously changing the pulling speed of the single crystal. As a result of eagerly examining defects and the like by growing an epitaxial layer on a wafer, it was found that the rapid cooling of the temperature range of 1100 ° C. to 900 ° C. after pulling suppresses the occurrence of epitaxial defects, and completed the present invention. did.
[0012]
That is, according to the present invention, boron is added, the resistivity is 0.008 to 0.025 Ω · cm, the oxygen concentration is 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) or more, and the single crystal is used. It was cooled at a cooling rate of 3.0 ° C./min or more in a temperature range of 1100 ° C. to 900 ° C. at the time of growth, and had a property that oxidation-induced stacking faults generated during high-temperature oxidation treatment were 1 × 10 ² / cm ² or less. An epitaxial wafer characterized by being a silicon single crystal characterized by being cut out from the silicon single crystal and polished, and having an epitaxial layer formed on a main surface thereof.
[0013]
That is, the present invention relates to a silicon single crystal to which boron is added, the resistivity is 0.008 to 0.025 Ω · cm, and the oxygen concentration is 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) or more. In the step of raising and growing by the Czochralski method, the step of cooling the temperature range from 1100 ° C. to 900 ° C. after the pulling at a cooling rate of 3.0 ° C./min or more reduces oxidation-induced stacking faults generated during high-temperature oxidation treatment. A method for producing a silicon single crystal, wherein a silicon single crystal having a property of 1 × 10 ² / cm ² or less is obtained. A method for manufacturing an epitaxial wafer, comprising a step of cutting out and polishing and a step of growing an epitaxial layer on a main surface.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
The present inventors conducted an experiment to change the speed at which a silicon single crystal having a diameter of 8 inches was pulled by the Czochralski method in order to investigate the influence of the thermal history during the growth of a silicon single crystal on the occurrence of epitaxial defects. Was done.
[0015]
That is, boron is added so that the resistance value becomes 0.012 Ωcm, the straight body is grown to a length of 500 mm at a pulling speed of 1.1 mm / min, and the pulling speed is changed to 1.8 mm / min at the time of 500 mm. Then, the pressure was returned to 1.1 mm / min again at 550 mm, and the seed was grown to 1000 mm.
[0016]
The single crystal grown by the above-mentioned heat history is moved from the temperature corresponding to the distance from the melt at the start of the change of the pulling speed, that is, the temperature from the solid-liquid interface to the low temperature side, at the start of the change of the pulling speed of the crystal. This means that it was rapidly cooled in a temperature range of about 100 ° C.
[0017]
Samples were cut out from the portions of these single crystals, which were quenched from the respective temperatures of 1400 to 600 ° C., processed at 850 ° C. for 2 hours, mirror-polished and finished, and a 5 μm epitaxial layer was grown. An epitaxial wafer was obtained. FIG. 1 shows the results of measuring surface defects having a size of 0.09 μm or more, that is, epitaxial defects, using a surface defect inspection apparatus (SP-1 manufactured by KLA-Tencor).
[0018]
As is clear from the graph of FIG. 1 showing the relationship between the change start temperature of the pulling rate and the defect density, it was found that by rapidly cooling the temperature range from 1100 ° C. to 900 ° C., the occurrence of epitaxial defects was suppressed. . This is considered to be because the size of the Crown-in oxygen precipitation nucleus of the p ⁺ silicon single crystal wafer was reduced due to rapid cooling.
[0019]
In the present invention, the resistivity of the silicon single crystal and the epitaxial wafer is specified to be 0.008 to 0.025 Ω · cm, as described above, in order to obtain a high-speed, high-performance, high-density semiconductor device. This is because of the properties.
[0020]
Further, the oxygen concentration of the silicon single crystal and the epitaxial wafer is preferably in the range of 11 to 18 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979). When the oxygen concentration is less than 11 × 10 ¹⁷ atoms / cm ^3, it is impossible to secure the amount of oxygen precipitation necessary for obtaining a sufficient gettering effect in the wafer in the device heat treatment step. If the oxygen concentration exceeds 18 × 10 ¹⁷ atoms / cm ³ , excessive oxygen precipitation may occur, and secondary defects may be generated in the wafer due to oxygen precipitates.
[0021]
In the present invention, a silicon single crystal and an epitaxial wafer are characterized in that oxidation-induced stacking faults generated during high-temperature oxidation treatment have a property of 1 × 10 ² / cm ² or less. If oxidation-induced stacking faults exceeds 1 × 10 ^{2 /} cm 2, the generation of epitaxial defects is increased, to lead to malfunction or the like after the device fabrication, in which a 1 × 10 ^{2 /} cm 2 or less, The better the oxidation-induced stacking faults are, the better the semiconductor device is.
[0022]
The method for producing a silicon single crystal of the present invention employs a method of pulling and growing a silicon single crystal by the Czochralski method, and any known method and apparatus can be employed. In particular, in order to realize the step of cooling the temperature range of 1100 ° C. to 900 ° C. at the time of pulling at a cooling rate of 3.0 ° C./min or more, which is a feature of the present invention, a single crystal to be grown as shown in Examples It is possible to adopt a configuration and method such as arranging a heat shield material surrounding the heat shield material and further attaching a cooling cylinder to the heat shield material.
[0023]
In the present invention, the fact that the specific cooling temperature range is from 1100 ° C. to 900 ° C. is based on the knowledge of the inventor, and the cooling rate of 3.0 ° C./min or more is based on the Crown-in oxygen precipitation. This is because the size of the nucleus can be reduced and the desired epitaxial defects can be reduced, and the preferable cooling rate is from 3.0 ° C./min to 6.5 ° C./min. However, excessive cooling of the crystal increases the thermal stress during the growth of the single crystal, and may break the single crystal during the growth of the single crystal. Therefore, it is preferable to keep the temperature at 6.5 ° C./min or less.
[0024]
In the present invention, boron is added by the Czochralski method so as to have a resistivity of 0.008 to 0.025 Ω · cm to pull up and grow a silicon single crystal, and the aforementioned specific temperature range is rapidly cooled. Even when a cooling cylinder is installed on the outer periphery of the single crystal which is most effective for cooling, in order to ensure a cooling rate of 3.0 ° C./min or more in a temperature range of 1100 ° C. to 900 ° C., a pulling rate of the single crystal is required. Needs to be set to 0.9 mm / min or more. Further, in order to keep the cooling rate at 6.5 ° C./min or less, it is necessary to suppress the pulling rate to 1.8 mm / min or less.
[0025]
In the present invention, in order to obtain an epitaxial wafer from a silicon single crystal having an oxidation-induced stacking fault of 1 × 10 ² / cm ² or less, which is generated during the high-temperature oxidation treatment obtained by the above-described method, at least the single crystal is required. It is necessary to go through a step of cutting and polishing a wafer and a step of growing an epitaxial layer on the main surface. There is no particular limitation on a method of cutting into a wafer, a method of polishing a main surface or an edge of a wafer, and a method of forming an epitaxial film, and any known method, configuration, and apparatus can be adopted.
[0026]
In the present invention, when a wafer is cut from a single crystal in the manufacture of an epitaxial wafer and subjected to a heat treatment at a temperature of 700 ° C. or more and less than 900 ° C. for 30 minutes to 4 hours before the mirror polishing, the epitaxial wafer 1G (Intrinsic gettering) effect, which promotes the growth of small nuclei with boron (B) as nuclei that disappear at high temperatures in the epitaxial process, and remains without being eliminated by the epitaxial growth process. The object is to increase the density of oxygen extract and to improve the gettering effect. This heat treatment is performed before mirror polishing in order not to leave scratches or the like from the holding jig during the heat treatment.
[0027]
As a preferable heat treatment condition, by performing in a mixed atmosphere of oxygen and an inert gas, a protective oxide film can be formed to prevent contamination of the wafer, and the oxide film can be removed by mirror polishing in a later step, In addition, it is desirable that such a heat treatment be performed before the mirror polishing because the scratches and the like from the holding jig during the heat treatment can be removed by mirror polishing.
[0028]
【Example】
FIG. 2 shows a configuration example of a silicon single crystal growing apparatus. More specifically, a crucible 1 is arranged at a center position of the apparatus, and the crucible 1 includes a quartz container 1a and a graphite container 1b arranged outside the container 1a.
[0029]
A heater 2 is arranged concentrically around the outer periphery of the crucible 1, and a melt 3 melted by the heater is accommodated in the crucible 1. Above the crucible 1, a pulling shaft 4 is attached to the seed crystal 5 so as to be rotatable and vertically movable with the seed crystal 5 mounted thereon, and a single crystal 6 can be grown from the lower end of the seed crystal 5. A heat shield material 7 is arranged so as to surround the single crystal 6 grown with the rise of 4.
[0030]
Comparative Example 1
Using the silicon single crystal growing apparatus of FIG. 2 described above, a single crystal having a diameter of 8 inches, a p-type (100), an oxygen concentration of 13 × 10 ¹⁷ atoms / cm ³ , and 0.015 Ω · cm to 0.012 Ω · cm. Was grown at a pulling rate of 1.2 mm / min. A wafer was cut out from the grown silicon single crystal and mirror-polished (Example No. 1), and a wafer subjected to a heat treatment of holding at 850 ° C. for 1 hour before the mirror-polishing step (Example No. 2). ) And prepared.
[0031]
On the two kinds of wafers, a hydrogen bake was performed at 1150 ° C. for 1 minute using an epitaxial film forming apparatus, and then an epitaxial layer was grown to a thickness of 5 μm at a deposition temperature of 1075 ° C. Surface defects (epitaxial defects) having a size of 0.09 μm or more were counted on the obtained epitaxial wafer using a surface defect inspection apparatus (manufactured by KLA-Tencor; SP-1).
[0032]
Next, these epitaxial wafers are subjected to a heat treatment at 1000 ° C. for 16 hours to cleave the wafers, selectively etched with a light etchant for 5 minutes, counted the etching pit density with an optical microscope, The density of oxygen precipitate (BMD) formed in the wafer was determined. Table 1 shows the measurement results.
[0033]
The number of epitaxial defects in Table 1 indicates the total number of 25 epitaxial wafers measured. The cooling rate in the temperature range of 1100 ° C. to 900 ° C. is 3.0 ° C./min or less. 1 and No. In No. 2, the number of epitaxial defects is large. No. In Run No. 2, the heat treatment was not performed before the epitaxial film formation. Although BMD density higher than that of No. 1 was obtained, epitaxial defects occurred frequently.
[0034]
Example 1
As shown in FIG. 3, in the silicon single crystal growing apparatus shown in FIG. 2, a cooling cylinder 8 is incorporated inside the heat shielding material 7 and a temperature range of 1100 ° C. to 900 ° C. of a single crystal pulled up by circulating a cooling liquid. As in Comparative Example 1, silicon having a diameter of 8 inches, a p-type (100), an oxygen concentration of 13 × 10 ¹⁷ atoms / cm ³ , 0.015 Ωcm to 0.012 Ωcm as in Comparative Example 1. Single crystals were grown at various pulling rates.
[0035]
Wafers were cut out from a silicon single crystal grown at a pulling rate of 0.9 to 1.35 mm / min and mirror-polished (Example Nos. 3 to 5). A heat-treated wafer held at 850 ° C. for 1 hour (No. 6 to No. 8) was prepared.
[0036]
On the two kinds of wafers, a hydrogen bake was performed at 1150 ° C. for 1 minute using an epitaxial film forming apparatus, and then an epitaxial layer was grown to a thickness of 5 μm at a deposition temperature of 1075 ° C. Surface defects (epitaxial defects) having a size of 0.09 μm or more were counted on the obtained epitaxial wafer using a surface defect inspection apparatus (manufactured by KLA-Tencor; SP-1).
[0037]
Next, these epitaxial wafers are subjected to a heat treatment at 1000 ° C. for 16 hours to cleave the wafers, selectively etched with a light etchant for 5 minutes, counted the etching pit density with an optical microscope, The BMD density formed in the wafer was determined. Table 1 shows the measurement results.
[0038]
In the embodiment of the present invention in which the cooling rate in the temperature range of 1100 ° C. to 900 ° C. is 3.0 ° C./min or more (No. 3 to No. 8), the cooling rate is 3.0 ° C./min or less. It can be seen that the epitaxial defects are lower than those of the samples (Examples No. 1 and No. 2), and the generation thereof is suppressed. In addition, Example No. in which heat treatment was performed before the epitaxial film formation. 3-No. Also in No. 5, the number of epitaxial defects was suppressed low.
[0039]
In addition, a wafer grown at a cooling rate of 1100 ° C. to 900 ° C. at a rate of 3.0 ° C./min or more is subjected to an epitaxial pretreatment, so that the BMD density effective for gettering is high and p / It can be seen that a p ⁺ epitaxial wafer can be manufactured.
[0040]
In the embodiment of the present invention in which the thermal history is optimized as described above, a single crystal can be grown at a pulling rate of 0.9 mm / min or more, and high quality p / p ⁺ can be obtained without lowering the productivity of the single crystal production. An epitaxial wafer can be manufactured.
[0041]
Example 2
Furthermore, the execution No. The same sample wafers as the silicon wafers prepared in 1 to 8 were prepared, and to each sample wafer before the epitaxial growth treatment, the extent to which oxidation-induced stacking faults occurred when subjected to high-temperature oxidation treatment was investigated.
[0042]
The experimental conditions were as follows: each sample wafer was subjected to a heat treatment at a temperature of 1100 ° C. for 16 hours in an oxidizing atmosphere, the wafer surface was etched using a light etching solution at 5 μm, and then the wafer surface was observed at a plurality of points with an optical microscope. The number of pits (oxidation-induced stacking fault density) observed at each observation point was counted to measure the density at each observation point. Table 1 shows the measurement results. In the table, the oxide stacking fault density indicates the maximum value obtained at each of the observed points. Also, <1 × 10 ² in the table indicates the lower limit of detection in the measurement.
[0043]
As is clear from Table 1, in Examples of the present invention (Examples Nos. 3 to 8), no crystal region in which oxidation-induced stacking faults exceed 1 × 10 ² / cm ² is observed in the wafer plane. On the other hand, in Comparative Examples (Examples Nos. 1 and 2), a crystal region having an oxidation-induced layer defect exceeding 1 × 10 ² / cm ² was observed in the wafer surface. This means that the amount of oxidation-induced stacking faults greatly affects the amount of epitaxial faults generated.
[0044]
[Table 1]

[0045]
【The invention's effect】
According to the present invention, the pulling speed can be increased when growing a silicon single crystal, without lowering the productivity of single crystal production, and by optimizing the thermal history at the time of growing, the desired epitaxial growth after wafering can be achieved. The number of defects is reduced, the in-plane uniformity of the oxygen precipitate density is good and a high gettering ability can be provided, and the p / p ⁺ epitaxial layer having a resistivity of 0.008 to 0.025 Ω · cm is more stably provided. A wafer can be provided.
[Brief description of the drawings]
FIG. 1 is a graph showing the relationship between the epitaxial defect density and the temperature at the start of the pulling rate change when the pulling rate in the middle of the process is changed by the CZ method.
FIG. 2 is an explanatory diagram showing a schematic configuration of a silicon single crystal growing apparatus.
FIG. 3 is an explanatory view showing a configuration in which a cooling means is incorporated in the heat shield material of FIG. 2;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Crucible 1a Quartz container 1b Graphite container 2 Heater 3 Melt 4 Pull-up shaft 5 Seed crystal 6 Single crystal 7 Heat shield material 8 Cooling cylinder

Claims (7)

Boron is added, the resistivity is 0.008 to 0.025 Ω · cm, the oxygen concentration is 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) or more, and the temperature is from 1100 ° C. to 900 when growing a single crystal. A silicon single crystal having the property of being cooled at a cooling rate of 3.0 ° C./min or more at a temperature of 30 ° C. and having an oxidation-induced stacking fault of 1 × 10 ² / cm ² or less generated during high-temperature oxidation treatment. Boron is added, the resistivity is 0.008 to 0.025 Ω · cm, the oxygen concentration is 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) or more, and the temperature is from 1100 ° C. to 900 when growing a single crystal. An oxidation-induced stacking fault generated during a high-temperature oxidation treatment at a temperature range of 3.0 ° C./min at a cooling rate of 3.0 ° C./min or more is cut out from a silicon single crystal having a property of 1 × 10 ² / cm ² or less. Epitaxial wafer with a polished wafer and an epitaxial layer deposited on its main surface. A silicon single crystal to which boron is added, the resistivity is 0.008 to 0.025 Ω · cm, and the oxygen concentration is not less than 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) is pulled up by the Czochralski method. In the growing step, the temperature range of 1100 ° C. to 900 ° C. after the pulling is cooled at a cooling rate of 3.0 ° C./min or more, so that oxidation-induced stacking faults generated during high-temperature oxidation treatment are 1 × 10 ² / cm. ^A method for producing a silicon single crystal for obtaining a silicon single crystal having properties of ² or less. The method for producing a silicon single crystal according to claim 3, wherein the pulling speed of the silicon single crystal is 0.9 mm / min or more. A silicon single crystal to which boron is added, the resistivity is 0.008 to 0.025 Ω · cm, and the oxygen concentration is not less than 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) is pulled up by the Czochralski method. In the growing step, the temperature range from 1100 ° C. to 900 ° C. after the pulling is cooled at a cooling rate of 3.0 ° C./min or more, so that oxidation-induced stacking faults generated during high-temperature oxidation treatment are 1 × 10 ² / cm ^2. A method for producing an epitaxial wafer, comprising the steps of obtaining a silicon single crystal having the following properties, cutting and polishing a wafer from the single crystal, and growing an epitaxial layer on the main surface of the wafer. The method for producing an epitaxial wafer according to claim 5, wherein a pulling speed of the silicon single crystal is 0.9 mm / min or more. The method for producing an epitaxial wafer according to claim 5, wherein after the wafer is cut out of the single crystal and before the mirror polishing, a heat treatment is performed at a temperature of 700C or more and less than 900C for 30 minutes to 4 hours.

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