JP2004088742A - Offset control circuit and signal processing device - Google Patents

Abstract

Provided is an offset control circuit capable of high-speed operation, preventing a decrease in signal quality due to deterioration in distortion characteristics, and performing offset adjustment with high accuracy.
A voltage-current converter generates a differential current (I +, I−) proportional to a potential difference between differential input voltage signals (VIN +, VIN−), and an offset adjustment current generator 11 generates an offset adjustment current ( Iofs +, Iofs−), and a current (Ir) proportional to the potential difference between the differential terminals 107 and 108 flows in the current-voltage converter 12. The differential current output terminals 105 and 106, the offset adjustment current output terminals 101 and 102, and the differential terminals 107 and 108 are connected. An offset component included in the differential input voltage signal (VIN +, VIN−) is adjusted by an offset adjustment current (Iofs +, Iofs−), and a differential obtained by adding an offset component to the differential input voltage signal (VIN +, VIN−). Output voltage signals (VO +, VO-) are generated.
[Selection diagram] FIG.

Description

となる。前記差動入出力電流Ｉｒは、前記（式１）、前記（式２）及び前記（式５）から、

となる。
【００４６】
従って、差動電圧出力端子１１６及び１１５から出力される差動出力電圧（ＶＯ＋−　ＶＯ−）は、電流電圧変換部１２の変換係数をＲとすると、

となる。
【００４７】
次に、差動電圧入力端子１０９及び１１０から各々入力される差動入力電圧信号ＶＩＮ＋及びＶＩＮ−にオフセット電圧が含まれている場合を考える。差動入力電圧ＶＩＮ＋及びＶＩＮ−のオフセット電圧を各々Ｖｏｆｆとすると、電圧電流変換部１０から出力される差動出力電流Ｉ＋及びＩ−は各々、
Ｉ＋　＝　Ｇｍ　×　（　ＶＩＮ＋　＋　Ｖｏｆｆ）　　　　　　　　　　　　　　　（式１０）
Ｉ−　＝　Ｇｍ　×　（　ＶＩＮ−　−　Ｖｏｆｆ）　　　　　　　　　　　　　　　　　　（式１１）
となる。
【００４８】
従って、オフセット制御回路１において、電流電圧変換部１２内に流れる差動入出力電流のＩｒは、前記（式６）、前記（式１０）及び前記（式１１）から、

となる。これにより、差動出力電圧（ＶＯ＋　−　ＶＯ−）は、

となる。
【００４９】
前記（式１３）から、オフセット制御回路１の差動出力電圧ＶＯ＋及びＶＯ−については、差動入力電圧ＶＩＮ＋及びＶＩＮ−のオフセット電流（Ｇｍ×Ｖｏｆｆ）が、オフセット調整電流Ｉｏｆｓ＋及びＩｏｆｓ−により調整されていることが判る。
【００５０】
以上のように、本実施の形態によれば、差動信号処理を基本とするため、入力電圧とオフセット電圧の加算に従来のような演算増幅器２０１を必要としない。更に、入力電圧に対するオフセット電圧の加算は、入力電圧、オフセット電圧を各々電流に変換した後に、キルヒホッフの法則に基づいた簡単な構成の電流加算によって実現されるので、非常に高速にオフセット電圧の調整を行うことができる。
【００５１】
また、従来の演算増幅器２０１を用いたオフセット加算方式では、演算増幅器２０１の帯域を入力信号帯域よりも１桁〜２桁程度高くする必要があり、回路規模の増加、消費電力の増加、処理速度上限の低下などが問題となるが、本第１の実施の形態によれば、キルヒホッフの法則に基づいて電流を加算するだけという簡単な構成により、回路規模をより縮小できると共に、より高速なオフセット加算処理を行うことができる。
【００５２】
更に、本実施の形態のオフセット制御回路１は、差動信号処理を基本とするため、ノイズに強く、また、信号の歪みも生じ難い。従来のオフセット制御回路２００を用いた場合でも、オフセット制御回路２００を２系統設けることにより、差動信号処理を行うことができるが、これには２倍の回路規模と消費電力とが必要である。これに対して、本実施の形態のオフセット制御回路１では、より縮小された回路規模でもって、差動信号を用いたオフセット調整処理を行うことが可能である。
【００５３】
尚、本実施の形態では、オフセット制御回路１を含むフロントエンド５０、バックエンド６０及びシステムコントローラ７０を１チップ化したが、オフセット制御回路１を含むフロントエンド５０のみを１チップ化しても良いのは勿論である。
【００５４】
また、本実施の形態では、ＤＶＤ信号再生処理システムに備えるオフセット制御回路１について説明したが、本発明はこれに限定されず、ＤＶＤ信号再生処理システムに以外に備えるオフセット制御回路についても同様に適用できるのは勿論である。この場合には、オフセット制御回路と、このオフセット制御回路によりオフセット電圧を調整された差動出力電圧について所定の処理を行う処理回路とを１チップ化すれば良い。
【００５５】
（第２の実施の形態）
本第２の実施の形態では、電圧電流変換部１０の一具体例として電圧電流変換回路１０Ａを用いてオフセット制御回路２を実現する場合である。
【００５６】
図４は、図３の電圧電流変換部１０の一具体例を示す回路図である。
【００５７】
図４において、電圧電流変換部１０Ａは、一対のバイアス電流源３０１及び３０２と、これらに各々接続された一対のＮ型の第１トランジスタＭ３及びＭ４と、これらに各々接続された一対のＮ型の第２トランジスタＭ１及びＭ２とを有している。
【００５８】
バイアス電流源３０１及び３０２は各々、差動電流出力端子１０５及び１０６に各々接続されており、バイアス電流Ｉｂが各々流れるようになっている。
【００５９】
第１トランジスタＭ３及びＭ４は各々の各ゲートが制御端子１１１と共通接続されており、その各ゲートに制御電圧Ｖｂｉａｓが入力される。また、第１トランジスタＭ３及びＭ４は、各々各ドレインが差動電流出力端子１０５及び１０６に各々接続されており、差動電流出力端子１０５及び１０６から各々差動電流Ｉ＋及びＩ−が各々出力される。
【００６０】
前記Ｎ型の第２トランジスタＭ１及びＭ２は、各々の各ゲートが差動電圧入力端子１０９及び１１０に各々接続されており、差動入力電圧信号ＶＩＮ＋及びＶＩＮ−が各々入力される。また、前記Ｎ型の第２トランジスタＭ１及びＭ２は、各々の各ドレインが第１トランジスタＭ３及びＭ４の各ソースに各々接続され、各ソースが各々接地されている。
【００６１】
前記構成により、電圧電流変換回路１０Ａにおいて、Ｎ型の第１トランジスタＭ３及びＭ４は各々ソースフォロワ回路として動作し、その各ゲートに制御電圧Ｖｂｉａｓが各々入力され、Ｎ型の各第１トランジスタＭ３及びＭ４によって、しきい値電圧Ｖｔｈ分程度低くなった各電圧が各ソースから各々出力される。これによって、Ｎ型の第２トランジスタＭ１及びＭ２の各ドレイン電圧が一定に保たれ、Ｎ型の第２トランジスタＭ１及びＭ２のドレイン−ソース間電圧Ｖｄｓはほぼ一定に保たれる。
【００６２】
Ｎ型の第２トランジスタＭ１及びＭ２は、各々、非飽和領域で動作するようにバイアスされている。このとき、Ｎ型の両第２トランジスタＭ１及びＭ２に流れるドレイン電流ＩＤＳ１及びＩＤＳ２は各々、

（但し、βは第２トランジスタＭ１及びＭ２のトランスコンダクタンス、ＶｄｓはＮ型の第２トランジスタＭ１及びＭ２のドレイン−ソース間電圧とする。）
と表される。
【００６３】
ここで、本第２の実施の形態の電圧電流変換部１０Ａにおいて、差動出力電流（Ｉ＋　−　Ｉ−）はＩＤＳ１−ＩＤＳ２に等しく、この差動出力電流が電流電圧変換部１２に流れ込む。従って、

となる。
【００６４】
前記（式１６）から、差動出力電流Ｉ＋　−　Ｉ−は差動入力電圧ＶＩＮ＋　−　ＶＩＮ−に比例し、その比例係数（変換係数）Ｇｍはβ×Ｖｄｓとなることが判る。
【００６５】
以上のように、本第２の実施の形態の電圧電流変換回路１０Ａは、差動電圧電流変換回路として動作する。よって、これを図３の電圧電流変換部１０に適用することによって、本第２の実施の形態のオフセット制御回路２を実現することができる。この電圧電流変換回路１０Ａは、Ｎ型の第２トランジスタＭ１及びＭ２が非飽和領域で動作するようにバイアスすることにより、信号の歪みを少なくすることができ、この電圧電流変換回路１０Ａを用いてオフセット制御回路２を構成することによって、より歪み特性の劣化を防ぐことができる。尚、電圧電流変換部１０を図４に示すような回路構成としても、前記第１の実施の形態で説明したように、オフセット制御回路１における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【００６６】
また、本第２の実施の形態の電圧電流変換回路１０Ａでは、制御電圧Ｖｂｉａｓを調整することによって、前記（式１３）において変換係数Ｇｍを調整することができる。これは、前記（式１３）における入出力電圧比、即ち、差動入力電圧ＶＩＮ＋及びＶＩＮ−の係数である（１／２）×Ｒ×Ｇｍを制御できるということを意味する。従って、本第２の実施の形態のオフセット制御回路２は、オフセット調整機能のみならず、信号の増幅率を変化させる可変増幅器としても機能させることができる。
【００６７】
更に、本第２の実施の形態の電圧電流変換回路１０Ａにおいて、Ｎ型の第２トランジスタＭ１及びＭ２のドレイン電圧をより精度よく固定することもできる。例えば、Ｎ型の第２トランジスタＭ１及びＭ２のドレイン電圧が一定となるように、オペアンプ（演算増幅器）を用いてＮ型の第１トランジスタＭ３及びＭ４のゲート電圧を制御することもできる。この場合に用いられるオペアンプは、必ずしも高精度である必要はないため、オペアンプの帯域が信号帯域の１０倍程度であっても充分である。このようにＮ型の第１トランジスタＭ３及びＭ４のゲート電圧を制御するためのオペアンプを設けた構成としても、前記第１の実施の形態で説明したように、オフセット制御回路１における高速動作及び小面積化が可能であるという効果は何ら失１われることはない。
【００６８】
（第３の実施の形態）
本第３の実施の形態では、前記第２の実施の形態のオフセット制御回路２における信号の歪みを更に低減する場合である。
【００６９】
図５は、本発明のオフセット制御回路の第３の実施の形態における構成例を示す回路図である。
【００７０】
図５において、オフセット制御回路３は、前記第２の実施の形態のオフセット制御回路２において、オフセット調整電流生成部１１のオフセット調整電流出力端子１０１及び１０２が、各々、電圧電流変換部１０のＮ型の第１トランジスタＭ３及びＭ４のドレインではなく、Ｎ型の第２トランジスタＭ１及びＭ２のドレインに各々接続されることによって、前記第２の実施の形態のオフセット制御回路２における信号の歪みを更に低減することができる。
【００７１】
前記構成により、本第３の実施の形態のオフセット制御回路３について、差動入力電圧信号ＶＩＮ＋及びＶＩＮ−にオフセット電圧が含まれており、このオフセット電圧を除去するようにオフセット制御回路を動作させる場合について、前記実施形態１，２のオフセット制御回路１，２と比較してその動作を説明する。
【００７２】
前記第１及び第２の実施の形態のオフセット制御回路１、２では、Ｎ型の第２トランジスタＭ１及びＭ２、Ｎ型の第１トランジスタＭ３及びＭ４が対称回路であるにも拘わらず、差動入力電圧信号ＶＩＮ＋とＶＩＮ−との間にオフセット電圧が重畳しているため、各々の回路に異なるバイアス電流が流れる。このような電流の非対称性は、Ｎ型の第１トランジスタＭ３及びＭ４のドレインにおいて、オフセット調整電流生成部１１からオフセット電圧（オフセット成分）を相殺するオフセット調整電流Ｉｏｆｓ＋及びＩｏｆｓ−が各々加算されることによって相殺されるものの、Ｎ型の第２トランジスタＭ１及びＭ２、Ｎ型の第１トランジスタＭ３及びＭ４が非対称な状態で動作するために、信号の歪みが発生し易い。
【００７３】
一方、本第３の実施の形態のオフセット制御回路３では、オフセット調整電流生成部１１からのオフセット調整電流Ｉｏｆｓ＋及びＩｏｆｓ−がＮ型の第２トランジスタＭ１及びＭ２のドレインにおいて差動出力電流Ｉ＋及びＩ−に加算されるため、この時点で電流の非対称性が解消され、Ｎ型の第１トランジスタＭ３及びＭ４はバイアス電流Ｉ＋’及びＩ−’についても対称な差動回路として動作する。これによって、本第３の実施の形態のオフセット制御回路３によれば、前記第１及び第２の実施の形態のオフセット制御回路１、２に比べて、Ｎ型の第１トランジスタＭ３及びＭ４で発生する信号の歪みをより小さく抑えることができる。
【００７４】
更に、本第３の実施の形態のオフセット制御回路３では、Ｎ型の第２トランジスタＭ１及びＭ２は非対称な状態で動作するものの、非飽和領域で動作しているために、バイアス電流値が異なっていても、ソース−ドレイン間の電圧Ｖｄｓが同じであれば、電圧電流特性はほとんど変わらない。従って、オフセット制御回路３全体で発生する信号の歪みは、前記第１及び第２の実施の形態に比べて、更に大きく低減させることが可能である。
【００７５】
尚、オフセット制御回路３を図５に示すような回路構成としても、前記第１の実施形態で説明したように、オフセット制御回路１における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【００７６】
（第４の実施の形態）
本第４の実施の形態では、電圧電流変換部１０の他の具体例として電圧電流変換回路１０Ｃを用いて、入出力ゲインを抵抗比によって制御するオフセット制御回路４を実現する場合である。
【００７７】
図６は、図３の電圧電流変換部１０における他の具体例を示す回路図である。
【００７８】
図６において、電圧電流変換回路１０Ｃは、一対のバイアス電流源３０１及び３０２、一対のＮ型の第１トランジスタＭ７及びＭ８、一対のＮ型の第２トランジスタＭ５及びＭ６が各々設けられており、バイアス電流源３０１、Ｎ型の第１トランジスタＭ７及び第２トランジスタＭ５の直列回路とバイアス電流源３０２、Ｎ型の第１トランジスタＭ８及び第２トランジスタＭ６の直列回路とが２系列配設されている。また、Ｎ型の第１トランジスタＭ７及び第２トランジスタＭ５の接続点と、Ｎ型の第１トランジスタＭ８及び第２トランジスタＭ６の接続点との間に抵抗器Ｒ３が配設されている。
【００７９】
バイアス電流源３０１及び３０２は各々差動電流出力端子１０５及び１０６と各々接続されており、バイアス電流Ｉｂが各々流れるようになっている。
【００８０】
Ｎ型の第１トランジスタＭ７及びＭ８の各ゲートは各々差動電圧入力端子１０９及び１１０に各々接続されており、差動電圧入力端子１０９及び１１０に差動入力電圧ＶＩＮ＋及びＶＩＮ−が各々入力される。また、Ｎ型の第１トランジスタＭ７及びＭ８は各々その各ドレインが差動電流出力端子１０５及び１０６に各々接続され、その各ソース間に抵抗器Ｒ３が接続されている。
【００８１】
Ｎ型の第２トランジスタＭ５及びＭ６の各ゲートが制御端子１１１と共通接続されており、その制御端子１１１に制御電圧Ｖｂｉａｓが入力される。また、Ｎ型の第２トランジスタＭ５及びＭ６の各ドレインはＮ型の第１トランジスタＭ７及びＭ８の各ソースに各々接続され、その各ソースは各々接地されている。
【００８２】
以上のように構成された本第４の実施の形態の電圧電流変換回路１０Ｃにおいて、Ｎ型の第１トランジスタＭ７及びＭ８は各々ソースフォロワ回路として動作し、Ｎ型の第１トランジスタＭ７及びＭ８の各ゲートに入力される差動入力電圧信号ＶＩＮ＋及びＶＩＮ−に基づいて、しきい値電圧Ｖｔｈ分程度低くなった電圧が各ソースから各々出力されて抵抗器Ｒ３の両端に印加される。これによって、抵抗器Ｒ３には、（ＶＩＮ＋　−　ＶＩＮ−）の電位差が発生し、オームの法則により、（ＶＩＮ＋　−　ＶＩＮ−）／Ｒ３の電流が発生する。
【００８３】
従って、本第４の実施の形態の電圧電流変換回路１０Ｃにおける電流変換係数Ｇｍは、およそ１／Ｒ３となり、差動出力電流（ＶＩＮ＋−　ＶＩＮ−）／Ｒ３がＮ型の第１トランジスタＭ７及びＭ８を介して差動電流出力端子１０５及び１０６から出力される。Ｎ型の第２トランジスタＭ５及びＭ６は、Ｎ型の第１トランジスタＭ７及びＭ８に各々バイアス電流を与えるための回路として動作する。
【００８４】
以上のように、本第４の実施の形態の電圧電流変換回路１０Ｃは、差動電圧電流変換回路として動作する。これを図３に示す電圧電流変換部１０に適用することによって、オフセット制御回路４を実現することができる。この電圧電流変換部１０は、電流電圧係数Ｇｍがおよそ１／Ｒ３であるため、オフセット制御回路４として動作させた場合の入出力電圧比、即ち、前記（式１３）における差動入力電圧信号ＶＩＮ＋及びＶＩＮ−の変換係数である（１／２）×Ｇｍ×Ｒが、（１／２）×（Ｒ／Ｒ３）となり、電流電圧変換部１２の抵抗（変換係数）Ｒと、電圧電流変換部１０の抵抗Ｒ３との比で決定されることが判る。従って、本実施形態４のオフセット制御回路４は、入出力ゲインを抵抗比によって制御することができる。
【００８５】
尚、電圧電流変換部１０を図６に示すような回路構成としても、前記実施形態１で説明したように、オフセット制御回路１における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【００８６】
また、本第４の実施の形態の電圧電流変換回路１０Ｃにおいて、Ｎ型の第１トランジスタＭ７及びＭ８のソース電位がＮ型の第１トランジスタＭ７及びＭ８のゲート電位に一致するように、オペアンプを用いてフィードバックをかけることもできる。これによって、信号の歪みを更に低減し、抵抗値による入出力ゲインの設定精度を高くすることができる。このようにＮ型の第１トランジスタＭ７及びＭ８のゲート電位及びソース電位を制御するためのオペアンプを設けた構成としても、前記実施形態１で説明したように、オフセット制御回路１における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【００８７】
（第５の実施の形態）
本第５の実施の形態では、電圧電流変換部１０の更に他の具体例として電圧電流変換回路１０Ｄを用いて、極めて高速に動作させることができるオフセット制御回路５を実現する場合である。
【００８８】
図７は、図３の電圧電流変換部１０における更に他の具体例を示す回路図である。
【００８９】
図７において、電圧電流変換回路１０Ｄは、一対のバイアス電流源３０１及び３０２、Ｎ型の一対のトランジスタＭ９及びＭ１０が各々設けられており、バイアス電流源３０１とＮ型のトランジスタＭ９の直列回路とバイアス電流源３０２とＮ型のトランジスタＭ１０の直列回路とが２系列配設されている。
【００９０】
バイアス電流源３０１及び３０２は各々、差動電流出力端子１０５及び１０６に各々接続されており、バイアス電流Ｉｂが各々流れるようになっている。
【００９１】
Ｎ型のトランジスタＭ９及びＭ１０の各ゲートは各々差動電圧入力端子１０９及び１１０に各々接続されており、各差動電圧入力端子１０９及び１１０に差動入力電圧ＶＩＮ＋及びＶＩＮ−が各々入力される。また、Ｎ型のトランジスタＭ９及びＭ１０の各ドレインは各々差動電流出力端子１０５及び１０６に各々接続され、Ｎ型のトランジスタＭ９及びＭ１０の各ソースは各々接地されている。
【００９２】
このように構成された本第５の実施の形態の電圧電流変換回路１０Ｄにおいては、Ｎ型のトランジスタＭ９及びＭ１０の電圧電流変換特性に応じて、その各ゲートに各々入力される各差動入力電圧（ＶＩＮ＋−　ＶＩＮ−）が電流に変換されて、各差動電流（Ｉ＋　−　Ｉ−）として差動電流出力端子１０５及び１０６から各々出力される。
【００９３】
以上のように、本第５の実施の形態の電圧電流変換回路１０Ｄは差動電圧電流変換回路として動作する。従って、これを図３に示す電圧電流変換部１０として適用させることによって、本第５の実施の形態のオフセット制御回路５を実現することができる。この電圧電流変換回路１０Ｄは、差動電圧入力端子１０９及び１１０と差動電流出力端子１０５及び１０６との各間には各々、Ｎ型のトランジスタＭ９及びＭ１０が存在するだけであるため、極めて高速に動作させることができる。従って、本第５の実施の形態のオフセット制御回路５は、極めて高速に動作させることができる。尚、図３に示す電圧電流変換部１０を図７に示すような回路構成としても、前記第１の実施の形態で説明したように、オフセット制御回路１における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【００９４】
（第６の実施の形態）
本第６の実施の形態では、電流電圧変換部１２の一具体例として電流電圧変換回路１２Ａを用いて、オフセット制御回路６を実現する場合である。
【００９５】
図８は、図３の電流電圧変換部１２における一具体例を示す回路図である。
【００９６】
図８において、電流電圧変換回路１２Ａは差動端子１０７及び１０８間に抵抗器Ｒ４が設けられている。
【００９７】
このように構成された本第６の実施の形態の電流電圧変換回路１２Ａにおいて、抵抗器Ｒ４は、その抵抗器Ｒ４に流れる電流（差動入出力電流Ｉｒ）に比例する電圧をその両端子（差動端子）１０７及び１０８間に発生させることができる。従って、これを図３に示す電流電圧変換部１２として適用することによって、本第６の実施の形態のオフセット制御回路６を実現することができる。
【００９８】
尚、図３（又は図５）の電流電圧変換部１２を図８に示すような構成としても、前記第１の実施の形態（又は前記第３の実施の形態）で説明したように、オフセット制御回路１，３における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【００９９】
（第７の実施の形態）
本第７の実施の形態では、電流電圧変換部１２の他の具体例として電流電圧変換回路１２Ｂを用いて、オフセット制御回路７を実現する場合である。
【０１００】
図９は、図３の電流電圧変換部１２における他の具体例を示す回路図である。
【０１０１】
図９において、電流電圧変換回路１２Ｂは、一対の差動端子１０７及び１０８、一対のＮ型の第１トランジスタＭ１３及びＭ１４、一対のＮ型の第２トランジスタＭ１１及びＭ１２が各々設けられている。
【０１０２】
これらの差動端子１０７、Ｎ型の第１トランジスタＭ１３及びＮ型の第２トランジスタＭ１１と、差動端子１０８、Ｎ型の第１トランジスタＭ１４及び第２トランジスタＭ１２とは各々直列に接続されている。また、Ｎ型の第１トランジスタＭ１３及びＭ１４の各ゲートは、入出力電流制御端子１１２に共通接続されており、入出力電流制御端子１１２に制御電圧Ｖｂｉａｓ２が入力される。また、Ｎ型の第２トランジスタＭ１１及びＭ１２の各ゲートは各々、差動端子１０７及び１０８に各々接続されており、差動入出力電流Ｉｒに比例した電圧が差動端子１０７及び１０８に印加される。
【０１０３】
このように構成された本第７の実施の形態の電流電圧変換回路１２Ｂにおいて、Ｎ型の第１トランジスタＭ１３及びＭ１４、Ｎ型の第２トランジスタＭ１１及びＭ１２の動作は、図５に示す電圧電流変換部１０Ｂの第１トランジスタＭ３及びＭ４、第２トランジスタＭ１及びＭ２と同様に動作する。即ち、Ｎ型の第１トランジスタＭ１３及びＭ１４は各々ソースフォロワ回路として動作し、Ｎ型の第１トランジスタＭ１３及びＭ１４の各ゲートに入力される制御電圧Ｖｂｉａｓ２に基づいて、しきい値電圧Ｖｔｈ分程度低くなった電圧が各ソースから出力される。これによって、Ｎ型の第２トランジスタＭ１１及びＭ１２のドレイン電圧が一定に保たれ、Ｎ型の第２トランジスタＭ１１及びＭ１２のドレイン−ソース間電圧Ｖｄｓはほぼ一定に保たれる。
【０１０４】
Ｎ型の第２トランジスタＭ１１及びＭ１２は各々非飽和領域で動作するようにバイアスされており、その各ゲートに印加された電圧に比例した電流が差動端子１０７及び１０８から入出力される。
【０１０５】
従って、本第７の実施の形態の電流電圧変換部１２は、差動端子１０７及び１０８間に印加される電圧に比例する差動入出力電流Ｉｒを差動端子１０７及び１０８から入出力するように動作し、換言すると、差動端子１０７及び１０８に入出力される差動入出力電流に比例した電圧を差動端子１０７及び１０８間に発生させるように動作する。
【０１０６】
以上のように、本第７の実施の形態の電流電圧変換回路１２Ｂは差動電流電圧変換回路として動作する。従って、これを図３（又は図５）に示す電流電圧変換部１２に適用することによって、オフセット制御回路７を実現することができる。本第７の実施の形態の電流電圧変換回路１２Ｂでは、制御電圧Ｖｂｉａｓ２を調整することによって、前記（式１３）における電流電圧変換係数Ｒを調整することができる。よって、本第７の実施の形態のオフセット制御回路７は、オフセット調整機能のみならず、信号の増幅率を変化させることができる可変増幅器としても機能させることができる。尚、図３（又は図５）に示す電流電圧変換部１２を図９に示すような回路構成としても、前記第１の実施の形態（又は前記第３の実施の形態）で説明したように、オフセット制御回路１，３における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【０１０７】
（第８の実施の形態）
本第８の実施の形態では、電流電圧変換部１２の更に他の具体例として電流電圧変換回路１２Ｃを用いて、オフセット制御回路８を実現する場合である。
【０１０８】
図１０は、図３の電流電圧変換部１２における更に他の具体例を示す回路図である。
【０１０９】
図１０において、電流電圧変換回路１２Ｃとして、差動端子１０７及び１０８間にＰ型のトランジスタＭ１５が設けられている。このＰ型のトランジスタＭ１５のゲートは、入出力電流制御端子１１２に接続されており、入出力電流制御端子１１２に制御電圧Ｖｂｉａｓ２が入力される。
【０１１０】
このように構成された本第８の実施の形態の電流電圧変換回路１２Ｃにおいて、Ｐ型のトランジスタＭ１５は、そのゲートに印加される制御電圧Ｖｂｉａｓ２に応じて抵抗値を制御可能な可変抵抗として動作する。
【０１１１】
以上のように、本第８の実施の形態の電流電圧変換回路１２Ｃは、差動電流電圧変換回路として動作する。従って、これを図３（又は図５）に示す電流電圧変換部１２に適用することによって、本第８の実施の形態のオフセット制御回路８を実現することができる。本第８の実施の形態の電流電圧変換回路１２Ｃでは、制御電圧Ｖｂｉａｓ２を調整することによって、前記（式１３）における電流電圧変換係数Ｒを調整することができる。よって、本第８の実施の形態のオフセット制御回路８は、オフセット調整機能のみならず、信号の増幅率を変化させることができる可変増幅器としても機能させることができる。尚、図３（又は図５）に示す電流電圧変換部１２を図１０に示すような回路構成としても、前記第１の実施の形態（又は前記第３の実施の形態）で説明したように、オフセット制御回路１、３における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【０１１２】
（第９の実施の形態）
本第９の実施の形態では、オフセット調整電流生成部１１の一具体例としてオフセット調整電流生成回路１１Ａを用いて、オフセット制御回路９を実現する場合である。
【０１１３】
図１１は、図３のオフセット調整電流生成部１１における一具体例を示す回路図である。
【０１１４】
図１１において、オフセット調整電流生成部１１Ａは、バイアス電流源３０７と、一対のＰ型のトランジスタＭ１６及びＭ１７と、一対のオフセット調整電流出力端子１０１及び１０２とを有している。
【０１１５】
バイアス電流源３０７は、Ｐ型のトランジスタＭ１６及びＭ１７の各ソースと各々接続されており、バイアス電流Ｉｏｆｓが２つに分岐して流れるようになっている。
【０１１６】
前記Ｐ型のトランジスタＭ１６及びＭ１７の各ゲートは、各々、オフセット調整電流制御端子１０３及び１０４に各々接続されており、オフセット調整電流制御端子１０３及び１０４にオフセット調整電流制御電圧Ｖｏｆｓ＋及びＶｏｆｓ−が各々入力される。また、Ｐ型のトランジスタＭ１６及びＭ１７の各ドレインが各々オフセット調整電流出力端子１０１及び１０２に各々接続されており、オフセット調整電流Ｉｏｆｓ＋及びＩｏｆｓ−が各々流れる。
【０１１７】
このように構成された本第９の実施の形態のオフセット調整電流生成回路１１Ａにおいて、オフセット調整電流Ｉｏｆｓ＋及びＩｏｆｓ−は、オフセット調整電流制御電圧Ｖｏｆｓ＋及びＶｏｆｓ−によって各々の電流量が調整される。
【０１１８】
このように、オフセット調整電流生成回路１１Ａを図３（又は図５）に示すオフセット調整電流生成部１１に適用することによって、本第９の実施の形態のオフセット制御回路９を実現することができる。
【０１１９】
尚、図３（又は図５）に示すオフセット調整電流生成部１１を図１１に示すような回路構成としても、前記第１の実施の形態（又は前記第３の実施の形態）で説明したように、オフセット制御回路１、３における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【０１２０】
また、本第９の実施の形態のオフセット調整電流生成回路１１Ａにおいて、バイアス電流源３０７、Ｐ型のトランジスタＭ１６及びＭ１７とは逆極性のバイアス電流源３０８及びＰ型のトランジスタＭ１８及びＭ１９を用いて、図１２に示すようなオフセット調整電流生成回路１１Ｂを構成することも可能である。この場合にも、前述したように、図３（又は図５）に示すオフセット調整電流生成部１１を図１２に示すような回路構成としても、前記第１の実施の形態（又は前記第３の実施の形態）で説明したように、オフセット制御回路１、３における高速動作及び小面積化が１可能であるという効果は何ら失われることはない。
【０１２１】
（第１０の実施の形態）
本第１０の実施の形態では、オフセット調整電流生成部１１とは別のデジタル制御可能なオフセット調整電流生成部１３を用いて、オフセット制御回路１０を実現する場合である。
【０１２２】
図１３は、図３のオフセット調整電流生成部１１とは別の構成例を示す回路図である。
【０１２３】
図１３において、オフセット調整電流生成部１３は、図３（又は図５）に示すオフセット調整電流生成部１１のオフセット調整電流制御端子１０３及び１０４の代わりに、ｎを自然数として、ｎビットのレジスタ信号から１ビットのレジスタ信号が各々入力される入力端子（オフセット調整電流制御端子）１１３−１〜１１３−ｎを有している。これらの入力端子１１３−１〜１１３−ｎから入力されるｎビットのレジスタ信号の状態によって、オフセット調整電流Ｉｏｆｓ＋及びＩｏｆｓ−を高精度に制御することができる。
【０１２４】
図１４は、図１３のオフセット調整電流生成部１３の一具体例を示す回路図である。
【０１２５】
図１４において、オフセット調整電流生成部１３Ａは、ｎ個のサブオフセット調整電流生成部１３−１〜１３−ｎを有している。サブオフセット調整電流生成部１３−１〜１３−ｎは各々、インバータ１４−１〜１４−ｎと、バイアス電流源３０９−１〜３０９−ｎと、一対のＰ型のトランジスタＭ２０−１〜Ｍ２０−ｎ及びＭ２１−１〜Ｍ２１−ｎとを有している。
【０１２６】
バイアス電流源３０９−１は、Ｐ型のトランジスタＭ２０−１及びＭ２１−１の各ソースと各々接続されており、Ｐ型のトランジスタＭ２０−１及びＭ２１−１の各ソースに２つに分岐してバイアス電流が流れる。また同様に、ｎを自然数として、バイアス電流源３０９−ｎは、Ｐ型のトランジスタＭ２０−ｎ及びＭ２１−ｎの各ソースと各々接続されており、Ｐ型のトランジスタＭ２０−ｎ及びＭ２１−ｎの各ソースに２つに分岐してバイアス電流が流れる。バイアス電流源３０９−１〜３０９−ｎは、各々の電流量に重み付けがされており、各々、Ｉｏｆｓ’、２×Ｉｏｆｓ’、・・・、ｎ×Ｉｏｆｓ’となっている。
【０１２７】
前記Ｐ型のトランジスタＭ２０−１〜Ｍ２０−ｎの各ゲートは各々、入力端子１１３−１〜１１３−ｎに各々接続されており、入力端子１１３−１〜１１３−ｎに各々１ビットのレジスタ信号が入力される。また、入力端子１１３−１〜１１３−ｎは各々、インバータ１４−１〜１４−ｎを各々介してＰ型のトランジスタＭ２１−１〜Ｍ２１−ｎの各ゲートに各々接続されており、Ｐ型のトランジスタＭ２１−１〜Ｍ２１−ｎの各ゲートに各々１ビットのレジスタ信号（オフセット調整電流制御信号）を反転させた信号が入力される。
【０１２８】
また、Ｐ型のトランジスタＭ２０−１〜Ｍ２０−ｎの各ドレインはオフセット調整電流出力端子１０１と接続されており、サブオフセット調整電流Ｉｏｆｓ（１）＋〜Ｉｏｆｓ（ｎ）＋が各々一括して流れる。また、Ｐ型のトランジスタＭ２１−１〜Ｍ２１−ｎの各ドレインはオフセット調整電流出力端子１０２と接続されており、サブオフセット調整電流Ｉｏｆｓ（１）−〜Ｉｏｆｓ（ｎ）−が各々一括して流れる。これによって、オフセット調整電流Ｉｏｆｓ＋はＩｏｆｓ（１）＋、Ｉｏｆｓ（２）＋、・・・Ｉｏｆｓ（ｎ）＋を合計した電流量となり、オフセット調整電流Ｉｏｆｓ−はＩｏｆｓ（１）−、Ｉｏｆｓ（２）−、・・・Ｉｏｆｓ（ｎ）−を合計した電流量となる。
【０１２９】
このように構成された本第１０の実施の形態のオフセット調整電流生成回路１３Ａにおいて、オフセット調整電流を制御するための制御信号であるレジスタ信号は、入力端子１１３−１〜１１３−ｎから入力される。例えば、入力端子１１３−１に入力されるレジスタ信号がＨレベルとなった場合、サブオフセット調整電流生成部１３−１では、Ｐ型のトランジスタＭ２０−１のゲートにＨレベルの信号が印加される。また、入力端子１１３−１のレジスタ信号はインバータ１４−１にて反転されてＬレベルとなるので、Ｐ型のトランジスタＭ２１−１のゲートには、Ｌレベルの信号が印加される。Ｐ型のトランジスタＭ２０−１及びＭ２１−１は共に、ゲートにＬレベルの信号が印加されたときにオン状態になるため、Ｐ型のトランジスタＭ２０−１はオフ状態になってＩｏｆｓ（１）＋は流れず、Ｐ型のトランジスタＭ２１−１はオン状態となってＩｏｆｓ（１）−が流れ出す。
【０１３０】
一方、入力端子１１３−１に入力されるレジスタ信号がＬレベルとなった場合には、Ｐ型のトランジスタＭ２０−１のゲートにＬレベルの信号が印加される。また、入力端子１１３−１のレジスタ信号はインバータ１４−１にて反転されてＨレベルとなるので、Ｐ型のトランジスタＭ２１−１のゲートには、Ｈレベルの信号が印加される。よって、Ｐ型のトランジスタＭ２０−１がオン状態となってＩｏｆｓ（１）＋が流れ出し、Ｐ型のトランジスタＭ２１−１はオフ状態となってＩｏｆｓ（１）−は流れない。
【０１３１】
このように、入力端子１１３−１に入力されるレジスタ信号の状態によって、サブオフセット調整電流生成部１３−１においてＩｏｆｓ（１）＋及びＩｏｆｓ（１）−のいずれか一方が流れる。電流Ｉｏｆｓ（１）＋及びＩｏｆｓ（１）−が流れるときの電流値は、バイアス電流Ｉｏｆｓ’に等しい。
【０１３２】
同様に、入力端子１１３−２〜１１３−ｎから入力されるレジスタ信号の状態によって、Ｐ型のトランジスタＭ２０−２〜Ｍ２０−ｎがオン／オフ制御されてＩｏｆｓ（２）＋、・・・、Ｉｏｆｓ（ｎ）＋が設定され、Ｐ型のトランジスタＭ２１−２〜Ｍ２１−ｎがオン／オフ制御されてＩｏｆｓ（２）−、・・Ｉｏｆｓ（ｎ）−が設定される。
【０１３３】
このとき、電流組（Ｉｏｆｓ（１）＋、Ｉｏｆｓ（１）−）、（Ｉｏｆｓ（２）＋、Ｉｏｆｓ（２）−）、・・・、（Ｉｏｆｓ（ｎ）＋、Ｉｏｆｓ（ｎ）−）は、いずれか一方が流れると、他方は流れないようになっている。
【０１３４】
レジスタ信号はｎビットからなり、レジスタ信号が全てＬレベルである場合（ＬＬ・・・Ｌ）からレジスタ信号が全てＨレベルである場合（ＨＨ・・・Ｈ）まで、ｎ通りのレジスタ信号がある。
【０１３５】
レジスタ信号が全てＬレベルである場合には、Ｐ型のトランジスタＭ２０−１〜Ｍ２０−ｎが全てオン状態となってオフセット調整電流Ｉｏｆｓ＋が流れ、オフセット調整電流Ｉｏｆｓ＋の電流量は最大となる。このとき、Ｐ型のトランジスタＭ２１−１〜Ｍ２１−ｎは全てオフ状態となってオフセット調整電流Ｉｏｆｓ−は流れない。
【０１３６】
また、レジスタ信号が全てＨレベルである場合には、Ｐ型のトランジスタＭ２１−１〜Ｍ２１−ｎが全てオン状態となってオフセット調整電流Ｉｏｆｓ−が流れ、オフセット調整電流Ｉｏｆｓ−の電流量は最大となる。このとき、Ｐ型のトランジスタＭ２０−１〜Ｍ２０−ｎは全てオフ状態となってオフセット調整電流Ｉｏｆｓ＋は流れない。
【０１３７】
また、レジスタ信号が全てがＬレベル又は全てＨレベルでない場合には、ｎビットのレジスタ信号のうち、Ｌレベルとなっているレジスタ信号の個数だけＰ型のトランジスタＭ２０−１〜Ｍ２０−ｎがＯＮ状態となり、それに応じてＩｏｆｓ（１）＋、Ｉｏｆｓ（２）＋、・・・、Ｉｏｆｓ（ｎ）＋が流れ出し、その合計値がオフセット調整電流Ｉｏｆｓ＋の電流値となる。また、ｎビットのレジスタ信号のうち、Ｈレベルとなっているレジスタ信号の個数だけＰ型のトランジスタＭ２１−１〜Ｍ２１−ｎがＯＮ状態となり、それに応じてＩｏｆｓ（１）−、Ｉｏｆｓ（２）−、・・・、Ｉｏｆｓ（ｎ）−が流れ出し、その合計値がオフセット調整電流Ｉｏｆｓ−の電流値となる。
【０１３８】
以上のように、本第１０の実施の形態のオフセット調整電流生成回路１３Ａは、差動電流を出力するＤＡ変換器として動作し、オフセット調整電流Ｉｏｆｓ＋及びＩｏｆｓ−は、ｎビットのレジスタ信号によってＩｏｆｓ＋／ｎ又はＩｏｆｓ−／ｎ刻みの精度で調整することが可能となる。また、本第１０の実施の形態によれば、オフセット調整電流生成部１３がｎビットのＤＡ変換器として構成されており、オフセット調整量をデジタル回路にて制御することができるため、より多彩なオフセット調整を容易に実現することができる。
【０１３９】
また、図１４に示すオフセット調整電流生成回路１３Ａにおいて、レジスタ信号のビット数ｎを多くすることによって、電流調整の精度を高くすることができる。尚、図１３のオフセット調整電流生成部１３を図１４に示すような回路構成としても、前記第１の実施の形態（又は前記第３の実施の形態）で説明したように、オフセト制御回路１、３における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【０１４０】
尚、本第１０の実施の形態のオフセット調整電流生成回路１３Ａにおいて、バイアス電流源３０９−１〜３０９−ｎ、Ｐ型のトランジスタＭ２０−１〜Ｍ２０−ｎ及びＭ２１−１〜Ｍ２１−ｎとは逆極性のバイアス電流源３１０−１〜３１０−ｎ、Ｐ型のトランジスタＭ２２−１〜Ｍ２２−ｎ及びＭ２３−１〜Ｍ２３−ｎを用い、インバータ１４−１〜１４−ｎの接続方向を変えたインバータ１５−１〜１５−ｎを設けて、図１５に示すようなオフセット調整電流生成回路１３Ｂを構成することも可能である。図１３のオフセット調整電流生成部１３を図１５に示すような回路構成としても、前記第１の実施の形態（又は前記第３の実施の形態）で説明したように、オフセト制御回路１、３における高速動作及び小面積化が可能であるという効果は何ら失われることはない。
【０１４１】
【発明の効果】
以上のように、請求項１〜１２記載の発明によれば、差動入力電圧（ＶＩＮ＋、ＶＩＮ−）の電位差に比例する差動出力電流（Ｉ＋、Ｉ−）が出力される電圧電流変換部の差動電流出力端子と、オフセット調整電流（Ｉｏｆｓ＋、Ｉｏｆｓ−）が出力されるオフセット調整電流生成部のオフセット調整電流出力端子と、差動端子間の電位差に比例する差動入出力電流（Ｉｒ）が入出力される電流電圧変換部の差動端子とを互いに接続することにより、差動入力電圧信号（ＶＩＮ＋、ＶＩＮ−）にオフセット電圧（Ｖｏｆｆ＋、Ｖｏｆｆ−）が含まれていても、そのオフセット電圧をオフセット調整電流（Ｉｏｆｓ＋、Ｉｏｆｓ−）によって調整して、差動入力電圧信号（ＶＩＮ＋、ＶＩＮ−）にオフセット電圧に応じたオフセット調整信号を加えた差動出力電圧信号（ＶＯ＋、ＶＯ−）を生成することができる。
【０１４２】
この場合の差動入力電圧へのオフセット調整信号の加算は、差動入力電圧を差動出力電流（Ｉ＋、Ｉ−）に変換した後にオフセット調整電流（Ｉｏｆｓ＋、Ｉｏｆｓ−）を電流加算するため、オフセット電圧調整を高速に行うことができる。また、従来のオフセット制御回路のように演算増幅器を必要としないため、回路規模の小型化を図ることができる。また、差動信号処理を行うことにより、ノイズに強く、信号の歪みも生じにくくなり、高精度の信号処理を行うことができる。
【０１４３】
また、オフセット調整電流生成部をｎビットのＤＡ変換器にて構成することによって、オフセット調整量の制御幅をデジタル制御にて設定することができ、オフセット調整の精度を高めることができる。
【図面の簡単な説明】
【図１】ＤＶＤ信号再生処理システムの全体構成を示す図である。
【図２】同ＤＶＤ信号再生処理システムに備えるアナログフロントエンド及びＰＲＭＬリードチャネルの内部構成を示す図である。
【図３】本発明のオフセット制御回路の第１の実施の形態における構成例を示すブロック図である。
【図４】図３の電圧電流変換部の一具体例を示す回路図である。
【図５】本発明のオフセット制御回路の第３の実施の形態における構成例を示す回路図である。
【図６】図３の電圧電流変換部における他の具体例を示す回路図である。
【図７】図３の電圧電流変換部における更に他の具体例を示す回路図である。
【図８】図３の電流電圧変換部における一具体例を示す回路図である。
【図９】図３の電流電圧変換部における他の具体例を示す回路図である。
【図１０】図３の電流電圧変換部における更に他の具体例を示す回路図である。
【図１１】図３のオフセット調整電流生成部における一具体例を示す回路図である。
【図１２】図３のオフセット調整電流生成部における他の具体例を示す回路図である。
【図１３】図３のオフセット調整電流生成部とは別の構成例を示す回路図である。
【図１４】図１３のオフセット調整電流生成部における一具体例を示す回路図である。
【図１５】図１３のオフセット調整電流生成部における他の具体例を示す回路図である。
【図１６】従来のオフセット制御回路の回路図である。
【符号の説明】
１〜１０、５１ｃ　　　　　　　　オフセット制御回路
１０　　　　　　　　　　　　　　　　　　　　電圧電流変換部
１０Ａ〜１０Ｄ　　　　　　　　　　電圧電流変換回路
１１　　　　　　　　　　　　　　　　　　　　オフセット調整電流生成部
１１Ａ，１１Ｂ，
１３，１３Ａ，１３Ｂ　　　　オフセット調整電流生成部
１２　　　　　　　　　　　　　　　　　　　　電流電圧変換部
１２Ａ〜１２Ｃ　　　　　　　　　　電流電圧変換回路
１３−１〜１３−ｎ　　　　　　サブオフセット調整電流生成部
１４−１〜１４−ｎ、
１５−１〜１５−ｎ　　　　　　インバータ
４０　　　　　　　　　　　　　　　　　　　　ＤＶＤ
５０　　　　　　　　　　　　　　　　　　　　フロントエンド
５１　　　　　　　　　　　　　　　　　　　　アナログフロントエンド
６０　　　　　　　　　　　　　　　　　　　　バックエンド
７０　　　　　　　　　　　　　　　　　　　　システムコントローラ
１０１，１０２　　　　　　　　　　オフセット調整電流出力端子
１０３，１０４　　　　　　　　　　オフセット調整電流制御端子
１０５，１０６　　　　　　　　　　差動電流出力端子
１０７，１０８　　　　　　　　　　差動端子
１０９，１１０　　　　　　　　　　差動電圧入力端子
１１１　　　　　　　　　　　　　　　　　　制御端子
１１２　　　　　　　　　　　　　　　　　　入出力電流制御端子
１１３−１〜１１３−ｎ　　レジスタ信号入力端子
１１５，１１６　　　　　　　　　　差動電圧出力端子
３０１，３０２，
３０７，３０８，
３０９−１〜３０９−ｎ，
３１０−１，３１０−ｎ　　バイアス電流源
Ｍ１〜Ｍ１９，
Ｍ２０−１〜Ｍ２０−ｎ，
Ｍ２１−１〜Ｍ２１−ｎ，Ｐ型のトランジスタ
Ｍ２２−１〜Ｍ２２−ｎ，
Ｍ２３−１〜Ｍ２３−ｎ　　Ｎ型のトランジスタ
Ｒ１〜Ｒ４　　　　　　　　　　　　　　抵抗[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an offset control circuit that adjusts an output voltage corresponding to an input voltage.
[0002]
[Prior art]
Conventionally, for example, an offset control circuit as shown in FIG. 16 is used to adjust an offset amount included in input / output of an operational amplifier.
[0003]
In FIG. 16, an offset control circuit 200 includes an operational amplifier 201 (operational amplifier) in which resistors R1 and R2 and a variable voltage source 202 are connected in series to an output terminal of the operational amplifier 201, and a connection point of the resistors R1 and R2 is connected to the minus side of the operational amplifier 201. It is configured to be connected to the input terminal. The input voltage VIN + is input to the + input terminal of the operational amplifier 201, and the output voltage VO is output from its output terminal.
[0004]
Here, in order to generate an output voltage VO by adding an offset voltage to the input voltage VIN of the operational amplifier 201, the output voltage V2 from the variable voltage source 202 is configured to be variable. The input voltage V1 (VIN−) applied to the negative input terminal of the operational amplifier 201 has the same voltage value as the input voltage VIN + to the positive input terminal due to the characteristics of the operational amplifier 201. The output voltage signal VO from the operational amplifier 201 is determined by the resistors R1 and R2, the input voltage VIN +, and the output voltage V2. Therefore, the output voltage VO from the operational amplifier 201 can be output by adjusting the offset amount with respect to the input voltage VIN by adjusting the output voltage V2 by the variable voltage generation source 202.
[0005]
[Problems to be solved by the invention]
However, the conventional offset control circuit 200 uses the operational amplifier 201, and the operation of the operational amplifier 201 is low, so that it is not suitable for high-speed operation. Normally, the operational amplifier 201 cannot operate normally unless it has a band that is 10 to 100 times the signal band to be used. Therefore, although it is necessary to use a transistor having a large capacity, this operational amplifier 201 In order to configure the 201 so that it can operate at high speed, it is necessary to use a transistor having a higher capacity. As a result, there is a problem that the power consumption is remarkably increased and the circuit scale is increased.
[0006]
Further, since the conventional offset control circuit 200 has a single configuration in which one input voltage VIN + is input to the operational amplifier 201, when the input voltage signal VIN + includes a non-ideal factor component such as a noise component. In this case, the distortion characteristic of the signal voltage deteriorates, and the quality of the output voltage VO decreases.
[0007]
In order to prevent such distortion characteristics from deteriorating, a pair of differential input voltages are input to the offset control circuit, and a differential output voltage proportional to the voltage difference between the two input voltages is generated. It is conceivable to perform offset adjustment. Actually, when performing high-accuracy analog signal processing, it is necessary to perform offset adjustment using a differential output voltage in order to prevent signal signal distortion characteristics from deteriorating.
[0008]
However, in order to perform the offset adjustment by the differential output voltage using the conventional offset control circuit 200, two offset control circuits 200 are required, and there is a problem that the circuit scale increases.
[0009]
An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide an offset control that can be reduced in size without increasing the circuit scale, can operate at high speed, and can prevent deterioration of signal distortion characteristics. It is to provide a circuit.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a differential input voltage is converted into a current value, and then an offset adjustment current is added to the differential current value. By converting the value into a voltage value, it is possible to reduce the deterioration of signal distortion characteristics at high speed without using an operational amplifier as an offset control circuit.
[0011]
Specifically, in the offset control circuit according to the first aspect of the present invention, a differential voltage is input from a pair of differential voltage input terminals, and an offset voltage included in the differential input voltage is adjusted. An offset control circuit that outputs a dynamic voltage from a pair of differential voltage output terminals, the offset control circuit including the pair of differential voltage input terminals and the pair of differential current output terminals, and is input from the pair of differential voltage input terminals. A voltage-current conversion unit that generates a pair of differential output currents according to a potential difference between the pair of differential input voltages, and outputs the pair of differential output currents from the pair of differential current output terminals; An offset adjustment current output terminal connected to a pair of differential current output terminals of the unit, and two or more offset adjustment current control terminals, and an offset input from the offset adjustment current control terminal A pair of offset adjustment current generation sections that are controlled by the adjustment current control signal to generate a pair of offset adjustment currents and output the pair of offset adjustment currents from the pair of offset adjustment current output terminals; A differential voltage output terminal, a pair of offset adjustment current output terminals of the offset adjustment current generator, and a pair of differential terminals connected to the pair of differential voltage output terminals, wherein the pair of differential terminals And a current-to-voltage conversion unit that converts the current to a voltage corresponding to the current by flowing a current between the two differential terminals, and generates the converted voltage at the pair of differential voltage output terminals. It is characterized by having.
[0012]
Further, in the invention according to claim 2, in the offset control circuit according to claim 1, the voltage-current conversion unit includes: a pair of bias current sources connected to the pair of differential current output terminals; Each of the differential current output terminals is connected to each of the first drive terminals, and each of the gates is commonly connected to the control terminal. A pair of first transistors, and each of the pair of first transistors has a second drive terminal, A pair of second transistors each connected to each first drive terminal, each gate thereof being respectively connected to the pair of differential voltage input terminals, and each second drive terminal being connected to a reference potential supply point; It is characterized by having.
[0013]
Further, in the offset control circuit according to the third aspect of the present invention, a differential voltage is input from a pair of differential voltage input terminals, and an offset voltage included in the differential input voltage is adjusted. From a pair of differential voltage output terminals, a voltage-current converter having the pair of differential voltage input terminals and the pair of differential current output terminals, a pair of offset adjustment current output terminals, and 2 An offset adjustment current generator having one or more offset adjustment current control terminals, and a current-voltage converter having a pair of differential terminals, wherein the voltage-current converter is connected to the pair of differential current output terminals. A pair of bias current sources, a pair of differential current output terminals connected to a first drive terminal, and a pair of gates connected to a pair of control terminals; A second driving terminal of the first transistor is connected to the first driving terminal, a gate is connected to each of the pair of differential voltage input terminals, and a second driving terminal is connected to the reference potential supply point. And generating a pair of differential output currents in accordance with a potential difference between the pair of differential input voltages input from the pair of differential voltage input terminals. A voltage output from a dynamic current output terminal, wherein the offset adjustment current generation section includes a pair of offset adjustment current output terminals connected to a first drive terminal of a pair of second transistors of the voltage / current conversion section; Controlled by an offset adjustment current control signal input from an adjustment current control terminal, a pair of offset adjustment currents is generated, and the pair of offset adjustment currents is adjusted to the pair of offset adjustment currents. The current-to-voltage converter is configured such that the pair of differential terminals are connected to a pair of differential voltage output terminals of the voltage-to-current converter to form the pair of differential terminals. A current flows between two differential terminals, the current is converted into a voltage corresponding to the current, and the converted voltage is generated at the pair of differential voltage output terminals.
[0014]
In addition, in the invention according to claim 4, in the offset control circuit according to claim 1, the voltage-current converter includes a pair of bias current sources to which each of the pair of differential current output terminals is connected. A pair of second transistors each having the pair of differential current output terminals connected to each of the first drive terminals, and a gate connected to each of the pair of differential voltage input terminals; A pair of first transistors, each of which has a second driving terminal connected to each of the first driving terminals, a gate of which is commonly connected to a control terminal, and each of which has a second driving terminal connected to a reference potential supply point. And a resistance means having a predetermined resistance value connected between the second drive terminals of the pair of second transistors.
[0015]
Further, in the invention according to claim 5, in the offset control circuit according to claim 1, the voltage-current converter includes a pair of bias current sources to which each of the pair of differential current output terminals is connected, Each of the pair of differential current output terminals is connected to each of the first drive terminals, each of its gates is connected to each of the pair of differential voltage input terminals, and each of the second drive terminals is connected to a reference potential supply point. And a pair of transistors connected to each other.
[0016]
Further, in the invention according to claim 6, in the offset control circuit according to claim 1 or 3, the current-to-voltage converter is a resistance unit having a predetermined resistance value connected between the pair of differential terminals. It is characterized by the following.
[0017]
In addition, in the invention according to claim 7, in the offset control circuit according to claim 1 or 3, each of the pair of differential terminals is connected to each of the first drive terminals. A pair of third transistors, each gate of which is commonly connected to the input / output current control terminal, and each second drive terminal of the pair of third transistors is connected to each first drive terminal. Each of the second driving terminals is connected to the pair of differential terminals, and each of the second driving terminals is connected to a reference potential supply point.
[0018]
Also, in the invention according to claim 8, in the offset control circuit according to claim 1 or 3, the current-to-voltage converter is a fifth transistor connected between the pair of differential terminals, and The input / output current control terminal is connected to the gate of the five transistors.
[0019]
Further, in the invention according to claim 9, in the offset control circuit according to claim 1 or 3, the offset adjustment current generation unit includes a current source, and a second drive terminal connected to the current source. Two offset adjustment current control terminals are respectively connected to a gate, and a pair of sixth transistors each having the pair of offset adjustment current output terminals connected to each first drive terminal.
[0020]
In addition, in the invention according to claim 10, in the offset control circuit according to claim 1 or 3, the offset adjustment current generator has n (n is a natural number) sub-offset adjustment current generators, Each of the sub-offset adjustment current generators includes an offset adjustment current control terminal to which a non-overlapping one-bit signal of the n-bit register signal is input, a current source, and a second driving unit connected to the current source. Terminals are connected to each other, the offset adjustment current control terminal is connected to one of the gates, and the other of the gates is connected to the other of the gates via an inverter. The pair of offset adjustment current output terminals are connected to the first drive terminals. And a pair of seventh transistors connected to each other, and the pair of sub-offset adjustment currents generated by the sub-offset adjustment current generation unit are: S, characterized in that it is supplied to each of the pair of offset adjusting current output terminal.
[0021]
Also, in the signal processing device according to the present invention, predetermined processing is performed on the offset control circuit according to the first or third aspect and the differential output voltage whose offset voltage has been adjusted by the offset control circuit. A processing circuit, wherein the offset control circuit and the processing circuit are formed on one chip.
[0022]
Further, in the signal processing device according to the twelfth aspect of the present invention, in the signal processing device according to the eleventh aspect, the signal processing device constitutes a DVD playback device, and the offset control circuit reads out from the DVD. Adjusting the offset voltage included in the adjusted signal, outputting the adjusted signal as a differential output voltage, and the processing circuit filters the differential output voltage having the offset voltage adjusted by the offset control circuit. And a back end for converting an output signal of the front end into a video signal and an audio signal.
[0023]
As described above, the first to twelfth aspects of the invention have the following effects.
[0024]
That is, in the present invention, the differential current output terminal of the voltage-current converter for outputting the differential output current (I +, I-) proportional to the potential difference between the differential input voltage signals (VIN +, VIN-) is provided. And an offset adjustment current output terminal of the offset adjustment current generation unit to which the offset adjustment currents (Iofs +, Iofs-) are output and a differential input / output current (Ir) that is proportional to the potential difference between the differential terminals. Since the differential terminal of the voltage converter is connected, the differential voltage output terminal connected to the differential terminal outputs the differential output voltage (proportional to the addition current of the differential output current and the offset adjustment current) VO +, VO-) are output. Therefore, even if the offset voltage (Voff +, Voff-) is included in the differential input voltage (VIN +, VIN-), the offset voltage can be adjusted by the offset adjustment current (Ioffs +, Iofs-). A differential output voltage (VO +, VO-) can be generated by adding an offset adjustment signal according to the offset voltage to the input voltage (VIN +, VIN-).
[0025]
Therefore, the offset adjustment voltage is added to the differential input voltage by converting the output into the differential output current (I +, I−) and the offset adjustment current (Iofs +, Iofs−) by current addition. It is possible to do it.
[0026]
Further, since an operational amplifier (operational amplifier) is not required unlike the conventional offset control circuit, the circuit size can be reduced, and since the differential signal processing is performed, the circuit is resistant to noise and the signal distortion is reduced. Hard to occur.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, first to tenth embodiments of the offset control circuit of the present invention will be described with reference to the drawings.
[0028]
(First Embodiment)
FIG. 1 shows the overall configuration of a DVD signal reproduction processing system including an offset control circuit according to the present invention.
[0029]
In the DVD signal reproduction processing system (signal processing device) shown in FIG. 1, reference numeral 40 denotes a DVD or CD (hereinafter, represented by DVD); 41, an optical pickup for extracting a signal from the DVD; . The laser driver 42 is controlled by a laser controller 43. Reference numeral 44 denotes a disk motor for rotating the DVD 40, which is driven by a motor driver 45.
[0030]
Reference numeral 50 denotes a front end, reference numeral 60 denotes a back end, reference numeral 70 denotes a system controller, which are mounted on the same chip and integrated into one chip. In brief, the front end 50 performs data extraction processing including reading, demodulation, and error correction of data from the DVD 40, and outputs a control signal to the laser controller 43 and the motor driver 45 to perform servo control and laser control. Perform control. On the other hand, the back end 60 converts a reproduction signal of the DVD 40 sent from the front end 50 into a video signal and an audio signal. Further, the system controller 70 controls a series of processes of the front end 50 and a series of processes of the back end 60.
[0031]
The front end 50 has, as main parts, an analog front end 51 for performing processing such as noise removal of a signal read from the DVD 40 by the optical pickup 41, and a digital PRML read channel 52. The analog front end 51 has an offset control circuit 51c (see FIG. 2) according to the present invention, as described later. The analog front end 51 calculates a servo focus error signal and a tracking error signal, and outputs these signals to the servo DSP 53. The servo DSP 53 controls the motor driver 45 so that the optical pickup 41 accurately traces the recording data on the DVD 40, and controls the laser controller 43 to perform laser power control.
[0032]
The PRML read channel 52 performs, together with the analog front end 51, a PR (Partial Response) process of reproducing an original waveform by using a characteristic that a reproduced signal is subjected to intersymbol interference, and a characteristic of a recording signal of the DVD 40. The data with the highest probability is read from the reproduced signal based on the data. The data extracted from the PRML read channel 52 is output to the formatter FMT. The ECC 54 performs an error correction (Error-Correcting Code) on the extracted data using Reed-Solomon. The data on which demodulation and error correction have been completed are output to the back end 60 via the AUDIO / VISUAL interface I / F. The above processing is controlled by the 32-bit CPU 55.
[0033]
On the other hand, the back end 60 has an IO processor 61, a pixel control processor 62, and an AV decode processor 63. The AUDIO / VISUAL data input from the front end 50 via the stream interface 64 is subjected to stream analysis by the IO processor 61, pixel processing by the pixel control processor 62, and decoding processing by the AV decode processor 63. Are output as audio / video data through the AV interface 65.
[0034]
In FIG. 1, the SDRAM 80 is provided externally to the chip and is shared by the front end 50 and the back end 60. Access to the SDRAM 80 is controlled by an SDRAM interface 66 provided in the back end 60. When the front end 50 accesses the SDRAM 80, the front end 50 accesses the SDRAM interface 66 via the UMAC 56 provided in the front end 50.
[0035]
FIG. 2 shows the internal configuration of the analog front end 51 and the PRML read channel 52.
[0036]
In the figure, an analog front end 51 includes an analog buffer 51a, a VGA circuit 51b, an offset control circuit 51c according to the present invention, a fifth-order Gm-C filter 51d, two DACs (Digital Analog Converter) 51e, and a wobble detector 51f. , And a servo pre-processing circuit 51g. On the other hand, the PRML read channel 52 includes a 7-bit ADC (Analog Digital Converter) 52a, a 7-tap FIR (adaptive equalization) filter 52b, a Viterbi decoder 52c, an LMS 52d, a digital controller 52e, and a PLL 52f. The PR processing is performed by a fifth-order Gm-C filter 51d of the front end 51 and an FIR filter 52b of the PRML read channel 52. The PRML read channel 52 performs detection processing on the data quantized by the ADC 52a to perform peak / bottom detection, and performs amplitude control of an RF signal and offset control in the offset control circuit 51c based on the detection result. This offset control is performed by 8-bit digital control.
[0037]
Next, the offset control circuit 51c provided in the analog front end 51 will be specifically described.
[0038]
FIG. 3 is a block diagram showing a configuration example of the offset control circuit according to the first embodiment of the present invention.
[0039]
In FIG. 3, the offset control circuit 1 includes a voltage / current converter 10, an offset adjustment current generator 11 connected to both output terminals of the voltage / current converter 10, and two output terminals of the voltage / current converter 10. And a current / voltage converter 12 connected to each other.
[0040]
The voltage-current converter 10 includes a pair of differential voltage input terminals 109 and 110, a control terminal 111, and a pair of differential current output terminals 105 and 106, and each of the differential input voltages VIN + and VIN−. Each of the differential output currents is input to a pair of differential voltage input terminals 109 and 110 and controlled by a control signal input to a control terminal 111, and the differential output currents I + and I + are proportional to the differential input voltages VIN + and VIN−, respectively. -Is generated. The generated differential output currents I + and I− are output from a pair of differential current output terminals 105 and 106, respectively.
[0041]
Assuming that the conversion coefficient of the voltage-current converter 10 is Gm, the difference between the differential input voltages VIN + and VIN− and the differential output currents I + and I− is as follows.
I + = Gm × VIN + (formula 1)
I− = Gm × VIN− (formula 2)
Is established.
[0042]
The offset adjustment current generation unit 11 has a pair of offset adjustment current output terminals 101 and 102 and offset adjustment current control terminals 103 and 104, and control signals input to the offset adjustment current control terminals 103 and 104, respectively. , The offset adjustment currents Iofs + and Iofs− are respectively generated. The generated offset adjustment currents Iofs + and Iofs− are output from a pair of offset adjustment current output terminal pairs 101 and 102, respectively.
[0043]
The current-to-voltage converter 12 has a pair of differential terminals 107 and 108 and an input / output current control terminal 112, and outputs a current (differential input / output) proportional to the potential difference between the pair of differential terminals 107 and 108. (Current) Ir flows. The differential terminal 107 of the current-to-voltage converter 12 is connected to the differential current output terminal 105 of the voltage-to-current converter 10 and the offset adjustment current output terminal 101 of the offset adjustment current generator 11. The differential terminal 108 of the unit 12 is connected to the differential current output terminal 106 of the voltage / current converter 10 and the offset adjustment current output terminal 102 of the offset adjustment current generator 11. The pair of differential terminals 107 and 108 are respectively connected to a pair of differential voltage output terminals 115 and 116 from which the respective differential output voltage signals VO− and VO + are respectively output.
[0044]
In the offset control circuit 1 of the present embodiment thus configured, the differential input / output current flowing through the current-voltage converter 12 is defined as Ir, and the current flowing inside the differential terminal 108 from the differential terminal 107 is When the direction is positive, at the differential terminal 107,
I + = Ir + Iofs + (Equation 3)
Holds, and at the differential terminal 108,
I − = − Ir + Iofs− (formula 4)
Is established.
[0045]
When the differential input / output current Ir flowing between the differential terminals 107 and 108 of the current-to-voltage converter 12 is obtained from the above (Equation 3) and (Equation 4),

It becomes. The differential input / output current Ir is calculated from the above (Equation 1), (Equation 2) and (Equation 5).

It becomes.
[0046]
Therefore, the differential output voltage (VO + −VO−) output from the differential voltage output terminals 116 and 115 is represented by the following equation, where the conversion coefficient of the current / voltage converter 12 is R.

It becomes.
[0047]
Next, a case is considered in which the differential input voltage signals VIN + and VIN− input from the differential voltage input terminals 109 and 110 respectively include an offset voltage. Assuming that the offset voltages of the differential input voltages VIN + and VIN− are Voff, the differential output currents I + and I− output from the voltage-current converter 10 are respectively
I + = Gm × (VIN ++ Voff) (Equation 10)
I− = Gm × (VIN−−Voff) (Equation 11)
It becomes.
[0048]
Therefore, in the offset control circuit 1, the Ir of the differential input / output current flowing in the current-voltage converter 12 is calculated from the above (Equation 6), (Equation 10) and (Equation 11).

It becomes. Thereby, the differential output voltage (VO + −VO−) is

It becomes.
[0049]
From the above (Equation 13), regarding the differential output voltages VO + and VO− of the offset control circuit 1, the offset currents (Gm × Voff) of the differential input voltages VIN + and VIN− are adjusted by the offset adjustment currents Iofs + and Iofs−. You can see that it is.
[0050]
As described above, according to the present embodiment, since the differential signal processing is basically performed, the operational amplifier 201 as in the related art is not required for adding the input voltage and the offset voltage. Further, the addition of the offset voltage to the input voltage is realized by current addition of a simple configuration based on Kirchhoff's law after converting the input voltage and the offset voltage into respective currents, so that the offset voltage can be adjusted very quickly. It can be performed.
[0051]
Further, in the conventional offset addition method using the operational amplifier 201, the bandwidth of the operational amplifier 201 needs to be higher by about one to two digits than the input signal bandwidth, so that the circuit scale increases, the power consumption increases, and the processing speed increases. Although the lower limit of the upper limit becomes a problem, according to the first embodiment, the circuit scale can be further reduced by a simple configuration in which only the current is added based on Kirchhoff's law, and the higher-speed offset can be achieved. An addition process can be performed.
[0052]
Furthermore, since the offset control circuit 1 of the present embodiment is based on differential signal processing, it is resistant to noise and hardly causes signal distortion. Even when the conventional offset control circuit 200 is used, the differential signal processing can be performed by providing two systems of the offset control circuit 200, but this requires twice the circuit scale and power consumption. . On the other hand, in the offset control circuit 1 of the present embodiment, it is possible to perform an offset adjustment process using a differential signal with a smaller circuit scale.
[0053]
In the present embodiment, the front end 50 including the offset control circuit 1, the back end 60, and the system controller 70 are integrated into one chip. However, only the front end 50 including the offset control circuit 1 may be integrated into one chip. Of course.
[0054]
Further, in the present embodiment, the offset control circuit 1 provided in the DVD signal reproduction processing system has been described, but the present invention is not limited to this, and the present invention is similarly applied to the offset control circuit provided other than in the DVD signal reproduction processing system. Of course you can. In this case, the offset control circuit and a processing circuit that performs a predetermined process on the differential output voltage whose offset voltage has been adjusted by the offset control circuit may be integrated into one chip.
[0055]
(Second embodiment)
In the second embodiment, the offset control circuit 2 is realized by using a voltage-current conversion circuit 10A as a specific example of the voltage-current conversion unit 10.
[0056]
FIG. 4 is a circuit diagram showing a specific example of the voltage-current converter 10 of FIG.
[0057]
In FIG. 4, the voltage-current converter 10A includes a pair of bias current sources 301 and 302, a pair of N-type first transistors M3 and M4 respectively connected thereto, and a pair of N-type first transistors M3 and M4 respectively connected thereto. Of the second transistor M1 and M2.
[0058]
The bias current sources 301 and 302 are connected to the differential current output terminals 105 and 106, respectively, so that the bias current Ib flows.
[0059]
Each gate of the first transistors M3 and M4 is commonly connected to the control terminal 111, and the control voltage Vbias is input to each gate. The drains of the first transistors M3 and M4 are respectively connected to the differential current output terminals 105 and 106, and the differential currents I + and I− are output from the differential current output terminals 105 and 106, respectively. You.
[0060]
The N-type second transistors M1 and M2 have respective gates connected to the differential voltage input terminals 109 and 110, respectively, and receive the differential input voltage signals VIN + and VIN−, respectively. The drains of the N-type second transistors M1 and M2 are respectively connected to the sources of the first transistors M3 and M4, and the respective sources are grounded.
[0061]
With the above configuration, in the voltage-current conversion circuit 10A, the N-type first transistors M3 and M4 each operate as a source follower circuit, the control voltage Vbias is input to each gate thereof, and the N-type first transistors M3 and By M4, each voltage lowered by about the threshold voltage Vth is output from each source. As a result, the drain voltages of the N-type second transistors M1 and M2 are kept constant, and the drain-source voltage Vds of the N-type second transistors M1 and M2 is kept almost constant.
[0062]
The N-type second transistors M1 and M2 are each biased to operate in an unsaturated region. At this time, the drain currents IDS1 and IDS2 flowing through the N-type second transistors M1 and M2 are respectively

(However, β is the transconductance of the second transistors M1 and M2, and Vds is the drain-source voltage of the N-type second transistors M1 and M2.)
It is expressed as
[0063]
Here, in the voltage-current converter 10A of the second embodiment, the differential output current (I + −I−) is equal to IDS1−IDS2, and the differential output current flows into the current-voltage converter 12. Therefore,

It becomes.
[0064]
From the above (Equation 16), it can be seen that the differential output current I + −I− is proportional to the differential input voltage VIN + −VIN−, and the proportional coefficient (conversion coefficient) Gm is β × Vds.
[0065]
As described above, the voltage-current conversion circuit 10A according to the second embodiment operates as a differential voltage-current conversion circuit. Therefore, by applying this to the voltage-to-current converter 10 in FIG. 3, the offset control circuit 2 of the second embodiment can be realized. The voltage-current conversion circuit 10A can reduce signal distortion by biasing the N-type second transistors M1 and M2 to operate in an unsaturated region. By configuring the offset control circuit 2, it is possible to further prevent the deterioration of the distortion characteristic. Even when the voltage-current converter 10 is configured as shown in FIG. 4, as described in the first embodiment, the effect that the offset control circuit 1 can operate at high speed and reduce the area can be obtained. Nothing is lost.
[0066]
In the voltage-current conversion circuit 10A according to the second embodiment, the conversion coefficient Gm can be adjusted in (Equation 13) by adjusting the control voltage Vbias. This means that the input / output voltage ratio in the above (Equation 13), that is, the coefficient of the differential input voltages VIN + and VIN− (1/2) × R × Gm can be controlled. Therefore, the offset control circuit 2 of the second embodiment can function not only as an offset adjustment function but also as a variable amplifier that changes the amplification factor of a signal.
[0067]
Further, in the voltage-current conversion circuit 10A of the second embodiment, the drain voltages of the N-type second transistors M1 and M2 can be fixed with higher accuracy. For example, the gate voltages of the N-type first transistors M3 and M4 can be controlled using an operational amplifier (operational amplifier) so that the drain voltages of the N-type second transistors M1 and M2 become constant. Since the operational amplifier used in this case does not necessarily need to have high precision, it is sufficient if the operational amplifier has a band of about 10 times the signal band. As described above, the configuration in which the operational amplifier for controlling the gate voltages of the N-type first transistors M3 and M4 is provided as described in the first embodiment. The effect that the area can be increased is not lost at all.
[0068]
(Third embodiment)
The third embodiment is a case where the signal distortion in the offset control circuit 2 of the second embodiment is further reduced.
[0069]
FIG. 5 is a circuit diagram showing a configuration example of the offset control circuit according to the third embodiment of the present invention.
[0070]
5, the offset control circuit 3 is different from the offset control circuit 2 of the second embodiment in that the offset adjustment current output terminals 101 and 102 of the offset adjustment current generator 11 By being connected to the drains of the N-type second transistors M1 and M2 instead of the drains of the N-type first transistors M3 and M4, signal distortion in the offset control circuit 2 of the second embodiment is further reduced. Can be reduced.
[0071]
With the configuration described above, in the offset control circuit 3 of the third embodiment, the offset voltage is included in the differential input voltage signals VIN + and VIN−, and the offset control circuit is operated to remove the offset voltage. In the case, the operation will be described in comparison with the offset control circuits 1 and 2 of the first and second embodiments.
[0072]
In the offset control circuits 1 and 2 of the first and second embodiments, although the N-type second transistors M1 and M2 and the N-type first transistors M3 and M4 are symmetrical circuits, the differential Since the offset voltage is superimposed between the input voltage signals VIN + and VIN−, different bias currents flow through the respective circuits. Such asymmetry of the current is caused by adding the offset adjustment currents Iofs + and Iofs− that offset the offset voltage (offset component) from the offset adjustment current generator 11 at the drains of the N-type first transistors M3 and M4. However, since the N-type second transistors M1 and M2 and the N-type first transistors M3 and M4 operate in an asymmetric state, signal distortion is likely to occur.
[0073]
On the other hand, in the offset control circuit 3 according to the third embodiment, the offset adjustment currents Iofs + and Iofs− from the offset adjustment current generator 11 are the differential output currents I + and I + at the drains of the N-type second transistors M1 and M2. Since the current is added to I-, the current asymmetry is eliminated at this point, and the N-type first transistors M3 and M4 operate as a symmetric differential circuit with respect to the bias currents I + 'and I-'. Thus, according to the offset control circuit 3 of the third embodiment, compared to the offset control circuits 1 and 2 of the first and second embodiments, the N-type first transistors M3 and M4 are used. The generated signal distortion can be reduced.
[0074]
Further, in the offset control circuit 3 according to the third embodiment, although the N-type second transistors M1 and M2 operate in an asymmetric state, they operate in an unsaturated region, so that the bias current values are different. Even if the voltage Vds between the source and the drain is the same, the voltage-current characteristics hardly change. Therefore, the signal distortion generated in the entire offset control circuit 3 can be further reduced as compared with the first and second embodiments.
[0075]
Even if the offset control circuit 3 has the circuit configuration as shown in FIG. 5, the effect that the high-speed operation and the small area of the offset control circuit 1 can be achieved is lost as described in the first embodiment. Will not be heard.
[0076]
(Fourth embodiment)
In the fourth embodiment, as another specific example of the voltage-current converter 10, a voltage-current converter 10C is used to realize an offset control circuit 4 that controls an input / output gain by a resistance ratio.
[0077]
FIG. 6 is a circuit diagram showing another specific example of the voltage-current converter 10 in FIG.
[0078]
In FIG. 6, the voltage-current conversion circuit 10C includes a pair of bias current sources 301 and 302, a pair of N-type first transistors M7 and M8, and a pair of N-type second transistors M5 and M6, respectively. A bias current source 301, a series circuit of an N-type first transistor M7 and a second transistor M5, and a bias current source 302 and a series circuit of an N-type first transistor M8 and a second transistor M6 are arranged in two series. . Further, a resistor R3 is provided between a connection point between the N-type first transistor M7 and the second transistor M5 and a connection point between the N-type first transistor M8 and the second transistor M6.
[0079]
The bias current sources 301 and 302 are connected to the differential current output terminals 105 and 106, respectively, so that the bias current Ib flows.
[0080]
The gates of the N-type first transistors M7 and M8 are connected to differential voltage input terminals 109 and 110, respectively, and the differential input voltages VIN + and VIN− are input to the differential voltage input terminals 109 and 110, respectively. You. The drains of the N-type first transistors M7 and M8 are respectively connected to the differential current output terminals 105 and 106, and the resistor R3 is connected between the respective sources.
[0081]
The gates of the N-type second transistors M5 and M6 are commonly connected to a control terminal 111, and a control voltage Vbias is input to the control terminal 111. The drains of the N-type second transistors M5 and M6 are respectively connected to the sources of the N-type first transistors M7 and M8, and the respective sources are grounded.
[0082]
In the voltage-current conversion circuit 10C of the fourth embodiment configured as described above, the N-type first transistors M7 and M8 each operate as a source follower circuit, and the N-type first transistors M7 and M8 Based on the differential input voltage signals VIN + and VIN− input to the respective gates, voltages reduced by the threshold voltage Vth are output from the respective sources and applied to both ends of the resistor R3. As a result, a potential difference of (VIN + −VIN−) is generated in the resistor R3, and a current of (VIN + −VIN −) / R3 is generated according to Ohm's law.
[0083]
Therefore, the current conversion coefficient Gm in the voltage-current conversion circuit 10C of the fourth embodiment is approximately 1 / R3, and the differential output current (VIN + −VIN −) / R3 is the N-type first transistor M7 and M8. Are output from the differential current output terminals 105 and 106 via the. The N-type second transistors M5 and M6 operate as circuits for applying a bias current to the N-type first transistors M7 and M8, respectively.
[0084]
As described above, the voltage-current conversion circuit 10C according to the fourth embodiment operates as a differential voltage-current conversion circuit. By applying this to the voltage-current converter 10 shown in FIG. 3, the offset control circuit 4 can be realized. Since the voltage-current converter 10 has a current-voltage coefficient Gm of about 1 / R3, the input-output voltage ratio when operated as the offset control circuit 4, that is, the differential input voltage signal VIN + in the above (Equation 13). (変 換) × Gm × R, which is a conversion coefficient of V IN and VIN−, becomes (１ ／) × (R / R3), and the resistance (conversion coefficient) R of the current-voltage conversion unit 12 and the voltage-current conversion unit It can be seen that it is determined by the ratio of 10 to the resistor R3. Therefore, the offset control circuit 4 of the fourth embodiment can control the input / output gain by the resistance ratio.
[0085]
Even when the voltage-current converter 10 is configured as shown in FIG. 6, the effect that the high-speed operation and the reduction in area of the offset control circuit 1 are possible is lost as described in the first embodiment. Never.
[0086]
In the voltage-current conversion circuit 10C according to the fourth embodiment, the operational amplifier is set so that the source potentials of the N-type first transistors M7 and M8 match the gate potentials of the N-type first transistors M7 and M8. You can also use it to give feedback. As a result, signal distortion can be further reduced, and the setting accuracy of the input / output gain based on the resistance value can be increased. As described above, the configuration in which the operational amplifiers for controlling the gate potential and the source potential of the N-type first transistors M7 and M8 are provided as described in the first embodiment. The effect of being able to increase the area is not lost at all.
[0087]
(Fifth embodiment)
In the fifth embodiment, as another specific example of the voltage-to-current converter 10, a voltage-to-current converter 10D is used to realize an offset control circuit 5 that can operate at an extremely high speed.
[0088]
FIG. 7 is a circuit diagram showing still another specific example of the voltage-current converter 10 of FIG.
[0089]
In FIG. 7, the voltage-current conversion circuit 10D includes a pair of bias current sources 301 and 302 and a pair of N-type transistors M9 and M10. The series circuit includes the bias current source 301 and the N-type transistor M9. A bias current source 302 and a series circuit of an N-type transistor M10 are arranged in two series.
[0090]
The bias current sources 301 and 302 are connected to the differential current output terminals 105 and 106, respectively, so that the bias current Ib flows.
[0091]
The gates of the N-type transistors M9 and M10 are respectively connected to the differential voltage input terminals 109 and 110, and the differential input voltages VIN + and VIN− are input to the differential voltage input terminals 109 and 110, respectively. . The drains of the N-type transistors M9 and M10 are respectively connected to the differential current output terminals 105 and 106, and the sources of the N-type transistors M9 and M10 are grounded.
[0092]
In the voltage-current conversion circuit 10D of the fifth embodiment configured as described above, each differential input that is input to each gate thereof according to the voltage-current conversion characteristics of the N-type transistors M9 and M10. The voltage (VIN + −VIN−) is converted into a current, and is output from the differential current output terminals 105 and 106 as differential currents (I + −I−).
[0093]
As described above, the voltage-current converter 10D according to the fifth embodiment operates as a differential voltage-current converter. Therefore, by applying this to the voltage / current converter 10 shown in FIG. 3, the offset control circuit 5 of the fifth embodiment can be realized. This voltage-current conversion circuit 10D has very high speed because there are only N-type transistors M9 and M10 between the differential voltage input terminals 109 and 110 and the differential current output terminals 105 and 106, respectively. Can be operated. Therefore, the offset control circuit 5 according to the fifth embodiment can operate at extremely high speed. Note that, even when the voltage-current converter 10 shown in FIG. 3 has a circuit configuration as shown in FIG. 7, as described in the first embodiment, high-speed operation and a small area of the offset control circuit 1 are possible. The effect of being is not lost at all.
[0094]
(Sixth embodiment)
In the sixth embodiment, the offset control circuit 6 is realized by using the current-voltage conversion circuit 12A as a specific example of the current-voltage conversion unit 12.
[0095]
FIG. 8 is a circuit diagram showing a specific example of the current-voltage converter 12 of FIG.
[0096]
8, a resistor R4 is provided between the differential terminals 107 and 108 in the current-voltage conversion circuit 12A.
[0097]
In the current-voltage conversion circuit 12A of the sixth embodiment configured as described above, the resistor R4 applies a voltage proportional to the current (differential input / output current Ir) flowing through the resistor R4 to both terminals thereof. (Differential terminal) 107 and 108. Therefore, the offset control circuit 6 of the sixth embodiment can be realized by applying this to the current-voltage converter 12 shown in FIG.
[0098]
Note that, even if the current-voltage converter 12 in FIG. 3 (or FIG. 5) is configured as shown in FIG. 8, as described in the first embodiment (or the third embodiment), The effect that the control circuits 1 and 3 can operate at high speed and reduce the area is not lost at all.
[0099]
(Seventh embodiment)
In the seventh embodiment, the offset control circuit 7 is realized by using a current-voltage conversion circuit 12B as another specific example of the current-voltage conversion unit 12.
[0100]
FIG. 9 is a circuit diagram showing another specific example of the current-voltage converter 12 in FIG.
[0101]
9, the current-voltage conversion circuit 12B is provided with a pair of differential terminals 107 and 108, a pair of N-type first transistors M13 and M14, and a pair of N-type second transistors M11 and M12.
[0102]
The differential terminal 107, the N-type first transistor M13 and the N-type second transistor M11, and the differential terminal 108, the N-type first transistor M14 and the second transistor M12 are connected in series, respectively. . The gates of the N-type first transistors M13 and M14 are commonly connected to the input / output current control terminal 112, and the control voltage Vbias2 is input to the input / output current control terminal 112. The gates of the N-type second transistors M11 and M12 are connected to the differential terminals 107 and 108, respectively, and a voltage proportional to the differential input / output current Ir is applied to the differential terminals 107 and 108. You.
[0103]
In the current-voltage conversion circuit 12B according to the seventh embodiment having the above-described configuration, the operations of the N-type first transistors M13 and M14 and the N-type second transistors M11 and M12 correspond to the voltage-current shown in FIG. It operates similarly to the first transistors M3 and M4 and the second transistors M1 and M2 of the converter 10B. That is, each of the N-type first transistors M13 and M14 operates as a source follower circuit. Based on the control voltage Vbias2 input to each gate of the N-type first transistors M13 and M14, the threshold voltage is about Vth2. The reduced voltage is output from each source. As a result, the drain voltages of the N-type second transistors M11 and M12 are kept constant, and the drain-source voltage Vds of the N-type second transistors M11 and M12 is kept almost constant.
[0104]
The N-type second transistors M11 and M12 are each biased to operate in an unsaturated region, and currents proportional to the voltages applied to the respective gates are input and output from the differential terminals 107 and 108.
[0105]
Therefore, the current-voltage converter 12 of the seventh embodiment inputs and outputs the differential input / output current Ir proportional to the voltage applied between the differential terminals 107 and 108 from the differential terminals 107 and 108. In other words, it operates so as to generate a voltage proportional to the differential input / output current input / output to / from the differential terminals 107 and 108 between the differential terminals 107 and 108.
[0106]
As described above, the current-voltage conversion circuit 12B of the seventh embodiment operates as a differential current-voltage conversion circuit. Therefore, by applying this to the current-to-voltage converter 12 shown in FIG. 3 (or FIG. 5), the offset control circuit 7 can be realized. In the current-voltage conversion circuit 12B of the seventh embodiment, by adjusting the control voltage Vbias2, the current-voltage conversion coefficient R in (Equation 13) can be adjusted. Therefore, the offset control circuit 7 of the seventh embodiment can function not only as an offset adjustment function but also as a variable amplifier that can change the amplification factor of a signal. It should be noted that the current-voltage converter 12 shown in FIG. 3 (or FIG. 5) may have a circuit configuration as shown in FIG. 9 as described in the first embodiment (or the third embodiment). In addition, the effect that the high-speed operation and the area reduction in the offset control circuits 1 and 3 are not lost at all.
[0107]
(Eighth embodiment)
In the eighth embodiment, the offset control circuit 8 is realized by using a current-voltage conversion circuit 12C as still another specific example of the current-voltage conversion unit 12.
[0108]
FIG. 10 is a circuit diagram showing still another specific example of the current-voltage converter 12 in FIG.
[0109]
In FIG. 10, a P-type transistor M15 is provided between the differential terminals 107 and 108 as the current-voltage conversion circuit 12C. The gate of the P-type transistor M15 is connected to the input / output current control terminal 112, and the control voltage Vbias2 is input to the input / output current control terminal 112.
[0110]
In the current-voltage conversion circuit 12C of the eighth embodiment thus configured, the P-type transistor M15 operates as a variable resistor whose resistance can be controlled according to the control voltage Vbias2 applied to its gate. I do.
[0111]
As described above, the current-voltage conversion circuit 12C according to the eighth embodiment operates as a differential current-voltage conversion circuit. Therefore, by applying this to the current-voltage converter 12 shown in FIG. 3 (or FIG. 5), the offset control circuit 8 of the eighth embodiment can be realized. In the current-voltage conversion circuit 12C of the eighth embodiment, the current-voltage conversion coefficient R in the above (Equation 13) can be adjusted by adjusting the control voltage Vbias2. Therefore, the offset control circuit 8 of the eighth embodiment can function not only as an offset adjustment function but also as a variable amplifier that can change the amplification factor of a signal. Note that, even if the current-voltage converter 12 shown in FIG. 3 (or FIG. 5) has a circuit configuration as shown in FIG. 10, as described in the first embodiment (or the third embodiment). The effect that the offset control circuits 1 and 3 can operate at high speed and reduce the area is not lost at all.
[0112]
(Ninth embodiment)
In the ninth embodiment, the offset control circuit 9 is realized by using an offset adjustment current generation circuit 11A as a specific example of the offset adjustment current generation unit 11.
[0113]
FIG. 11 is a circuit diagram showing a specific example of the offset adjustment current generator 11 in FIG.
[0114]
In FIG. 11, the offset adjustment current generator 11A has a bias current source 307, a pair of P-type transistors M16 and M17, and a pair of offset adjustment current output terminals 101 and 102.
[0115]
The bias current source 307 is connected to each of the sources of the P-type transistors M16 and M17, so that the bias current Iofs branches into two and flows.
[0116]
The gates of the P-type transistors M16 and M17 are respectively connected to offset adjustment current control terminals 103 and 104, and the offset adjustment current control voltages Vofs + and Vofs- are respectively connected to the offset adjustment current control terminals 103 and 104. Is entered. The drains of the P-type transistors M16 and M17 are connected to the offset adjustment current output terminals 101 and 102, respectively, and the offset adjustment currents Iofs + and Iofs− flow.
[0117]
In the offset adjustment current generation circuit 11A of the ninth embodiment configured as described above, the amount of each of the offset adjustment currents Iofs + and Iofs- is adjusted by the offset adjustment current control voltages Vofs + and Vofs-.
[0118]
As described above, by applying the offset adjustment current generation circuit 11A to the offset adjustment current generation unit 11 shown in FIG. 3 (or FIG. 5), the offset control circuit 9 of the ninth embodiment can be realized. .
[0119]
Note that the offset adjustment current generator 11 shown in FIG. 3 (or FIG. 5) may have a circuit configuration as shown in FIG. 11, as described in the first embodiment (or the third embodiment). In addition, the effect that the offset control circuits 1 and 3 can operate at high speed and reduce the area is not lost at all.
[0120]
Further, in the offset adjustment current generating circuit 11A of the ninth embodiment, the bias current source 307, the bias current source 308 having a polarity opposite to that of the P-type transistors M16 and M17, and the P-type transistors M18 and M19 are used. It is also possible to configure an offset adjustment current generation circuit 11B as shown in FIG. Also in this case, as described above, even if the offset adjustment current generation unit 11 shown in FIG. 3 (or FIG. 5) has a circuit configuration as shown in FIG. 12, the first embodiment (or the third embodiment) As described in the embodiment, the effect that the offset control circuits 1 and 3 can achieve high-speed operation and small area is not lost at all.
[0121]
(Tenth embodiment)
In the tenth embodiment, the offset control circuit 10 is realized by using a digitally controllable offset adjustment current generator 13 different from the offset adjustment current generator 11.
[0122]
FIG. 13 is a circuit diagram showing a configuration example different from the offset adjustment current generation unit 11 of FIG.
[0123]
In FIG. 13, the offset adjustment current generator 13 uses an n-bit register signal instead of the offset adjustment current control terminals 103 and 104 of the offset adjustment current generator 11 shown in FIG. 3 (or FIG. 5), where n is a natural number. 1 to 1-bit register signals (offset adjustment current control terminals) 113-1 to 113-n. The offset adjustment currents Iofs + and Iofs- can be controlled with high accuracy depending on the state of the n-bit register signal input from these input terminals 113-1 to 113-n.
[0124]
FIG. 14 is a circuit diagram showing a specific example of the offset adjustment current generator 13 in FIG.
[0125]
In FIG. 14, the offset adjustment current generator 13A has n sub-offset adjustment current generators 13-1 to 13-n. The sub-offset adjustment current generators 13-1 to 13-n respectively include inverters 14-1 to 14-n, bias current sources 309-1 to 309-n, and a pair of P-type transistors M20-1 to M20-n. n and M21-1 to M21-n.
[0126]
The bias current source 309-1 is connected to each of the sources of the P-type transistors M20-1 and M21-1 and branches into two at each of the sources of the P-type transistors M20-1 and M21-1. Bias current flows. Similarly, when n is a natural number, the bias current source 309-n is connected to each of the sources of the P-type transistors M20-n and M21-n, and the bias current source 309-n is connected to the P-type transistors M20-n and M21-n. A bias current flows to each source in two branches. In the bias current sources 309-1 to 309-n, respective current amounts are weighted, and they are respectively Iofs', 2 × Iofs',..., N × Iofs'.
[0127]
The gates of the P-type transistors M20-1 to M20-n are connected to input terminals 113-1 to 113-n, respectively, and the input terminals 113-1 to 113-n each have a 1-bit register signal. Is entered. The input terminals 113-1 to 113-n are respectively connected to the gates of P-type transistors M21-1 to M21-n via inverters 14-1 to 14-n, respectively. A signal obtained by inverting a 1-bit register signal (offset adjustment current control signal) is input to each of the gates of the transistors M21-1 to M21-n.
[0128]
The drains of the P-type transistors M20-1 to M20-n are connected to the offset adjustment current output terminal 101, and the sub-offset adjustment currents Iofs (1) + to Iofs (n) + flow collectively. . The drains of the P-type transistors M21-1 to M21-n are connected to the offset adjustment current output terminal 102, and the sub-offset adjustment currents Iofs (1) to Iofs (n) flow collectively. . As a result, the offset adjustment current Iofs + is a current amount obtained by summing Iofs (1) +, Iofs (2) +,. ) −,... Iofs (n) −.
[0129]
In the offset adjustment current generation circuit 13A of the tenth embodiment configured as described above, the register signal that is a control signal for controlling the offset adjustment current is input from the input terminals 113-1 to 113-n. You. For example, when the register signal input to the input terminal 113-1 becomes H level, the sub-offset adjustment current generation unit 13-1 applies an H level signal to the gate of the P-type transistor M20-1. . Further, since the register signal of the input terminal 113-1 is inverted by the inverter 14-1 and becomes L level, an L level signal is applied to the gate of the P-type transistor M21-1. Both the P-type transistors M20-1 and M21-1 are turned on when an L-level signal is applied to the gate, so that the P-type transistor M20-1 is turned off and Iofs (1) + Does not flow, the P-type transistor M21-1 is turned on, and Iofs (1)-flows out.
[0130]
On the other hand, when the register signal input to the input terminal 113-1 becomes L level, an L level signal is applied to the gate of the P-type transistor M20-1. Further, since the register signal of the input terminal 113-1 is inverted by the inverter 14-1 to become H level, an H level signal is applied to the gate of the P-type transistor M21-1. Therefore, the P-type transistor M20-1 is turned on and Iofs (1) + flows out, and the P-type transistor M21-1 is turned off and Iofs (1)-does not flow.
[0131]
Thus, depending on the state of the register signal input to the input terminal 113-1, one of Iofs (1) + and Iofs (1)-flows in the sub-offset adjustment current generation unit 13-1. The current value when the currents Iofs (1) + and Iofs (1) − flow is equal to the bias current Iofs ′.
[0132]
Similarly, the P-type transistors M20-2 to M20-n are turned on / off according to the state of the register signal input from the input terminals 113-2 to 113-n, and Iofs (2) +,. Iofs (n) + is set, and P-type transistors M21-2 to M21-n are turned on / off to set Iofs (2)-,... Iofs (n)-.
[0133]
At this time, the current sets (Iofs (1) +, Iofs (1) −), (Iofs (2) +, Iofs (2) −),..., (Iofs (n) +, Iofs (n) −) Is such that when one flows, the other does not flow.
[0134]
The register signal is composed of n bits, and there are n types of register signals from when the register signals are all at L level (LL... L) to when all the register signals are at H level (HH... H). .
[0135]
When all the register signals are at the L level, all the P-type transistors M20-1 to M20-n are turned on, the offset adjustment current Iofs + flows, and the amount of the offset adjustment current Iofs + becomes the maximum. At this time, all the P-type transistors M21-1 to M21-n are turned off, and the offset adjustment current Iofs- does not flow.
[0136]
When all the register signals are at the H level, the P-type transistors M21-1 to M21-n are all turned on, the offset adjustment current Iofs- flows, and the current amount of the offset adjustment current Iofs- is maximum. It becomes. At this time, the P-type transistors M20-1 to M20-n are all turned off, and the offset adjustment current Iofs + does not flow.
[0137]
If not all of the register signals are at the L level or all of the H level, the P-type transistors M20-1 to M20-n are turned on by the number of register signals at the L level among the n-bit register signals. In this state, Iofs (1) +, Iofs (2) +,..., Iofs (n) + flow out, and the total value becomes the current value of the offset adjustment current Iofs +. Also, among the n-bit register signals, the P-type transistors M21-1 to M21-n are turned ON by the number of register signals at H level, and accordingly, Iofs (1)-and Iofs (2) ,..., Iofs (n) − flow out, and the total value thereof becomes the current value of the offset adjustment current Iofs−.
[0138]
As described above, the offset adjustment current generation circuit 13A according to the tenth embodiment operates as a DA converter that outputs a differential current, and the offset adjustment currents Iofs + and Iofs− are changed to Iofs + by the n-bit register signal. / N or Iofs- / n. Further, according to the tenth embodiment, the offset adjustment current generator 13 is configured as an n-bit DA converter, and the offset adjustment amount can be controlled by a digital circuit. Offset adjustment can be easily realized.
[0139]
Further, in the offset adjustment current generation circuit 13A shown in FIG. 14, by increasing the number n of bits of the register signal, the accuracy of the current adjustment can be increased. Incidentally, even if the offset adjustment current generator 13 in FIG. 13 is configured as a circuit as shown in FIG. 14, as described in the first embodiment (or the third embodiment), the offset control circuit 1 3 does not lose the effect of enabling high-speed operation and small area.
[0140]
In the offset adjustment current generating circuit 13A of the tenth embodiment, the bias current sources 309-1 to 309-n, the P-type transistors M20-1 to M20-n, and M21-1 to M21-n The connection direction of the inverters 14-1 to 14-n was changed using bias current sources 310-1 to 310-n of opposite polarity and P-type transistors M22-1 to M22-n and M23-1 to M23-n. By providing the inverters 15-1 to 15-n, it is also possible to configure an offset adjustment current generation circuit 13B as shown in FIG. Even if the offset adjustment current generation unit 13 in FIG. 13 has a circuit configuration as shown in FIG. 15, as described in the first embodiment (or the third embodiment), the offset control circuits 1, 3 There is no loss of the effect that high speed operation and small area are possible.
[0141]
【The invention's effect】
As described above, according to the first to twelfth aspects of the present invention, the voltage-current converter that outputs the differential output current (I +, I−) proportional to the potential difference between the differential input voltages (VIN +, VIN−). And a differential input / output current (Ir) proportional to a potential difference between the differential terminals, an offset adjustment current output terminal of an offset adjustment current generator for outputting offset adjustment currents (Iofs +, Iofs−), and a differential terminal. ) Are connected to the differential terminals of the current-to-voltage converter for inputting and outputting, even if the differential input voltage signals (VIN +, VIN−) include the offset voltages (Voff +, Voff−), The offset voltage is adjusted by an offset adjustment current (Iofs +, Iofs-), and an offset adjustment signal corresponding to the offset voltage is added to the differential input voltage signal (VIN +, VIN-). Example was the differential output voltage signal (VO +, VO-) can be generated.
[0142]
In this case, the offset adjustment signal is added to the differential input voltage because the differential input voltage is converted into the differential output current (I +, I−) and then the offset adjustment current (Iofs +, Iofs−) is added. The offset voltage adjustment can be performed at high speed. Further, since an operational amplifier is not required unlike the conventional offset control circuit, the circuit size can be reduced. In addition, by performing differential signal processing, it is resistant to noise and hardly causes signal distortion, so that highly accurate signal processing can be performed.
[0143]
Further, by configuring the offset adjustment current generator with an n-bit DA converter, the control width of the offset adjustment amount can be set by digital control, and the accuracy of the offset adjustment can be increased.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a DVD signal reproduction processing system.
FIG. 2 is a diagram showing an internal configuration of an analog front end and a PRML read channel provided in the DVD signal reproduction processing system.
FIG. 3 is a block diagram illustrating a configuration example according to a first embodiment of the offset control circuit of the present invention.
FIG. 4 is a circuit diagram showing a specific example of a voltage-current converter of FIG. 3;
FIG. 5 is a circuit diagram showing a configuration example according to a third embodiment of the offset control circuit of the present invention.
FIG. 6 is a circuit diagram showing another specific example of the voltage-current converter in FIG. 3;
FIG. 7 is a circuit diagram showing still another specific example of the voltage-current converter in FIG. 3;
FIG. 8 is a circuit diagram showing a specific example of the current-voltage converter in FIG. 3;
FIG. 9 is a circuit diagram showing another specific example of the current-voltage converter in FIG. 3;
FIG. 10 is a circuit diagram showing still another specific example of the current-voltage converter of FIG. 3;
11 is a circuit diagram showing a specific example of the offset adjustment current generator in FIG.
FIG. 12 is a circuit diagram showing another specific example of the offset adjustment current generator of FIG. 3;
FIG. 13 is a circuit diagram showing another configuration example different from the offset adjustment current generation unit in FIG. 3;
FIG. 14 is a circuit diagram showing a specific example of the offset adjustment current generator of FIG.
15 is a circuit diagram showing another specific example of the offset adjustment current generator of FIG.
FIG. 16 is a circuit diagram of a conventional offset control circuit.
[Explanation of symbols]
1-10, 51c offset control circuit
10 Voltage-current converter
10A-10D voltage-current conversion circuit
11 Offset adjustment current generator
11A, 11B,
13, 13A, 13B offset adjustment current generator
12 Current-voltage converter
12A-12C current-voltage conversion circuit
13-1 to 13-n Sub-offset adjustment current generator
14-1 to 14-n,
15-1 to 15-n inverter
40 DVD
50 Front end
51 Analog Front End
60 backend
70 System Controller
101, 102 Offset adjustment current output terminal
103, 104 Offset adjustment current control terminal
105,106 differential current output terminal
107,108 Differential terminal
109,110 differential voltage input terminal
111 control terminal
112 I / O current control terminal
113-1 to 113-n register signal input terminals
115, 116 differential voltage output terminal
301, 302,
307, 308,
309-1 to 309-n,
310-1, 310-n bias current source
M1 to M19,
M20-1 to M20-n,
M21-1 to M21-n, P-type transistors
M22-1 to M22-n,
M23-1 to M23-n N-type transistors
R1 to R4 resistance

Claims (12)

An offset control circuit that receives a differential voltage from a pair of differential voltage input terminals, adjusts an offset voltage included in the differential input voltage, and outputs the adjusted differential voltage from the pair of differential voltage output terminals. At
A pair of differential voltage input terminals and a pair of differential current output terminals, and a pair of differential output currents corresponding to a potential difference between the pair of differential input voltages input from the pair of differential voltage input terminals. A voltage-current converter that generates and outputs the pair of differential output currents from the pair of differential current output terminals;
An offset adjustment current output terminal connected to a pair of differential current output terminals of the voltage-current converter and two or more offset adjustment current control terminals, and an offset input from the offset adjustment current control terminal An offset adjustment current generation unit that is controlled by the adjustment current control signal, generates a pair of offset adjustment currents, and outputs the pair of offset adjustment currents from the pair of offset adjustment current output terminals.
A pair of differential current output terminals of the voltage-current conversion unit, a pair of offset adjustment current output terminals of the offset adjustment current generation unit, and a pair of differential terminals connected to the pair of differential voltage output terminals. Then, a current is caused to flow between two differential terminals constituting the pair of differential terminals, the current is converted into a voltage corresponding to the current, and the converted voltage is output to the pair of differential voltage output terminals. An offset control circuit, comprising: a current-to-voltage converter that generates the current. The offset control circuit according to claim 1,
The voltage-current converter,
A pair of bias current sources connected to the pair of differential current output terminals,
A pair of first transistors, each of the pair of differential current output terminals being respectively connected to each first drive terminal, and each gate being commonly connected to a control terminal;
The second drive terminals of the pair of first transistors are respectively connected to the respective first drive terminals, the gates thereof are respectively connected to the pair of differential voltage input terminals, and the respective second drive terminals are respectively connected. An offset control circuit, comprising: a pair of second transistors each connected to a reference potential supply point. An offset control circuit that receives a differential voltage from a pair of differential voltage input terminals, adjusts an offset voltage included in the differential input voltage, and outputs the adjusted differential voltage from the pair of differential voltage output terminals. At
The pair of differential voltage input terminals, and a voltage-current converter having a pair of differential current output terminals connected to the pair of differential voltage output terminals,
A pair of offset adjustment current output terminals, and an offset adjustment current generation unit having two or more offset adjustment current control terminals,
A current-to-voltage converter having a pair of differential terminals,
The voltage-current converter,
A pair of bias current sources to which the pair of differential current output terminals are connected,
A pair of first transistors having the pair of differential current output terminals connected to a first drive terminal and the gates connected to a pair of control terminals;
A second drive terminal of the pair of first transistors is connected to a first drive terminal, a gate is connected to each of the pair of differential voltage input terminals, and a second drive terminal is connected to a reference potential supply point. And a second transistor of
A pair of differential output currents are generated in accordance with a potential difference between the pair of differential input voltages input from the pair of differential voltage input terminals, and the differential output currents are output from the pair of differential current output terminals. Things,
The offset adjustment current generator,
The pair of offset adjustment current output terminals are connected to a first drive terminal of a pair of second transistors of the voltage-current converter,
An offset adjustment current control signal input from the offset adjustment current control terminal generates a pair of offset adjustment currents, and outputs the pair of offset adjustment currents from the pair of offset adjustment current output terminals. ,
The current-voltage converter,
The pair of differential terminals are connected to the pair of differential current output terminals of the voltage-current converter,
A current flows between two differential terminals constituting the pair of differential terminals, the current is converted into a voltage corresponding to the current, and the converted voltage is generated at the pair of differential voltage output terminals. An offset control circuit, characterized in that: The offset control circuit according to claim 1,
The voltage-current converter,
A pair of bias current sources to which each of the pair of differential current output terminals is connected,
A pair of second transistors, each of the pair of differential current output terminals connected to each of the first drive terminals, and a gate thereof connected to each of the pair of differential voltage input terminals;
Each pair of second driving terminals of the pair of second transistors is connected to each first driving terminal, each gate is commonly connected to a control terminal, and each second driving terminal is connected to a reference potential supply point. A first transistor of
An offset control circuit comprising: a resistor having a predetermined resistance value connected between each second drive terminal of the pair of second transistors. The offset control circuit according to claim 1,
The voltage-current converter,
A pair of bias current sources to which each of the pair of differential current output terminals is connected,
Each of the pair of differential current output terminals is connected to each of the first drive terminals, each of its gates is connected to each of the pair of differential voltage input terminals, and each of the second drive terminals is connected to a reference potential supply point. An offset control circuit, comprising: a pair of transistors connected to each other. The offset control circuit according to claim 1 or 3,
The offset control circuit according to claim 1, wherein the current-voltage converter is a resistor having a predetermined resistance value connected between the pair of differential terminals. The offset control circuit according to claim 1 or 3,
The current-voltage converter,
A pair of third transistors, each of the pair of differential terminals being connected to each first drive terminal, and each gate thereof being commonly connected to an input / output current control terminal;
The second driving terminals of the pair of third transistors are respectively connected to the first driving terminals, the gates thereof are respectively connected to the pair of differential terminals, and the second driving terminals are connected to the reference potential supply. An offset control circuit, comprising: a pair of fourth transistors each connected to a point. The offset control circuit according to claim 1 or 3,
The offset control circuit, wherein the current-voltage converter is a fifth transistor connected between the pair of differential terminals, and an input / output current control terminal is connected to a gate of the fifth transistor. The offset control circuit according to claim 1 or 3,
The offset adjustment current generator,
A current source;
Each of the second drive terminals is connected to the current source, two of the offset adjustment current control terminals are respectively connected to the gates, and the pair of offset adjustment current output terminals are respectively connected to the first drive terminals. And a sixth transistor. The offset control circuit according to claim 1 or 3,
The offset adjustment current generator has n (n is a natural number) sub-offset adjustment current generators,
Each of the sub-offset adjustment current generation units includes:
an offset adjustment current control terminal to which a non-overlapping one-bit signal of the n-bit register signal is input;
A current source;
Each of the second drive terminals is connected to the current source, and the offset adjustment current control terminal is connected to one of the gates and connected to the other of the gates via an inverter, and the first drive terminal is connected to the first drive terminal. And a pair of seventh transistors to which the pair of offset adjustment current output terminals are respectively connected,
An offset control circuit, wherein a pair of sub-offset adjustment currents generated by the sub-offset adjustment current generator are supplied to each of the pair of offset adjustment current output terminals. An offset control circuit according to claim 1 or 3,
A processing circuit that performs a predetermined process on the differential output voltage whose offset voltage has been adjusted by the offset control circuit,
A signal processing device, wherein the offset control circuit and the processing circuit are formed on one chip. The signal processing device according to claim 11, wherein
The signal processing device constitutes a DVD playback device,
The offset control circuit adjusts an offset voltage included in a signal read from the DVD, and outputs the adjusted signal as a differential output voltage;
The processing circuit includes:
A front end including a filter for filtering a differential output voltage having an offset voltage adjusted by the offset control circuit;
A signal processing apparatus comprising: a back end that converts an output signal of the front end into a video signal and an audio signal.

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