JP2004088405A - Image processing device - Google Patents

Abstract

When the intervals of gray scales that can be displayed by a display device are not equal, it is difficult to increase the gray scale in a pseudo manner by using both error diffusion processing and dither processing.
The number of bits b of an image signal input to a display device 103 is at least Log2 (n × m) ≦ Δb
The number-of-bits extension means 100 for increasing the number of bits of the image signal by Δb that satisfies the following equation: m) A gradation restriction table for restricting an image signal to twice as many gradations, a gradation restriction unit 101 for performing an error diffusion process using the restricted difference as a display error, and an image signal using a dither element depending on the image signal. And a level conversion means 104 for finally converting the image signal into an image signal of b bits and c gradations.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing apparatus for performing halftone display of a display device having a characteristic in which displayable gradations are discrete and gradation intervals are not equal.
[0002]
[Prior art]
In a display device such as a plasma display panel (PDP) or a liquid crystal display device, if the number of displayable gray scales (hereinafter simply referred to as display gray scales) is not sufficient, it is difficult to express a smooth halftone, and Is observed as a pattern (so-called false contour) like a contour line of a map, and image display quality is significantly deteriorated. In this case, error diffusion processing and dither processing are known as techniques for increasing the number of gray levels in a pseudo manner.
[0003]
Hereinafter, a general method when the error diffusion processing and the dither processing are used together will be described with reference to the drawings. As an example, it is assumed that the input image signal is 256 gradations of 8 bits, the display gradation of the display device is 32 gradations of 5 bits, and the dither matrix (n × m) of the dither processing means is n = 2 and m = 2. At this time, the intervals of the display gradation of the display device used here are equal.
[0004]
In FIG. 8, an error diffusion circuit 802 receives an 8-bit image signal 801, performs an error diffusion process on a lower 1-bit signal, and sends the upper 7 bits to a next dither circuit 803. The dither circuit 803 performs dither processing on the 7-bit signal and outputs a 5-bit image signal to the display device 804.
[0005]
First, the error diffusion processing will be described. Now, assume that signal processing of the pixel P0 shown in FIG. 9 is performed. At this time, a predetermined weighting process as shown in FIG. 9 is performed on the display error of the pixels P1, P2, P3 and the immediately preceding pixel P4 one line before the pixel P0, that is, the value of the lower one bit, and the input image of the pixel P0 Add to the signal. The lower 1 bit, which is a display error of the pixel P0, is subjected to a predetermined weighting process and diffused to surrounding pixels P5, P6, P7, P8. The solid arrow in FIG. 9 indicates an error added to P0 from surrounding pixels, and the dotted arrow indicates an error diffused from P0 to surrounding pixels. Numerical values attached to the arrows indicate the magnitude of each weight. FIG. 10 is a block diagram of the error diffusion circuit. T in the block indicates a one-pixel delay circuit, H indicates a one-line delay circuit, and the numerical value of each block following each delay circuit indicates the magnitude of each weight. As shown in FIG. 10, the upper 7 bits of the result of the addition are output to the dither circuit 803. Regarding the error of the lower 1 bit, 7/16 is assigned to the pixel P5 next to the pixel P0, 3/16 is assigned to the pixel P6 at the lower left of the pixel P0, 5/16 is assigned to the pixel P7 immediately below the pixel P0, and 3/16 is added to the pixel P8 at the lower left of the pixel P0. By performing such addition for each pixel, the error is diffused to surrounding pixels.
[0006]
Next, signal processing in the dither circuit 803 will be described. FIG. 11A shows an arrangement of a 2 × 2 dither matrix, where the upper left dither element is d1, the lower right is d2, the lower left is d3, and the upper right is d4. FIG. 11B shows a case where d1 = 0, d2 = 1, d3 = 2, and d4 = 3 in FIG. 11A. FIG. 11C shows an example of a 7-bit image signal after being processed by the error diffusion circuit 802. The dither circuit 803 adds the dither elements shown in FIG. The result of addition is shown in FIG. 11 (d). Since this signal is 7 bits, the lower 2 bits are truncated to form FIG. 11 (e), and finally only the upper 5 bits are taken out to obtain FIG. 11 (f). Get the value of
[0007]
The principle of the dither processing performed here is as follows. If the lower 2 bits of the original 7 bits are 0, that is, XXXXXX00 (X = 1 or 0) in binary notation, the upper 5 bits do not increase regardless of which dither element is added. For example, when the image signal is 20, it is 0010100 in binary notation and the dither element 3 is 0000011. Therefore, when these are added, it becomes 0010111, and the upper 5 bits do not increase. The same applies to dither elements 2 and 1.
[0008]
When the lower 2 bits of the original 7 bits are 1, the upper 5 bits are carried up only when the dither element is 3. For example, when the image signal is 21, the binary number is 0010101 and the dither element 3 is 0000011. Therefore, when these are added, they become 24, that is, 001000, and the upper 5 bits are carried up. Since the probability that the dither element is 3 is 1/4, the probability that the upper 5 bits are carried up in this case is 1/4.
[0009]
Similarly, if the lower 2 bits of the original 7 bits are 2, the upper 5 bits are carried up when the dither elements are 3 and 2. Since the probability that the dither element is 3 or 2 is 1/4, respectively, the probability that the upper 5 bits are carried up in this case is 2/4.
[0010]
Further, if the lower 2 bits of the original 7 bits are 3, the upper 5 bits are carried up when the dither elements are 3, 2 and 1, and the probability is 3/4.
[0011]
Therefore, for example, if the original 7 bits are 21, it is rounded up to 24 with a probability of 1/4, otherwise it is rounded down to 20 at last, so the average of the image after dither processing is 20. An appropriate gradation is 24 × １ ／ + 20 × 3/4 = 21. As described above, finally, the original 7 bits can be represented by 5 bits in a pseudo manner.
[0012]
In this example, a dither matrix of (n × m) = (2 × 2) has four dither elements d1 to d4, and thus represents two bits (four gradations) in a pseudo manner. If a dither matrix of (n × m) = (4 × 4) is used, four bits (16 gradations) can be represented in a pseudo manner since there are 16 dither elements.
[0013]
[Problems to be solved by the invention]
The above-described gradation correction method is for displaying a halftone image favorably on a display device in which the display gradation intervals are equal. On the other hand, in the case of a display device in which the intervals between display gradations are not equal, such an image processing method is not effective. For example, in the case of a display device having display gradations of 0, 1, 3, 7, 13, 23, 37, 56, 82, 115, 155, 202, and 255, the dither matrix used is If the above is the same as above, if the gradation value is 13 or more, even if dither processing is performed, no carryover occurs and there is no effect. On the other hand, if the value of the gradation is 3 or less, the carry-up is too large, and on the contrary, the image quality is deteriorated. This is because the values of the four dither elements d1 to d4 are fixed.
[0014]
On the other hand, Japanese Patent Application Laid-Open No. 8-286634 discloses that in a display device in which a plurality of pixel units are arranged in a two-dimensional matrix format, after adding a dither pattern corresponding to an input image signal, A halftone display method for performing an error diffusion process is disclosed. In this method, the threshold value of error diffusion can be changed for each gradation, for each dot, and for each line by an input signal and a signal from a timing generator. By selecting the optimal dither pattern according to the gradation of the input image signal before performing the error diffusion processing, flicker and fixed pattern can be compared with the conventional halftone display method that always inserts a fixed dither pattern. Etc. can be suppressed. However, in this example, dither processing is used not for improving the gradation but for preventing the flicker by scattering the threshold values of the error diffusion in a staggered manner. Therefore, in the case of a display device in which the number of display gradations of the display device is not sufficient and the intervals between the gradations are not equal, there is a problem that a sufficient halftone display cannot be performed.
[0015]
The present invention enables smooth halftone expression even in a display device having such a small number of display gradations.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the image processing apparatus according to the present invention is configured so that at least Log2 (n × m) ≦ Δb
A bit number extending means for increasing the number of bits of the image signal by Δb which satisfies the following condition, and approximately (n × m) times the number of gradations in a pseudo manner by dither processing. A gradation restriction table for restricting an image signal to n × m) times gradation, gradation restriction means for performing an error diffusion process using the restricted difference as a display error, and an image using a dither element dependent on the image signal. Level converting means for dithering the signal and finally converting the signal into an image signal of b bits and c gradations.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
That is, according to the first aspect of the present invention, at least Log2 (n × m) ≦ Δb (m, n) with respect to the number of bits of an image signal input to a display device having a characteristic in which displayable gradation intervals are not constant. Is a natural number)
Bit number expansion means for increasing the number of bits of the image signal by Δb that satisfies the following equation, and outputting the first image signal as a first image signal; A gradation restriction table for restricting the output to a gradation obtained by equally dividing the interval into (n × m), a first image signal restricted to the gradation of the gradation restriction table, and output as a second image signal; A gradation limiting unit that performs an error diffusion process using a difference generated by the limitation as a display error, and a dither matrix (n × m) determined based on the second image signal. An image processing apparatus includes dither processing means for performing dither processing and outputting the third image signal as a third image signal, and level conversion means for converting the third image signal into a bit number and a gradation that can be displayed on a display device.
[0018]
According to a second aspect of the present invention, in the first aspect, the bit number extending means has an inverse gamma correction circuit and an error diffusion circuit, and the inverse gamma correction circuit temporarily converts the input image signal into a first image signal. An image processing apparatus for converting an image signal into an image signal having a larger number of bits.
[0019]
Further, the invention according to claim 3 is inserted in claim 1 in order to equally divide (n × m) each of the gradations obtained by multiplying the displayable gradation by (n × m) ( For n × m−1) gradations, i = 2, 3,..., n × m
, The probability that the i-th gray scale is raised to the larger value of the gray scale obtained by multiplying the displayable gray scale by (n × m) is (i−1) / (n × m)
And the probability of not moving is {(n × m) − (i−1)} / (n × m)
An image processing apparatus characterized in that the value of a dither element of a dither matrix is set such that
[0020]
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0021]
(Embodiment 1)
The configuration and operation of the image processing apparatus according to the first embodiment will be described below. In this embodiment, the input image signal is 8 bits and 256 gradations, the dither matrix (n × m) of the dither processing means is n = 2 and m = 2, and the display gradation of the display device is 8 bits and 13 gradations. An example in which display intervals are provided and display intervals are not equal intervals will be described as an example. Here, it is assumed that the specific display gradation is (0, 1, 3, 7, 13, 23, 37, 56, 82, 115, 155, 202, 255).
[0022]
In FIG. 1, an 8-bit input image signal (image signal A) 106 is converted into a 10-bit image signal B by a bit number expansion unit 100. Next, the image signal B is converted by the gradation limiting means 101 into an image signal C whose gradation is limited to 49 gradations while keeping 10 bits. Further, the image signal C is subjected to dither processing by the dither processing means 102 to be converted into a 10-bit image signal D. Then, the image signal D is converted by the level conversion means 104 into an image signal E of 8 bits and 13 gradations, and an image is finally displayed on the display device 103 based on the image signal E.
[0023]
Each process will be described below.
[0024]
As shown in FIG. 2, the bit number extending means 100 includes an inverse gamma correction circuit 200 and a first error diffusion circuit 201. The inverse gamma correction circuit 200 performs inverse gamma correction on the 8-bit image signal A (x = 0 to 255) according to the following equation to convert it into a 12-bit image signal (y = 0 to 4095).
[0025]
y = (x / 255) ＾ 2.2 × 4095
Here, it should be noted that the increase from 8 bits to 12 bits is the dynamic range (the ratio between the maximum gradation and the gradation 1) of the image signal, and does not mean that the number of gradations itself has increased. . The gradations that can be expressed are 256 kinds of y values corresponding to 256 kinds of x values (x = 0 to 255).
[0026]
Next, the first error diffusion circuit 201 performs a first error diffusion process using the lower 2 bits of the 12-bit image signal after the inverse gamma correction as a display error to generate a 10-bit image signal (image signal B). Output. Since the first error diffusion processing is almost the same as the conventional technique, detailed description will be omitted. However, in the prior art, an example in which the lower 1 bit of an 8-bit input signal is spread and the upper 7 bits are used as an output signal has been described. In the present embodiment, the lower 2 bits of a 12-bit input signal are spread and the upper 10 bits are spread. Is an output signal.
[0027]
Next, the gradation limiting means 101 will be described.
[0028]
The display gradation of the display device used in the present embodiment is the following 8-bit 13 gradations (0, 1, 3, 7, 13, 23, 37, 56, 82, 115, 155, 202, 255). . If these are multiplied by four and expressed by 10 bits, they are (0, 4, 12, 28, 52, 92, 148, 224, 328, 460, 620, 808, 1020). Hereinafter, this is abbreviated as 4 magnification display gradation. Here, if three gradations are inserted at equal intervals so as to divide the respective gradations into four equal parts, 10-bit 49 gradations (0, 1, 2, 3, 4, 6, 8, 10, 12, 16, 16) , 20, 24, 28, 34, 40, 46, 52, 62, 72, 82, 92, 106, 120, 134, 148, 167, 186, 205, 224, 250, 276, 302, 328, 361, 394 , 427, 460, 500, 540, 580, 620, 667, 714, 761, 808, 861, 914, 967, 1020). Hereinafter, this is abbreviated as a four-fold expanded display gradation. The quadruple expanded display gray scale is anticipated to increase the gray scale to 4 times in a pseudo manner by using the dither processing unit 102 later.
[0029]
The gradation limiting unit 101 limits the 10-bit image signal B to the above 49 quadruple expanded display gradations. FIG. 3 is a circuit block diagram of the gradation limiting unit 101. T in the block indicates a one-pixel delay circuit, and H indicates a one-line delay circuit. The gradation limiting unit 101 limits the output image signal C to a four-fold expanded display gradation by using the gradation restriction table 301, and uses the difference between the input image signal B and the gradation-limited signal as a display error as a second error. Is performed. Now, it is assumed that attention is paid to a certain pixel P0 and a corresponding 10-bit image signal B is input. At this time, the predetermined weights shown in FIG. 3, that is, 1/16, 5/16, 3/16 and 7/16 are applied to the display errors of the pixels P1, P2, P3 and the immediately preceding pixel P4 one line before the pixel P0. Multiplied and added to the input signal of the pixel P0. The added signal is compared with the numerical value of the gradation limit table 301, that is, the quadruple expanded display gradation, and the numerical value closest to the added signal is output as the image signal C. At the same time, the difference between the original signal and the output signal is set as a display error, and 7/16 is set as the pixel P5 next to the pixel P0, 3/16 is set as the pixel P6 at the lower left of the pixel P0, and 5/16 is set as the pixel error. 1/16 is diffused to the pixel P7 immediately below the pixel P0, and 1/16 is diffused to the pixel P8 below the pixel P0.
[0030]
The configuration of the gradation limit table 301 may be, for example, a ROM table that outputs an image signal C and a display error with respect to an input signal. A combination of subtraction circuits for calculating the display error by subtracting the signal C may be used.
[0031]
Next, the dither processing means 102 will be described.
[0032]
The dither element determination circuit 401 outputs the dither element determined based on the image signal C to the dither circuit 400. As shown in FIG. 4, the values of the dither elements (d1 to d4) are determined for each of the 49 possible gradations of the image signal C. The dither element used in the present embodiment is determined as follows. First, among the four-times expanded display gradations, all four dither elements are set to 0 for a gradation that matches the four-times display gradation. Otherwise, of the three gray levels inserted to divide the gray levels into four equal parts, three of the four dither elements are set to 0 for the smallest gray level, and the second smallest gray level , Two of the four dither elements are set to 0, and for the third smallest gradation, one of the four dither elements is set to 0. If the gradation is not 0, the difference between the smallest gradation that is equal to or higher than the gradation among the four-magnification display gradations and the gradation. For example, when the image signal C is 82, the difference between the 4th magnification display gradation 92 which is equal to or greater than 82 and the smallest gradation and the gradation 82 is 10, so that d1 = 0, d2 = 10, d3 = 10, d4. = 10. Here, when the transmitted image signal C is at a position corresponding to d4 of the dither matrix, the value output to the dither circuit 400 is 10.
[0033]
Next, signal processing in the dither circuit 400 will be described with reference to FIG. FIG. 5A shows an arrangement of a dither matrix used in the present embodiment, wherein the upper left dither element is d1, the lower right is d2, the lower left is d3, and the upper right is d4. For the sake of explanation, it is assumed that the image signal C for each pixel is as shown in FIG. At this time, the dither element corresponding to each image signal C is determined by the table of FIG. 4 and is represented as shown in FIG. The dither circuit 400 adds the image signal C and the corresponding dither element for each pixel and outputs the result as an image signal D. FIG. 5D shows the result of adding these two values. This is the image signal D. As described above, the dither element is optimally determined according to the image signal C, and is converted into the image signal D.
[0034]
Next, the level conversion means 104 will be described. The level conversion means 104 performs truncation of the image signal D using the 4 magnification display gradation (0, 4, 12, 28, 52, 92, 148, 224, 328, 460, 620, 808, 1020) as a threshold. , And divide the result by 4. FIG. 5E shows the result of the truncation, and FIG. 5F shows the result of dividing by 4. For example, the value of the image signal D corresponding to the pixel in the first row and the third column in FIG. Therefore, it is rounded down to 52, which is the largest value below 82, and divided by 4 to be 13. In addition, the value of the image signal C in the first row and the second column is 92, and in this case, no round-down occurs and the value is divided by 4 to 23. As described above, the image signal D is finally converted into an 8-bit, 13-gradation image signal E that can be displayed on a display device.
[0035]
The result of the dither processing performed here will be described by taking as an example a range between 52 and 92, which are four-magnification display gradations. When the value of the image signal C is 52, the signal does not change and remains at 52 because all four dither elements are 0. When the value of the image signal C is 62, among the four dither elements, d1 to d3 are 0 and only d4 is 30, so that the probability of being cut down to 52 by the level conversion means 104 is 3/4, and it goes up to 92. The probability is 1/4. As a result, since 52 × 3/4 + 92 × １ ／ = 62, 62 was obtained on average. When the value of the image signal C is 72, d1 and d2 of the dither elements are 0 and d3 and d4 are 20, so that the probability of falling to 52 is 2/4 and the probability of rising to 92 is 2/4. Yes, an average of 72 is obtained. Similarly, when the value of the image signal C is 82, the probability of being rounded down to 52 is 1/4, the probability of being raised to 92 is 3/4, and 82 is displayed on average. In this way, pseudo gradation expression is performed according to the principle of the original dither processing, and the same applies to other gradations.
[0036]
By such image processing, even in a display device having characteristics in which display gradations are discrete and gradation intervals are not equal, a good halftone image is displayed by using both error diffusion processing and dither processing. be able to. For example, a liquid crystal display device driven by a TFT, a liquid crystal display device driven by a dot matrix method using an STN liquid crystal material, or a PDP device in which image contrast is reduced or a false contour is generated by using a subfield method. , A good halftone can be displayed.
[0037]
In particular, in the present invention, the image data is extended to 10 bits by using the bit number extending means. This is because even if the display grayscale interval is 1, the interval between the display grayscales is divided into four and three grayscales are inserted, so that the effect of the dither processing can be reliably obtained. The display gradations of the display device used here are 0, 1, 3, 7, 13, 23, 37, 56, 82, 115, 155, 202 and 255, and the gradation intervals are small in the low luminance portion. Has become. Visually, the sensitivity to the luminance change in the low luminance portion is high. Therefore, it is particularly important to faithfully reproduce the gradation between 0 and 1 and between 1 and 3. Means for expanding the number are essential.
[0038]
In this embodiment, the input image signal has been described as 8 bits, the dither matrix has 2 × 2, and the number of display gradations has 13 gradations. At this time, the reason why the image signal was limited to 49 gradations, which is a 4-fold extended display gradation, was that the number of elements of the dither matrix was 4 (= 2 × 2). The reason why the 10-bit 13-gradation obtained by quadrupling the 8-bit 13-gradation that can be expressed by the display device is used is to accurately produce 49 gradations divided into four equal parts. Further, for the same reason, the gradation number is extended from 8 bits to 10 bits by the bit number extension means.
[0039]
However, the present invention is not limited to this. Generally, when the input image signal is b bits, the dither matrix is (n × m), and the number of display gradations is c, the number of bits of the input image is set to b + log 2 (n × m) by the bit number expansion unit.
In the following gradation limiting means, a gray scale obtained by multiplying the display gray scale c by (n × m) (hereinafter abbreviated as mn magnification display gray scale) is expressed by (n × m) or the like. In the following dither circuit, a dither matrix is added to the divided gray scales (abbreviated as mn-fold extended display gray scales), and the subsequent level conversion circuit rounds down the display scale to the mn magnification display gray scale in the display device. Then, by dividing by (nxm), an image signal to be displayed on the display device can be obtained.
[0040]
The dither matrix used here is created as follows.
[0041]
First, among the gradations output from the gradation limiting unit, all the (n × m) dither elements are set to 0 for the gradation that matches the mn magnification display gradation. Next, among the (n × m−1) gradations inserted to equally divide the mn magnification display gradation between (n × m), the (n × m) gradation is the smallest gradation. (N × m−1) of the elements are set to 0, and (n × m−2) of the (n × m) elements are set to 0 for the second smallest gradation. Similarly, for the i-th smallest gradation, (n × m−i) elements among the (n × m) elements are set to 0. A non-zero dither element is the difference between the mn magnification display gradation and the smallest one that is equal to or higher than the gradation and the gradation.
[0042]
That is, the dither element in the general case is obtained according to the following equation.
[0043]
The display gradation of the display device is {0,..., R, s,.
And At this time, the mn magnification display gradation is {0,..., (N × m) × r, (n × m) × s,.
It becomes. The gradation that divides n × m equally between (n × m) × r and (n × m) × s is (n × m) × r, (n × m) × r + (s−r) × 1 , (N × m) × r + (s−r) × 2, (n × m) × r + (s−r) × 3,..., (N × m) × r + (s−r) × (i −1),..., (N × m) × r + (s−r) × (n × m−1)
It becomes.
[0044]
Here, (n × m) × r + (s−r) × (i−1) is a gradation obtained by equally dividing (n × m) × r and (n × m) × s by n × m. Out of (n × m) × r is the first to i-th gradations. Using these symbols, each dither element for the i-th gradation is set as follows.
[0045]
d (nxm-0) = (sr) x {(nxm)-(i-1)}
d (n × m−1) = (s−r) × {(n × m) − (i−1)}
・
・
d (n × m− (i−2)) = (s−r) × {(n × m) − (i−1)}
d (nxm- (i-1)) = 0
・
・
d2 = 0
d1 = 0
For example, in the example used in the present embodiment, if m = 2, n = 2, r = 13, and s = 23, the dither element for 52 (i = 1) in the gradation restriction table is
d4 = 0
d3 = 0
d2 = 0
d1 = 0
It becomes. The dither element for 62 (i = 2) in the gradation restriction table is
d4 = (23−13) × {(2 × 2) − (2-1)} = 30
d3 = 0
d2 = 0
d1 = 0
It becomes. The dither element for 72 (i = 3) in the gradation restriction table is
d4 = (23−13) × {(2 × 2) − (3-1)} = 20
d3 = (23−13) × {(2 × 2) − (3-1)} = 20
d2 = 0
d1 = 0
It becomes. The dither element for 82 (i = 4) in the gradation restriction table is
d4 = (23−13) × {(2 × 2) − (4-1)} = 10
d3 = (23−13) × {(2 × 2) − (4-1)} = 10
d2 = (23−13) × {(2 × 2) − (4-1)} = 10
d1 = 0
Thus, it can be seen that the values coincide with the table of FIG.
[0046]
(Embodiment 2)
In the present embodiment, a result similar to that of the first embodiment can be obtained even if the circuit scale is reduced by simplifying the dither element determination circuit. The dither circuit and the level converting means of the gradation expanding means, the gradation limiting means and the dither processing means of the present embodiment are the same as those of the first embodiment, and therefore their explanation is omitted. The present embodiment differs from the first embodiment in the value of the dither element of the dither element determination circuit. As shown in FIG. 6, the dither elements of the dither matrix corresponding to the four gradations obtained by dividing the four-magnification display gradation into four equal parts are all set to the same value. For example, the dither elements for gradations 52, 62, 72, and 82 have the same value as d1 = 0, d2 = 10, d3 = 20, and d4 = 30. Therefore, the process of setting the dither element based on the image signal is simplified, so that the circuit scale and the memory capacity can be reduced.
[0047]
The configuration will be described below together with the operation. In this embodiment, as in the first embodiment, the input image signal has 256 gradations of 8 bits, the dither matrix (n × m) of the dither processing means is n = 2, m = 2, and the display floor of the display device. It is assumed that the tone is (0, 1, 3, 7, 13, 23, 37, 56, 82, 115, 155, 202, 255) with 8 bits and 13 tones.
[0048]
The dither element used in the present embodiment is determined as follows. First, d1 of the four dither elements is all set to 0 regardless of the gradation. Next, K1, K2, and K3 (assuming that K1 <K2 <K3) are used as the three gradations inserted to divide the four-magnification display gradation into four equal parts. The display gradation is K4. d2 is the difference between the largest gradation among the three gradations and K4 (in this case, K4-K3). d3 is the difference between the second largest gradation among the three gradations and K4 (in this case, K4-K2). d4 is the difference between the smallest gradation among the above three gradations and K4 (in this case, K4-K1). For example, for gradations 52, 62, 72, and 82, K1 = 62, K2 = 72, K3 = 82, and K4 = 92, so that d1 = 0, d2 = 92−82 = 10, and d3 = 92. −72 = 20, d4 = 92−62 = 30, and the dither coefficient shown in FIG. 6 is obtained.
[0049]
FIG. 7 shows the result of performing dither processing using the dither element according to the present embodiment. FIG. 7A shows an arrangement of a dither matrix used in the present embodiment, which is the same as that in the first embodiment. It is assumed that the image signal C for each pixel is as shown in FIG. This is also the same as in the first embodiment. At this time, the dither element corresponding to each image signal C is determined by the table of FIG. 6 and is represented as shown in FIG. 7B. The dither circuit 400 adds the image signal C and the corresponding dither element for each pixel and outputs the result as an image signal D. FIG. 7D shows the result of adding these two values. The signal values in FIGS. 7B and 7D have different values from FIGS. 5B and 5D corresponding to the first embodiment. The subsequent level conversion means 104 uses the 4 magnification display gradation (0, 4, 12, 28, 52, 92, 148, 224, 328, 460, 620, 808, 1020) as a threshold to cut off the image signal D. And divide the result by four. FIG. 7E shows the result of the truncation, and FIG. 7F shows the result of dividing by 4. At this point, it can be seen that the values have returned to the same values as in FIGS. 5E and 5F corresponding to the first embodiment. Thus, by setting the dither elements as shown in the table of FIG. 6, the same result as in the first embodiment could be obtained.
[0050]
With the above processing method, it is possible to display a good halftone image by using both the error diffusion process and the dither process even in a display device having a characteristic in which display gradations are discrete and gradation intervals are not equal. Become. In addition, since the process of setting the dither element based on the image signal output after the error diffusion is simplified, the circuit scale can be reduced and the memory capacity can be reduced. As a result, an image processing device capable of pseudo-halftone expression at low cost can be realized.
[0051]
In this embodiment, generally, when the input image is b bits, the dither matrix is n × m, and the number of display gradations is c, the dither coefficient is obtained as follows.
[0052]
The display gradation of the display device is {0,..., R, s,.
And At this time, the mn magnification display gradation is {0,..., (N × m) × r, (n × m) × s,.
It becomes. The gradation that divides n × m equally between (n × m) × r and (n × m) × s is (n × m) × r, (n × m) × r + (s−r) × 1 , (N × m) × r + (s−r) × 2, (n × m) × r + (s−r) × 3,..., (N × m) × r + (s−r) × (i −1),..., (N × m) × r + (s−r) × (n × m−1).
[0053]
Here, (n × m) × r + (s−r) × (i−1) is a gradation obtained by equally dividing (n × m) × r and (n × m) × s by n × m. Out of (n × m) × r is the first to i-th gradations. Using these symbols, each dither element is set as follows.
[0054]
d1 = {(n × m) × s} − {(n × m) × r + (s−r) × (n × m−0)} = 0
d2 = {(n × m) × s} − {(n × m) × r + (s−r) × (n × m−1)}
d3 = {(n × m) × s} − {(n × m) × r + (s−r) × (n × m−2)}
d4 = {(n × m) × s} − {(n × m) × r + (s−r) × (n × m−3)}
・
・
di = {(n × m) × s} − {(n × m) × r + (s−r) × (n × m− (i−1))}
・
・
d (n × m) = {(n × m) × s} − {(n × m) × r + (s−r) × (n × m− (n × m−1))}
= {(N × m) × s} − {(n × m) × r + (s−r) × 1}
For example, in the example used in the present embodiment, m = 2, n = 2, r = 13, and s = 23. At this time, the dither element for 52 (i = 1) in the gradation restriction table is
d1 = {(2 × 2) × 23} − {(2 × 2) × 13 + (23−13) × (2 × 2-0)} = 0
d2 = {(2 × 2) × 23} − {(2 × 2) × 13 + (23−13) × (2 × 2-1)} = 10
d3 = {(2 × 2) × 23} − {(2 × 2) × 13 + (23−13) × (2 × 2-2)} = 20
d4 = {(2 × 2) × 23} − {(2 × 2) × 13 + (23−13) × (2 × 2-2)} = 30
Thus, it can be seen that the result matches the table of FIG.
[0055]
【The invention's effect】
By adopting such a configuration, even a display device having display characteristics in which display grayscales are discrete and in which the intervals between the grayscales are not equal intervals is pseudo continuous grayscales. It is possible to realize an image display device capable of expressing and achieving good halftone display. Further, by simplifying the value of the dither element of the dither matrix, the memory capacity of the dither element output means and the circuit scale of the dither circuit can be reduced, so that the cost of the image processing apparatus can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram of an image processing apparatus according to Embodiments 1 and 2 of the present invention. FIG. 2 is a diagram illustrating a bit number extension unit of the image processing apparatus according to Embodiments 1 and 2 of the present invention. FIG. 3 is a circuit block diagram of a gradation limiting unit of the image processing apparatus according to the first and second embodiments of the present invention. FIG. 4 shows values of dither elements according to the first embodiment of the present invention. FIG. 5 is a diagram illustrating the operation of a dither processing unit and a level conversion unit according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating values of dither elements according to the second embodiment of the present invention. FIG. 8 is a diagram for explaining the operation of dither processing means and level conversion means according to the second embodiment of the present invention. FIG. 8 is a circuit block diagram of an image processing apparatus according to the prior art. Block diagram of the dither circuit in the block diagram of the error diffusion circuit in FIG. [10] Conventional techniques for explaining processing contents of dispersion [11] of the prior art [Description of symbols]
100 bit number expansion means 101 gradation limiting means 102 dither processing means 103, 804 display device 104 level conversion means 106 input image signal (image signal A)
200 inverse gamma correction circuit 201 first error diffusion circuit 301 gradation limit table 401 dither element determination circuit 801 image signal 802 error diffusion circuit 803 dither circuit

Claims (3)

At least Log2 (n × m) ≦ Δb (m and n are natural numbers) with respect to the number of bits of an image signal input to a display device having a characteristic in which a displayable gradation interval is not constant.
Bit number extending means for increasing the number of bits of the image signal by Δb that satisfies
A gradation restriction table for restricting an output to a gradation obtained by equally dividing (n × m) between each gradation with respect to a gradation obtained by multiplying a displayable gradation of the display device by (n × m);
Tone limiting means for limiting the first image signal to the tone of the tone limit table and outputting the second image signal as a second image signal, and performing an error diffusion process using a difference generated by the limitation as a display error;
Dither processing means for performing dither processing on the second image signal using each dither element of a dither matrix (n × m) determined based on the second image signal, and outputting the result as a third image signal;
An image processing apparatus comprising: a level conversion unit configured to convert the third image signal into a bit number and a gradation that can be displayed on the display device. The bit number extending means has an inverse gamma correction circuit and an error diffusion circuit, and the inverse gamma correction circuit temporarily converts an input image signal into an image signal having a larger number of bits than the first image signal. The image processing apparatus according to claim 1, wherein: Smaller than (n × m-1) tones inserted to divide (n × m) equally between each of the tones which are (n × m) times the displayable tones I = 2, 3,..., N × m
, The probability that the i-th gray scale is raised to the larger value of the gray scale obtained by multiplying the displayable gray scale by (n × m) is (i−1) / (n × m)
And the probability of not moving is {(n × m) − (i−1)} / (n × m)
2. The image processing apparatus according to claim 1, wherein a value of a dither element of the dither matrix is set such that

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