JP2004088022A

JP2004088022A - High power semiconductor devices

Info

Publication number: JP2004088022A
Application number: JP2002250066A
Authority: JP
Inventors: Hiroshi Fukuyoshi; 福吉　寛
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2002-08-29
Filing date: 2002-08-29
Publication date: 2004-03-18

Abstract

<P>PROBLEM TO BE SOLVED: To realize miniaturization and making high reliability of a power semiconductor device. <P>SOLUTION: Sandwiching and fixing the power semiconductor chip 5 with a first insulation circuit board 3 and a second laminated insulation circuit board 9 and fitting a board 20, comprising a material having a small linear expansion coefficient in the second board 9, suppresses the deformation of a conductive layer of the fixing part with the chip 5, relaxing the stresses generated in the fixing part in between the chip 5 and the board 9. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、インバーターやコンバーター、スィッチング電源などに用いられる大電力用半導体装置に関するものである。
【０００２】
【従来の技術】
従来、この種の大電力用半導体装置は、一般に、図１６に示すような構造になっている。図１６は、従来の大電力用半導体装置の断面図である。
【０００３】
図１６において、１０１は樹脂製の側壁部分からなる無底箱体状のケースで、このケース１０１の底部には放熱を兼ねた金属ベース１０２が取り付けられている。この金属ベース１０２上には、第１の絶縁回路基板１０３がハンダを介して固着されている。
【０００４】
この第１の絶縁回路基板１０３の上に設けた所定の導体層１０４上にはパワー素子としてのＩＧＢＴが形成された電力用半導体チップ１０５がハンダを介して固着されており、電力用半導体チップ１０５のエミッタ電極と信号電極の各々が第１の絶縁回路基板１０３上の所定の導体層１０４に金属ワイヤ１０６および１０７を介してそれぞれ電気的に接続されている。
【０００５】
また、第１の絶縁回路基板１０３の所定の導体層１０４とケース１０１にインサート成形された外部導出用リード１０８とが、金属ワイヤ１０９を介して電気的に接続されている。一方、第２の絶縁回路基板１１１が、第１の絶縁回路基板１０３の上方に配置されて、ケース１０１内壁の段部に支持されている。この第２の絶縁回路基板１１１上の所定の導体層１１５に制御回路ＩＣ１１０が固着され、これらの第１および第２の絶縁回路基板１０３、１１１の所定の導体層１０４、１１５が金属ワイヤ１１２で互いに電気的に接続している。
【０００６】
また、信号導出用リード１１３を支持した蓋体１１４がケース１０１の最上部に配置され、信号導出用リード１１３が第２の絶縁回路基板１１１の所定の導体層１１５に固着されている。そして、ケース１０１内の空間には、ゲル状のシリコーン樹脂１１６が封入されている。
【０００７】
このような従来の大電力用半導体装置においては、多数の金属ワイヤ１０６、１０７、１０９、１１２に対するボンディング配線領域を確保する必要があり、装置が大型化するという問題がある。
【０００８】
この問題を解決するための大電力用半導体装置の例が、特開平１０−１２８１２号公報に開示されている。この大電力用半導体装置は、放熱ベースを兼ねた金属ベース上に設けた第１の絶縁回路基板上に電力用半導体チップを配置し、この電力用半導体チップ上に第２の絶縁回路基板を配置して、電力用半導体チップの各電極と第１の絶縁回路基板および第２の絶縁回路基板の各導体層とをハンダにより固着することにより、小型化を図ったものである。
【０００９】
このような大電力用半導体装置においては、電流容量が増えるに従い、電力用半導体チップ自体の発熱、および電力用半導体チップの電極と第２の絶縁回路基板の導体層との固着部分の電気抵抗による発熱が増え、電力用半導体チップの電極と第２の絶縁回路基板の導体層との固着部分において温度上昇が起こる。
【００１０】
そして、電力用半導体チップ、例えばシリコンと第２の絶縁回路基板の導体層、例えばＣｕ（銅）との線膨張係数の差により、電力用半導体チップの電極と第２の絶縁回路基板の導体層との固着部分への応力が生じ、その固着部分が剥離し、大電力半導体装置の信頼性が低下する問題がある。
【００１１】
【発明が解決しようとする課題】
上記した従来の大電力用半導体装置においては、装置の小型化が困難である。
また、温度上昇する電力用半導体チップと第２の絶縁回路基板の導体層の線膨張係数の差により、電力用半導体チップの電極と第２の絶縁回路基板の導体層との固着部分の剥離が起こり、装置の信頼性が低下するという問題がある。
【００１２】
本発明は、上記問題を解決するためになされたもので、小型で、かつ信頼性の高い大電力用半導体装置を提供することを目的とする。
【００１３】
【課題を解決するための手段】
上記目的を達成するために、本発明の大電力用半導体装置は、上面に導体層を有する第１の絶縁回路基板と、前記絶縁回路基板の導体層上に固着され、且つ上面に主電極を有する電力用半導体チップと、前記電力用半導体チップの上方に配置され、且つ前記電力用半導体チップの主電極に導体層が固着された第２の絶縁回路基板と、前記第１及び第２の絶縁回路基板の導体層に各々電気的接続された外部導出端子とを具備し、前記第２の絶縁回路基板は、上下両面を貫通するビアを有する絶縁性基板と、前記絶縁性基板の両主面及び前記ビアの内壁部に形成された導体層と、前記導体層より小さい線膨張係数を有し、前記電力用半導体チップの主電極と対向配置されて該導体層に固着された緩衝部材とを有することを特徴とする。
【００１４】
このように構成された本発明の大電力用半導体装置によれば、電力用半導体チップは、第１の絶縁回路基板の導体層と第２の積層絶縁回路基板の両面及びビア内に形成された導体層を介して外部導出用端子と接続しているため、金属ワイヤによるボンディング領域が不要となり、小型化が可能である。
【００１５】
また、第２の積層絶縁回路基板内に導体層より小さい線膨張係数を有する緩衝部材を電力用半導体チップの主電極と対向配置し、且つ電力用半導体チップの主電極が固着される該導体層に固着している。そのため、電力用半導体チップと積層絶縁回路基板の導体層との線膨張係数の差による応力が緩和され、積層絶縁回路基板の導体層と電力用半導体チップの主電極との固着部分の信頼性を向上し得る。
【００１６】
また、上記目的を達成するために、本発明の大電力用半導体装置は、上面に導体層を有する第１の絶縁回路基板と、前記絶縁回路基板の導体層上に固着され、且つ上面に主電極を有する電力用半導体チップと、前記電力用半導体チップの上方に配置され、且つ前記電力用半導体チップの主電極に導体層が固着された第２の絶縁回路基板と、前記第１及び第２の絶縁回路基板の導体層に各々電気的接続された外部導出端子とを具備し、前記第２の絶縁回路基板は、上下両面を貫通するビアを有する絶縁性基板と、前記絶縁性基板の両面及び前記ビアの内壁部に形成された導体層と、前記電力用半導体チップ側の前記導体層に固着され、且つ前記電力用半導体チップの主電極と固着される網状金属細線の緩衝部材とを有することを特徴とする。
【００１７】
このような構成の本発明の大電力用半導体装置によれば、電力用半導体チップは、第１の絶縁回路基板の導体層と第２の積層絶縁回路基板の両面及びビア内に形成された導体層を介して外部導出用端子と接続しているため、金属ワイヤによるボンディング領域が不要となり、小型化が可能である。
【００１８】
また、電力用半導体チップの主電極と固着される導体層に網状金属細線の緩衝部材を固着しており、この緩衝部材の変形により、電力用半導体チップと積層絶縁回路基板の導体層との線膨張係数の差による応力が緩和され、積層絶縁回路基板の導体層と電力用半導体チップの主電極との固着部分の信頼性を向上し得る。
【００１９】
更に、上記目的を達成するために、本発明の大電力用半導体装置は、上面に導体層を有する第１の絶縁回路基板と、前記絶縁回路基板の導体層上に固着され、且つ上面に主電極を有する電力用半導体チップと、前記電力用半導体チップの上方に配置され、且つ前記電力用半導体チップの主電極に導体層が固着された第２の絶縁回路基板と、前記第１及び第２の絶縁回路基板の導体層に各々電気的接続された外部導出端子とを具備し、前記第２の絶縁回路基板は、上下両面を貫通するビアを有する絶縁性基板と、前記絶縁性基板の両面及び前記ビアの内壁部に形成された導体層と、前記電力用半導体チップ側の前記導体層に固着され、且つ前記電力用半導体チップの主電極と固着されるモリブデン製緩衝部材とを有することを特徴とする。
【００２０】
このような構成の本発明の大電力用半導体装置によれば、電力用半導体チップは、第１の絶縁回路基板の導体層と第２の積層絶縁回路基板の両面及びビア内に形成された導体層を介して外部導出用端子と接続しているため、金属ワイヤによるボンディング領域が不要となり、小型化が可能である。
【００２１】
また、電力用半導体チップの主電極と固着される導体層にモリブデン製の緩衝部材を固着しているため、電力用半導体チップと積層絶縁回路基板の導体層との線膨張係数の差による応力が緩和され、積層絶縁回路基板の導体層と電力用半導体チップの主電極との固着部分の信頼性を向上し得る。
【００２２】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を説明する。
【００２３】
（第１の実施の形態）
図１は、本発明の第１の実施の形態に係る大電力用半導体装置を示す断面図である。まず、本実施の形態の大電力用半導体装置の構造の概略を説明する。
【００２４】
図１に示すように、本実施の形態の大電力用半導体装置は、樹脂製の側壁部分からなる無底箱体状のケース１の底部には、放熱を兼ねた金属ベース２が取り付けられている。
【００２５】
この金属ベース２上には、第１の絶縁回路基板３がハンダを介して固着されている。この第１の絶縁回路基板３上の所定の導体層４には、パワー素子としてＩＧＢＴが形成された電力用半導体チップ５のコレクタ電極８がハンダを介して固着される。
【００２６】
また、この電力用半導体チップ５上には、第２の積層絶縁回路基板９が配置され、この第２の積層絶縁回路基板９の下面に設けられた所定のエミッタ導体層１０および信号導体層１１が電力用半導体チップ５の上面に設けられたエミッタ電極６および信号電極７に、それぞれハンダを介して固着されている。
【００２７】
そして、この第２の積層絶縁回路基板９の内部にエミッタ導体層１０より小さい線膨張係数を有するセラミックスなどの緩衝部材２０が、このエミッタ電極６と対向して配置され、かつエミッタ導体層１０に固着されている。
【００２８】
また、第２の積層絶縁回路基板９の上面に形成された図示略の信号導体層上に制御回路ＩＣ１６が固着され、第２の積層絶縁回路基板９によって電力用半導体チップ５と電気的に接続されている。
【００２９】
そして、コレクタ導出用リード１２が第２の積層絶縁回路基板９に嵌挿されて第１の絶縁回路基板３上の導体層４にハンダによって固着され、一方、エミッタ導出用リード１３は、コレクタ導出用リード１２に絶縁部材１４によって支持され、第２の積層絶縁回路基板９内に挿入されて、第２の積層絶縁回路基板９内部に設けたエミッタ導体層１５にハンダによって固着されている。
【００３０】
また、コレクタ導出用リード１２とエミッタ導出用リード１３と信号導出用リード３０を支持した、蓋体１７がケース１の最上部に配置され、信号導出用リード３０は、第２の積層絶縁回路基板９内部の信号導体層２９にハンダによって固着される。そして、ケース１内の空間には、ゲル状のシリコーン樹脂１８が封入されている。
【００３１】
次に、上記第１の絶縁回路基板３の具体的な構造を図２を参照して説明する。なお、図２は、第１の絶縁回路基板３上に電力用半導体チップ５が実装された状態を示した平面図である。
【００３２】
図２に示すように、第１の絶縁回路基板３は、セラミックス、ガラスエポキシ樹脂、ポリエステル樹脂、ポリイミド樹脂などの絶縁性基板３ａを有する。この絶縁性基板３ａの下面には図示略の導体層が形成されて、上面には導体層４が形成されている。そしてこの導体層４上には、例えば４個の電力用半導体チップ５がハンダを介して固着されている。また、この導体層４には、中央の接続部２３においてハンダを介してコレクタ導出用リード１２が固着されている。
【００３３】
この電力用半導体チップ５は、図１３に示すように、上面にエミッタ電極６および信号電極７が、下面にコレクタ電極８が形成されている。各電極は導電性接着性を高めるメタライズ処理が行われている。
【００３４】
なお、図２では更に導体層４上に、インダクタンスを含む負荷を駆動した時に生じる逆バイアス電流をバイパスし電力用半導体チップ５を保護するためのダイオードが形成された半導体チップ２１が固着されている。
【００３５】
次に、上記第２の積層絶縁回路基板９の具体的構造を図３乃至図６を参照して説明する。図３乃至図６は、第２の積層絶縁回路基板９を構成する各層の平面図およびＡ−Ａ線に沿った断面図である。
【００３６】
図３は、下側から第１層目の絶縁回路基板２４の平面図と断面図である。同図に示すように、第１層目の絶縁回路基板２４は、ガラスエポキシ樹脂、ポリエステル樹脂、ポリイミド樹脂などの絶縁性基板２４ａを有する。この絶縁性基板２４ａの中央部には、コレクタ導出用リード１２と絶縁部材１４が通過する穴２４ｂが設けられている。
【００３７】
また、絶縁性基板２４ａの下面の周辺部には、下側のエミッタ導体層１０が電力用半導体チップ５のエミッタ電極６に対向して設けられ、またその上面には、穴２４ａを取囲むように環状の上側のエミッタ導体層１５が設けられ、この下側のエミッタ導体層１０と上側のエミッタ導体層１５とはビアに埋め込まれた導体層２５によって電気的に接続されている。
【００３８】
そして、このエミッタ導体層１５にエミッタ導出用リード１３を接続するための接続部２６が設けられ、ここにエミッタ導出用リード１３が接続される。
【００３９】
また、絶縁性基板２４ａの下面には、下側の信号導体層１１が電力用半導体チップ５の信号電極７に対向して設けられ、またその上面には、上側の信号導体層２４ｃが設けられ、この下側の信号導体層１１と上側の信号導体層２４ｃとは、ビアに埋め込まれた導体層１９ａによって電気的に接続されている。
【００４０】
なお、図示しないが、半導体チップ２１の電極と接続される導体層が絶縁性基板２４ａに設けられている。
【００４１】
図４は、積層絶縁回路基板９を構成する第２層目の絶縁回路基板２７の平面図と断面図である。同図に示すように、第２層目の絶縁回路基板２７は、ガラスエポキシ樹脂、ポリエステル樹脂、ポリイミド樹脂などの絶縁性基板２７ａを有する。この絶縁性基板２７ａの中央部には、コレクタ導出用リード１２と絶縁部材１４とエミッタ導出用リード１３が通過する穴２７ｂが第１層目の絶縁回路基板２４の穴２４ｂに対応して設けられている。
【００４２】
また、絶縁性基板２７ａには、電力用半導体チップ５のエミッタ電極６に対応する位置に設けられた穴に、この絶縁性基板２７ａより線膨張係数の小さなセラミックなどの材料からなる緩衝部材２０が嵌合されている。この緩衝部材２０は、エミッタ電極６とほぼ同一の形状および面積に形成されている。
【００４３】
そして、この緩衝部材２０の下面は、メッキなどでメタライズ処理された接続層２０ａが設けられ、第１層目の絶縁回路基板２４のエミッタ導体層１５にハンダを介して固着されている。
【００４４】
また、絶縁性基板２７ａの下面には、第１層目の絶縁回路基板２４の信号導体層２４ｃと対向して下側の信号導体層２７ｃが設けられ、その上面には、上側の信号導体層２７ｄが設けられ、この下側の信号導体層２７ｃと上側の信号導体層２７ｄとは、ビアに埋め込まれた導体層１９ｂによって電気的に接続されている。そして、この下側の信号導体層２７ｃと第１層目の絶縁回路基板２４の上側の信号導体層２４ｃとが電気的接続されている。
【００４５】
図５は、積層絶縁回路基板９を構成する第３層目の絶縁回路基板２８の平面図と断面図である。同図に示すように、第３層目の絶縁回路基板２８は、ガラスエポキシ樹脂、ポリエステル樹脂、ポリイミド樹脂などの絶縁性基板２８ａを有する。この絶縁性基板２８ａの中央部には、コレクタ導出用リード１２と絶縁部材１４とエミッタ導出用リード１３が通過する穴２８ｂが第２層目の絶縁回路基板２７の穴２７ｂに対応して設けられている。
【００４６】
また、絶縁性基板２８ａの下面の周辺部には、第２層目の絶縁回路基板２７の信号導体層２７ｄと対向して下側の信号導体層２８ｃが設けられ、その上面には、各信号導電層を電気的接続するための所定パターンを有する上側の信号導体層２９が設けられ、この下側の信号導体層２８ｃと上側の信号導体層２９とは、ビアに埋め込まれた導体層１９ｃによって電気的に接続されている。
【００４７】
そして、この下側の信号導体層２８ｃと第２層目の絶縁回路基板２７の上側の信号導体層２７ｄとが電気的接続されている。
【００４８】
そして、上側の信号導体層２９には、信号導出用リード３０を接続するための接続部３１が設けられ、ここに信号導出用リード３０が接続される。
【００４９】
図６は積層絶縁回路基板９の最上側の第４層目の絶縁回路基板３２の平面図である。同図に示すように、第４層目の絶縁回路基板３２は、ガラスエポキシ樹脂、ポリエステル樹脂、ポリイミド樹脂などの絶縁性基板３２ａを有する。この絶縁性基板３２ａには、コレクタ導出用リード１２とエミッタ導出用リード１３と絶縁部材１４が通過する穴３２ｂおよび信号導出用リード３０が通過する穴３２ｃが、第３層目の絶縁回路基板２８の穴２８ｂ及び信号導出用リード３０の接続部３１に対応して夫々設けられている。
【００５０】
また、この第４層目の絶縁回路基板３２の上面には、図示しないが制御回路ＩＣ１６と電力用半導体チップ５の所定の電極とを電気的に接続するための配線導体層が設けられている。
【００５１】
次に、上記コレクタ導出用リード１２およびエミッタ導出用リード１３の具体的構成を図７および図８を参照して説明する。図７は、端子部の平面図で、図８は、図７の端子部のＢ−Ｂ線に沿った断面図である。
【００５２】
同図に示すように、コレクタ導出用リード１２とエミッタ導出用リード１３は、いずれも金属板を成形加工して作られ、上端部は逆Ｌ型に折り曲げられ、外部回路の電力配線体をネジ止めするための、ネジ穴が設けられ、また下端部もＬ字形に折り曲げ加工され、絶縁回路基板上の導体層との接続面積を増加させて確実な固着を実現するようにしている。
【００５３】
このような第１の実施の形態の大電力半導体装置によれば、電力用半導体チップ５は、第１の絶縁回路基板３の導体層４と第２の積層絶縁回路基板９の両面およびビア内に形成されたエミッタ導体層１０および信号導体層１１等の導体層を介してコレクタ導出用リード１２、エミッタ導出用リード１３および信号導出用リード３０等の外部導出用端子に接続されている。このため、金属ワイヤによるボンディング領域が不要となり装置の小型化が実現できる。
【００５４】
また、第２の積層絶縁回路基板９内に絶縁基板２７ａのエミッタ導体層より小さい線膨張係数を有するセラミックからなる緩衝部材２０を電力用半導体チップ５のエミッタ電極６と対向配置し、且つ電力用半導体チップ５のエミッタ電極６が固着されるエミッタ導体層１０に固着している。そのため、電力用半導体チップ５と積層絶縁回路基板９のエミッタ導体層１０との線膨張係数の差による応力が緩和され、積層絶縁回路基板９のエミッタ導体層１０と電力用半導体チップ５のエミッタ電極６との固着部分における剥離等の故障を減少でき、信頼性の高い大電力用半導体装置を実現し得る。
【００５５】
（第２の実施の形態）
次に本発明の第２の実施の形態に係る大電力用半導体装置を図９を参照して説明する。図９は、第２の実施の形態に係る大電力半導体装置の断面図である。この第２の実施の形態の各部について、上記第１の実施の形態に係る大電力用半導体装置の各部同一部分は同一符号を付し、説明を省略する。
【００５６】
この本実施の形態の大電力用半導体装置が、第１の実施の形態と異なる点は、第１の実施の形態の第２の積層絶縁回路基板９における第２層目の絶縁回路基板２７を取り除き、第２の積層絶縁回路基板３３における第１層目の絶縁回路基板の電力用半導体チップ５側のエミッタ導体層１０および信号導体層１１の各々に、緩衝部材としての例えば銅からなる網状金属細線３４および３５を固着し、この網状金属細線３４および３５を電力用半導体チップ５のエミッタ電極６および信号電極７にハンダにより固着した構成にしていることにある。
【００５７】
すなわち、図１０に示すように、第２の積層絶縁回路基板３３における第１層目の絶縁回路基板２４は、絶縁性基板２４ａの中央部に、コレクタ導出用リード１２と絶縁部材１４が通過する穴２４ｂが設けられ、絶縁性基板２４ａの下面の周辺部には、下側のエミッタ導体層１０が電力用半導体チップ５のエミッタ電極６に対向して設けられ、またその上面には、穴２４ａを取囲むように環状の上側のエミッタ導体層１５が設けられ、この下側のエミッタ導体層１０と上側のエミッタ導体層１５とはビアに埋め込まれた導体層２５によって電気的に接続されている。
【００５８】
また、絶縁性基板２４ａの下面には、下側の信号導体層１１が電力用半導体チップ５の信号電極７に対向して設けられ、またその上面には、上側の信号導体層２４ｃが設けられ、この下側の信号導体層１１と上側の信号導体層２４ｃとは、ビアに埋め込まれた導体層１９ａによって電気的に接続されている。
【００５９】
この下側のエミッタ導体層１０および下側の信号導体層１１には、Ｃｕなどの網状の導電性金属からなる網状金属細線３４および３５が固着されている。
【００６０】
それ以外の構成については、上記第１の実施の形態と同じである。また、この網状金属細線は、少なくとも特に発熱の大きなエミッタ電極６とエミッタ導体層１０との間に設ければ良く、信号電極７と信号導体層１１との間に、必ずしも設ける必要はない。
【００６１】
このような第２の実施の形態の大電力半導体装置によれば、電力用半導体チップ５は、第１の絶縁回路基板３の導体層４と第２の積層絶縁回路基板３３の両面およびビア内に形成されたエミッタ導体層１０および信号導体層１１等の導体層を介してコレクタ導出用リード１２、エミッタ導出用リード１３および信号導出用リード３０等の外部導出用端子に接続されている。このため、金属ワイヤによるボンディング領域が不要となり装置の小型化が実現できる。
【００６２】
また、第２の積層絶縁回路基板３３のエミッタ導体層１０および信号導体層１１の各々に、網状金属細線３４および３５を固着し、この網状金属細線３４および３５を電力用半導体チップ５のエミッタ電極６および信号電極７に固着している。
【００６３】
そのため、電力用半導体チップ５からの熱によりエミッタ導体層１０および信号導体層１１が熱膨張する時に、この網状金属細線３４および３５が柔軟に変形して、エミッタ電極６および信号電極７とエミッタ導体層１０および信号導体層１１との固着部分に加わる応力が小さくなるので、第２の積層絶縁回路基板３３のエミッタ導体層１０および信号導体層１１と電力用半導体チップ５のエミッタ電極６および信号電極７との固着部分における剥離等の故障を減少でき、信頼性の高い大電力用半導体装置を実現し得る。
【００６４】
（第３の実施の形態）
次に本発明の第３の実施の形態に係る大電力用半導体装置を図１１を参照して説明する。図１１は、第３の実施の形態に係る大電力半導体装置の断面図である。この第３の実施の形態の各部について、上記第１の実施の形態に係る大電力用半導体装置の各部同一部分は同一符号を付し、説明を省略する。
【００６５】
この本実施の形態の大電力用半導体装置が、第１の実施の形態と異なる点は、第１の実施の形態の第２の積層絶縁回路基板９における第２層目の絶縁回路基板２７を取り除き、第２の積層絶縁回路基板３６における第１層目の絶縁回路基板の電力用半導体チップ５側のエミッタ導体層１０および信号導体層１１の各々に、例えばモリブデン製緩衝部材３７および３８を固着し、このモリブデン製緩衝部材３７および３８を電力用半導体チップ５のエミッタ電極６および信号電極７にハンダにより固着した構成にしていることにある。
【００６６】
すなわち、図１２に示すように、第２の積層絶縁回路基板３６における第１層目の絶縁回路基板２４は、絶縁性基板２４ａの中央部に、コレクタ導出用リード１２と絶縁部材１４が通過する穴２４ｂが設けられ、絶縁性基板２４ａの下面の周辺部には、下側のエミッタ導体層１０が電力用半導体チップ５のエミッタ電極６に対向して設けられ、またその上面には、穴２４ａを取囲むように環状の上側のエミッタ導体層１５が設けられ、この下側のエミッタ導体層１０と上側のエミッタ導体層１５とはビアに埋め込まれた導体層２５によって電気的に接続されている。
【００６７】
また、絶縁性基板２４ａの下面には、下側の信号導体層１１が電力用半導体チップ５の信号電極７に対向して設けられ、またその上面には、上側の信号導体層２４ｃが設けられ、この下側の信号導体層１１と上側の信号導体層２４ｃとは、ビアに埋め込まれた導体層１９ａによって電気的に接続されている。
【００６８】
この下側のエミッタ導体層１０および下側の信号導体層１１に、これらの導体層に比べて線膨張係数の小さい、モリブデン製緩衝部材３７および３８が固着されている。
【００６９】
それ以外の構成については、上記第１の実施の形態と同じである。また、このモリブデン製緩衝部材は、少なくとも特に発熱の大きなエミッタ電極６とエミッタ導体層１０との間に設ければ良く、信号電極７と信号導体１１との間に、必ずしも設ける必要はない。
【００７０】
このような第３の実施の形態の大電力半導体装置によれば、電力用半導体チップ５は、第１の絶縁回路基板３の導体層４と第２の積層絶縁回路基板３６の両面およびビア内に形成されたエミッタ導体層１０および信号導体層１１等の導体層を介してコレクタ導出用リード１２、エミッタ導出用リード１３および信号導出用リード３０等の外部導出用端子に接続されている。このため、金属ワイヤによるボンディング領域が不要となり装置の小型化が実現できる。
【００７１】
また、第２の積層絶縁回路基板３６のエミッタ導体層１０および信号導体層１１の各々に、モリブデン製緩衝部材３７および３８を固着し、このモリブデン製緩衝部材３７および３８を電力用半導体チップ５のエミッタ電極６および信号電極７に固着している。そのため、電力用半導体チップ５からの熱によりエミッタ導体層１０および信号導体層１１が熱膨張する時に、このモリブデン製緩衝部材３７および３８の線膨張係数が電力用半導体チップ５の線膨張係数との差が小さいために、エミッタ電極６および信号電極７とエミッタ導体層１０および信号導体層１１との固着部分に加わる応力が小さくなるので、第２の積層絶縁回路基板３３のエミッタ導体層１０および信号導体層１１と電力用半導体チップ５のエミッタ電極６および信号電極７との固着部分における剥離等の故障を減少でき、信頼性の高い大電力用半導体装置を実現し得る。
【００７２】
本発明は、上記実施の形態に限定されるものではなく、発明の要旨を逸脱しない範囲で、種々変形し、実施できることは勿論である。
【００７３】
例えば、上記実施の形態においてケース１の代わりに、エポキシ等の樹脂でモールドして良いし、熱抵抗・コストを下げるためベース２を省いた構造としても良い。
【００７４】
また、電力用半導体チップ５は、図１３に示すエミッタ電極の構造に限定されず、図１４に示すように複数の島状に分割されたエミッタ電極構造を有するものでも良く、この場合には、積層絶縁回路基板の導体層との固着部分における応力を小さくすることができる。
【００７５】
また、電力用半導体チップ５は、図１５に示すように複数の制御信号電極３９を設けて制御回路を内蔵してもよく、過昇温防止機能や過電圧防止機能、省エネ機能などを持つ制御回路が内蔵されるため、最上層の絶縁回路基板を含めたスペース分大電力用半導体装置が小型化される。
【００７６】
また、上記第１乃至第３実施の形態において、第２の積層絶縁回路基板９、３３、３６の第１層目の絶縁回路基板２４のエミッタ導体層１５の配線形状は、環状に限定されるものでなく、接続部２６と、電力用半導体チップ５のエミッタ電極および半導体チップ２１との間の電気的接続が確保できる配線形状にしてもよい。
【００７７】
また、上記第１乃至第３実施の形態において、第１の絶縁回路基板３と、第２の積層絶縁回路基板９、３３、３６を全てセラミックスよりなる絶縁性基板で構成してもよく、この場合は、絶縁回路基板の線膨張係数と電力用半導体チップ５の線膨張係数との差が小さいために、電力用半導体チップ５のエミッタ電極および信号電極およびコレクタ電極と、エミッタ導体層および信号導体層およびコレクタ導体層とのそれぞれの固着面に加わる応力が小さくなり、信頼性が向上する。
【００７８】
また、上記第１乃至第３実施の形態において、第２の積層絶縁回路基板９、３３、３６の第１層目の絶縁回路基板２４の下面にエミッタ導体層１５をエミッタ導体層１０を覆うように設け、更に、上面にはエミッタ導出用リードを接続する接続部２６部分に相当するエミッタ導体層と信号導体層２９を設け、上面の接続部２６のエミッタ導体層と下面のエミッタ導体層１５とをビアまたは断面がＵ字型に折り曲げられた金属板を用いて接続するようにしてもよく、このように構成することで、第３層目の絶縁回路基板２８を取り除くことができる。
【００７９】
また、上記第１乃至第３実施の形態において、第２の積層絶縁回路基板９、３３、３９の第１層目の絶縁回路基板２４のエミッタ導体層１５が、エミッタ導体層を設けた複数の絶縁回路基板を積層して構成されるようにしてもよい。
【００８０】
また、上記第１乃至第３実施の形態において、第２の積層絶縁回路基板９、３３、３９の最上層に、エミッタ導体層を有する絶縁回路基板を追加して設けるようにしても良く、エミッタ導体層の電流密度の低減させて導体層での発熱を減少させるとともに、信号導体層への外部からのノイズ信号の混入を低減させることができる。
【００８１】
また、上記第２および第３実施の形態において、積層絶縁回路基板３３および３６に第１の実施の形態の第２層目の絶縁回路基板を追加して、４層構造にしても良い。
【００８２】
【発明の効果】
本発明によれば、小型で、かつ信頼性の高い大電力用半導体装置を実現できる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る大電力用半導体装置の断面図。
【図２】本発明の第１の実施形態に係る大電力用半導体装置の第１の絶縁回路基板の平面図。
【図３】本発明の第１の実施形態に係る大電力用半導体装置の第２の積層絶縁回路基板を構成する第１層目の絶縁回路基板の平面図と断面図。
【図４】本発明の第１の実施形態に係る大電力用半導体装置の第２の積層絶縁回路基板を構成する第２層目の絶縁回路基板の平面図と断面図。
【図５】本発明の第１の実施形態に係る大電力用半導体装置の第２の積層絶縁回路基板を構成する第３層目の絶縁回路基板の平面図と断面図。
【図６】本発明の第１の実施形態に係る大電力用半導体装置の第２の積層絶縁回路基板を構成する第４層目の絶縁回路基板の平面図。
【図７】本発明の第２の積層絶縁回路基板を構成する外部導出端子部の平面図。
【図８】図７のＢ−Ｂ線に沿う外部導出端子部の断面図。
【図９】本発明の第２の実施形態に係る大電力用半導体装置の断面図。
【図１０】本発明の第２の実施形態に係る大電力用半導体装置の第２の積層絶縁回路基板を構成する第１層目の絶縁回路基板の平面図と断面図。
【図１１】本発明の第３の実施形態に係る大電力用半導体装置の断面図。
【図１２】本発明の第３の実施形態に係る大電力用半導体装置の第２の積層絶縁回路基板を構成する第１層目の絶縁回路基板の平面図と断面図。
【図１３】電力用半導体チップの電極構造を示す平面図
【図１４】電力用半導体チップの他の電極構造を示す平面図
【図１５】電力用半導体チップの更に他の電極構造を示す平面図
【図１６】従来の大電力用半導体装置の構成図。
【符号の説明】
１、１０１　ケース
２、１０２　金属ベース
３、１０３　第１の絶縁回路基板
４、１０４　第１の絶縁回路基板上の導体層
５、１０５　電力用半導体チップ
６　エミッタ電極
７　信号電極
８　コレクタ電極
９、３３、３６　第２の積層絶縁回路基板
１０、１５　第２の積層絶縁回路基板上のエミッタ導体層（導体層）
１１　第２の積層絶縁回路基板上の信号導体層（導体層）
１２　コレクタ導出用リード（外部導出端子）
１３　エミッタ導出用リード（外部導出端子）
３０　信号導出用リード（外部導出端子）
１４　絶縁部材
１６、１１０　制御回路ＩＣ
１７、１１４　蓋体
１８、１１６　シリコーン樹脂
１９ａ、１９ｂ、１９ｃ、２５　ビア内の導体層
２０、３４、３５、３７、３８　緩衝部材
２１　半導体チップ
２３、２６、３１　接続部
２４、２７、２８、３２、３３、３６　第２の積層絶縁回路基板を構成する絶縁回路基板
３９ａ、３９ｂ、３９ｃ、３９ｄ　電力用半導体チップの制御信号電極
１０６、１０７、１０９、１１２　金属ワイヤ
１０８，１１３　外部導出用リード
１１１　第２の絶縁回路基板
１１５　第２の絶縁回路基板上の導体層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a high-power semiconductor device used for an inverter, a converter, a switching power supply, and the like.
[0002]
[Prior art]
Conventionally, this kind of high power semiconductor device generally has a structure as shown in FIG. FIG. 16 is a sectional view of a conventional high-power semiconductor device.
[0003]
In FIG. 16, reference numeral 101 denotes a bottomless box-shaped case made of a resin-made side wall, and a metal base 102 also serving as a heat radiation is attached to the bottom of the case 101. On this metal base 102, a first insulating circuit board 103 is fixed via solder.
[0004]
On a predetermined conductor layer 104 provided on the first insulating circuit board 103, a power semiconductor chip 105 on which an IGBT as a power element is formed is fixed via solder. Are electrically connected to a predetermined conductor layer 104 on the first insulated circuit board 103 via metal wires 106 and 107, respectively.
[0005]
Further, a predetermined conductor layer 104 of the first insulated circuit board 103 and an external lead-out lead 108 insert-molded in the case 101 are electrically connected via a metal wire 109. On the other hand, the second insulated circuit board 111 is disposed above the first insulated circuit board 103 and is supported by the step on the inner wall of the case 101. The control circuit IC 110 is fixed to a predetermined conductor layer 115 on the second insulated circuit board 111, and the predetermined conductor layers 104 and 115 of the first and second insulated circuit boards 103 and 111 are connected by metal wires 112. They are electrically connected to each other.
[0006]
Further, a lid 114 supporting the signal lead 113 is arranged at the uppermost part of the case 101, and the signal lead 113 is fixed to a predetermined conductor layer 115 of the second insulating circuit board 111. A gel silicone resin 116 is sealed in the space inside the case 101.
[0007]
In such a conventional high-power semiconductor device, it is necessary to secure a bonding wiring area for a large number of metal wires 106, 107, 109, and 112, and there is a problem that the device becomes large.
[0008]
An example of a high-power semiconductor device for solving this problem is disclosed in Japanese Patent Application Laid-Open No. 10-12812. In this high power semiconductor device, a power semiconductor chip is arranged on a first insulating circuit board provided on a metal base also serving as a heat dissipation base, and a second insulating circuit board is arranged on the power semiconductor chip. Then, each electrode of the power semiconductor chip and each conductor layer of the first insulating circuit board and the second insulating circuit board are fixed to each other by soldering, thereby achieving miniaturization.
[0009]
In such a high-power semiconductor device, as the current capacity increases, the heat generated by the power semiconductor chip itself and the electric resistance of the fixed portion between the electrode of the power semiconductor chip and the conductor layer of the second insulating circuit board are increased. Heat generation increases, and a temperature rise occurs in a portion where the electrode of the power semiconductor chip is fixed to the conductor layer of the second insulated circuit board.
[0010]
The electrode of the power semiconductor chip and the conductor layer of the second insulated circuit board are formed by the difference in linear expansion coefficient between the power semiconductor chip, for example, silicon, and the conductor layer of the second insulated circuit board, for example, Cu (copper). Then, a stress is generated in the fixed portion, and the fixed portion is separated, and there is a problem that the reliability of the high power semiconductor device is reduced.
[0011]
[Problems to be solved by the invention]
In the conventional high-power semiconductor device described above, it is difficult to reduce the size of the device.
Also, due to the difference in linear expansion coefficient between the power semiconductor chip and the conductor layer of the second insulated circuit board whose temperature rises, peeling of the fixed portion between the electrode of the power semiconductor chip and the conductor layer of the second insulated circuit board may occur. This causes a problem that the reliability of the device is reduced.
[0012]
The present invention has been made to solve the above problems, and has as its object to provide a small and highly reliable high-power semiconductor device.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a high-power semiconductor device according to the present invention includes a first insulated circuit board having a conductor layer on an upper surface, and a main electrode fixed on the conductor layer of the insulated circuit board and having a main electrode on the upper surface. A power semiconductor chip, a second insulating circuit board disposed above the power semiconductor chip, and a conductor layer fixed to a main electrode of the power semiconductor chip; and the first and second insulation boards. An external lead-out terminal electrically connected to the conductor layer of the circuit board, wherein the second insulated circuit board has an insulating board having vias penetrating both upper and lower surfaces, and both main surfaces of the insulating board. And a conductive layer formed on the inner wall of the via, and a buffer member having a smaller linear expansion coefficient than the conductive layer, and disposed opposite to the main electrode of the power semiconductor chip and fixed to the conductive layer. It is characterized by having.
[0014]
According to the high-power semiconductor device of the present invention thus configured, the power semiconductor chip is formed on both surfaces of the conductor layer of the first insulated circuit board and the second laminated insulated circuit board and in the via. Since the terminal is connected to the external lead-out terminal via the conductor layer, a bonding region using a metal wire is not required, and the size can be reduced.
[0015]
Also, a buffer member having a smaller linear expansion coefficient than the conductor layer is disposed in the second laminated insulated circuit board so as to face the main electrode of the power semiconductor chip, and the conductor layer to which the main electrode of the power semiconductor chip is fixed is attached. It is stuck to. As a result, stress due to the difference in linear expansion coefficient between the power semiconductor chip and the conductor layer of the laminated insulated circuit board is reduced, and the reliability of the fixed portion between the conductor layer of the laminated insulated circuit board and the main electrode of the power semiconductor chip is improved. Can improve.
[0016]
In order to achieve the above object, a high-power semiconductor device according to the present invention includes a first insulated circuit board having a conductor layer on an upper surface, a first insulated circuit board fixed on the conductor layer of the insulated circuit board, and A power semiconductor chip having electrodes; a second insulated circuit board disposed above the power semiconductor chip and having a conductor layer fixed to a main electrode of the power semiconductor chip; External lead-out terminals electrically connected to the conductor layers of the insulated circuit board, wherein the second insulated circuit board has vias penetrating the upper and lower surfaces, and both surfaces of the insulated substrate. And a conductive layer formed on the inner wall of the via, and a net-like thin metal buffer member fixed to the conductive layer on the power semiconductor chip side and fixed to the main electrode of the power semiconductor chip. It is characterized by the following.
[0017]
According to the high power semiconductor device of the present invention having such a configuration, the power semiconductor chip includes the conductor layer formed on both surfaces of the conductor layer of the first insulated circuit board and the second laminated insulated circuit board and in the via. Since the terminal is connected to the external lead-out terminal via the layer, a bonding region using a metal wire is not required, and the size can be reduced.
[0018]
In addition, a buffer member made of a reticulated metal wire is fixed to a conductor layer fixed to the main electrode of the power semiconductor chip, and the deformation of the buffer member causes a wire between the power semiconductor chip and the conductor layer of the laminated insulated circuit board. Stress due to the difference in expansion coefficient is reduced, and the reliability of the portion where the conductor layer of the laminated insulated circuit board and the main electrode of the power semiconductor chip are fixed can be improved.
[0019]
Further, in order to achieve the above object, a high power semiconductor device according to the present invention includes a first insulating circuit board having a conductor layer on an upper surface, a first insulating circuit board fixed on the conductor layer of the insulating circuit board, and A power semiconductor chip having electrodes; a second insulated circuit board disposed above the power semiconductor chip and having a conductor layer fixed to a main electrode of the power semiconductor chip; External lead-out terminals electrically connected to the conductor layers of the insulated circuit board, wherein the second insulated circuit board has vias penetrating the upper and lower surfaces, and both surfaces of the insulated substrate. And a conductor layer formed on the inner wall of the via, and a molybdenum buffer member fixed to the conductor layer on the power semiconductor chip side and fixed to a main electrode of the power semiconductor chip. Features.
[0020]
According to the high power semiconductor device of the present invention having such a configuration, the power semiconductor chip includes the conductor layer formed on both surfaces of the conductor layer of the first insulated circuit board and the second laminated insulated circuit board and in the via. Since the terminal is connected to the external lead-out terminal via the layer, a bonding region using a metal wire is not required, and the size can be reduced.
[0021]
Further, since the molybdenum buffer member is fixed to the conductor layer fixed to the main electrode of the power semiconductor chip, the stress due to the difference in linear expansion coefficient between the power semiconductor chip and the conductor layer of the laminated insulating circuit board is reduced. As a result, the reliability of the fixed portion between the conductor layer of the laminated insulated circuit board and the main electrode of the power semiconductor chip can be improved.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
(First Embodiment)
FIG. 1 is a sectional view showing a high power semiconductor device according to the first embodiment of the present invention. First, the outline of the structure of the high-power semiconductor device of the present embodiment will be described.
[0024]
As shown in FIG. 1, in the high power semiconductor device of the present embodiment, a metal base 2 also serving as a heat radiator is attached to the bottom of a bottomless box-shaped case 1 made of a resin-made side wall. I have.
[0025]
A first insulating circuit board 3 is fixed on the metal base 2 via solder. A collector electrode 8 of a power semiconductor chip 5 on which an IGBT is formed as a power element is fixed to a predetermined conductor layer 4 on the first insulating circuit board 3 via solder.
[0026]
On the power semiconductor chip 5, a second laminated insulated circuit board 9 is disposed, and a predetermined emitter conductor layer 10 and a signal conductor layer 11 provided on the lower surface of the second laminated insulated circuit board 9 are provided. Are fixed to the emitter electrode 6 and the signal electrode 7 provided on the upper surface of the power semiconductor chip 5 via solder, respectively.
[0027]
A buffer member 20 such as a ceramic having a linear expansion coefficient smaller than that of the emitter conductor layer 10 is disposed inside the second laminated insulated circuit board 9 so as to face the emitter electrode 6. It is fixed.
[0028]
Further, the control circuit IC 16 is fixed on a signal conductor layer (not shown) formed on the upper surface of the second laminated insulated circuit board 9, and is electrically connected to the power semiconductor chip 5 by the second laminated insulated circuit board 9. Have been.
[0029]
The lead 12 for leading the collector is inserted into the second laminated insulated circuit board 9 and fixed to the conductor layer 4 on the first insulated circuit board 3 by soldering. It is supported by the insulating member 14 on the lead 12, inserted into the second laminated insulated circuit board 9, and fixed to the emitter conductor layer 15 provided inside the second laminated insulated circuit board 9 by soldering.
[0030]
A lid 17 supporting the lead 12 for leading the collector, the lead 13 for leading the emitter and the lead 30 for leading the signal is disposed on the uppermost part of the case 1, and the lead 30 for leading the signal is connected to the second laminated insulated circuit board. 9 is fixed to the signal conductor layer 29 inside by soldering. The space inside the case 1 is filled with a gel-like silicone resin 18.
[0031]
Next, a specific structure of the first insulated circuit board 3 will be described with reference to FIG. FIG. 2 is a plan view showing a state where the power semiconductor chip 5 is mounted on the first insulated circuit board 3.
[0032]
As shown in FIG. 2, the first insulated circuit board 3 has an insulating substrate 3a made of ceramics, glass epoxy resin, polyester resin, polyimide resin, or the like. A conductor layer (not shown) is formed on the lower surface of the insulating substrate 3a, and the conductor layer 4 is formed on the upper surface. On the conductor layer 4, for example, four power semiconductor chips 5 are fixed via solder. Further, the lead 12 for leading the collector is fixed to the conductor layer 4 via solder at a central connection portion 23.
[0033]
As shown in FIG. 13, the power semiconductor chip 5 has an emitter electrode 6 and a signal electrode 7 on the upper surface and a collector electrode 8 on the lower surface. Each electrode has been subjected to a metallizing process for enhancing conductive adhesion.
[0034]
In FIG. 2, a semiconductor chip 21 on which a diode for protecting a power semiconductor chip 5 by bypassing a reverse bias current generated when a load including an inductance is driven is further fixed on the conductor layer 4. .
[0035]
Next, a specific structure of the second laminated insulated circuit board 9 will be described with reference to FIGS. 3 to 6 are a plan view of each layer constituting the second laminated insulated circuit board 9 and a cross-sectional view taken along line AA.
[0036]
FIG. 3 is a plan view and a cross-sectional view of the first-layer insulated circuit board 24 from the lower side. As shown in the figure, the first-layer insulating circuit board 24 has an insulating board 24a made of glass epoxy resin, polyester resin, polyimide resin or the like. A hole 24b through which the lead 12 for leading out the collector and the insulating member 14 pass is provided at the center of the insulating substrate 24a.
[0037]
A lower emitter conductor layer 10 is provided around the lower surface of the insulating substrate 24a so as to oppose the emitter electrode 6 of the power semiconductor chip 5, and the upper surface thereof is formed so as to surround the hole 24a. The upper emitter conductor layer 15 is provided in an annular shape, and the lower emitter conductor layer 10 and the upper emitter conductor layer 15 are electrically connected by a conductor layer 25 embedded in a via.
[0038]
The emitter conductor layer 15 is provided with a connecting portion 26 for connecting the lead 13 for leading out the emitter, to which the lead 13 for leading out the emitter is connected.
[0039]
A lower signal conductor layer 11 is provided on the lower surface of the insulating substrate 24a so as to face the signal electrode 7 of the power semiconductor chip 5, and an upper signal conductor layer 24c is provided on the upper surface. The lower signal conductor layer 11 and the upper signal conductor layer 24c are electrically connected by a conductor layer 19a embedded in a via.
[0040]
Although not shown, a conductor layer connected to the electrode of the semiconductor chip 21 is provided on the insulating substrate 24a.
[0041]
FIG. 4 is a plan view and a cross-sectional view of a second-layer insulated circuit board 27 constituting the laminated insulated circuit board 9. As shown in the figure, the second-layer insulated circuit board 27 has an insulating board 27a made of glass epoxy resin, polyester resin, polyimide resin or the like. In the center of the insulating substrate 27a, a hole 27b through which the lead 12 for leading out the collector, the insulating member 14 and the lead 13 leading out of the emitter pass is provided corresponding to the hole 24b of the first-layer insulating circuit board 24. ing.
[0042]
In the insulating substrate 27a, a buffer member 20 made of a material such as ceramic having a smaller linear expansion coefficient than that of the insulating substrate 27a is provided in a hole provided at a position corresponding to the emitter electrode 6 of the power semiconductor chip 5. Mated. This buffer member 20 is formed in substantially the same shape and area as the emitter electrode 6.
[0043]
The lower surface of the buffer member 20 is provided with a connection layer 20a which has been metallized by plating or the like, and is fixed to the emitter conductor layer 15 of the first insulating circuit board 24 via solder.
[0044]
A lower signal conductor layer 27c is provided on the lower surface of the insulating substrate 27a so as to face the signal conductor layer 24c of the first insulating circuit board 24. The upper signal conductor layer 27c is provided on the upper surface thereof. The lower signal conductor layer 27c and the upper signal conductor layer 27d are electrically connected by a conductor layer 19b embedded in a via. The lower signal conductor layer 27c is electrically connected to the upper signal conductor layer 24c of the first-layer insulated circuit board 24.
[0045]
FIG. 5 is a plan view and a cross-sectional view of the third-layer insulating circuit board 28 constituting the laminated insulating circuit board 9. As shown in the figure, the third-layer insulated circuit board 28 has an insulating board 28a made of glass epoxy resin, polyester resin, polyimide resin or the like. A hole 28b through which the lead 12 for leading the collector, the insulating member 14, and the lead 13 for leading the emitter pass is provided at a central portion of the insulating substrate 28a so as to correspond to the hole 27b of the second-layer insulating circuit board 27. ing.
[0046]
Further, a lower signal conductor layer 28c is provided around the lower surface of the insulating substrate 28a so as to face the signal conductor layer 27d of the second insulated circuit board 27. An upper signal conductor layer 29 having a predetermined pattern for electrically connecting the conductive layers is provided, and the lower signal conductor layer 28c and the upper signal conductor layer 29 are separated by a conductor layer 19c embedded in a via. It is electrically connected.
[0047]
The lower signal conductor layer 28c and the upper signal conductor layer 27d of the second-layer insulated circuit board 27 are electrically connected.
[0048]
The upper signal conductor layer 29 is provided with a connection portion 31 for connecting the signal derivation lead 30, to which the signal derivation lead 30 is connected.
[0049]
FIG. 6 is a plan view of the uppermost fourth-layer insulating circuit board 32 of the laminated insulating circuit board 9. As shown in the figure, the fourth-layer insulated circuit board 32 has an insulating board 32a of glass epoxy resin, polyester resin, polyimide resin or the like. The insulating substrate 32a includes a hole 32b through which the lead 12 for leading out of the collector, a lead 13 through which lead out of the emitter and the insulating member 14 pass, and a hole 32c through which the lead 30 through which the signal leads out pass. Are provided corresponding to the holes 28b and the connection portions 31 of the signal lead-out leads 30, respectively.
[0050]
Although not shown, a wiring conductor layer for electrically connecting the control circuit IC 16 and a predetermined electrode of the power semiconductor chip 5 is provided on the upper surface of the fourth-layer insulating circuit board 32. .
[0051]
Next, a specific configuration of the collector lead 12 and the emitter lead 13 will be described with reference to FIGS. 7 and 8. FIG. FIG. 7 is a plan view of the terminal portion, and FIG. 8 is a cross-sectional view of the terminal portion along line BB of FIG.
[0052]
As shown in the figure, the lead 12 for leading out the collector and the lead 13 for leading out the emitter are both formed by molding a metal plate, and the upper end is bent into an inverted L-shape, and the power wiring body of the external circuit is screwed. A screw hole for fixing is provided, and a lower end portion is also bent into an L-shape to increase a connection area with a conductor layer on the insulated circuit board so as to realize secure fixing.
[0053]
According to such a high-power semiconductor device of the first embodiment, the power semiconductor chip 5 includes the conductor layer 4 of the first insulated circuit board 3 and the both sides of the second laminated insulated circuit board 9 and the inside of the via. Are connected to external lead-out terminals such as a collector lead-out lead 12, an emitter lead-out lead 13, and a signal lead-out lead 30 through conductor layers such as the emitter conductor layer 10 and the signal conductor layer 11 formed in the above. For this reason, a bonding area using a metal wire is not required, and the device can be downsized.
[0054]
Also, a buffer member 20 made of ceramic having a linear expansion coefficient smaller than that of the emitter conductor layer of the insulating substrate 27a is disposed in the second laminated insulated circuit board 9 so as to face the emitter electrode 6 of the power semiconductor chip 5, and The emitter electrode 6 of the semiconductor chip 5 is fixed to the emitter conductor layer 10 to be fixed. Therefore, the stress due to the difference in linear expansion coefficient between the power semiconductor chip 5 and the emitter conductor layer 10 of the laminated insulating circuit board 9 is reduced, and the emitter conductor layer 10 of the laminated insulating circuit board 9 and the emitter electrode of the power semiconductor chip 5 are reduced. Failures such as peeling at the portion fixed to the semiconductor device 6 can be reduced, and a highly reliable high-power semiconductor device can be realized.
[0055]
(Second embodiment)
Next, a high power semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 9 is a sectional view of a high-power semiconductor device according to the second embodiment. Regarding each part of the second embodiment, the same parts as those of the high power semiconductor device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0056]
The high power semiconductor device of the present embodiment is different from the first embodiment in that the second-layer insulating circuit board 27 of the second laminated insulating circuit board 9 of the first embodiment is different from the first embodiment. In the second laminated insulated circuit board 33, the emitter conductor layer 10 and the signal conductor layer 11 on the power semiconductor chip 5 side of the first insulated circuit board of the second layer insulated circuit board are each provided with a mesh member made of, for example, copper as a buffer member. The thin wires 34 and 35 are fixed to each other, and the reticulated metal thin wires 34 and 35 are fixed to the emitter electrode 6 and the signal electrode 7 of the power semiconductor chip 5 by soldering.
[0057]
That is, as shown in FIG. 10, in the first-layer insulating circuit board 24 of the second laminated insulating circuit board 33, the lead-out lead 12 and the insulating member 14 pass through the center of the insulating board 24a. A hole 24b is provided, and a lower emitter conductor layer 10 is provided around the lower surface of the insulating substrate 24a so as to face the emitter electrode 6 of the power semiconductor chip 5, and a hole 24a is provided on the upper surface thereof. An annular upper emitter conductor layer 15 is provided so as to surround the lower emitter conductor layer 15, and the lower emitter conductor layer 10 and the upper emitter conductor layer 15 are electrically connected by a conductor layer 25 embedded in a via. .
[0058]
A lower signal conductor layer 11 is provided on the lower surface of the insulating substrate 24a so as to face the signal electrode 7 of the power semiconductor chip 5, and an upper signal conductor layer 24c is provided on the upper surface. The lower signal conductor layer 11 and the upper signal conductor layer 24c are electrically connected by a conductor layer 19a embedded in a via.
[0059]
On the lower emitter conductor layer 10 and the lower signal conductor layer 11, thin net-like metal wires 34 and 35 made of a net-like conductive metal such as Cu are fixed.
[0060]
Other configurations are the same as those of the first embodiment. Further, the reticulated thin metal wire may be provided at least between the emitter electrode 6 and the emitter conductor layer 10 that generate particularly large heat, and is not necessarily provided between the signal electrode 7 and the signal conductor layer 11.
[0061]
According to such a high-power semiconductor device of the second embodiment, the power semiconductor chip 5 includes the conductor layer 4 of the first insulating circuit board 3 and both sides of the second laminated insulating circuit board 33 and the inside of the via. Are connected to external lead-out terminals such as a collector lead-out lead 12, an emitter lead-out lead 13, and a signal lead-out lead 30 via conductor layers such as an emitter conductor layer 10 and a signal conductor layer 11 formed in the above. For this reason, a bonding area using a metal wire is not required, and the device can be downsized.
[0062]
Further, mesh metal fine wires 34 and 35 are fixed to each of the emitter conductor layer 10 and the signal conductor layer 11 of the second laminated insulated circuit board 33, and these mesh metal wires 34 and 35 are connected to the emitter electrode of the power semiconductor chip 5. 6 and the signal electrode 7.
[0063]
Therefore, when the emitter conductor layer 10 and the signal conductor layer 11 thermally expand due to the heat from the power semiconductor chip 5, the reticulated metal wires 34 and 35 are flexibly deformed, and the emitter electrode 6, the signal electrode 7, and the emitter conductor Since the stress applied to the fixed portion between the layer 10 and the signal conductor layer 11 is reduced, the emitter conductor layer 10 and the signal conductor layer 11 of the second laminated insulating circuit board 33 and the emitter electrode 6 and the signal electrode of the power semiconductor chip 5 are reduced. Failure such as peeling at a portion where the semiconductor device 7 is fixed can be reduced, and a highly reliable high-power semiconductor device can be realized.
[0064]
(Third embodiment)
Next, a high power semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 11 is a sectional view of a high-power semiconductor device according to the third embodiment. Regarding the respective parts of the third embodiment, the same parts as those of the respective parts of the high-power semiconductor device according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0065]
The high power semiconductor device of the present embodiment is different from the first embodiment in that the second-layer insulating circuit board 27 of the second laminated insulating circuit board 9 of the first embodiment is different from the first embodiment. Then, for example, molybdenum buffer members 37 and 38 are fixed to the emitter conductor layer 10 and the signal conductor layer 11 on the power semiconductor chip 5 side of the first insulating circuit board of the second laminated insulating circuit board 36, respectively. The molybdenum buffer members 37 and 38 are fixed to the emitter electrode 6 and the signal electrode 7 of the power semiconductor chip 5 by soldering.
[0066]
That is, as shown in FIG. 12, in the first-layer insulating circuit board 24 in the second laminated insulating circuit board 36, the lead-out lead 12 and the insulating member 14 pass through the center of the insulating board 24a. A hole 24b is provided, and a lower emitter conductor layer 10 is provided around the lower surface of the insulating substrate 24a so as to face the emitter electrode 6 of the power semiconductor chip 5, and a hole 24a is provided on the upper surface thereof. An annular upper emitter conductor layer 15 is provided so as to surround it, and the lower emitter conductor layer 10 and the upper emitter conductor layer 15 are electrically connected by a conductor layer 25 embedded in a via. .
[0067]
A lower signal conductor layer 11 is provided on the lower surface of the insulating substrate 24a so as to face the signal electrode 7 of the power semiconductor chip 5, and an upper signal conductor layer 24c is provided on the upper surface. The lower signal conductor layer 11 and the upper signal conductor layer 24c are electrically connected by a conductor layer 19a embedded in a via.
[0068]
Molybdenum buffer members 37 and 38 having a smaller linear expansion coefficient than these conductor layers are fixed to the lower emitter conductor layer 10 and the lower signal conductor layer 11.
[0069]
Other configurations are the same as those of the first embodiment. Further, the molybdenum buffer member may be provided at least between the emitter electrode 6 and the emitter conductor layer 10 which generate particularly large heat, and is not necessarily provided between the signal electrode 7 and the signal conductor 11.
[0070]
According to such a high power semiconductor device of the third embodiment, the power semiconductor chip 5 includes the conductor layer 4 of the first insulated circuit board 3 and the second laminated insulated circuit board 36 on both sides and in the via. Are connected to external lead-out terminals such as a collector lead-out lead 12, an emitter lead-out lead 13, and a signal lead-out lead 30 via conductor layers such as an emitter conductor layer 10 and a signal conductor layer 11 formed in the above. For this reason, a bonding area using a metal wire is not required, and the device can be downsized.
[0071]
Further, molybdenum buffer members 37 and 38 are fixed to each of the emitter conductor layer 10 and the signal conductor layer 11 of the second laminated insulated circuit board 36, and the molybdenum buffer members 37 and 38 are attached to the power semiconductor chip 5. It is fixed to the emitter electrode 6 and the signal electrode 7. Therefore, when the emitter conductor layer 10 and the signal conductor layer 11 thermally expand due to heat from the power semiconductor chip 5, the coefficient of linear expansion of the molybdenum buffer members 37 and 38 is different from the coefficient of linear expansion of the power semiconductor chip 5. Since the difference is small, the stress applied to the portion where the emitter electrode 6 and the signal electrode 7 are fixed to the emitter conductor layer 10 and the signal conductor layer 11 is reduced, so that the emitter conductor layer 10 and the signal Failures such as peeling at a portion where the conductor layer 11 and the emitter electrode 6 and the signal electrode 7 of the power semiconductor chip 5 are fixed can be reduced, and a highly reliable high power semiconductor device can be realized.
[0072]
The present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the spirit of the invention.
[0073]
For example, in the above embodiment, instead of the case 1, it may be molded with a resin such as epoxy, or the structure may be such that the base 2 is omitted in order to reduce heat resistance and cost.
[0074]
Further, the power semiconductor chip 5 is not limited to the structure of the emitter electrode shown in FIG. 13, but may have an emitter electrode structure divided into a plurality of islands as shown in FIG. 14. In this case, The stress in the portion of the laminated insulated circuit board fixed to the conductor layer can be reduced.
[0075]
The power semiconductor chip 5 may include a plurality of control signal electrodes 39 as shown in FIG. 15 and incorporate a control circuit therein. The control circuit having an overheat prevention function, an overvoltage prevention function, an energy saving function, and the like. , The size of the large power semiconductor device is reduced by the space including the uppermost insulating circuit board.
[0076]
In the first to third embodiments, the wiring shape of the emitter conductor layer 15 of the first insulating circuit board 24 of the second laminated insulated circuit boards 9, 33, 36 is limited to an annular shape. Instead, the wiring shape may be such that electrical connection between the connection portion 26 and the emitter electrode of the power semiconductor chip 5 and the semiconductor chip 21 can be secured.
[0077]
In the first to third embodiments, the first insulated circuit board 3 and the second laminated insulated circuit boards 9, 33, 36 may all be constituted by insulating boards made of ceramics. In this case, since the difference between the coefficient of linear expansion of the insulating circuit board and the coefficient of linear expansion of the power semiconductor chip 5 is small, the emitter electrode, the signal electrode, and the collector electrode of the power semiconductor chip 5, the emitter conductor layer, and the signal conductor The stress applied to the respective fixed surfaces of the layer and the collector conductor layer is reduced, and the reliability is improved.
[0078]
In the first to third embodiments, the emitter conductor layer 15 covers the emitter conductor layer 10 on the lower surface of the first-layer insulation circuit board 24 of the second multilayer insulated circuit boards 9, 33, and 36. Further, on the upper surface, an emitter conductor layer and a signal conductor layer 29 corresponding to the connection portion 26 for connecting the emitter lead-out lead are provided, and the emitter conductor layer of the connection portion 26 on the upper surface and the emitter conductor layer 15 on the lower surface are provided. May be connected using a via or a metal plate whose cross section is bent in a U-shape. With such a configuration, the third-layer insulating circuit board 28 can be removed.
[0079]
In the first to third embodiments, the emitter conductor layer 15 of the first insulating circuit board 24 of the second laminated insulated circuit boards 9, 33, and 39 has a plurality of emitter conductor layers provided with the emitter conductor layers. You may make it comprise laminated | stacked insulated circuit boards.
[0080]
In the first to third embodiments, an insulating circuit board having an emitter conductor layer may be additionally provided on the uppermost layer of the second laminated insulated circuit boards 9, 33, and 39. The current density in the conductor layer can be reduced to reduce heat generation in the conductor layer, and also reduce mixing of a noise signal from the outside into the signal conductor layer.
[0081]
In the second and third embodiments, the second-layer insulated circuit board of the first embodiment may be added to the laminated insulated circuit boards 33 and 36 to form a four-layer structure.
[0082]
【The invention's effect】
According to the present invention, a small and highly reliable semiconductor device for large power can be realized.
[Brief description of the drawings]
FIG. 1 is a sectional view of a high-power semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a plan view of a first insulated circuit board of the high-power semiconductor device according to the first embodiment of the present invention.
FIGS. 3A and 3B are a plan view and a cross-sectional view of a first-layer insulating circuit board constituting a second laminated insulating circuit board of the high-power semiconductor device according to the first embodiment of the present invention; FIGS.
FIGS. 4A and 4B are a plan view and a cross-sectional view of a second-layer insulating circuit board constituting a second laminated insulating circuit board of the high-power semiconductor device according to the first embodiment of the present invention;
FIGS. 5A and 5B are a plan view and a cross-sectional view of a third-layer insulated circuit board constituting a second laminated insulated circuit board of the high-power semiconductor device according to the first embodiment of the present invention; FIGS.
FIG. 6 is a plan view of a fourth-layer insulating circuit board constituting a second laminated insulating circuit board of the high-power semiconductor device according to the first embodiment of the present invention;
FIG. 7 is a plan view of an external lead-out terminal part constituting a second laminated insulated circuit board of the present invention.
FIG. 8 is a cross-sectional view of the external lead-out terminal section taken along the line BB of FIG. 7;
FIG. 9 is a sectional view of a high-power semiconductor device according to a second embodiment of the present invention.
FIGS. 10A and 10B are a plan view and a cross-sectional view of a first-layer insulating circuit board constituting a second laminated insulating circuit board of a high-power semiconductor device according to a second embodiment of the present invention.
FIG. 11 is a sectional view of a high-power semiconductor device according to a third embodiment of the present invention.
FIG. 12 is a plan view and a cross-sectional view of a first-layer insulating circuit board included in a second laminated insulating circuit board of a high-power semiconductor device according to a third embodiment of the present invention.
FIG. 13 is a plan view showing an electrode structure of a power semiconductor chip.
FIG. 14 is a plan view showing another electrode structure of the power semiconductor chip.
FIG. 15 is a plan view showing still another electrode structure of the power semiconductor chip.
FIG. 16 is a configuration diagram of a conventional high-power semiconductor device.
[Explanation of symbols]
1, 101 cases
2,102 metal base
3,103 First insulated circuit board
4,104 Conductive layer on first insulated circuit board
5,105 Power semiconductor chips
6 Emitter electrode
7 Signal electrode
8 Collector electrode
9, 33, 36 Second laminated insulated circuit board
10, 15 Emitter conductor layer (conductor layer) on second laminated insulated circuit board
11 Signal conductor layer (conductor layer) on second laminated insulated circuit board
12 Lead for leading the collector (external lead terminal)
13 Emitter lead (external lead terminal)
30 Lead for signal derivation (external derivation terminal)
14 Insulation member
16, 110 control circuit IC
17, 114 Lid
18, 116 silicone resin
19a, 19b, 19c, 25 Conductor layer in via
20, 34, 35, 37, 38 cushioning member
21 Semiconductor chip
23, 26, 31 Connection
24, 27, 28, 32, 33, 36 Insulated circuit board constituting second laminated insulated circuit board
39a, 39b, 39c, 39d Control signal electrodes of power semiconductor chip
106, 107, 109, 112 metal wire
108,113 Lead for external derivation
111 second insulated circuit board
115 Conductive Layer on Second Insulated Circuit Board

Claims

A first insulating circuit board having a conductor layer on an upper surface,
A power semiconductor chip fixed on a conductor layer of the insulated circuit board and having a main electrode on an upper surface;
A second insulating circuit board disposed above the power semiconductor chip and having a conductor layer fixed to a main electrode of the power semiconductor chip;
External lead-out terminals electrically connected to the conductor layers of the first and second insulated circuit boards, respectively.
The second insulated circuit board includes:
An insulating substrate having vias penetrating the upper and lower surfaces,
A conductor layer formed on both main surfaces of the insulating substrate and the inner wall of the via,
A high-power semiconductor device having a coefficient of linear expansion smaller than that of the conductor layer, and having a buffer member disposed opposite to the main electrode of the power semiconductor chip and fixed to the conductor layer.

The power semiconductor device according to claim 1, wherein the buffer member is made of ceramic.

The large power according to claim 1 or 2, further comprising an envelope that seals the first and second insulated circuit boards, the power semiconductor chip, and a part of the external lead-out terminal. For semiconductor devices.

3. The large power semiconductor according to claim 1, wherein each of the power semiconductor chip and the buffer member includes a plurality of members, and the buffer member is arranged to face the power semiconductor chip. 4. apparatus.

The high power semiconductor according to any one of claims 1 to 4, wherein a control circuit IC electrically connected to the power semiconductor chip is arranged on the second insulating circuit board. apparatus.

A first insulating circuit board having a conductor layer on an upper surface,
A power semiconductor chip fixed on a conductor layer of the insulated circuit board and having a main electrode on an upper surface;
A second insulating circuit board disposed above the power semiconductor chip and having a conductor layer fixed to a main electrode of the power semiconductor chip;
External lead-out terminals electrically connected to the conductor layers of the first and second insulated circuit boards, respectively.
The second insulated circuit board includes:
An insulating substrate having vias penetrating the upper and lower surfaces,
A conductor layer formed on both sides of the insulating substrate and the inner wall of the via,
A high-power semiconductor device comprising: a net-like thin metal wire buffer member fixed to the conductor layer on the power semiconductor chip side and fixed to a main electrode of the power semiconductor chip.

7. The high-power semiconductor device according to claim 6, wherein the buffer member is a reticulated metal wire made of copper.

A first insulating circuit board having a conductor layer on an upper surface,
A power semiconductor chip fixed on a conductor layer of the insulated circuit board and having a main electrode on an upper surface;
A second insulating circuit board disposed above the power semiconductor chip and having a conductor layer fixed to a main electrode of the power semiconductor chip;
External lead-out terminals electrically connected to the conductor layers of the first and second insulated circuit boards, respectively.
The second insulated circuit board includes:
An insulating substrate having vias penetrating the upper and lower surfaces,
A conductor layer formed on both sides of the insulating substrate and the inner wall of the via,
A high power semiconductor device comprising: a molybdenum buffer member fixed to the conductor layer on the power semiconductor chip side and fixed to a main electrode of the power semiconductor chip.