JP2004080006A - Manufacturing method of semiconductor device - Google Patents

Abstract

A semiconductor device that reduces the number of manufacturing steps and achieves cost reduction is provided.
A method of manufacturing a semiconductor device according to the present invention includes a step of forming metal pads 2a and 2b on a Si substrate 1 via a first oxide film 3, and supporting the Si substrate 1 and the Si substrate 1. A step of bonding the supporting substrate 8 to be bonded via the adhesive film 7 and etching the back surface of the Si substrate 1 to form an opening, and then forming a second oxide film in the back surface of the Si substrate 1 and in the opening. Forming a wiring 12 connected to the metal pads 2a and 2b after etching the second oxide film 10, and forming a conductive terminal 14 on the wiring 12; It has the process of dicing from the back surface of the Si substrate 1 to the said adhesive film 7, and the process of isolate | separating the said Si substrate 1 and the said support substrate 8. It is characterized by the above-mentioned.
[Selection] Figure 7

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a BGA (Ball Grid Array) type semiconductor device having ball-shaped conductive terminals.
[0002]
[Prior art]
Conventionally, there is a BGA type semiconductor device as a kind of surface mount type semiconductor device. In this method, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a grid pattern on one main surface of a package substrate, and bonded to a semiconductor chip mounted on the other main surface of the substrate for packaging. Is. And when incorporating in an electronic device, each conductive terminal is heat-welded to the wiring pattern on a printed circuit board, and a semiconductor chip and the external circuit mounted on a printed circuit board are electrically connected.
[0003]
Such a BGA type semiconductor device has a larger number of connection terminals than other surface mount type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side surface of the semiconductor device. It can be installed, and it is known that downsizing is advantageous.
[0004]
In recent years, this BGA type semiconductor device has been incorporated into the field of CCD image sensors, and is used as an image sensor chip for a digital camera mounted on a mobile phone that is strongly demanded for miniaturization.
[0005]
Further, three-dimensional mounting technology using wafer level CSP (Chip Size Package) or silicon (Si) penetration technology has been attracting attention. In these techniques, a method of stacking chips after stacking layers and then penetrating Si, or passing Si wafers through Si from the surface and then stacking them has been studied.
[0006]
[Patent Literature]
Japanese translation of PCT publication No. 2002-512436
[Problems to be solved by the invention]
However, since the conventional three-dimensional mounting technology performs processing such as Si penetration from the surface and fills the via hole with copper (Cu), it requires CMP (Chemical Mechanical Polishing) treatment on the surface side, Cu Since rewiring for connecting the Cu via and the pad is necessary after the via is formed, there is a drawback that the number of manufacturing steps increases. Moreover, although the technique using Cu is suitable for miniaturization, since the cost of Cu itself is high and a special apparatus has to be purchased separately, the high cost is unavoidable.
[0008]
[Means for Solving the Problems]
Accordingly, the present invention provides a step of forming a metal pad on a semiconductor wafer via a first insulating film, a step of bonding the wafer and a support substrate supporting the wafer via a film, and a back surface of the wafer Forming a second insulating film on the back surface of the wafer and in the opening, and wiring connected to the metal pad after etching the second insulating film Forming a protective film on the wiring, forming an electrode on the wiring not covered with the protective film, dicing from the back surface of the wafer to the film, The present invention provides a method for manufacturing a semiconductor device, comprising a step of separating the wafer and the support substrate.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
[0010]
First, as shown in FIG. 1, an oxide film is formed on a semiconductor wafer (hereinafter referred to as Si substrate 1) having a thickness of about 600 μm, and a plurality of metals (for example, Al, Al alloy, Cu, etc.) are formed on the oxide film. Pads 2a and 2b are formed, a SiO2 film or a PSG film is formed by plasma CVD so as to cover the pads 2a and 2b, and this and the oxide film are combined to form a first oxide film 3 having a predetermined thickness. Form. The pads 2a and 2b are connected to semiconductor elements formed on the Si substrate 1. Further, when flatness is particularly required, the first oxide film 3 may be physically polished, chemically etched, or the like. Then, using the photoresist film (not shown) as a mask, the first oxide film 3 on the pads 2a and 2b is etched to expose a part (surface portion) of the pads 2a and 2b. Thereafter, a first wiring 4 made of Al, Al alloy, Cu or the like is applied to the surfaces of the pads 2a and 2b. In the present embodiment, the thickness of the first oxide film 3 is about 5 μm as a whole.
[0011]
Next, as shown in FIG. 2, a polyimide film 5 is formed on the surface of the first wiring 4, and the polyimide film 5 is etched using a photoresist film (not shown) as a mask to be connected to the pads 2a and 2b. An opening is formed on the first wiring 4. FIG. 2 shows a state in which the openings are formed at both ends of the polyimide film 5.
[0012]
Then, after nickel (Ni) and gold (Au) (not shown) are formed in the opening, copper (Cu) is plated on the Cu post 6 by a general plating apparatus used in a semiconductor subsequent process. Embed. Further, Au may be plated on the Cu post 6 for preventing corrosion of the Cu post 6. In the present embodiment, the film thickness of the conductive member (Ni, Au, Cu, Au) embedded in the opening is about 25 μm as a whole.
[0013]
Here, when the present process is applied to a CSP process that is not used in a three-dimensional process, it is not necessary to form an opening and bury a conductive member, and the entire surface of the polyimide film 5 may be applied.
Alternatively, a support substrate 8 described later may be bonded to the upper side of the Si substrate 1 using an adhesive film without the polyimide film 5.
[0014]
Furthermore, when this process is employed in a CCD image sensor, the polyimide film 5 needs to be formed by using a screen printing method, such as a transparent polyimide film or a transparent glass epoxy resin.
[0015]
Alternatively, a glass plate material may be bonded using an epoxy resin.
[0016]
Subsequently, as shown in FIG. 3A, an adhesive film 7 is pasted on the polyimide film 5 including the Cu post 6 (or Cu post 6 / Au), and the support substrate 8 and the above-described film are interposed via the adhesive film 7. The Si substrate 1 side is bonded.
[0017]
Here, the support substrate 8 is a support material for preventing cracking of the Si substrate 1 during BG (back grinding) of the Si substrate 1 to be described later. For example, a Si substrate, an oxide film, a glass substrate, a ceramic, or the like is used. We are using. In the present embodiment, the film thickness necessary for the support material is about 400 μm.
[0018]
The adhesive film 7 employs an organic film soluble in acetone for the purpose of improving workability in the process of separating the Si substrate 1 and the support substrate 8 described later. In the present embodiment, the thickness of the adhesive film 7 is about 100 μm. The adhesive film 7 is disposed about 2 mm inside from the wafer edge for filling an epoxy resin 9 described later.
[0019]
Here, instead of the adhesive film 7, a film having no adhesive force may be used, and an adhesive may be attached to both surfaces of the film to bond the support substrate 8, the film, and the Si substrate 1 side. In this case, the support substrate 8, the Si substrate 1, and the film may be separated by dissolving the adhesive using a solvent that dissolves the adhesive.
[0020]
FIG. 3B is a schematic view and a plan view of FIG. 3A (plan view when the support substrate 8 is removed for convenience of explanation).
[0021]
The adhesive film 7 is sealed and hardened by filling the outer peripheral portion of the adhesive film 7 with an epoxy resin 9 as shown in FIG. This prevents the entry of chemicals such as organic solvents during various operations. Here, the epoxy resin 9 may be a polyimide resin.
[0022]
Next, as shown in FIG. 4A, the Si substrate 1 side is BG-processed to reduce the thickness of the Si substrate 1 to about 10 to 100 μm. At this time, the support substrate 8 supports the Si substrate 1 during the BG process. Then, the back side of the BG-treated Si substrate 1 and the first oxide film 3 are etched to form a first opening K1 so that the pads 2a and 2b are exposed.
[0023]
Further, as shown in FIG. 4B, after the second oxide film 10 is deposited on the back side of the Si substrate 1, the second oxide film 10 is etched using a photoresist film (not shown) as a mask. Two openings K2 are formed. Here, the first oxide film 3a is an etching remainder of the first oxide film 3 between the pad 2a and the pad 2b. In place of the second oxide film 10, a silicon nitride film, a polyimide film or the like may be used.
[0024]
Furthermore, in this embodiment, as shown in FIG. 4A, the first oxide film 3 is etched following the etching process of the Si substrate 1, and the Si substrate 1 including the opening K1 is formed on the Si substrate 1. The second oxide film 10 is formed, and the second oxide film 10 is etched to form the opening K2. For example, in the process corresponding to FIG. 4A, only the Si substrate 1 is etched. The second oxide film 10 is formed with the first oxide film 3 left under the pads 2a and 2b, and the second oxide film 10 and the first oxide film 3 are etched to form openings. It may be one that forms K2.
[0025]
Next, as shown in FIG. 5, the buffer member 11 is formed at a desired position on the surface of the second oxide film 10, and the surface of the buffer member 11, the surface of the second oxide film 10, and the second oxide film 10 are formed. Al, Al alloy, Cu, or the like is formed by sputtering so as to cover the opening K2, and the second wiring 12 is formed. The second wiring 12 may be a Cu wiring.
[0026]
Next, as shown in FIG. 6, the second wiring 12 is etched using the photoresist film (not shown) as a mask so that the first oxide film 3a is exposed. That is, by this etching, the exposed surfaces of the back surfaces of the pads 2a and 2b are covered with the second wiring 12, and the end portions of the pads 2a and 2b and the etching cross section of the second wiring 12 are formed to substantially coincide. . As a result, each of the pads 2a and 2b and the second wiring 12 are formed so as to have a surface contact of about 10 to several 100 μm. After the wiring is formed, electroless plating of nickel (Ni) and gold (Au) is performed.
Further, instead of Al sputtering, titanium tungsten (TiW) is sputtered, and after resist formation, electrolytic plating of copper (Cu) is performed, the resist is removed, and then titanium tungsten (TiW) is etched to form the second. The wiring 12 may be formed.
[0027]
Then, a solder mask (hereinafter referred to as a protective film 13) is formed on the surface of the second wiring 12, a solder paste is screen-printed on the protective film 13, and the solder paste is subjected to a reflow process. Solder balls (hereinafter referred to as conductive terminals 14) are formed on the second wiring 12. In this embodiment, as the protective film 13, a polyimide film made of Rika Coat (product of Shin Nippon Chemical Co., Ltd.) that can be imidized at 200 ° C. is used.
[0028]
Next, dicing is performed to form a dicing line D in the first oxide film 3a as shown in FIG. The dicing line D is provided to separate the semiconductor chips on the wafer one by one. FIG. 7B is a schematic view and a plan view of FIG. 7A (a plan view when the support substrate 8 is removed for convenience of explanation). In the schematic view of FIG. 7B, the dicing line D is formed from the back surface of the wafer to the position reaching the adhesive film 7, and in the plan view, the dicing line D is formed in a lattice shape.
[0029]
Then, by immersing the Si substrate 1 in an acetone solution tank (not shown), acetone enters from the dicing line (D) shown in FIG. 7B and dissolves the adhesive film 7. As a result, the Si substrate 1 (each chip) and the support substrate 8 are automatically separated, and a single CSP chip as shown in FIG. 8 is completed.
[0030]
Thus, in this embodiment, since the Si substrate 1 and the support substrate 8 are bonded together using the organic adhesive film 7 which melt | dissolves in acetone, after dicing, both can be made only by immersing the Si substrate 1 in acetone. It can be easily separated and has good workability.
[0031]
Further, instead of the adhesive film 7, a film having a weak adhesive force may be used to physically peel the chip after dicing. Furthermore, if transparent glass is used as the support substrate 8, a UV tape may be applied as the organic film 7, UV irradiation may be performed after dicing, and the chip may be peeled off.
[0032]
In addition, when the Si substrate 1 and the support substrate 8 are bonded to a film having no adhesive force instead of the adhesive film 7 and the Si substrate 1 and the support substrate 8 are bonded, The Si substrate 1 may be diced after the Si substrate 1 and the support substrate 8 are peeled off by UV irradiation and curing.
[0033]
In addition, after dicing, for example, heat is applied from the back surface of the wafer with a hot plate, and the organic film (adhesive film 7) sandwiched between the wafer and the support substrate 8 is melted and softened to peel off both. Also good. At this time, when the adhesive film 7 is an organic film soluble in acetone, the adhesive film 7 is melted by heating at about 200 ° C., and when a polyimide film is used, the adhesive film 7 is heated by about 400 ° C.
[0034]
As another form of peeling the Si substrate 1 and the support substrate 8, there is a method in which the epoxy resin at the edge is rotated with the wafer lengthwise and the outer periphery is immersed in a chemical such as acid (for example, sulfuric acid) before dicing. .
[0035]
In addition, as a method of directly peeling the Si substrate 1 and the support substrate 8, the epoxy resin portion on the outer periphery of the edge is shaved with a cutter such as a cutter, saw or knife, or the silicon wafer is ground together and the same portion is removed. For example, a method of removing both by shaving.
[0036]
Then, as shown in FIG. 9 as a second embodiment of the present invention, the single CSP chip (one of the semiconductor devices after separation in FIG. 8) is bonded to the Cu post 6 and the conductive terminal 14 by metal adhesion. By closely contacting (stacking) the CSP chips, three-dimensional mounting (any number of layers) is possible, and the capacity can be increased if the chip size is the same (memory, etc.).
[0037]
【The invention's effect】
In the present invention, since the wiring is formed by using a sputtering apparatus or a plating apparatus generally used in the field of mounting, a semiconductor device with a very simple process can be realized at a low cost.
[0038]
Further, since processing such as Si penetration is performed from the surface as in the conventional three-dimensional mounting technology, and via holes are not filled and formed with copper (Cu), CMP (Chemical Mechanical Polishing) is naturally necessary on the surface side in the conventional example. It is not necessary to perform the processing in this embodiment, and the number of processes can be reduced.
[0039]
Furthermore, after the formation of the Cu via in the laminated structure, rewiring for connecting the Cu via and the pad becomes unnecessary, and the number of manufacturing steps does not increase.
[0040]
Further, since the support substrate and the Si substrate are subjected to BG (back grinding) and subsequent processing after being bonded, the thickness of the chip can be made as thin as possible.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 8 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor device of the second embodiment of the present invention.

Claims (13)

Forming a metal pad on a semiconductor wafer via a first insulating film;
Bonding the wafer and a support substrate supporting the wafer through a film;
Forming a second insulating film in the back surface of the wafer and the opening after etching the back surface of the wafer to form an opening; and
Forming a wiring connected to the metal pad after etching the second insulating film;
Forming a protective film on the wiring;
Forming an electrode on the wiring not covered with the protective film;
Dicing from the back surface of the wafer to the film;
A method for manufacturing a semiconductor device, comprising the step of separating the wafer and the support substrate. 2. The semiconductor according to claim 1, wherein the step of bonding the wafer and the support substrate supporting the wafer through a film is a step of bonding only the peripheral edge portion of the wafer using an epoxy resin. Device manufacturing method. The method for manufacturing a semiconductor device according to claim 1, wherein the film is an organic film that is soluble in an acetone solution. The method of manufacturing a semiconductor device according to claim 1, wherein the film is an adhesive film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein when a UV tape is used as the film, a transparent glass is used as the support substrate, and UV irradiation is performed after the dicing step. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the wafer and the support substrate are separated by physically peeling the epoxy resin with a cutter such as a cutter, a saw, or a knife. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the wafer and the support substrate are separated by immersing the wafer in an acid and dissolving and chemically peeling the epoxy resin. 4. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the wafer and the supporting substrate are separated by grinding the peripheral portion of the wafer and grinding the epoxy resin portion. 4. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring is formed by plating nickel and gold after forming aluminum. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring is formed by performing copper plating after forming titanium tungsten. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the back surface is polished before forming the opening on the back surface of the wafer. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a wiring on the metal pad and forming a metal post for electrode connection on the wiring. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a UV-based adhesive is attached to the film to bond the semiconductor wafer and the support substrate, and then UV irradiation is performed.

Images