JP2004079722A - Method of manufacturing insulated gate field effect transistor, and said transistor - Google Patents

Abstract

When a gate electrode whose work function changes in a channel direction is formed, a gate insulating film and a semiconductor are attacked, and characteristics and reliability are reduced.
At least a source region of an impurity region formed in a semiconductor in which a channel is formed is covered with a thick insulating film, and a gate insulating film is formed on the channel forming region. To form The first conductive layer 12 is formed, the protective layer 13 is formed on a portion facing the side surface of the step, and the second conductive layer 14 is formed. Thereafter, the portion of the first conductive layer 12 in contact with the second conductive layer 14 is modified, and the work function difference of the first conductive layer 12 with respect to the channel formation region is determined above the channel formation region. And a step of differentiating the unmodified portion 12a and the modified portion 12b which are protected and not modified by the above.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an insulated gate field effect transistor having a change in work function difference with respect to a channel formation region in a gate electrode, and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, a method of controlling the threshold voltage Vth of a MOS (Metal Oxide Silicon) transistor formed on a bulk silicon substrate by changing the impurity concentration of a channel formation region has been generally used.
With respect to the threshold voltage Vth, it is known that a short channel effect, that is, a phenomenon that “a decrease in the threshold voltage Vth due to a decrease in the barrier of the channel formation region due to the drain electric field becomes significant with a decrease in the gate length Lg”.
In order to suppress the short channel effect, the channel impurity profile at the drain end to which a high electric field is applied is optimized so that the original threshold voltage Vth that appears when the gate length Lg is sufficiently long is increased as the gate length Lg is shortened. Have been dealt with.
[0003]
In order to control the channel impurity profile depending on the gate length Lg, an ion implantation technique called a pocket or a halo is generally known. In these ion implantation techniques, oblique ion implantation is performed on the gate electrode in a self-aligned manner. Accordingly, the impurity concentration at the end of the channel formation region, that is, the portion where the P-type channel formation region is in contact with the N-type source / drain regions is increased. As a result, it is possible to compensate for the decrease in the threshold voltage Vth due to the reduction in the gate length Lg.
[0004]
However, with the miniaturization of elements, it is becoming difficult to sufficiently suppress the short channel effect only by controlling the impurity profile by pocket ion implantation or halo ion implantation. This is because there is a limit in increasing the impurity concentration of halo ion implantation due to a trade-off with an increase in junction leakage in a fine transistor. In many cases, the application of halo ion implantation cannot be performed. For example, a so-called Fin-type MOS transistor is a device in which a channel is formed on the upper surface and two side surfaces of a ridge (so-called fin) of single-crystal silicon. In a device having such a three-dimensional channel, halo ion implantation cannot be applied structurally because oblique ion implantation using a gate electrode as a mask cannot be performed uniformly over the entire channel.
[0005]
In view of the above background, there is a need for a method capable of effectively suppressing the short channel effect by a method other than controlling the impurity profile of the channel formation region, such as halo ion implantation.
[0006]
In a conventional insulated gate field effect transistor, materials having different work functions are arranged in the direction of the gate length through which a channel current flows, and a gate electrode formed by electrically connecting the two is used to reduce the short channel effect of the transistor. Proposals have been made to achieve suppression (for example, see Patent Document 1).
Patent Document 1 discloses various types of gate electrode structures. Roughly speaking, a conventional first method in which a gate electrode is formed and then covered with an interlayer insulating film, and a second method in which a groove is first formed in an interlayer insulating film or the like and a gate electrode material is buried in the groove. Can be categorized into methods.
In the first method, a gate electrode portion made of a second conductive material having a different work function is added outside a gate electrode made of a first conductive material. However, in this method, the gate length is increased in the process of forming the gate electrode using two types of materials, so that the final gate length Lg is longer than the minimum dimension of lithography, and is not suitable for the gate structure of a fine MOS transistor.
On the other hand, the second method is more suitable for miniaturization than the first method in that the final gate size is defined by the groove.
[0007]
6A to 6D are cross-sectional views illustrating a method for manufacturing a gate electrode of a field-effect transistor described in Patent Document 1.
As shown in FIG. 6A, in an SOI substrate in which a semiconductor layer 33 is provided on a silicon substrate 31 via a buried oxide film 32, a laminated pattern of a pad oxide film 60 and a dummy nitride film 61 is formed on the surface thereof. I do. Source / drain regions 38 are formed in the semiconductor layers on both sides of the dummy nitride film 61 and covered with a CVD oxide film 62.
[0008]
As shown in FIG. 6B, an opening 70 is provided in the CVD oxide film 62 by photolithography and RIE, and the upper portion of the dummy nitride film 61 is exposed.
[0009]
In FIG. 6C, the dummy nitride film 61 is removed by wet etching using hot phosphoric acid. Then, the pad oxide film 60 is removed with dilute hydrofluoric acid. At this time, since the surface of the CVD oxide film 62 is also partially etched, an oxide film side wall is formed to adjust the surface state.
A gate oxide film 40 is formed on the exposed surface of the semiconductor layer 33. ⁺ Deposit doped polysilicon. N ⁺ The doped polysilicon is etched back by RIE, and N ⁺ A polysilicon layer 53 is provided.
[0010]
In FIG. 6D, a W layer 54 is deposited on the entire surface, and is processed by photolithography and RIE to form a gate electrode.
[0011]
According to this method for manufacturing a field effect transistor, it is possible to change the work function of the gate electrode in the channel direction while forming a gate electrode having a size close to the minimum line width of lithography in the trench. That is, as shown in FIG. 6D, the gate electrode material is N ⁺ Polysilicon layer 53, W layer 54, N ⁺ It is different from the polysilicon layer 53. Accordingly, the work function of the gate electrode with respect to the channel formation region (the P-type region of the semiconductor layer 33) changes.
[0012]
[Patent Document 1]
JP-A-2000-12851
(Pages 14-15, Figures 19-24)
[0013]
[Problems to be solved by the invention]
In the method of manufacturing a field effect transistor described in Patent Document 1, N ⁺ There is a problem that the etch back of the doped polysilicon adversely affects the underlying thin gate oxide film 40 and the channel formation region.
[0014]
As described above, in the step of FIG. 6C, etch back is performed using RIE (Reactive Ion Etching) capable of increasing anisotropy, and a so-called sidewall (Side Wall) shape is formed on the wall surface of the groove. N ⁺ A polysilicon layer 53 is formed. At this time, the film to be etched (N ⁺ In consideration of the thickness variation of the doped polysilicon film) and the variation of the etching in the wafer surface, the over-etching amount is usually set to at least several tens of percent. Therefore, at the final stage of the etching, a part of the gate oxide film 40 is exposed to the RIE plasma. As a result, non-uniform “deformation” occurs in the gate oxide film 40 due to over-etching. At this time, the gate oxide film 40 and the Si active region (channel formation region) are more or less damaged.
The above-mentioned inconveniences appear remarkably in the form of reduced characteristics and reliability when the element is miniaturized. For this reason, in the above-described method of forming a gate electrode, there is a possibility that the characteristics and reliability may be reduced rather than forming a gate electrode with a changed work function in order to improve the characteristics and reliability of the fine transistor. In this respect, the method for forming the gate of the fine transistor is incomplete.
[0015]
SUMMARY OF THE INVENTION It is an object of the present invention to provide an insulated gate field effect including a step of forming a gate electrode having a work function changing in a channel direction without affecting characteristics and reliability of a gate insulating film and a semiconductor thereunder. An object of the present invention is to provide a transistor manufacturing method and the insulated gate field effect transistor.
[0016]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a method of manufacturing an insulated gate field effect transistor, wherein a source region and a drain region are formed separately from each other in a semiconductor in which a channel is formed, and at least the source region is formed with a thick insulating film. Forming a gate insulating film on at least a channel forming region that is a portion of the semiconductor between the source region and the drain region, and forming a step by the gate insulating film and the thick insulating film Forming a first conductive layer covering an upper surface of the gate insulating film, an upper surface of the thick insulating film, and a side surface of the step; and forming a first conductive layer facing the side surface of the step. Forming a protective layer on a surface portion, forming a second conductive layer covering the exposed surface of the first conductive layer and the protective layer, and forming the second conductive layer in contact with the second conductive layer. A portion of the conductive layer is modified, and the work function difference of the first conductive layer with respect to the channel formation region is changed to an unmodified portion that is protected by the protection layer and is not modified above the channel formation region. A step of differentiating between the modified portions and a step of processing the first conductive layer and the second conductive layer into a gate electrode pattern.
[0017]
According to this manufacturing method, a gate electrode is formed by a stacked body of the first conductive layer and the second conductive layer. When forming a gate electrode, first, a first conductive layer is formed so as to be in contact with a gate insulating film, and a second conductive layer is formed thereover without etching the formed first conductive layer. .
In order to provide a work function difference, a layer of a material having a different work function is not arranged on the gate insulating film, but a part of the first conductive layer is modified to change the work function. Specifically, a first conductive layer is formed in a portion including a step, and a protective film is formed on a side surface of the step using the step. A second conductive layer is formed thereover. As a result, a portion of the first conductive layer that does not directly contact the second conductive layer occurs at a portion in contact with the side surface of the step, and another portion of the first conductive layer contacts the second conductive layer. Next, reforming is performed. Whether or not the two conductive layers are in contact determines whether or not the reforming is performed. Therefore, as a gate electrode portion in contact with the gate insulating film, an unmodified portion near the step side surface and another modified portion are formed. When the stacked body of the conductive layers is patterned, gate electrodes having different work function differences from the channel formation region are completed.
[0018]
According to a second aspect of the present invention, there is provided a method of manufacturing an insulated gate field effect transistor, comprising: forming a gate insulating film on a semiconductor on which a channel is to be formed; Forming a sacrificial layer, forming a source region and a drain region in the semiconductor at a distance from each other by ion implantation using the sacrificial layer as a mask, and filling a periphery of the sacrificial layer with an interlayer insulating film; Removing a sacrificial layer and forming a step with the gate insulating film and the interlayer insulating film; and a first conductive layer covering an upper surface of the gate insulating film, an upper surface of the interlayer insulating film, and a side surface of the step. Forming a layer, forming a protective layer on a surface portion of the first conductive layer facing a side surface of the step, and forming a second layer covering the exposed surface of the first conductive layer and the protective layer. Forming a conductive layer, modifying a portion of the first conductive layer in contact with the second conductive layer, and forming a channel forming region that is a portion of the semiconductor between the source region and the drain region. A step of differentiating a work function difference of the first conductive layer with respect to the channel forming region between an unmodified part protected by the protective layer and not modified and a modified part, and Processing the layer and the second conductive layer into a pattern of a gate electrode.
[0019]
This second aspect corresponds to the trench gate process.
First, a sacrifice layer is formed, an interlayer insulating film is buried around the sacrifice layer, and then the sacrifice layer is removed. A gate insulating film is formed on the semiconductor surface exposed by removing the sacrificial layer. A step is formed by the thin gate insulating film and the thick interlayer insulating film.
Thereafter, as in the first aspect, the first conductive layer is formed, the protective layer is formed using a step, the second conductive layer is formed, the first conductive layer is partially modified, and the pattern of the conductive layer is formed. After finishing, the gate electrode is completed.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of an insulated gate field effect transistor (MISFET) and a method of manufacturing the same according to the present invention will be described with reference to the drawings, using a SOI MOS transistor having an N-type channel conductivity as an example. In the case where the MOS transistor is a P-type, the following description can be applied by analogy by setting the conductivity type of the impurity added to each part to the opposite polarity.
[0021]
FIG. 1 shows a sectional view of a MOS transistor.
In the MOS transistor 1 illustrated in FIG. 1, a buried insulating film 3 made of, for example, silicon oxide is formed on a substrate 2 such as a semiconductor or glass. On the buried insulating film 3, a semiconductor (hereinafter, referred to as an SOI layer) 4 made of P-type single crystal silicon or the like and having an SOI-type substrate isolation structure is formed. The thickness of the SOI layer 4 differs depending on whether the transistor is of a partially depleted type or a fully depleted type. For example, the thickness of the SOI layer 4 for making it completely depleted is set to 50 nm or less. As a method for forming such a thin SOI layer 4, a so-called substrate bonding method or a SIMOX (Separation by Implanted Oxygen) method can be employed.
[0022]
The SOI layer 4 is partially insulated, whereby an element isolation insulating layer 5 is formed. By being surrounded by the element isolation insulating layer 5, the SOI layer 4 to be a region for forming the MOS transistor is formed in an island shape. On the SOI layer 4 and the element isolation insulating layer 5, a thick insulating film (hereinafter, referred to as a first interlayer insulating film) 10 made of, for example, silicon oxide is formed. The first interlayer insulating film 10 has an opening substantially at the center of the SOI layer 4.
On the surface of the SOI layer 4 exposed at the bottom of the opening of the first interlayer insulating film 10, a gate insulating film 11 made of, for example, silicon oxide is formed. A sufficient step is formed by the difference in film thickness between the thin gate insulating film 11 and the thick insulating film (first interlayer insulating film) 10.
[0023]
A gate electrode 15 is formed on the gate insulating film 11 and buried in the opening of the first interlayer insulating film 10. The gate electrode 15 includes, for example, a first conductive layer 12 made of polysilicon having a conductivity increased by adding a P-type impurity and a second conductive layer 14 made of a high melting point metal such as tungsten W. Have been.
The first conductive layer 12 is formed of a single conductive film (N-type polysilicon film) in contact with the side surface of the opening and the upper surface of the gate insulating film 11 located at the bottom of the opening. The second conductive layer 14 is buried in almost the entire area of the concave portion formed on the surface of the first conductive layer 12. However, the protective layer 13 is embedded between the second conductive layer 14 and the first conductive layer 12 along the side surface of the opening, that is, the side surface of the step. The protective layer 13 is made of, for example, a dense insulating material such as silicon nitride, and is buried in two steps on both sides in the channel direction.
[0024]
The first conductive layer 12 has an unmodified portion 12a made of unmodified P-type polysilicon protected by the protective layer 13 and a modified portion modified at the bottom portion of the opening without the protective layer 13. 12b. As long as the modification effectively changes the work function, there is no limitation on the method. In this example, the first conductive layer material is P-type polysilicon and the second conductive layer material is heat-treated. The silicide is formed by reacting with a high melting point metal (for example, tungsten W).
Note that the protective layer 13 is required when a modification method based on a reaction of a gate electrode material by heat treatment is employed. Therefore, the protective layer 13 is not necessarily required depending on the modification method employed.
[0025]
In the SOI layer 4, an N-type source region 8 is formed on one side in the channel direction of the opening of the first interlayer insulating film 10, and an N-type drain region 9 is formed on the other side. The SOI layer portion between the source region 8 and the drain region 9 serves as a channel formation region where a channel is formed during operation of the transistor.
Note that the impurity profiles of the source region 8 and the drain region 9 are not limited. In addition to the simplest impurity profile formed by one ion implantation, a so-called S / D extension (Extension), which has a shallow N-type region extending toward the center of the channel, or a so-called impurity profile Various forms such as an impurity profile having a P-type region formed around an N-type region, which is called a halo, can be implemented.
[0026]
On the upper surface of the gate electrode 15 of the MOS transistor thus formed and the upper surface of the first interlayer insulating film 10, a second interlayer insulating film 16 is formed.
Two contact holes 17 and 18 are formed penetrating the interlayer insulating films 16 and 10 in the thickness direction. The contact hole 17 is connected to the source region 8, and the contact hole 18 is connected to the drain region 9. A conductive material, for example, metal such as tungsten W or polysilicon is buried in the contact holes 17 and 18.
A source wiring layer 19 connected to the contact hole 17 and a drain wiring layer 20 connected to the contact hole 18 are formed on the second interlayer insulating film 16.
[0027]
Hereinafter, a method of manufacturing the MOS transistor illustrated in FIG. 1 will be described with reference to the drawings.
2A to 4C are cross-sectional views of the MOS transistor according to the embodiment of the present invention, which are being manufactured. FIGS. 5A and 5B are enlarged cross-sectional views showing a state of reforming the gate electrode before and after the heat treatment following FIG. 4C.
[0028]
For example, an SOI substrate, that is, a substrate in which the buried insulating film 3 is formed on the substrate 2 and the SOI layer 4 is formed on the buried insulating film 3 is formed by a substrate bonding method or a SIMOX method. The SOI layer 4 is made of single crystal silicon to which a P-type impurity is added during or after the formation, and has a thickness of 50 nm at the maximum.
As shown in FIG. 2A, a part of the SOI layer 4 is insulated by a method such as a partial thermal oxidation method which is performed by masking a transistor formation region or an STI (Shallow Trench Isolation) method. An element isolation insulating layer 5 having a predetermined pattern is formed on the SOI layer 4.
[0029]
In FIG. 2B, a gate insulating film 6 is formed on the surface of the SOI layer 4 where the element isolation insulating layer 5 is not formed. The gate insulating film 6 is made of, for example, silicon oxide formed by a thermal oxidation method.
Next, the sacrificial layer 7 is formed. The sacrificial layer is a layer used for defining a groove shape in the groove gate process, and is a layer that is finally removed. Specifically, for example, about 150 nm of polysilicon is deposited by a CVD (Chemical Vapor Deposition) method, and the formed polysilicon film is patterned into a pattern substantially similar to the gate electrode.
[0030]
In FIG. 2C, N-type impurity ions are implanted to form a source region 8 and a drain region 9. For example, arsenic ions As as ion species ⁺ With an acceleration energy of 2.5 keV and a dose of 1.8 × 10 ^Fifteen ions / cm ² Then, ions are implanted into the SOI layer 4 at an implantation angle of 0 °. At this time, the sacrifice layer 7 and the element isolation insulating layer 5 function as a self-alignment mask, and the gate insulating film 6 serves as a protective film for preventing contamination of the surface of the SOI layer or a through film for reducing defects introduced at the time of implantation. Function. Subsequently, if necessary, ion implantation for forming a halo region is performed. The ion implantation for forming the halo region is performed using a P-type impurity at an implantation angle larger than 0 °.
Thereby, the N-type source region 8 and the drain region 9 are simultaneously formed in the SOI layer portions on both sides of the sacrifice layer 7.
Note that a step of forming a sidewall spacer on the side surface of the sacrificial layer 7 and injecting an N-type impurity under conditions different from the above may be added before the formation. Thereby, the source region 8 and the drain region 9 can have an extension structure.
[0031]
A thick insulating film (first interlayer insulating film) 10 such as silicon oxide is deposited by a CVD method so as to completely cover the sacrificial layer 7.
After that, as shown in FIG. 3A, the surface of the first interlayer insulating film 10 is polished by a technique such as CMP (Chemical Mechanical Polishing). Polishing is performed until the upper surface of the sacrificial layer 7 is exposed. As a result, the first interlayer insulating film 10 is substantially uniform in thickness with the sacrificial layer 7, and their surfaces are flattened.
[0032]
As shown in FIG. 3B, the exposed sacrificial layer 7 is removed by, for example, a wet process. When the sacrificial layer 7 is made of polysilicon, for example, 0.5% ethylenediamine (NH ₂ (CH ₂ ) 2NH ₂ A) The treatment using the aqueous solution is performed at room temperature (20 ° C) for about 2 minutes. This 2-minute processing time corresponds to a case where about 100% overetching is performed at a calculation rate of 160 nm / min.
Subsequently, the gate insulating film 6 is etched using an HF-based solution and removed. Then, the gate insulating film 11 is formed again on the surface of the SOI layer 4 by, for example, a thermal oxidation method.
Note that the gate insulating film 6 may be left as it is without being removed and used as a gate insulating film of a transistor. In that case, the step of removing the gate insulating film 6 and the step of forming the gate insulating film 11 can be omitted. However, here, the gate insulating film is formed again from the viewpoint of ensuring film quality and reliability.
[0033]
In FIG. 3C, a polysilicon film as the first conductive layer 12 is deposited to a thickness of about 30 nm using, for example, a vertical CVD apparatus. Silane SiH as a source gas for CVD ₄ , Hydrogen H ₂ , Nitrogen N ₂ Are mixed at a flow rate of 30 sccm, 100 sccm, and 500 sccm, respectively. The substrate temperature is 610 ° C., and the furnace pressure is 40 Pa.
Subsequently, as the protective layer 13, for example, Si ₃ N ₄ A film is deposited to about 10 nm using a vertical CVD apparatus. Dichlorosilane SiH as a source gas for CVD ₂ Cl ₂ , Ammonia NH ₃ , Hydrogen H ₂ Are used at a flow rate of 90 sccm, 600 sccm, and 500 sccm, respectively. The substrate temperature is 760 ° C., and the furnace pressure is 53 Pa.
P-type impurity ions are implanted to perform doping of polysilicon. For example, boron ion B as an ion species ⁺ With an acceleration energy of 10 keV and a dose of 3 × 10 ^Fifteen ions / cm ² Then, ions are implanted into polysilicon to be the first conductive layer 12.
[0034]
Here, the protective layer 13 has a function of suppressing the reaction between the subsequently deposited second conductive layer and the first conductive layer and the mutual diffusion of impurities. When a polysilicon film is used as the first conductive layer 12 as in this example, the polysilicon film is directly nitrided, ₃ N ₄ A film (at most, for example, 2 nm) may be used as the protective layer 13. The nitridation at this time is, for example, RTA (Rapid Thermal Annealing) treatment. ₃ In the atmosphere, heating is performed at 850 ° C. for a short time of 60 seconds.
[0035]
The entire surface of the formed protective layer 13 is etched (etched back) using, for example, a magnetron type etcher. As an etching gas, trifluoromethane CHF ₃ At a flow rate of 45 sccm, the temperature in the chamber is set to 20 ° C., the pressure is set to 2.7 Pa, and RF power of 1000 W is applied. When etch-back is performed for a predetermined time under this condition, as shown in FIG. 4A, the protective layer 13 having an appropriate thickness is left on the side surface (groove side surface) of the step.
[0036]
As shown in FIG. 4B, as the second conductive layer 14, a film of tungsten W, for example, is deposited to a thickness of 300 nm. In the deposition at this time, silane SiH was used as a source gas for CVD. ₄ , Tungsten hexafluoride WF ₆ , Hydrogen H ₂ Are mixed at flow rates of 3 cc / min, 5 cc / min and 50 cc / min, respectively. The substrate temperature is 450 ° C. and the furnace pressure is 70 Pa.
[0037]
As shown in FIG. 4C, CMP (Chemical Mechanical Polishing) is performed to remove the conductive layer portion located on the upper surface of the first interlayer insulating film 10. At this time, in the CMP, a wet foamed nonwoven fabric type cloth (model number: Suba400) is used as a polishing pad, and a hydrogen peroxide solution H is used as an abrasive. ₂ O ₂ Amorphous alumina (α-Al ₂ O ₃ ) Is used. 400g / cm weight of wafer ² Then, rotary polishing is performed at a rotation speed of 40 rpm while flowing an abrasive at a flow rate of 50 cc / min. As a result, the gate electrode 15 buried in the groove is left.
[0038]
Next, a heat treatment for partially modifying the first conductive layer 12 is performed. This heat treatment is, for example, RTA (Rapid Thermal Annealing), and specifically, heating is performed at 550 ° C. for 60 seconds in an argon Ar atmosphere. By this heating, the protective film (Si ₃ N ₄ In the portion where the film 13 has been removed, the polysilicon of the first conductive layer 12 and the tungsten of the second conductive layer react with each other to form tungsten silicide WSi. ₂ (Reforming unit 12b). The source-side end and the drain-side end where the protective layer 13 is interposed between the tungsten and the tungsten remain unreacted and remain as the original polysilicon (unmodified portion 12a).
This heat treatment lowers the work function of the gate electrode at the center of the channel from the work function of P-type polysilicon (about 5.2 eV) to the work function of tungsten silicide (about 4.5 to 4.6 eV). Thus, the threshold voltage Vth increases with a reduction in the gate length of the transistor, and the roll-off phenomenon of the short channel effect is suppressed.
[0039]
Thereafter, although not particularly shown, the deposition of the second interlayer insulating film 16, the opening of the contact holes 17 and 18, the embedding of metal, and the formation of the wirings 19 and 20 are sequentially performed to complete the MOS transistor 1.
[0040]
The case where the present invention is applied to the SOI type NMOS transistor has been described above, but this is merely an example. The present invention is not limited to the above-described device structure, its forming conditions, and the like.
For example, the transistor may be formed on a bulk silicon substrate. Even in the case of an SOI transistor, the design of the type of the SOI substrate, the thickness of the SOI layer, and the like can be changed as appropriate.
Although the method for manufacturing an NMOS transistor has been described, the present invention can be applied to a PMOS transistor by changing the conductivity type of an impurity.
A transistor having a CMOS structure can be manufactured by using a mask to separate impurities.
The sacrificial layer 7 is made of silicon nitride Si besides polysilicon. ₃ N ₄ , Or a metal film such as tungsten W.
[0041]
Also, silicon nitride Si is used as the material of the protective layer. ₃ N ₄ In the present invention, a material containing nitrogen atoms is desirable, and a typical example thereof is silicon nitride Si. ₃ N ₄ Is an example. The nitrogen content is desirably a thin film containing 0.5% by weight or more. As such a material, silicon nitride Si ₃ N ₄ Besides, there are silicon oxynitride (SiON) SiON, titanium nitride TiN, titanium oxynitride TiON, tungsten nitride WN, tungsten nitride silicide WSiN, and the like.
[0042]
Further, the combination of the materials of the first conductive layer 12 and the second conductive layer 14 may be any combination of materials that cause a solid phase reaction with each other. High N-type impurity concentration polysilicon (N ⁺ Polysilicon (polysilicon), polysilicon (P ⁺ Any combination of two or more of polysilicon (polysilicon) and refractory metals (W, Co, Ti, Mo, Pt, Ni, etc.) may be selected. This combination is determined in consideration of the work function difference to be changed.
N ⁺ Polysilicon and P ⁺ In the case of the combination with the polysilicon, the modification is performed in the lower part of the groove by the mutual diffusion of the impurities, not the "reaction" of the two, thereby changing the work function. The work function of the polysilicon after the interdiffusion is about the same as that of the tungsten silicide described above, and the same effect can be obtained.
[0043]
Embodiments of the present invention are not limited to the trench filling gate process. At least, the work function of the gate electrode may be changed locally at the source region side where the change in the threshold voltage Vth is large. In this case, a step is formed with a thick insulating film or the like, a gate insulating film 11 and a first conductive layer 12 are sequentially formed, a protective layer 13 is formed on the step, and a second conductive layer 14 is formed. Is patterned by photolithography and etching instead of CMP. Also in this case, the gate length Lg can be set to the minimum size for photolithography.
Further, the present invention can be applied to a device structure having a three-dimensional channel, such as a so-called Fin-type MOSFET.
[0044]
In the present embodiment, the following effects can be obtained.
The gate electrode 15 whose work function is controlled in the channel direction can be formed while maintaining the line width defined by lithography. As a result, the short channel effect can be suppressed by a technique other than the halo ion implantation.
In the step of forming the gate electrode, after the first conductive layer is once deposited and covered on the gate insulating film 11, the gate insulating film 11 is exposed and is not directly exposed to plasma such as RIE. . As a result, uneven "shearing" of the gate insulating film 11 is prevented, and no damage is introduced into the gate insulating film 11 and the channel formation region thereunder. Therefore, a MOS transistor which is excellent in film thickness uniformity and reliability and maintains high characteristics is realized.
[0045]
【The invention's effect】
According to the insulated gate field effect transistor and the method of manufacturing the same according to the present invention, the gate whose work function changes in the channel direction without affecting the characteristics and reliability of the gate insulating film and the semiconductor under the gate insulating film. Electrodes can be formed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a MOS transistor according to an embodiment of the present invention.
FIGS. 2A to 2C are cross-sectional views showing up to an ion implantation step for forming a source region and a drain region in the manufacture of the MOS transistor according to the embodiment of the present invention;
FIGS. 3A to 3C are cross-sectional views subsequent to FIG. 2C, and show the steps up to the step of doping polysilicon which is to be a first conductive layer.
FIGS. 4A to 4C are cross-sectional views subsequent to FIG. 3C, and show steps up to a step of patterning a gate electrode by CMP.
5A is an enlarged cross-sectional view of the gate portion immediately after the step of FIG. 4C, and FIG. 5B is an enlarged cross-sectional view of the gate portion after a heat treatment for modifying a part of the gate electrode. .
FIG. 6 is a cross-sectional view of a MOSFET described in Patent Document 1 and showing a conventional method of forming a gate electrode.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Insulated gate field effect transistor, 2 ... Substrate, 3 ... Buried insulating film, 4 ... Semiconductor SOI layer in which a channel is formed, 5 ... Element isolation insulating layer, 6 ... Gate insulating film, 7 ... Sacrificial layer, 8 ... Source Region 9, drain region, 10 thick insulating film or first interlayer insulating film, 11 gate insulating film, 12 first conductive layer, 12a unmodified portion, 12b modified portion, 13 protection Layer, 14: second conductive layer, 15: gate electrode, 16: second interlayer insulating film, 17, 18: contact hole, 19, 20: wiring layer

Claims (7)

Forming a source region and a drain region apart from each other in a semiconductor in which a channel is formed;
Covering at least the source region side with a thick insulating film;
Forming a gate insulating film over a channel forming region that is a portion of the semiconductor between at least the source region and the drain region, and forming a step with the gate insulating film and the thick insulating film;
Forming a first conductive layer covering an upper surface of the gate insulating film, an upper surface of the thick insulating film, and a side surface of the step;
Forming a protective layer on a surface portion of the first conductive layer facing a side surface of the step;
Forming a second conductive layer covering the exposed surface of the first conductive layer and the protective layer;
Modifying the portion of the first conductive layer that is in contact with the second conductive layer to determine a work function difference between the first conductive layer and the channel formation region above the channel formation region, A step of differentiating between the unmodified part and the modified part which are protected and not modified by
Processing the first conductive layer and the second conductive layer into a gate electrode pattern;
A method for manufacturing an insulated gate field effect transistor, comprising: The method according to claim 1, wherein in the step of forming the protective layer, a film containing nitrogen is deposited on the entire surface, the deposited film is anisotropically etched, and other portions are removed except for a portion facing the side surface of the step. A method for manufacturing the insulated gate field effect transistor according to the above. Forming a gate insulating film over the semiconductor on which the channel is formed;
Forming a sacrificial layer having substantially the same pattern as the gate electrode on the gate insulating film;
Forming a source region and a drain region apart from each other in the semiconductor by ion implantation using the sacrificial layer as a mask;
Filling the periphery of the sacrificial layer with an interlayer insulating film;
Removing a sacrifice layer and forming a step with the gate insulating film and the interlayer insulating film;
Forming a first conductive layer covering an upper surface of the gate insulating film, an upper surface of the interlayer insulating film, and a side surface of the step;
Forming a protective layer on a surface portion of the first conductive layer facing a side surface of the step;
Forming a second conductive layer covering the exposed surface of the first conductive layer and the protective layer;
Modifying a portion of the first conductive layer that is in contact with the second conductive layer, and forming a first conductive layer above a channel forming region that is a portion of the semiconductor between the source region and the drain region; A work function difference of the layer with respect to the channel forming region, a step of different between an unmodified portion and a modified portion which are protected and not modified by the protective layer,
Processing the first conductive layer and the second conductive layer into a gate electrode pattern;
A method for manufacturing an insulated gate field effect transistor, comprising: 4. The method according to claim 3, wherein in the step of forming the protective layer, a film containing nitrogen is deposited on the entire surface, the deposited film is anisotropically etched, and other portions are removed except for a portion facing the side surface of the step. A method for manufacturing the insulated gate field effect transistor according to the above. A source region formed in the semiconductor in which the channel is formed;
A drain region formed at a location of the semiconductor remote from the source region, and a gate insulating film formed at least on a semiconductor surface between the source region and the drain region;
And a gate electrode formed on the gate insulating film,
At least a portion of the gate electrode in contact with the gate insulating film is formed of a single conductive film, and at least one of the portion on the source region side and another portion of the conductive film is modified, and the work function for the semiconductor is improved. Insulated gate field effect transistors with different differences. The gate electrode comprises the first conductive layer partially modified, and a second conductive layer formed on the first conductive layer;
6. The gate electrode according to claim 5, further comprising a protection layer locally embedded between the first conductive layer and the second conductive layer to prevent the modification. Insulated gate field effect transistor. 7. The insulated gate field effect transistor according to claim 6, wherein said protective layer is made of a material containing nitrogen.

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