JP2004077192A - Semiconductor inspecting device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct a skew error occurring in sampling a response waveform of a semiconductor device in a frequency region, and to largely improve measuring accuracy in an analog test. <P>SOLUTION: The response waveform of an analog signal outputted from the semiconductor device DUT is sampled by a parallel A/D conversion circuit 9 and then stored in a memory 10, and a waveform synthesizing means 11 synthesizes it to a waveform of a digital sampling signal string. Then, Fourier conversion is performed by an FFT 13. Then, a skew error correcting means 14 corrects degradation of the measuring accuracy in a frequency spectrum resulting from the skew error based on the frequency spectrum obtained by the Fourier conversion. The corrected frequency spectrum is evaluated by a measured item evaluating means 15. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an analog test technique for a semiconductor device, and more particularly to a technique that is effective when applied to correction of a skew error generated when sampling a response signal.
[0002]
[Prior art]
For example, an analog test in a system LSI or the like is performed by a semiconductor inspection device such as an analog / mixed signal test system, or a logic tester and an external analog BOST (Build Out Self Test) system.
[0003]
In this case, an analog signal generated from a DUT such as a system LSI is waveform-sampled and digitized, and the digital signal is temporarily stored in a memory and subjected to a Fourier transform. The ratio (SNR), total harmonic distortion (THD), and the like are obtained.
[0004]
Essentially, waveform sampling is processed by one A / D (analog / digital) converter. However, according to the Nyquist theorem, the sampling frequency Fs of the A / D converter must be at least twice the frequency Ft of the analog signal to be measured.
[0005]
In order to measure the AC characteristics of a high-speed analog device, an A / D converter for high-speed and high-accuracy sampling is required. However, in the case of a single A / D converter, there is a reciprocal relationship between the conversion accuracy and the conversion speed, so that there is a limitation on the sampling speed for a high-precision A / D converter.
[0006]
Therefore, as shown in FIG. 8, the semiconductor inspection apparatus is provided with a parallel ADC (analog / digital converter) sampling system 30 that realizes high-speed and high-accuracy sampling. The parallel ADC sampling system 30 includes, for example, three delay circuits 31 and four high-precision A / D converters 32.
[0007]
The parallel ADC sampling system 30 has a configuration in which analog signals output from the semiconductor device DUT are simultaneously input to the four A / D converters 32 based on the test waveform output from the waveform pattern generator 37.
[0008]
The sampling frequency Fs of each A / D converter 32 is sampled at the same frequency Fs generated by the sampling clock generation circuit 38 after shifting the phase by a certain amount through the three delay circuits 31. In setting the delay time of each delay circuit 31, it is necessary to set delay times of 1 / nFs, 2 / nFs,... (N-1) / nFs from the second channel to the n-th channel. .
[0009]
After the sampling data D1 (i), D2 (i), D3 (i), D4 (i),... Dn (i) of all lengths obtained from each channel are stored in the memory 33, D1 (0), D2 (0), D3 (0), D4 (0),... Dn (0), D1 (1), D2 (1), D3 (1), D4 (1), ..., Dn (1), D1 (2), D2 (2), D3 (2), D4 (2), ... Dn (2), D1 (m- 1), D2 (m-1), D3 (m-1), D4 (m-1),..., Dn (m-1) Synthesized.
[0010]
The sampling data synthesized in this way can be considered to be the same as taking sampling data of the same length n × m at the sampling frequency of nFs using one high-speed and high-accuracy A / D converter.
[0011]
Then, the synthesized sampling data is subjected to fast Fourier transform by the FFT 35, and the measurement item evaluation means 36 evaluates the measurement item by frequency spectrum analysis.
[0012]
Japanese Patent Application Laid-Open No. 2001-184602 discloses an example of a patent that describes in detail a technique for sampling an analog signal using a plurality of A / D converters.
[0013]
[Problems to be solved by the invention]
However, the present inventor has found that there is the following problem in the analog test technology such as the system LSI using the semiconductor inspection device as described above.
[0014]
That is, an error (skew) occurs in the delay time obtained from the delay circuit for each channel from the ideal delay value i / nFs. Due to this skew error, the constituted sampling signal differs from data obtained by sampling from one ideal A / D converter.
[0015]
When the synthesized sampling signal including such a skew error is subjected to Fourier transform, an extra noise component caused by the skew error is generated, the amplitude value of the signal component is reduced, and the measurement accuracy is deteriorated. Problem.
[0016]
An object of the present invention is to correct a skew error generated when a response waveform of a semiconductor device is sampled in a frequency domain, thereby significantly improving measurement accuracy in an analog test and manufacturing a semiconductor device. It is to provide a method.
[0017]
[Means for Solving the Problems]
A semiconductor inspection apparatus according to the present invention includes a master clock, a pattern generator that generates pattern data including information on a test waveform, a timing generator that receives the master clock and the pattern data and generates a test waveform, And a data processing means for obtaining a frequency spectrum from the sampling data sampled by the sampling means, wherein the sampling means generates a sampling clock. A clock generation unit, a (n-1) delay unit for delaying the sampling clock of the clock generation unit, a sampling clock output from the clock generation unit, and a sampling clock output from the (n-1) delay units. Based, semi N digital converters for converting a response waveform output from the body device into digital data, a storage unit for storing sampling data output from the n digital converters, and a sampling unit stored in the storage unit A data synthesizing unit for synthesizing data and generating a digital sampling waveform, wherein the data processing means generates a frequency spectrum from the digital sampling waveform in which noise components generated by skew in the n-1 delay units are corrected. It is characterized by the following.
[0018]
Further, the semiconductor inspection apparatus of the present invention includes a master clock, a pattern generator that generates pattern data including information on a test waveform, a timing generator that receives the master clock and the pattern data, and generates a test waveform, A driver for applying a test waveform to the semiconductor device; sampling means for sampling a response waveform from the semiconductor device; and data processing means for generating a time-domain waveform from the sampling data sampled by the sampling means. , A clock generation unit for generating a sampling clock, n-1 delay units for delaying the sampling clock of the clock generation unit, a sampling clock output from the clock generation unit, and n-1 delay units. Based on sampling clock to output , N digital converters for converting a response waveform output from the semiconductor device into digital data, a storage unit for storing sampling data output from the n digital converters, and a storage unit for storing the sampling data output from the n digital converters. A waveform synthesizing unit for synthesizing the sampling data and generating a digital sampling waveform, wherein the data processing means generates, from the digital sampling waveform, a frequency spectrum in which a noise component generated by skew in the n-1 delay units is corrected. And generating a time-domain waveform from the frequency spectrum.
[0019]
Further, in the method of manufacturing a semiconductor device according to the present invention, a semiconductor device is formed on a semiconductor wafer, a semiconductor chip is formed, and a response waveform output from the semiconductor device is sampled based on a test waveform. Generating a frequency spectrum in which the noise component is corrected from, and inspecting the response waveform of the semiconductor device using the corrected frequency spectrum; and dicing the semiconductor wafer along a dicing line to singulate into semiconductor chips. Forming a semiconductor device using the singulated semiconductor chips.
[0020]
Further, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor chip on a semiconductor wafer to form a semiconductor chip, and a step of converting a response waveform output from the semiconductor device based on a test waveform into n digital converters. , And a data processor that performs time domain waveform generation from the sampled sampled data by using the n−1 delay units that delay the sampling clock, and obtains a frequency spectrum by Fourier transforming the sampled data. Correcting the noise component generated by the skew in the (n−1) delay units, inspecting the response waveform of the semiconductor device using the corrected frequency spectrum, dicing the semiconductor wafer along the dicing line, And a semiconductor device using the singulated semiconductor chip. Characterized by a step of forming.
[0021]
Further, in the method of manufacturing a semiconductor device according to the present invention, a semiconductor element is formed on a semiconductor wafer to form a semiconductor chip, and a response waveform output from the semiconductor device based on a test waveform is converted into n digital converters. , And a data processor that performs time domain waveform generation from the sampled sampled data by using the n−1 delay units that delay the sampling clock, and obtains a frequency spectrum by Fourier transforming the sampled data. Correcting the noise component generated by the skew in the (n−1) delay units, inspecting the response waveform of the semiconductor device using the corrected frequency spectrum, dicing the semiconductor wafer along the dicing line, A semiconductor device using the singulated semiconductor chips. Characterized by a step of forming a.
[0022]
Further, a method of manufacturing a semiconductor device according to the present invention includes the steps of forming a semiconductor element on a semiconductor wafer and forming a semiconductor chip, sampling a response waveform output from the semiconductor device based on a test waveform, and sampling the sampled data. Generating a time-domain waveform in which a noise component is corrected from the data, inspecting a response waveform of the semiconductor device using the corrected time-domain waveform, and dicing the semiconductor wafer along a dicing line to separate the semiconductor wafer into semiconductor chips. A method for manufacturing a semiconductor device, comprising: a step of forming a semiconductor device by using singulated semiconductor chips.
[0023]
Further, in the method of manufacturing a semiconductor device according to the present invention, a semiconductor device is formed on a semiconductor wafer to form a semiconductor chip, and a response waveform output from the semiconductor device based on a test waveform is converted into n digital converters. , And sampling using the n-1 delay units for delaying the sampling clock, performing a Fourier transform on the sampled data to obtain a frequency spectrum, and then generating a noise component due to skew in the n-1 delay units. Correcting the frequency spectrum, inverse Fourier transforming the corrected frequency spectrum to generate a time-domain waveform, inspecting the response waveform of the semiconductor device using the time-domain waveform, and dicing the semiconductor wafer along a dicing line, The method includes a step of dividing into individual chips and a step of forming a semiconductor device using the divided semiconductor chips. It is characterized by doing.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0025]
(Embodiment 1)
FIG. 1 is an overall block diagram of a semiconductor inspection apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram of a WFD and a data processor provided in the semiconductor inspection apparatus of FIG. 1, and FIGS. FIG. 7 is a simulation diagram of a frequency spectrum in sampling data.
[0026]
In the first embodiment, the semiconductor inspection device 1 performs an analog test of a system LSI or the like. As shown in FIG. 1, the semiconductor inspection device 1 includes a control unit 2 and an analog / mixed signal tester 3.
[0027]
The control unit 2 is composed of, for example, a personal computer or a work station, and controls all controls in the analog / mixed signal tester 3. The analog / mixed signal tester 3 includes a waveform pattern generator 4, an arbitrary waveform generator 5, a WFD (Wave Form Digitizer) 6, a data processor 7, and a clock generator (master clock) 8.
[0028]
The waveform pattern generator 4 includes a pattern generator 4a, a timing generator 4b, and a driver 4c. The pattern generator 4a generates a test pattern, and the timing generator 4b generates a test waveform composed of a sine waveform pattern of a digital signal based on the test pattern generated by the pattern generator 4a. The driver 4c outputs a test waveform to the semiconductor device DUT to be tested.
[0029]
The arbitrary waveform generator 5 generates an arbitrary waveform and outputs it to the semiconductor device DUT. The WFD (sampling means) 6 samples an analog response waveform output from the semiconductor device DUT.
[0030]
The data processor 7 performs a Fourier transform on the data sampled by the WFD 6 and evaluates a response waveform output from the semiconductor device DUT. The clock generator 8 supplies a reference clock to the waveform pattern generator 4, the arbitrary waveform generator 5, the WFD 6, and the data processor 7, and drives the analog / mixed signal tester 3.
[0031]
The configurations of the WFD 6 and the data processor 7 will be described with reference to FIG.
[0032]
The WFD 6 includes a parallel A / D conversion circuit 9, a memory (storage unit) 10, a waveform synthesis unit (waveform synthesis unit) 11, and a sampling clock generation circuit (clock generation unit) 12. The parallel A / D conversion circuit 9 includes three delay circuits (delay units) 9a ₁ ~ 9a ₃ And four A / D converters (digital conversion units) 9b ₁ ~ 9b ₄ It is composed of
[0033]
Delay circuit 9a ₁ ~ 9a ₃ The sampling clock Fs output from the sampling clock generating circuit 12 is input to the input section of the first section, and the sampling clock Fs is output after being delayed by a certain time. These delay circuits 9a ₁ ~ 9a ₃ Have different delay times, for example, 1/4 Fs, 2/4 Fs, and 3/4 Fs, respectively.
[0034]
A / D converter 9b ₁ ~ 9b ₄ , An analog response waveform output from the semiconductor device DUT is input. A / D converter 9b ₁ Are connected so that the sampling clock Fs output from the sampling clock generation circuit 12 is directly input, and perform waveform sampling based on the sampling clock Fs.
[0035]
On the other hand, the A / D converter 9b ₂ ~ 9b ₄ Is connected to a delay terminal 9a ₁ ~ 9a ₃ Are connected so as to input the sampling signals delayed by. A / D converter 9b ₂ ~ 9b ₄ Performs waveform sampling based on these delayed sampling signals.
[0036]
A / D converter 9b ₁ ~ 9b ₄ Are output to the memory 10, respectively. The memory 10 includes an A / D converter 9b ₁ ~ 9b ₄ And store the sampling data.
[0037]
The sampling data stored in the memory 10 is output to the waveform synthesizing unit 11. The waveform synthesizing means 11 includes an A / D conversion circuit 9b ₁ ~ 9b ₄ Are combined, and combined into a waveform of one digital sampling signal train.
[0038]
The data processor 7 includes an FFT (Fourier transform processing unit) 13, a skew error correction unit (skew error correction unit) 14, and a measurement item evaluation unit (measurement evaluation unit) 15.
[0039]
The FFT 13 performs a Fourier transform process on the digital sampling data synthesized by the waveform synthesis unit 11. The skew error correcting means 14 converts the frequency spectrum obtained by the Fourier transform of the FFT 13 into a delay circuit 9a. ₁ ~ 9a ₃ , A noise component generated due to a so-called skew is detected, and the noise component is deleted and output to the measurement item evaluation means 15.
[0040]
The measurement item evaluation means 15 evaluates AC characteristics such as signal-to-noise ratio (SNR) and total harmonic distortion (THD) from the input frequency spectrum.
[0041]
Next, a technique for correcting a skew error by the semiconductor inspection apparatus 1 according to the present embodiment will be described with reference to FIGS. 1, 2, and 3 and 4 and FIG.
[0042]
First, single-frequency sine wave generation data generated by the waveform pattern generator 4 of the semiconductor inspection apparatus 1 is applied to the semiconductor device DUT. The semiconductor device DUT outputs an output waveform (response waveform) of an analog signal having received the sine wave generation data to the WFD 6.
[0043]
This output waveform is sampled by the parallel A / D conversion circuit 9, stored in the memory 10, and synthesized into one digital sampling signal train waveform by the waveform synthesis unit 11.
[0044]
Thereafter, the waveform of the digital sampling signal sequence is subjected to frequency analysis by a frequency spectrum by Fourier transform by the FFT 13.
[0045]
Here, a frequency spectrum including a skew error will be considered.
[0046]
For example, the frequency of the applied analog signal is Ft, and each A / D converter 9b ₁ ~ 9b ₄ With the sampling frequency Fs, the noise component generated from the skew error exists only in the following special frequency components.
[0047]
The special frequency components are Fs-Ft, Fs + Ft, 2Fs-Ft, 2Fs + Ft,... 2Fs / n-Ft. Incidentally, the frequency of the skew error depends on the frequency Ft of the applied analog signal and the frequency of each A / D converter 9b. ₁ ~ 9b ₄ And the number of channels (A / D converters) constituting the A / D conversion circuit 9. Among them, 2Fs / n is an equivalent Nyquist frequency of the A / D conversion circuit 9 configured by using n A / D converters.
[0048]
3 and 4 show simulation results of the frequency spectrum by the FFT 13. FIG.
[0049]
FIG. 3A shows a frequency spectrum when there is no skew error, and FIG. 3B shows a frequency spectrum when there is a skew error. FIG. 4 is a frequency spectrum when the skew error is corrected by the skew error correction means 14 provided in the data processor 7.
[0050]
3 and FIG. 4, each A / D converter 9b ₁ ~ 9b ₄ Is 1.5 GHz, and the frequency of the analog signal output from the semiconductor device DUT is 200 MHz.
[0051]
In FIG. 3B, the frequency Ft of the analog signal output from the semiconductor device DUT and the A / D converter 9b ₁ ~ 9b ₄ Sampling frequency Fs used by the A / D converter and four A / D converters 9b ₁ ~ 9b ₄ Therefore, the frequency components of the skew error are Fs−Ft, Fs + Ft, and 2Fs−Ft.
[0052]
Using the frequency characteristics of the skew error, the amplitude of the signal component and the amplitudes (Fs−Ft), (Fs + Ft), and (2Fs−Ft) of the skew error components can be obtained from the frequency spectrum.
[0053]
Thus, even if the magnitude of the skew error of each channel changes, the frequency components of these skew errors do not change, and only the amplitudes of the frequency skew noise components change.
[0054]
The skew error correcting means 14 calculates the amplitude A1 of the signal component and the amplitudes A2 (Fs-Ft), A3 (Fs + Ft), and A4 (2Fs-Ft) of the skew error components from the frequency spectrum.
[0055]
Originally, the amplitude A0 of the signal component of the frequency Ft is equal to the signal power A0. ² Is not changed by sampling and Fourier transform. By the way, A0 = √ (A1 ² + A2 ² + A3 ² + A4 ² ).
[0056]
Then, the skew error correction means 14 generates a skew error when calculating noise or distortion in the frequency spectrum because the frequency components of Fs-Ft, Fs + Ft, and 2Fs-Ft are noise components caused by the skew error. The amplitude of the frequency component to be processed is set to zero, and the processing is performed as a non-target.
[0057]
As described above, the skew error correction unit 14 corrects the deterioration of the measurement accuracy in the frequency spectrum caused by the skew error. Thereafter, the frequency spectrum in which the skew error has been corrected is output to the measurement item evaluation means 15, and the AC characteristics such as the signal-to-noise ratio and the total harmonic distortion are evaluated.
[0058]
Thus, according to the first embodiment, since a noise component caused by a skew error can be excluded, the semiconductor device DUT can be evaluated with high accuracy.
[0059]
(Embodiment 2)
FIG. 5 is a block diagram of a WFD and a data processor provided in a semiconductor inspection device according to a second embodiment of the present invention. FIG. 6 is a sine waveform obtained by inverse Fourier transform by IFFT provided in the semiconductor inspection device. FIG.
[0060]
In the second embodiment, a semiconductor inspection apparatus 1 (FIG. 1) for performing an analog test of a system LSI or the like includes a control unit and an analog / mixed signal tester 3, and has the same configuration as that of the first embodiment. It has become.
[0061]
5, the analog / mixed signal tester 3 also includes the WFD 6 and the data processor 7a, and has the same configuration as that of the first embodiment.
[0062]
The internal configuration of the WFD 6 is the same as that of the first embodiment, and includes a parallel A / D conversion circuit 9, a memory 10, a waveform synthesizing unit 11, and a sampling clock generation circuit 12. The parallel A / D conversion circuit 9 includes three delay circuits 9a ₁ ~ 9a ₃ And four A / D converters 9b ₁ ~ 9b ₄ It is composed of
[0063]
In the data processor 7a, an FFT (inverse Fourier transform processing unit) 16 and a waveform quality evaluation unit (measurement evaluation unit) 17 are newly provided in the FFT 13 and the skew error correction unit 14 described in the first embodiment. It has a configuration.
[0064]
The IFFT 16 is connected to the skew error correction means 14, and the IFFT 16 is an inverse Fourier transform means for converting the frequency spectrum corrected by the skew error correction means 14 into time domain waveform data.
[0065]
The waveform quality evaluation means 17 is connected to the IFFT 16 and evaluates the quality of the time domain waveform data converted by the IFFT 16.
[0066]
Next, the operation of the WFD 6, the waveform quality evaluation means 17 and the data processor 7a will be described.
[0067]
After the data sampled by the A / D conversion circuit 9 is stored in the memory 10, the waveform synthesizing unit 11 synthesizes the digital sampling signal sequence into one digital sampling signal sequence waveform, and outputs it to the FFT 13.
[0068]
The input digital sampling data is Fourier-transformed by the FFT 13. The skew error correction unit 14 eliminates a noise component generated due to the skew from the frequency spectrum obtained by the Fourier transform.
[0069]
From the frequency spectrum from which the noise component has been eliminated, a sine waveform shown in FIG. 6A is obtained by inverse Fourier transform by IFFT16. This sine waveform is evaluated by the waveform quality evaluation means 17.
[0070]
As a result, time waveform data in which the delay time error of the A / D conversion circuit 9 has been corrected can be obtained, and the time-time domain characteristics such as signal amplitude and half-value width of the time-domain waveform output from the semiconductor device DUT can be obtained. It becomes possible to measure or evaluate accurately.
[0071]
In addition, by making the signal input to the semiconductor inspection device 1 a known signal waveform, the characteristics of the corrected time waveform data can be evaluated. Furthermore, by performing a comparison operation on the corrected time waveform data and the known signal waveform, the quality evaluation or self-test of the semiconductor inspection apparatus 1 becomes possible, and the reliability of the semiconductor inspection apparatus 1 can be improved.
[0072]
FIG. 6B shows an example of waveform data when the frequency spectrum including the skew error is inverse Fourier-transformed by the FFT 16 according to the study of the present inventors.
[0073]
As shown in the figure, a signal waveform that should be a sine wave is a delay circuit 9a. ₁ ~ 9a ₃ The skew error causes an error in the waveform amplitude, resulting in deformation, which may make it difficult to accurately measure and evaluate the time-time domain characteristics.
[0074]
On the other hand, the waveform quality evaluation means 17 obtains the time waveform data in which the delay time error is corrected, so that the time time domain characteristics such as the signal amplitude and the half width with respect to the time domain waveform output from the semiconductor device DUT can be accurately determined. It can be measured or evaluated.
[0075]
In addition, by making the signal input to the semiconductor inspection device 1 a known signal waveform, the characteristics of the corrected time waveform data can be evaluated. Furthermore, by performing a comparison operation on the corrected time waveform data and the known signal waveform, the quality evaluation or self-test of the semiconductor inspection apparatus 1 becomes possible, and the reliability of the semiconductor inspection apparatus 1 can be improved.
[0076]
Lastly, an example of a method for manufacturing the semiconductor device DUT according to the first and second embodiments will be described.
[0077]
First, the manufactured product wafer is subjected to initial defect selection by P inspection (Pellet inspection). In the P test, an analog test of the semiconductor device DUT is performed.
[0078]
Then, the selected non-defective semiconductor wafers are diced, and only non-defective chips are individually packaged. Thereafter, the product having the final shape in which the package is formed is subjected to a burn-in test, and then a final selection test is performed. In this final screening test, an analog test of the semiconductor device DUT is performed.
[0079]
Semiconductor devices that have become non-defective in the final screening test are shipped after undergoing labeling and appearance inspection processes.
[0080]
Thus, in the second embodiment, the time-time domain characteristic can be measured and evaluated with high accuracy by performing an analog test using the time waveform data in which the delay time error has been corrected.
[0081]
The present invention is not limited to the above-described embodiment, and it goes without saying that various changes can be made without departing from the scope of the invention.
[0082]
Further, in the first and second embodiments, the case where the test waveform is a sine wave signal output from the semiconductor device has been described. However, the present invention is not limited to a sine wave for the test target signal, and may have any period. A signal waveform can be realized, and a test object includes a module product such as a hard disk drive in addition to a semiconductor device that outputs an arbitrary periodic signal waveform.
[0083]
Further, in the first and second embodiments, an example is described in which the waveform pattern generator 4, the arbitrary waveform generator 5, the WFD 6, the data processor 7, and the clock generator 8 are integrally configured. For example, as shown in FIG. 7, the semiconductor inspection apparatus 1a may be configured such that an analog BOST (Build Out Self System) 19 for performing an analog test is externally connected to a logic tester 18 for performing a logic test of the semiconductor device.
[0084]
In this case, the analog BOST 19 includes the arbitrary waveform generator 5, the WFD 6, the data processor 7, and the clock generator 8, as in the first and second embodiments.
[0085]
Also, the internal configuration of the WFD 6 and the data processor 7 has the same configuration as either the configuration shown in FIG. 2 of the first embodiment or the configuration shown in FIG. 5 of the second embodiment.
[0086]
Further, the representative aspects disclosed in the above embodiment are as follows.
[0087]
1. A master clock, a pattern generator for generating pattern data including information on a test waveform, a timing generating circuit for receiving the master clock and the pattern data and generating a test waveform, and applying the test waveform to the semiconductor device And a data processing unit that obtains a frequency spectrum from sampling data sampled by the sampling unit, wherein the sampling unit includes a sampling unit that samples a response waveform from the semiconductor device. A clock generating unit for generating a clock, n-1 delay units for delaying a sampling clock of the clock generating unit, a sampling clock output from the clock generating unit, and the n-1 delay units. Output An n digital converter that converts a response waveform output from the semiconductor device into digital data based on a sampling clock; a storage unit that stores sampling data output from the n digital converters; A waveform synthesizing unit for synthesizing the sampling data stored in the storage unit to generate a digital sampling waveform, wherein the data processing unit generates the digital sampling waveform from the digital sampling waveform by skew in the (n-1) delay units. This is to generate a frequency spectrum in which a noise component has been corrected.
[0088]
2. In the above item (1), the data processing means performs a Fourier transform on the digital sampling waveform generated by the waveform synthesizing section and generates a frequency spectrum of the digital sampling waveform, and the Fourier transform processing section generates the Fourier transform processing section. A skew error correction unit for detecting and correcting a noise component generated by the skew of the n-1 delay units from the frequency spectrum.
[0089]
3. In the above item 1 or 2, the data processing means includes a measurement evaluator for evaluating the response waveform from the frequency spectrum corrected by the skew error corrector.
[0090]
4. A master clock, a pattern generator for generating pattern data including information on a test waveform, a timing generating circuit for receiving the master clock and the pattern data and generating a test waveform, and applying the test waveform to the semiconductor device And a data processing means for generating a time-domain waveform from the sampling data sampled by the sampling means, wherein the sampling means comprises: , A clock generation unit for generating a sampling clock, n-1 delay units for delaying the sampling clock of the clock generation unit, a sampling clock output from the clock generation unit, and the n-1 delay units Output each An n digital converter that converts a response waveform output from the semiconductor device into digital data based on a pulling clock, a storage unit that stores sampling data output from the n digital converters, A waveform synthesizing unit for synthesizing the sampling data stored in the storage unit to generate a digital sampling waveform, wherein the data processing unit generates the digital sampling waveform from the digital sampling waveform by skew in the (n-1) delay units. A frequency spectrum in which a noise component is corrected is generated, and a time domain waveform is generated from the frequency spectrum.
[0091]
5. In the above paragraph 4, the data processing means performs a Fourier transform on the digital sampling waveform generated by the waveform synthesizing section, and generates a frequency spectrum of the digital sampling waveform, and the Fourier transform processing section generates the frequency spectrum. A skew error correction unit for detecting and correcting a noise component generated by the skew of the n-1 delay units from the frequency spectrum, and an inverse Fourier transform of the frequency spectrum corrected by the skew error correction unit, And an inverse Fourier transform processing unit for generating a waveform.
[0092]
6. In the fourth or fifth aspect, the data processing means performs a measurement for evaluating a time domain characteristic of a signal amplitude and a half width in the response waveform from a time domain waveform generated by the inverse Fourier transform processing unit. It has an evaluation unit.
[0093]
7. A process of forming a semiconductor element on a semiconductor wafer, forming a semiconductor chip, sampling a response waveform output from a semiconductor device based on a test waveform, and generating a frequency spectrum in which a noise component is corrected from the sampled data, Inspecting the response waveform of the semiconductor device using the corrected frequency spectrum; dicing the semiconductor wafer along a dicing line to singulate the semiconductor chip; and singulating the singulated semiconductor chip. And a step of forming a semiconductor device using the method.
[0094]
8. A process of forming a semiconductor chip on a semiconductor wafer to form a semiconductor chip, and converting a response waveform output from the semiconductor device based on a test waveform into n digital converters and n-1 A data processing unit that performs sampling using a delay unit and generates a time-domain waveform from the sampled sampled data, obtains a frequency spectrum by performing a Fourier transform on the sampled data, and then calculates a skew in the (n−1) delay units. Correcting the generated noise component, inspecting the response waveform of the semiconductor device using the corrected frequency spectrum, dicing the semiconductor wafer along a dicing line, and dividing the semiconductor wafer into individual semiconductor chips. Forming a semiconductor device using the singulated semiconductor chip It is a manufacturing method of a semiconductor device having a.
[0095]
9. A process of forming a semiconductor element on a semiconductor wafer to form a semiconductor chip, sampling a response waveform output from a semiconductor device based on a test waveform, and generating a time-domain waveform in which a noise component is corrected from the sampled data. Inspecting the response waveform of the semiconductor device using the corrected time-domain waveform, dicing the semiconductor wafer along a dicing line, and dividing the semiconductor wafer into the semiconductor chips; Forming a semiconductor device using a semiconductor chip.
[0096]
10. A process of forming a semiconductor chip on a semiconductor wafer to form a semiconductor chip, and converting a response waveform output from the semiconductor device based on a test waveform into n digital converters and n-1 After sampling using a delay unit and performing a Fourier transform on the sampled data to obtain a frequency spectrum, the noise component generated by the skew in the n-1 delay units is corrected, and the corrected frequency spectrum is inverted. Generating a time-domain waveform by performing Fourier transform, inspecting a response waveform of the semiconductor device using the time-domain waveform, and dicing the semiconductor wafer along a dicing line to singulate the semiconductor chip. A semiconductor device using the singulated semiconductor chip. It is a method of manufacture.
[0097]
11. In any one of the above items 1 to 3, the skew error correction section specifies a frequency of a noise component generated by skew from the frequency spectrum, and deletes the frequency component.
[0098]
12. In any one of the above items 1 to 3, the skew error correction unit specifies a frequency of a noise component generated by skew from the frequency spectrum, deletes the frequency component, and removes a frequency component of the response waveform in the frequency spectrum. This is to correct the frequency component.
[0099]
13. In any one of the above items 1 to 3, the skew error correction section specifies a frequency of a noise component generated by skew from the frequency spectrum, deletes the frequency component, and determines a frequency of the noise component based on the frequency. First, a time domain waveform is corrected.
[0100]
【The invention's effect】
(1) According to the present invention, it is possible to provide a semiconductor inspection device capable of greatly improving the measurement accuracy of analog characteristics in a semiconductor device.
(2) Further, according to the present invention, the semiconductor device can be manufactured by inspecting the response waveform of the semiconductor device with high accuracy.
[Brief description of the drawings]
FIG. 1 is an overall block diagram of a semiconductor inspection device according to an embodiment of the present invention.
FIG. 2 is a block diagram of a WFD and a data processor provided in the semiconductor inspection device of FIG. 1;
FIG. 3 is a simulation diagram showing an example of a frequency spectrum in sampling data.
FIG. 4 is a simulation diagram showing another example of a frequency spectrum in sampling data.
FIG. 5 is a block diagram of a WFD and a data processor provided in a semiconductor inspection device according to a second embodiment of the present invention.
FIG. 6 is a sine waveform diagram obtained by inverse Fourier transform by IFFT provided in the semiconductor inspection device.
FIG. 7 is a block diagram of a WFD and a data processor provided in a semiconductor inspection device according to another embodiment of the present invention.
FIG. 8 is a block diagram of a semiconductor inspection device studied by the present inventors.
[Explanation of symbols]
1, 1a: semiconductor inspection device, 2: control unit, 3: analog / mixed signal tester, 4: waveform pattern generator, 4a: pattern generator, 4b: timing generator, 5: arbitrary waveform generator, 6: WFD (Sampling means), 7, 7a: data processor, 8: clock generator, 9: parallel A / D conversion circuit, 9a ₁ ~ 9a ₃ ... Delay circuit (delay part), 9b ₁ ~ 9b ₄ ... A / D converter (digital converter), 10 ... memory (storage unit), 11 ... waveform synthesizing means (waveform synthesizing unit), 12 ... sampling clock generation circuit (clock generating unit), 13 ... FFT (Fourier transform processing) ), 14 skew error correction means (skew error correction section), 15 ... measurement item evaluation means (measurement evaluation section), 16 ... IFFT (inverse Fourier transform processing section), 17 ... waveform quality evaluation means (measurement evaluation section) , 18 ... Logic tester, 19 ... Analog BOST
DUT semiconductor device

Claims (10)

A master clock, a pattern generator for generating pattern data including information on a test waveform, a timing generator for receiving the master clock and the pattern data and generating a test waveform, and applying the test waveform to the semiconductor device A semiconductor inspection apparatus, comprising: a driver that performs sampling; a sampling unit that samples a response waveform from the semiconductor device; and a data processing unit that obtains a frequency spectrum from sampling data sampled by the sampling unit.
The sampling means,
A clock generation unit that generates a sampling clock;
N-1 delay units for delaying a sampling clock of the clock generation unit;
N digital conversion units for converting a response waveform output from the semiconductor device into digital data based on a sampling clock output from the clock generation unit and a sampling clock output from each of the n-1 delay units. Container,
A storage unit for storing the sampling data output from the n digital converters;
A waveform synthesizing unit that synthesizes the sampling data stored in the storage unit and generates a digital sampling waveform,
The data processing means includes:
A semiconductor inspection apparatus, wherein a frequency spectrum in which a noise component generated due to skew in the n-1 delay units is generated from the digital sampling waveform. The semiconductor inspection device according to claim 1,
The data processing means includes:
Fourier transform the digital sampling waveform generated by the waveform synthesizing unit, a Fourier transform processing unit that generates a frequency spectrum of the digital sampling waveform,
A semiconductor inspection apparatus, comprising: a skew error correction unit that detects and corrects a noise component generated by skew of the (n−1) delay units from a frequency spectrum generated by the Fourier transform processing unit. The semiconductor inspection apparatus according to claim 1, wherein
The data processing means includes:
A semiconductor inspection device, comprising: a measurement evaluation unit that evaluates the response waveform from the frequency spectrum corrected by the skew error correction unit. A master clock, a pattern generator for generating pattern data including information on a test waveform, a timing generator for receiving the master clock and the pattern data and generating a test waveform, and applying the test waveform to the semiconductor device And a sampling unit for sampling a response waveform from the semiconductor device,
A data processing unit for generating a time-domain waveform from the sampling data sampled by the sampling unit,
The sampling means,
A clock generation unit that generates a sampling clock;
N-1 delay units for delaying a sampling clock of the clock generation unit;
N digital conversion units for converting a response waveform output from the semiconductor device into digital data based on a sampling clock output from the clock generation unit and a sampling clock output from each of the n-1 delay units. Container,
A storage unit for storing the sampling data output from the n digital converters;
A waveform synthesizing unit that synthesizes the sampling data stored in the storage unit and generates a digital sampling waveform,
The data processing means includes:
A semiconductor inspection apparatus, comprising: generating a frequency spectrum in which a noise component generated by skew in the n-1 delay units is corrected from the digital sampling waveform, and generating a time domain waveform from the frequency spectrum. The semiconductor inspection apparatus according to claim 4,
The data processing means includes:
Fourier transform the digital sampling waveform generated by the waveform synthesizing unit, a Fourier transform processing unit that generates a frequency spectrum of the digital sampling waveform,
A skew error correction unit that detects a noise component generated by the skew of the n−1 delay units from the frequency spectrum generated by the Fourier transform processing unit, and corrects the noise component;
A semiconductor inspection apparatus comprising: an inverse Fourier transform processing unit that performs an inverse Fourier transform on the frequency spectrum corrected by the skew error correction unit and generates a time domain waveform. The semiconductor inspection device according to claim 4 or 5,
The data processing means includes:
A semiconductor inspection apparatus, comprising: a measurement evaluation unit that evaluates a time domain characteristic of a signal amplitude and a half width of the response waveform from a time domain waveform generated by the inverse Fourier transform processing unit. Forming semiconductor elements on a semiconductor wafer to form semiconductor chips;
A response waveform output from the semiconductor device is sampled based on the test waveform, a frequency spectrum in which a noise component is corrected is generated from the sampled data, and a response waveform of the semiconductor device is inspected using the corrected frequency spectrum. Process and
Dicing the semiconductor wafer along a dicing line, and singulating into the semiconductor chips;
Forming a semiconductor device using the singulated semiconductor chips. Forming semiconductor elements on a semiconductor wafer to form semiconductor chips;
The response waveform output from the semiconductor device based on the test waveform is sampled using n digital converters and n-1 delay units that delay the sampling clock, and the sampled data is subjected to Fourier transform. Obtaining a frequency spectrum, correcting a noise component generated by skew in the n-1 delay units, and inspecting a response waveform of the semiconductor device using the corrected frequency spectrum;
Dicing the semiconductor wafer along a dicing line, and singulating into the semiconductor chips;
Forming a semiconductor device using the singulated semiconductor chips. Forming semiconductor elements on a semiconductor wafer to form semiconductor chips;
A response waveform output from the semiconductor device is sampled based on the test waveform, a time-domain waveform in which a noise component is corrected is generated from the sampled data, and a response waveform of the semiconductor device is calculated using the corrected time-domain waveform. Inspecting,
Dicing the semiconductor wafer along a dicing line, and singulating into the semiconductor chips;
Forming a semiconductor device using the singulated semiconductor chips. Forming semiconductor elements on a semiconductor wafer to form semiconductor chips;
The response waveform output from the semiconductor device based on the test waveform is sampled using n digital converters and n-1 delay units that delay the sampling clock, and the sampled data is subjected to Fourier transform. After obtaining the frequency spectrum, the noise component generated by the skew in the n-1 delay units is corrected, the corrected frequency spectrum is subjected to inverse Fourier transform to generate a time domain waveform, and the time domain waveform is used. Inspecting the response waveform of the semiconductor device by:
Dicing the semiconductor wafer along a dicing line, and singulating into the semiconductor chips;
Forming a semiconductor device using the singulated semiconductor chips.

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