JP2004071862A - Semiconductor device manufacturing method and semiconductor device manufacturing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which reduces dispersion in an STI step in wafers or in lots. <P>SOLUTION: In STI formation process, after an insulation film 6 is deposited, polishing is carried out until a stopper film is exposed. Thereafter, the film thickness of the stopper film is measured. The average value of film thickness of the stopper film for each wafer or each lot is calculated from film thickness measurement result. Then, wet etching time of the insulation film 6 is selected according to the film thickness of the stopper film based on a prepared correspondence table 15 between an average value of nitride film thickness and etching time of an insulation film. Since dispersion in a STI step 12 is thereby reduced and generation of the STI step 12 can be also restrained, a semiconductor device of high yield and reliability can be provided. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device provided with a groove separation for electrically insulating transistors from each other in manufacturing an VLSI.
[0002]
[Prior art]
As an element isolation technology, a trench isolation technology (hereinafter, referred to as STI) has been widely put into practical use. For example, B. Davari et al. , IEDM Tech. Digest, 92, (1998).
[0003]
This STI forming step includes a step of removing an excessively deposited film by the CMP step and flattening the film surface. Because the CMP process is unstable, the conventional method uses a polishing apparatus having an end point function for polishing an insulating film embedded in a concave portion and detecting an end point of polishing when the stopper film is exposed. Was.
[0004]
[Problems to be solved by the invention]
However, with the recent miniaturization of transistors, there is a case where the thickness of the stopper film varies between wafers or lots even when polishing is performed by a polishing apparatus having an endpoint function.
[0005]
On the wafer, there are regions where the transistor formation region is sparse and dense, or regions where the transistor formation region is wide or narrow.
[0006]
Specifically, a step occurs between the STIs as follows.
[0007]
First, as shown in FIG. 6A, a silicon oxide film 2 on the surface of a transistor formation region and a silicon oxide film 5 on a surface of a trench 4 are deposited on a semiconductor substrate 1 having an STI. 2, a silicon nitride film 3 is deposited, and an insulating film 6 is deposited on the entire semiconductor substrate so as to completely bury the STI.
[0008]
Here, the thickness of the insulating film 6 deposited thereon greatly differs depending on whether the width of the transistor formation region is narrow or wide. For example, when the width of the transistor formation region is small, the thickness of the insulating film 6 deposited thereon is small, and when the width of the transistor formation region is large, the thickness of the insulating film 6 deposited thereon is large. ing.
[0009]
When polishing is performed in this state, as shown in FIG. 6B, the stopper film is exposed from the portion where the insulating film is deposited first, and the stopper film 3 in the transistor forming region where the thick insulating film is deposited is removed. In this case, the film thickness varies.
[0010]
As a result, as shown in FIG. 6C, when the stopper film 3 is removed, the height of the top surface of the STI in which the insulating film is embedded and the top surface of the silicon oxide film 2 on the semiconductor substrate 1 are different. A step 12 occurs.
[0011]
Here, the height of the STI step 12 varies between wafers or lots. This is because the flatness of the film surface is not necessarily uniform between wafers or lots, even when polishing is performed under uniform conditions when removing the insulating film 6. In particular, in the case of wafers in which the degree of density, width, or width of the transistor formation region is different, the variation in the stopper film thickness generated after polishing the insulating film 6 differs between wafers or lots. The STI step 12 varies between units or lots.
[0012]
Therefore, an object of the present invention is to provide a semiconductor device manufacturing method capable of suppressing variation in STI steps between wafers or lots even when variation in stopper film thickness occurs between wafers or lots. A method and a manufacturing apparatus are provided.
[0013]
[Means for Solving the Problems]
In order to solve the problem, according to the present invention, in a case where a transistor formation region is dense, dense, or wide or narrow, a step of forming a stopper film over the transistor formation region and forming a groove between the transistor formation region are A step of depositing an insulating film on the transistor formation region and embedding the insulating film in the trench; a step of polishing the insulating film until the stopper film is exposed; and a step of polishing the insulating film embedded in the trench. Measuring the thickness of the stopper film after the polishing step, and etching the upper portion of the insulating film in the groove by the measured thickness of the stopper film in the method of manufacturing a semiconductor device comprising the steps of: And a method of manufacturing a semiconductor device comprising:
[0014]
As a result, since the thickness of SiN is measured between wafers or lots and the etching amount is changed, variations in STI steps occurring between wafers or lots can be suppressed, and the thickness of the stopper film or the insulating film can be reduced. Even when variations occur, a method and an apparatus for manufacturing a semiconductor device with high yield and high reliability can be provided.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
[0016]
(Embodiment 1)
Embodiment 1 is characterized by a method for determining the wet etching amount after the CMP process. First, a method for forming a transistor having STI will be described with reference to the drawings.
[0017]
As shown in FIG. 1A, after a first silicon oxide film 2 and a silicon nitride film 3 are sequentially deposited on a semiconductor substrate (silicon substrate) 1, a lithography method using a resist 14 To pattern the resist.
[0018]
Next, as shown in FIG. 1B, the silicon nitride film serving as the stopper film 3 is etched by dry etching, and then the silicon substrate 1 is etched by dry etching using the stopper film 3 as a mask. Then, a groove 4 to be STI is formed.
[0019]
After that, as shown in FIG. 1C, after a second silicon oxide film 5 is formed on the surface of the groove 4, an insulating film 6 is deposited on the groove 4 so that the groove 4 is completely buried. Here, as the insulating film 6, a silicon oxide film such as an NSG film or a TEOS film that can be deposited by a CVD method is used.
[0020]
Subsequently, as shown in FIG. 2A, after the insulating film 6 is annealed, the stopper film 3 is exposed by chemical mechanical polishing (hereinafter, CMP) of the insulating film 6 previously buried in the groove 4. Polish until
[0021]
Next, as shown in FIG. 2B, to suppress the height of the insulating film 6, the upper surface of the insulating film 6 is removed by, for example, wet etching. The step of determining the etching amount has a feature of the present invention, and the step will be described in detail later.
[0022]
After that, as shown in FIG. 2C, the stopper film 3 is selectively removed with phosphoric acid or the like to form an STI in which the generation of the STI step 12 is suppressed.
[0023]
Finally, as shown in FIG. 2D, a gate electrode 7 and side walls 8, a source 9, and a drain 10 are sequentially formed to complete a transistor.
[0024]
Next, a method of determining the etching amount of the insulating film 6, which is a feature of the present embodiment, will be described with reference to the drawings.
[0025]
First, FIG. 3 (a1) is the same as FIG. 2 (a), and shows a state in which a large step of the insulating film 6 is removed in the CMP process and the upper surface of the stopper film 3 is exposed. This step is formed larger when the transistor formation regions are densely arranged or when a wide region of the transistor formation region and a region with a small element isolation width are mixed.
[0026]
Next, as shown in FIG. 3 (a2), in advance for a particular 25 points in the wafer of the same layout, measuring the thickness d of the stopper film 3, and the average film thickness d _a obtained from the measurement result Then, a correspondence table 15 is created in which the etching time t of the upper part of the insulating film 6 in the groove 4 is compared.
[0027]
According to the correspondence table 15, when the thickness of the silicon nitride film 3 is d (nm), when the insulating film 6 is wet-etched by t (s), the height of the insulating film 6 is set within a range where the STI step 12 is not so large. Can be adjusted.
[0028]
Specifically, the correspondence table 15 is created as follows using a test pattern for creating the correspondence table 15 in accordance with the transistor formation method described above.
[0029]
First, the NSG film as the insulating film 6 is polished until the entire surface of the SiN film as the stopper film 3 on the wafer is exposed.
[0030]
Next, the thickness d of the stopper film 3 in the dense portion at this stage is measured. For example, the thickness d of the stopper film 3 at 25 points in one wafer is measured, and the average value d _a (nm) is obtained.
[0031]
Thereafter, based on the average value d _a (nm) of the thickness of the stopper film 3 obtained earlier, the wet etching is completed in a range where the STI step 12 does not become too large. For that purpose, it is necessary to determine in advance how much the insulating film 6 should be removed, that is, the film thickness to be removed. Specifically, as shown in FIG. 3 (a1), if wet etching the film thickness d _{a (nm)} min insulating film 6 of the stopper film 3, and the substrate 1 surface, STI surface insulating film 6 is embedded The wet etching can be completed within a range in which the STI step 12 does not become too large, without a large deviation in height between the steps.
[0032]
Therefore, the end point of the wet etching of the insulating film 6 is determined based on the average film thickness d _a (nm) of the stopper film 3, and how much time t (s) is required to wet-etch the insulating film 6 to that point. Whether or not it is necessary is determined according to the thickness of each stopper film 3. As a result, the summarized average film thickness d _a of the stopper film 3 _(nm) and the wet etching time of the insulating film 6 t (s), the correspondence table 15 is completed.
[0033]
Then, in the step of FIG. 3B, in order to examine the variation in the film thickness between the wafers, the film thickness of the stopper film 3 was measured on the wafer 1 after the CMP process by using a film thickness measuring device. Perform at the location. Here, in order to control the variation between wafers, it is necessary to measure all the wafers and determine the etching amount for each wafer.
[0034]
Then, in step in FIG. 3 (c), to calculate the average film thickness of the stopper film 3 in the wafer plane d _{a (nm)} from the film thickness measurement results. More specifically, since it is desired to suppress variations for each wafer, an average of measured values within each wafer surface is obtained.
[0035]
Next, in step in FIG. 3 (d), by a comparison of the average film thickness of the correspondence table 15 and the stopper film 3 'each wafer "d _{a (nm),} an upper portion of the insulating film 6 in the next step The etching time t (s) is determined.
[0036]
For example, from the correspondence table 15 in FIG. 3A2, if the average value of the thickness of the stopper film 3 is 55 nm, the etching time of the insulating film 6 is 60 s, and if the average value of the thickness of the stopper film 3 is 60 nm. For example, the etching time of the insulating film 6 is set to 70 s.
[0037]
Then, in the step of FIG. 3E, the upper surface of the insulating film 6 is etched using the wet etching apparatus 17 for the etching time t (s) determined in the step of FIG. As a result, the STI step 12 can be adjusted to a desired height, and a structure can be formed in which the variation of the STI step 12 between wafers hardly occurs.
[0038]
In addition, using the same method, the variation of the STI step difference between “lots” can be suppressed.
[0039]
In this case, when performing the film thickness measurement in FIG. 3B, the film thickness of the stopper film 3 is measured at a plurality of locations in the wafer surface for a plurality of sheets in one lot. For example, five of the twenty-five lots in one lot are extracted, and 25 points are measured for each of the five wafers. Thereafter, the wet etching amount for one lot is determined from the average value of the measurement results for the five wafers. Here, for the same lot, wet etching is performed on all the wafers with the wet etching amount.
[0040]
Thereafter, in FIG. 3C, the average thickness d _a (nm) of each measurement is calculated “for each lot”, and the wet etching time t of the insulating film 6 is determined using the correspondence table 15.
[0041]
As a result, in order to determine the wet etch time t based on the stopper average film thickness d _a of "each lot", it is possible to suppress the variation in the STI step height 12 between lots.
[0042]
As described above, in the present embodiment, the thickness d of the stopper film 3 which changes depending on the degree of the density of the transistor formation region and the degree of the wide or narrow region between wafers or lots is measured, and the insulating film is measured. By optimizing the wet etching amount of No. 6, variations in the height of the STI step 12 between wafers or lots can be minimized.
[0043]
Here, the present invention is characterized in that the etching amount is determined based on the measured value of the stopper film, and is particularly effective when the height of the STI bottom varies between wafers or between lots.
[0044]
Specifically, as shown in FIG. 4A, when there is a wafer 1 and a wafer 2 having an average variation in the bottom of the STI of 20 nm, the wafer 1 has a stopper film (SiN) after the STI-CMP process. The average value of the film is 65 nm, the thickness of the insulating film buried in the STI trench is 385 nm, and the average value of the stopper film (SiN film) after the STI-CMP process is 85 nm and the insulating film buried in the STI trench is wafer 2. Has a thickness of 385 nm. Here, the step (for example, 20 nm) at the bottom of the STI affects the thickness of the stopper film, and the stopper film of the wafer 2 having the step at the STI bottom becomes thicker at the STI bottom (85 nm), and the stopper film of the wafer 2 The thickness is larger than the stopper film thickness (65 nm) of the wafer 1.
[0045]
Therefore, when the thickness of the stopper film is measured according to the method of the present invention, the thickness of the SIN film, which is the stopper film, is measured to determine the etching amount. Therefore, as shown in FIG. Can be adjusted by the thickness of the step (20 nm) at the bottom of the STI, and the variation in the STI step between wafers or lots can be further suppressed.
[0046]
On the other hand, the step at the bottom of the STI is not reflected in the thickness of the insulating film embedded in the STI. Therefore, even when the bottom of the STI varies, the thickness of the insulating film of the wafer 1 may be substantially equal to the thickness of the insulating film of the wafer 2, for example, 385 nm, for example, 385 nm. As a result, as shown in FIG. 4C, even if the bottom of the STI is varied, when the thickness of the insulating film is measured and the etching amount is determined, the etching amounts of the wafer 1 and the wafer 2 become equal, Variations between wafers are not eliminated.
[0047]
As described above, according to the present embodiment, as shown in FIG. 4B, even when the STI bottom portion varies, the stopper film thickness reflecting the variation of the STI bottom portion is measured to measure the etching amount of the insulating film. Is determined, the variation in the STI step can be suppressed more accurately.
[0048]
In the present embodiment, the SiN film is used as the stopper film 3. However, the stopper film is a film having a lower polishing rate than the insulating film 6 buried in the groove 4, and is buried in the groove 4 when removing the stopper film. A film other than the SiN film may be used as long as the etching rate is sufficiently high for the insulating film 6.
[0049]
(Embodiment 2)
In the present embodiment, a specific configuration example of the semiconductor manufacturing apparatus 100 of the present invention will be described with reference to FIG.
[0050]
The semiconductor manufacturing apparatus 100 includes a polishing block A on which a polishing apparatus 101 is installed, a cleaning block B for removing slurry on the front and back surfaces of the wafer after polishing, and a thickness of a stopper film on the wafer polished by the polishing apparatus 101. A measurement block C for measuring the thickness, an operation block D for storing the thickness measurement result and determining the etching amount of the insulating film 6 in the groove 4, and an etching block E for etching the insulating film 6 for the determined time. And a storage block F for storing wafers that need to be polished. Each block is separated by a transparent plastic wall 102 except for a hole necessary for carrying the wafer.
[0051]
The measuring block C is provided with an optical film thickness measuring device 103 for measuring the film thickness of the stopper film on the wafer polished by the polishing apparatus 101. The optical film thickness measuring device 103 has been subjected to a vibration proof treatment in order to prevent the influence of vibration during polishing.
[0052]
A computer 105 that controls the etching apparatus 104 installed in the etching block E is installed in the arithmetic block D, and the memory in the computer previously correlates the film thickness measurement result with the insulating film etching time. Data 15 is stored.
[0053]
The storage block F is provided with a wafer cassette 106 for storing a large number of wafers that need to be polished.
[0054]
Hereinafter, the operation of the semiconductor manufacturing apparatus 100 of the present embodiment will be described.
[0055]
First, the wafer taken out of the wafer cassette 106 is held by the carrier head 107 and moves onto the polishing pad 108.
[0056]
Then, the wafer is polished in the polishing apparatus 101. Here, as shown in FIG. 1C, the wafer is in a state where the insulating film 6 is buried in the groove 4 and is polished. After the polishing of the wafer is completed, the wafer is transferred to the cleaning block B, and the slurry on the front surface and the back surface is removed. Here, the wafer is in a state as shown in FIG.
[0057]
Subsequently, the wafer is transported to the measurement block C, and the optical film thickness measuring device 103 measures the film thickness of the stopper film 3 in a predetermined region. This measurement result is stored in the memory in the computer 105 provided in the operation block D, and the processor in the computer 105 instantaneously determines the etching time t of the insulating film 6.
[0058]
Next, the wafer is conveyed to the etching block E, and the insulating film 6 is etched by the installed etching apparatus 104 for the time determined previously. As a result, as shown in FIG. 2C, a semiconductor device having almost no variation in the STI step is formed.
[0059]
Finally, the wafer returns to the same place in the wafer cassette 106 that has been previously taken out, and the processing ends.
[0060]
Note that the optical film thickness measuring device 103 installed in the measurement block C often measures a wafer with a pattern, and thus preferably has an alignment function.
[0061]
In this embodiment, the cleaning block B for removing the slurry on the front and back surfaces of the wafer after polishing and the etching block E for etching the insulating film are separately provided. However, the same apparatus is used for removing the slurry and etching the insulating film. If it can be performed, it is preferable to share these and make one block.
[0062]
As described above, according to the present invention, the step of adjusting the variation of the STI step and the series of processes for forming the STI can be performed in one apparatus, so that the TAT can be shortened and the productivity can be improved.
[0063]
【The invention's effect】
According to the present invention, the wet etching conditions can be adjusted by measuring the thickness of the stopper film, so that not only the variation of the STI step between wafers or lots but also the occurrence of the STI step can be minimized. As a result, the withstand voltage of the gate oxide film does not decrease or the occurrence of characteristic failure in the transistor is reduced, so that a semiconductor device with high yield and high reliability can be manufactured.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view of Embodiment 1 of the present invention. FIG. 2 is a process cross-sectional view of Embodiment 1. FIG. 3 is a view showing a process of Embodiment 1. FIG. FIG. 5 illustrates a semiconductor device according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a problem of a conventional method.
REFERENCE SIGNS LIST 1 silicon substrate 2 first silicon oxide film 3 silicon nitride film 4 groove portion 5 second silicon oxide film 6 insulating film 7 gate electrode 8 sidewall 9 source region 10 drain region 11 resist film thickness difference 12 STI step 13 gate oxide film 14 resist 15 Correspondence table of average film thickness of stopper film and wet etching time 16 Transistor formation region 100 Semiconductor manufacturing apparatus 101 Polishing apparatus 102 Wall 103 Optical film thickness measuring instrument 104 Etching apparatus 105 Computer 106 Wafer cassette 107 Carrier head 108 Polishing pad

Claims (5)

In the case where the transistor formation region is sparse, dense, wide or narrow,
Forming a stopper film on the transistor formation region;
Forming a groove between the transistor forming regions,
Depositing an insulating film on the transistor formation region and burying the insulating film in the trench;
Polishing the insulating film until the stopper film is exposed;
Removing the upper portion of the insulating film embedded in the groove by etching, the method of manufacturing a semiconductor device,
Measuring the thickness of the stopper film after the polishing step;
Determining the amount of etching of the upper part of the insulating film in the trench based on the measured thickness of the stopper film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an etching amount of the upper portion of the insulating film in the trench is determined for each lot. 2. The method according to claim 1, wherein the amount of etching of the upper portion of the insulating film in the groove determines the amount of etching for each wafer. A gate electrode in the region where the transistor is to be formed;
A wafer having a portion formed by introducing impurities into the semiconductor substrate,
2. The method according to claim 1, further comprising: a source / drain region formed by introducing an impurity into the semiconductor substrate on both sides of the gate electrode. In the apparatus main body, a wafer polishing unit, a slurry removal unit after polishing, a film thickness measurement unit, a calculation unit for calculating the stopper film thickness and the etching amount of the insulating film, and an etching unit for etching the insulating film,
The stopper film thickness measurement unit measures a stopper film thickness on a transistor formation region formed on the semiconductor substrate,
The calculation unit calculates an etching amount of the insulating film based on the measurement result of the film thickness,
The semiconductor device manufacturing apparatus, wherein the etching unit etches the insulating film according to the etching amount.

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