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JP2004071597A - Semiconductor module - Google Patents

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Publication number
JP2004071597A
JP2004071597A JP2002224486A JP2002224486A JP2004071597A JP 2004071597 A JP2004071597 A JP 2004071597A JP 2002224486 A JP2002224486 A JP 2002224486A JP 2002224486 A JP2002224486 A JP 2002224486A JP 2004071597 A JP2004071597 A JP 2004071597A
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JP
Japan
Prior art keywords
semiconductor element
semiconductor
module
wiring board
heat
Prior art date
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Pending
Application number
JP2002224486A
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Japanese (ja)
Inventor
Yasuo Osone
大曽根　靖夫
Tsuneo Endo
遠藤　恒雄
Mikio Negishi
根岸　幹夫
Daiki Noto
能登　大樹
Norio Nakazato
中里　典生
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2002224486A priority Critical patent/JP2004071597A/en
Publication of JP2004071597A publication Critical patent/JP2004071597A/en
Pending legal-status Critical Current

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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the thermal resistance of the heat dissipating route of a three-dimensionally mounted semiconductor element by causing the route to become independent. <P>SOLUTION: In a semiconductor module, wiring and a circuit component or a first semiconductor element are mounted on one surface of a first wiring board and a cavity housing a second semiconductor element or another circuit component is formed on the other surface of the wiring board. In the module, the second semiconductor element is mounted on a second wiring board having wiring and the first and second wiring boards are electrically and thermally joined to each other. In addition, the heat dissipating route through which the heat released from the second semiconductor element is conducted to the outside of the module is formed in the second wiring board. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、複数の半導体素子を三次元実装する半導体モジュールに関し、実装した半導体素子の放熱特性を向上させるものである。
【０００２】
【従来の技術】
移動体通信の端末機である携帯電話端末機では、使用者の要求に応えるため急速に小型化が進んだが、使い勝手などを考慮すると小型化にはおのずから限度があり、将来的に現行製品と比べて大幅な外形の小型化が求められる状況にはないと考えられる。
【０００３】
しかし、携帯電話端末用パワーアンプモジュールなどの半導体モジュールの分野においては、外形の小型化要求が緩和されても、端末の高機能化の進展に伴い搭載モジュール数が増えることによって、半導体モジュールが搭載されるプリント基板等の実装基板の面積自体も現状より大幅に拡大されることは期待できないため、現行製品と同等のサイズの基板により多くのモジュールを搭載しなければならず、個々のモジュールに許容される占有面積が縮小される傾向にあるため個々のモジュールの省寸法化を図らざるを得ない。
【０００４】
高機能化について具体的には、例えば欧米やアジアで広く使用されているＧＳＭ系の携帯電話端末では、９００ＭＨｚ帯や１８００ＭＨｚ帯等の複数の周波数帯が用いられており、携帯電話の汎用性の確保という観点から、特に端末の送受信系の回路、すなわちＲＦ回路モジュールについて、複数の周波数帯の信号を単一のモジュールで処理することが要請されており、こうした複数の周波数帯の信号を単一のモジュールで処理する所謂デュアルバンド対応のモジュールが一般的であるが、今後はさらに他の周波数帯にも対応できるトリプルバンド対応やトリプルバンドにデータ通信機能（ＥＤＧＥ：Ｅｎｈａｎｃｅｄ　Ｄａｔａ　ｒａｔｅｓ　ｆｏｒ　ＧＳＭ　Ｅｖｏｌｕｔｉｏｎ）を付加したモジュールが市場では要求されている。
【０００５】
図２に示すのは従来用いられてきた半導体モジュールの例であり、この半導体モジュールでは、配線基板１の一方の面に形成された中央部の凹部に、単結晶シリコン等の半導体基板に素子を形成した半導体素子２を収容し、半導体素子２は導電性接合部材３によって配線基板１に固定されており、配線基板１は、セラミック或いはガラスエポキシ等の絶縁層４に銅箔等をパターニングした配線を各層に形成した積層構造の多層配線基板となっている。
【０００６】
この配線基板１では、最上層の配線は、その一端が半導体素子２の接続端子であるパッドとボンディングワイヤ６によって接続されており、配線基板１を貫通するビアホール配線７によって複数層の配線の層間接続を行ない、配線基板１の他方の面に形成された最下層の配線５が半導体モジュールの外部端子となり、この外部端子を製品端末機の実装基板の配線に接続する。
【０００７】
また、半導体素子２の裏面が導電性接合部材３によって放熱用のビアホール配線であるサーマルビア７ａの一端と熱的に接続されており、サーマルビア７ａの他端が最下層の放熱用の配線５ａに接続されている。
【０００８】
なお、配線基板１の前記一方の面には、半導体素子２の他に抵抗・キャパシタ等の回路部品８が搭載されており、ボンディングワイヤ６を含む半導体素子２と配線基板１との接続部分及び回路部品８はエポキシ樹脂等を用いた封止体（図示せず）で覆い封止してある。
【０００９】
このような従来用いられてきた半導体モジュールの構造では、前述したＲＦ回路モジュールの高機能化と、モジュールの省寸法化という相反するニーズに対し、搭載される回路部品の小型化等により半導体モジュールの寸法を小さくする趨勢にあるが、それだけでは省寸法化の波に対応しきれない状況になりつつあり、許された寸法内に全ての機能を搭載することが困難になりつつある。
【００１０】
そこで、多層配線基板の裏面にキャビティを形成し、表面側に回路部品を搭載し、キャビティ側に半導体素子をフリップチップ実装する三次元実装構造が例えば特開２００１−４４２４３号公報において開示され、また、表面側に放熱素子を搭載し、キャビティ側に半導体素子をフリップチップ実装或いはボンディングワイヤ実装する三次元実装構造が、例えば特開平７−３０２８６６号公報、特開平９−８１８７号公報などに開示されている。
【００１１】
このような三次元実装構造を前記半導体モジュールに適用し半導体基板１の両面に半導体素子を搭載した例を図３に示す。この半導体モジュールでは、配線基板１の一方の面に第１の半導体素子２を収容し、半導体素子２はバンプ電極９を介してフリップチップ実装によって配線基板１にフェイスダウンで固定されており、配線基板１の他方の面に形成された中央部のキャビティに第２の半導体素子１０を収容し、半導体素子１０はバンプ電極１１を介してフリップチップ実装によって配線基板１にフェイスアップで固定されている。
【００１２】
配線基板１は、最下層の配線が半導体モジュールの外部端子となっており、この外部端子が導電性接合部材１２によって他の配線基板１３に接続され、同様の導電性接合部材１２によって第２の半導体素子１０の裏面が配線基板１３の金属部材に接続されている。
【００１３】
【発明が解決しようとする課題】
こうした三次元実装構造に関し、特開平７−３０２８６６号公報で開示された半導体モジュールでは、半導体素子で生じた熱を電極と反対側の面に接続された放熱フィンによって放熱する構成となっている。しかし、携帯電話端末機では筐体内部が各種部品及び基板等によって大部分が既に占められ残余の空間が少なく、加えて内部に滞留する空気の移動が難しい等の空間的な余裕度の観点から、モジュール外部に接続する放熱機構が機能し難いため、このような放熱経路を採用することはできない。
【００１４】
また、特開平９−８１８７号公報で開示されている技術では、素子から生じた熱を、多層配線基板を経由して接続カードに放熱する構成となっており、許容される温度が比較的低い半導体素子を搭載した場合、その許容値を超えてしまう可能性が懸念される場合がある。
【００１５】
特に、多層配線基板の上面に他の半導体素子を搭載する場合には、上面に搭載された半導体素子からの放熱の影響をキャビティ側に搭載された半導体素子が受けてしまうため、発熱による温度上昇の幅が拡大する場合がある。こうした他の半導体素子の発熱による影響を回避するためには、三次元実装構造を有する半導体モジュールにおいては、個々の半導体素子からの放熱経路を独立させることが技術的に要請されている。
【００１６】
一方、特開２００１−４４２４３号公報において開示されている技術では、フリップチップ実装された半導体素子の実装面と反対側に放熱部材を具備したことを特徴としているが、実装される回路形成面に生じた熱が半導体素子の半導体基板を縦断して基板裏面から、放熱部材を介してマザーボードに放熱される構成であるため、放熱部材の材質や厚さによっては、やはり熱抵抗を十分低減できない可能性がある。
【００１７】
また、発熱する回路形成面でフリップチップ実装されているためバンプ電極を介して配線基板に相当量の熱が流れることが予想され、放熱経路が完全には独立していない。加えて、配線基板と半導体素子裏面とを夫々接続するため、半導体素子の搭載時に高さの精度が要求されるので工程管理が難しくなる。
【００１８】
このように、従来の三次元実装構造を有する半導体モジュールでは、個々の半導体素子からの放熱経路が独立していないという課題及び低熱抵抗化が十分図られていないという課題がある。例えば、今後普及が進むと考えられている動画対応機能では、ＲＦ回路モジュールが連続して高出力を維持する必要があり、放熱対策はさらに重要な課題となっている。
【００１９】
本発明の課題は、これらの問題点を解決し、三次元実装された半導体素子の放熱経路を独立させ、低抵抗化することが可能な技術を提供することにある。
本発明の前記ならびにその他の課題と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。
【００２０】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。
【００２１】
一方の面に配線と回路部品或いは第１の半導体素子が搭載され、他方の面にキャビティが形成された第１の配線基板の前記キャビティ内に第２の半導体素子或いは回路部品が収容される半導体モジュールにおいて、前記第２の半導体素子は配線を有する第２の配線基板に搭載され、前記第１の配線基板と第２の配線基板は電気的、熱的に接合され、第２の半導体素子から発生した熱をモジュール外部に放熱する放熱経路を前記第２の配線基板に形成する。
【００２２】
また、配線基板の厚さ方向の異なる位置に夫々半導体素子が搭載された半導体モジュールにおいて、許容される温度の上限が小さい半導体素子をモジュールの放熱経路の下流側に配置する、あるいは許容される温度の上限が小さい半導体素子の放熱経路の出口までの熱抵抗が小さくなるよう放熱経路を形成する。
【００２３】
同様の半導体モジュールにおいて、許容される温度または熱抵抗の上限が小さい素子の温度が、他の素子から発生する熱の影響を受けない構造を有する。
【００２４】
上述した本発明によれば、三次元実装構造に関する上述の課題を解決することが可能となる。
以下、本発明の実施の形態を説明する。
なお、実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
【００２５】
【発明の実施の形態】
（実施の形態１）
図１に示す本実施の形態の半導体モジュールの断面構造図を用いて、本発明の基本的な実施形態を説明する。
【００２６】
この半導体モジュールでは、第１の配線基板１には、一方の面に第１の半導体素子２がバンプ電極９を介してフリップチップ実装によってフェイスダウンで固定され、配線基板１の前記一方の面には、半導体素子２の他に抵抗・キャパシタ等の回路部品８が搭載されている。
【００２７】
配線基板１の他方の面には中央部にキャビティが形成され、このキャビティに第２の半導体素子１０を収容し、半導体素子１０はバンプ電極１１を介してフリップチップ実装によって第２の配線基板１３にフェイスダウンで固定されている。
【００２８】
配線基板１は、セラミック或いはガラスエポキシ等の絶縁層４に銅箔等をパターニングした配線５を各層に形成した積層構造の多層配線基板となっている。最上層の配線は、その一端が第１の半導体素子２の接続端子であるパッドとバンプ電極９によって接続されており、配線基板１を貫通するビアホール配線７によって複数層の配線の層間接続を行なっている。
【００２９】
なお、実際には第１の配線基板１、第２の配線基板１３の各層、及び層間を電気的、熱的に接続する配線パターンやビアホール７は多数存在するが、図中では説明に必要なもののみ記載して他は省略してある。
【００３０】
第１の配線基板１では最下層の配線が導電性接合部材１２によって第２の配線基板１３に接続され、この第２の配線基板１３によって半導体モジュールを実装基板に接続する。第２の半導体素子１０は、バンプ電極１１によって第２の配線基板１３に電気的に接続されており、放熱用のバンプ電極１１ａによって配線基板１３に形成された熱拡散板１４と熱的に接続されている。
【００３１】
なお、図１では、第１の配線基板１上面に第１の半導体素子２が１個と回路部品が２個示されており、キャビティ内に１個の第２の半導体素子１０が示されているが、これらの部品数は図に示された数に限定されるものではなく、他の回路部品が搭載されていてもかまわない。また、図示はしないが、バンプ電極９，１１を含む半導体素子２，１０と配線基板１，１３との接続部分及び回路部品８は、夫々がエポキシ樹脂等を用いた封止体で封止され、これらの封止体を含む半導体モジュール全体がキャップによって覆われている。
【００３２】
この半導体モジュールでは、放熱用バンプ電極１１ａと熱拡散板１４とは熱伝導率の高い導電性の材料で形成されており、放熱用のバンプ電極１１ａは、最も発熱の大きな配線系統、例えばバイポーラトランジスタではエミッタ領域と接続する配線、ＦＥＴではゲート配線に接続するのが望ましく、回路構成がエミッタ接地回路である場合には、第２の半導体素子１０の放熱経路を接地用の配線として機能させることができる。
【００３３】
この放熱用バンプ電極１１ａは、図１に示すように、熱通過断面積の大きな単一のはんだバンプで構成してもよいし、複数のはんだバンプを並設して構成してもよいし、銅などの熱伝導率の高い金属部材をはんだ等で接合する構成としても構わない。
【００３４】
本実施の形態の半導体モジュールの放熱経路に関して、先ず第１の半導体素子２からモジュール外部への放熱経路は、第１の半導体素子２の発熱面から、第１の半導体素子２を搭載するためのバンプ電極９、第１の配線基板１とその内部の配線とビアホール配線７を経由して、第１の配線基板１と第２の配線基板１３とを電気的・熱的に接合する導電性接合部材１２、第２の配線基板１３を経由してモジュール外部に至る構成となっている。
【００３５】
これに対し、第２の半導体素子１０からモジュール外部への放熱経路は、第２の半導体素子１０の発熱面、第２の半導体素子１０を搭載するためのバンプ電極１１及び放熱用バンプ電極１１ａ、第２の配線基板１３の熱拡散板１４を経由してモジュール外部に至る構成となっている。
【００３６】
こうした放熱構造により、第１の半導体素子２からの放熱経路と第２の半導体素子１０からの放熱経路を独立させることができることに加えて、図１において第２の半導体素子１０をフェイスダウンで実装し、半導体素子の発熱面からモジュール外部までの距離を短縮することができるため、第２の半導体素子１０の熱抵抗を大幅に低減することが可能である。
【００３７】
この半導体モジュールでは、第１の半導体素子２と第２の半導体素子１０の、設計上の熱抵抗の許容値については、実装構造を調整して、各素子の回路が形成されている発熱面（実装面）からモジュール外の放熱面側までの熱抵抗の小さい位置に熱抵抗の許容値が小さい素子を搭載するのが望ましい。
【００３８】
図１に示す例では、第２の半導体素子１０の熱抵抗を第１の半導体素子２の熱抵抗より低減することが構造的に容易であるため、例えば発熱量が大きい、あるいは温度許容値が低い等の理由で、熱抵抗の許容値の小さい素子を第２の半導体素子１０の位置に搭載することが望ましい。
【００３９】
具体的には、例えば、比較的発熱の少ない制御回路を第１の半導体素子２とし、発熱の多い出力回路を第２の半導体素子１０とする。或いは比較的発熱の少ない増幅器の入力側を第１の半導体素子２とし、発熱の多い増幅器の出力側を第２の半導体素子１０とすることが考えられる。
【００４０】
また、図１に示す半導体モジュールの配線基板１３に形成された熱拡散板１４に替えて、図４に示すように、側面に金属メッキ層を形成した放熱用のビアホールであるサーマルビア１５を複数形成した放熱領域を形成してもよい。
【００４１】
熱拡散板１４を形成した場合と比較して、第２の半導体素子１０で発生した熱が第２の配線基板１３を厚さ方向に熱が通過する際の、熱伝導率の高い領域の断面積が減少するため熱抵抗の低減効果は減少するが、熱拡散板１４と異なりサーマルビア１５は、第２の配線基板１３の製造プロセスに組み込んで作ることができるため、行程数及び部品点数の削減によりコストを低減することができる。
【００４２】
なお、この場合にも、前述したように放熱用バンプ電極１１ａは、図示のように放熱領域を覆う単一のバンプとしても、複数のバンプによって放熱用バンプ電極１１ａの機能を果たす構造としても構わない。また、前述した実施形態では、バンプ電極９，１１を介して半導体素子２，１０がフリップチップ実装される場合を示したが、フリップチップ実装以外の場合にも、本発明を適用することによって同様の効果を期待できる。
【００４３】
例えば、図５に示す例では、第１の半導体素子２が第１の配線基板１に、はんだや導電性金属ペースト等の導電性接合部材３により接合され、ボンディングワイヤ６を介して配線基板１と電気的に接続され、第２の半導体素子１０が第２の配線基板１３に、はんだや導電性金属ペースト等の導電性接合部材１２により接合され、ボンディングワイヤ６を介して配線基板１３と電気的に接続されている。この半導体モジュールでは、第２の半導体素子１０から発生した熱は、導電性接合部材１２、第２の配線基板１３を通してモジュール外部に放熱される。
【００４４】
なお、図１，４に示す例では半導体素子２，１０がバンプ電極９，１１によって発熱の生じる回路形成面を配線基板１，１３側に向けたいわゆるフリップチップ方式で搭載されており、図５に示す例では半導体素子２，１０が導電性接合部材３によって発熱の生じる回路形成面とは反対側を配線基板１，１３に向けて搭載されているが、夫々の搭載方法を混在させても構わない。また、第１の配線基板１と第２の配線基板１３とを接続する導電性接合部材１２は、第１の配線基板１と第２の配線基板１３との間を構造的、電気的、熱的に接続するものであれば、図のようなバンプ形状である必要はなく、例えば異方性導電膜等を用いてもよい。
【００４５】
前述した本発明の実施形態においては、第２の半導体素子１０から生じた熱の放熱経路は、第１の配線基板１を含まず、かつ、第１の半導体素子２から生じた熱の放熱経路は、第２の半導体素子１０の発熱を含まない。即ちそれぞれ独立した放熱経路を形成して、第２の配線基板１３からモジュール外部の例えばマザーボード等の実装基板に放熱される点が重要である。
【００４６】
このため、半導体モジュールの熱設計では、従来の放熱経路が共通な半導体モジュールと比較して、夫々の放熱経路について独立して設計することが可能であり、パラメータが少なくなるためシミュレーションが単純化される。また、一方の半導体素子を変更した場合に他の半導体素子の放熱経路に影響を与えることがないので設計変更が容易である。
【００４７】
なお、熱的には第１の半導体素子２と第２の半導体素子１０とは独立しているが、第２の半導体素子１０と　第１の半導体素子２もしくは回路部品８との間の電気的な信号は、第２の配線基板１３からはんだバンプ等の導電性接合部材１２、第１の配線基板１に形成されたビアホール配線７等を経由して伝達されることになる。
【００４８】
この場合、第１の半導体素子２の接地性或いは放熱性を充分に確保したい場合には、図６に示すように、第１の半導体素子２から第２の配線基板１３の外側までの接地と放熱の機能を強化するサーマルビア７ａと接地配線５ａを形成するのが有効である。但し、図６のサーマルビア７ａ及び接地配線５ａの構造は、十分な放熱性と接地性が確保できれば、必ずしも図の通りである必要はない。
【００４９】
（実施の形態２）
本発明の他の実施形態について、図７を用いて説明する。本実施の形態では配線基板の厚さ方向の異なる位置に配置された複数の半導体素子について、温度の許容値が小さい素子を放熱経路の下流側に配置する、あるいは、温度の許容値が小さい素子の放熱経路の熱抵抗を小さくする。
【００５０】
この実施の形態では、配線基板１６の一方の面にスタック状に半導体素子１７〜２１を導電性接合部材２２によって積層して搭載し、樹脂等の封止体２３で半導体素子１７〜２１をモールドし、配線基板１６の他方の面にアレイ状に外部電極２４を形成したモジュール構造であり、最上層の半導体素子１７で生じた熱の大半は半導体素子１７と配線基板１６との間に位置する他の半導体素子１８〜２１を経由して外部電極２４からモジュール外部に放熱される。このため、例えば最下層の半導体素子２１では、上層の半導体素子１８〜２０で生じた熱が集積されていることになる。
【００５１】
本実施形態では、配線基板１６から離れた位置である上層に実装する半導体素子ほど、半導体素子１７〜２１の発熱量が小さくなるよう機能や利用方法を制御する、あるいは、温度の許容値の高い素子ほど配線基板１６から離れた位置である上層に実装する。
【００５２】
この構成によって、半導体素子１７〜２１の温度上昇を許容値以下に抑えることが可能となる。この構造は、半導体素子１７〜２１の全てもしくは一部がフリップチップ実装されていても、途中にインターポーザーを挿入する構造であっても、前記のように、発熱量或いは温度許容値を基準として、半導体素子１７〜２１の配置を設定することで、半導体素子１７〜２１の温度上昇をすべて許容値以下に抑え、素子の信頼性を向上させることができる。
【００５３】
以上、本発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。
【００５４】
【発明の効果】
本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
【００５５】
本発明により、三次元実装された複数の発熱素子の放熱経路を独立させたため、各素子の熱抵抗を低減し、素子の温度上昇を許容値以下に抑えることができる。また、本発明により、発熱素子である第２の半導体素子が直接モジュール外部のマザーボード等に接続されることがなくなるため、製造プロセス上の信頼性を高めることができる。
【図面の簡単な説明】
【図１】本発明の一実施の形態である半導体モジュールを示す断面構造図である。
【図２】従来の半導体モジュールを示す断面構造図である。
【図３】従来の半導体モジュールを示す断面構造図である。
【図４】本発明の一実施の形態である半導体モジュールの変形例を示す断面構造図である。
【図５】本発明の一実施の形態である半導体モジュールの変形例を示す断面構造図である。
【図６】本発明の一実施の形態である半導体モジュールの変形例を示す断面構造図である。
【図７】本発明の他の実施の形態である半導体モジュールを示す断面構造図である。
【符号の説明】
１，１３…配線基板、２，１０…半導体素子、３，１２…導電性接合部材、４…絶縁層、５，５ａ…配線、６…ボンディングワイヤ、７…ビアホール配線、７ａ，１５…サーマルビア、８…回路部品、９，１１，１１ａ…バンプ電極、１４…熱拡散板、１６…配線基板、１７，１８，１９，２０，２１…半導体素子、２２…導電性接合材、２３…封止体、２４…外部電極。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor module in which a plurality of semiconductor elements are three-dimensionally mounted, and to improve heat radiation characteristics of the mounted semiconductor elements.
[0002]
[Prior art]
Mobile phone terminals, which are mobile communication terminals, have been rapidly miniaturized to meet the demands of users.However, considering the ease of use, miniaturization is naturally limited, and it will not be possible to compare it with current products in the future. Therefore, it is considered that there is no need to greatly reduce the size of the external shape.
[0003]
However, in the field of semiconductor modules such as power amplifier modules for mobile phone terminals, even if the demand for smaller external dimensions has been eased, the number of mounted modules will increase with the advancement of terminal functions, and semiconductor modules will be mounted. Since the area of the mounting board itself, such as a printed circuit board, cannot be expected to be significantly larger than the current situation, more modules must be mounted on a board of the same size as the current product. Because the occupied area tends to be reduced, the size of each module must be reduced.
[0004]
Specifically, for example, in a GSM-based mobile phone terminal widely used in Europe, the United States, and Asia, a plurality of frequency bands such as a 900 MHz band and a 1800 MHz band are used. From the viewpoint of securing, it is required to process signals of a plurality of frequency bands by a single module, particularly for a circuit of a transmission / reception system of a terminal, that is, an RF circuit module. In general, a so-called dual-band compatible module processed by the above-described module will be used. In the future, a data communication function (EDGE: Enhanced Data rates for GSM Evolution) will be provided for a triple band or a triple band capable of supporting other frequency bands. Additional modules are required in the market.
[0005]
FIG. 2 shows an example of a conventionally used semiconductor module. In this semiconductor module, an element is placed on a semiconductor substrate such as single crystal silicon in a central recess formed on one surface of a wiring board 1. The formed semiconductor element 2 is accommodated, and the semiconductor element 2 is fixed to the wiring board 1 by a conductive bonding member 3. The wiring board 1 is a wiring in which an insulating layer 4 such as ceramic or glass epoxy is patterned with copper foil or the like. Are formed in each layer to form a multilayer wiring board having a laminated structure.
[0006]
In the wiring board 1, one end of the uppermost wiring is connected to a pad, which is a connection terminal of the semiconductor element 2, by a bonding wire 6. The connection is made, and the lowermost wiring 5 formed on the other surface of the wiring board 1 becomes an external terminal of the semiconductor module, and this external terminal is connected to the wiring of the mounting board of the product terminal.
[0007]
Further, the back surface of the semiconductor element 2 is thermally connected to one end of a thermal via 7a, which is a via-hole wiring for heat dissipation, by the conductive bonding member 3, and the other end of the thermal via 7a is connected to the lowermost layer of the wiring 5a for heat dissipation. It is connected to the.
[0008]
A circuit component 8 such as a resistor and a capacitor is mounted on the one surface of the wiring board 1 in addition to the semiconductor element 2, and a connection portion between the semiconductor element 2 including the bonding wires 6 and the wiring board 1 and The circuit component 8 is covered and sealed with a sealing body (not shown) using an epoxy resin or the like.
[0009]
In such a conventional structure of a semiconductor module, in response to the above-mentioned conflicting needs for higher functionality of the RF circuit module and size reduction of the module, the size of the mounted circuit components has been reduced by reducing the size of the mounted circuit components. Although there is a trend to reduce the size, it is becoming impossible to cope with the wave of size reduction by itself, and it is becoming difficult to mount all functions within the permitted size.
[0010]
Therefore, a three-dimensional mounting structure in which a cavity is formed on the back surface of a multilayer wiring board, circuit components are mounted on the front surface side, and a semiconductor element is flip-chip mounted on the cavity side is disclosed in, for example, JP-A-2001-44243. A three-dimensional mounting structure in which a heat dissipating element is mounted on the surface side and a semiconductor element is flip-chip mounted or bonded wire mounted on the cavity side is disclosed in, for example, JP-A-7-302866 and JP-A-9-8187. ing.
[0011]
An example in which such a three-dimensional mounting structure is applied to the semiconductor module and semiconductor elements are mounted on both surfaces of the semiconductor substrate 1 is shown in FIG. In this semiconductor module, a first semiconductor element 2 is housed on one surface of a wiring board 1, and the semiconductor element 2 is fixed to the wiring board 1 face down by flip-chip mounting via bump electrodes 9. The second semiconductor element 10 is housed in a central cavity formed on the other surface of the substrate 1, and the semiconductor element 10 is fixed to the wiring substrate 1 face-up by flip-chip mounting via bump electrodes 11. .
[0012]
In the wiring board 1, the wiring in the lowermost layer is an external terminal of the semiconductor module. This external terminal is connected to another wiring board 13 by a conductive bonding member 12, and the second terminal is connected by a similar conductive bonding member 12. The back surface of the semiconductor element 10 is connected to a metal member of the wiring board 13.
[0013]
[Problems to be solved by the invention]
Regarding such a three-dimensional mounting structure, the semiconductor module disclosed in Japanese Patent Application Laid-Open No. 7-302866 has a configuration in which heat generated in a semiconductor element is radiated by radiating fins connected to a surface opposite to the electrodes. However, in mobile phone terminals, the interior of the housing is already occupied mostly by various components and substrates, and the remaining space is small, and in addition, it is difficult to move air trapped inside the housing. Since the heat radiation mechanism connected to the outside of the module is difficult to function, such a heat radiation path cannot be adopted.
[0014]
Further, in the technology disclosed in Japanese Patent Application Laid-Open No. 9-8187, heat generated from the element is radiated to the connection card via the multilayer wiring board, and the allowable temperature is relatively low. When a semiconductor element is mounted, there is a possibility that the allowable value may be exceeded.
[0015]
In particular, when another semiconductor element is mounted on the upper surface of the multilayer wiring board, the semiconductor element mounted on the cavity side receives the influence of heat radiation from the semiconductor element mounted on the upper surface, so that the temperature rise due to heat generation. May increase in width. In order to avoid the influence of heat generated by other semiconductor elements, it is technically required that a semiconductor module having a three-dimensional mounting structure has independent heat radiation paths from individual semiconductor elements.
[0016]
On the other hand, the technology disclosed in Japanese Patent Application Laid-Open No. 2001-44243 is characterized in that a heat radiating member is provided on the side opposite to the mounting surface of the flip-chip mounted semiconductor element. The generated heat is radiated to the motherboard through the heat dissipation member from the back surface of the semiconductor element through the semiconductor substrate of the semiconductor element, so the thermal resistance cannot be sufficiently reduced depending on the material and thickness of the heat dissipation member. There is.
[0017]
Further, since the circuit is formed by flip-chip mounting on the surface on which heat is generated, a considerable amount of heat is expected to flow to the wiring board via the bump electrodes, and the heat radiation paths are not completely independent. In addition, since the wiring board and the back surface of the semiconductor element are connected to each other, height accuracy is required at the time of mounting the semiconductor element, so that process management becomes difficult.
[0018]
As described above, in the semiconductor module having the conventional three-dimensional mounting structure, there are a problem that the heat radiation paths from the individual semiconductor elements are not independent and a problem that the thermal resistance is not sufficiently reduced. For example, in a moving image handling function that is expected to be widely used in the future, it is necessary for the RF circuit module to continuously maintain a high output, and measures for heat dissipation are an even more important issue.
[0019]
It is an object of the present invention to solve these problems and to provide a technology capable of reducing the resistance by making the heat dissipation path of a three-dimensionally mounted semiconductor element independent.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0020]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0021]
A semiconductor in which a wiring and a circuit component or a first semiconductor element are mounted on one surface, and a second semiconductor element or a circuit component is accommodated in the cavity of the first wiring substrate having a cavity formed on the other surface. In the module, the second semiconductor element is mounted on a second wiring board having a wiring, and the first wiring board and the second wiring board are electrically and thermally joined to each other. A heat radiating path for radiating generated heat to the outside of the module is formed in the second wiring board.
[0022]
Further, in a semiconductor module having semiconductor elements mounted at different positions in the thickness direction of the wiring board, a semiconductor element having a small upper limit of allowable temperature is arranged downstream of the heat radiation path of the module, or the allowable temperature is reduced. The heat radiation path is formed so that the heat resistance of the semiconductor element to the exit of the heat radiation path of the semiconductor element having a small upper limit is small.
[0023]
A similar semiconductor module has a structure in which the allowable temperature or the temperature of an element having a small upper limit of thermal resistance is not affected by heat generated from other elements.
[0024]
According to the above-described present invention, it is possible to solve the above-described problem regarding the three-dimensional mounting structure.
Hereinafter, embodiments of the present invention will be described.
In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
A basic embodiment of the present invention will be described with reference to the sectional structural view of the semiconductor module of the present embodiment shown in FIG.
[0026]
In this semiconductor module, the first semiconductor element 2 is fixed face-down on one surface of the first wiring substrate 1 by flip-chip mounting via bump electrodes 9, and is mounted on the one surface of the wiring substrate 1. Is mounted with circuit components 8 such as resistors and capacitors in addition to the semiconductor element 2.
[0027]
A cavity is formed in the center of the other surface of the wiring board 1, and the second semiconductor element 10 is accommodated in the cavity. The semiconductor element 10 is flip-chip mounted via the bump electrode 11 on the second wiring board 13. It is fixed face down.
[0028]
The wiring board 1 is a multilayer wiring board having a laminated structure in which wirings 5 in which an insulating layer 4 of ceramic or glass epoxy or the like is patterned with copper foil or the like are formed in each layer. One end of the uppermost layer wiring is connected to a pad serving as a connection terminal of the first semiconductor element 2 by a bump electrode 9, and a plurality of wiring layers are connected by a via hole wiring 7 penetrating through the wiring board 1. ing.
[0029]
Although there are actually many layers of the first wiring board 1 and the second wiring board 13 and a large number of wiring patterns and via holes 7 for electrically and thermally connecting the layers, they are necessary for explanation in the drawings. Only those are described and others are omitted.
[0030]
In the first wiring board 1, the lowermost wiring is connected to the second wiring board 13 by the conductive bonding member 12, and the semiconductor module is connected to the mounting board by the second wiring board 13. The second semiconductor element 10 is electrically connected to the second wiring board 13 by the bump electrodes 11 and is thermally connected to the heat diffusion plate 14 formed on the wiring board 13 by the heat-dissipating bump electrodes 11a. Have been.
[0031]
In FIG. 1, one first semiconductor element 2 and two circuit components are shown on the upper surface of the first wiring board 1, and one second semiconductor element 10 is shown in the cavity. However, the number of these components is not limited to the number shown in the figure, and other circuit components may be mounted. Although not shown, the connection portions between the semiconductor elements 2 and 10 including the bump electrodes 9 and 11 and the wiring boards 1 and 13 and the circuit components 8 are respectively sealed with a sealing body using epoxy resin or the like. The entire semiconductor module including these sealing bodies is covered with the cap.
[0032]
In this semiconductor module, the heat-dissipating bump electrode 11a and the heat diffusion plate 14 are formed of a conductive material having a high thermal conductivity, and the heat-dissipating bump electrode 11a is formed of a wiring system that generates the most heat, for example, a bipolar transistor. In the case of the FET, it is desirable to connect to the wiring connected to the emitter region, and in the case of the FET, it is preferable to connect to the gate wiring. it can.
[0033]
As shown in FIG. 1, the heat-dissipating bump electrode 11a may be constituted by a single solder bump having a large heat-passing cross-sectional area, or may be constituted by arranging a plurality of solder bumps in parallel. A configuration in which a metal member having high thermal conductivity such as copper is joined by solder or the like may be used.
[0034]
Regarding the heat dissipation path of the semiconductor module of the present embodiment, first, the heat dissipation path from the first semiconductor element 2 to the outside of the module is provided from the heating surface of the first semiconductor element 2 for mounting the first semiconductor element 2. Conductive bonding for electrically and thermally bonding the first wiring board 1 and the second wiring board 13 via the bump electrodes 9, the first wiring board 1, the wiring therein, and the via hole wiring 7. The structure extends to the outside of the module via the member 12 and the second wiring board 13.
[0035]
On the other hand, the heat radiating path from the second semiconductor element 10 to the outside of the module includes a heat generating surface of the second semiconductor element 10, a bump electrode 11 for mounting the second semiconductor element 10, and a heat radiating bump electrode 11a. It is configured to reach the outside of the module via the heat diffusion plate 14 of the second wiring board 13.
[0036]
With such a heat dissipation structure, the heat dissipation path from the first semiconductor element 2 and the heat dissipation path from the second semiconductor element 10 can be made independent, and the second semiconductor element 10 is mounted face down in FIG. However, since the distance from the heating surface of the semiconductor element to the outside of the module can be reduced, the thermal resistance of the second semiconductor element 10 can be significantly reduced.
[0037]
In this semiconductor module, with respect to the allowable value of the thermal resistance in design of the first semiconductor element 2 and the second semiconductor element 10, the mounting structure is adjusted, and the heating surface (where the circuit of each element is formed) is formed. It is desirable to mount an element having a small allowable value of the thermal resistance at a position where the thermal resistance is small from the mounting surface to the heat radiation surface outside the module.
[0038]
In the example shown in FIG. 1, it is structurally easier to reduce the thermal resistance of the second semiconductor element 10 than the thermal resistance of the first semiconductor element 2. It is desirable to mount an element having a small allowable value of the thermal resistance at the position of the second semiconductor element 10 for reasons such as low temperature.
[0039]
Specifically, for example, a control circuit that generates relatively little heat is the first semiconductor element 2, and an output circuit that generates a lot of heat is the second semiconductor element 10. Alternatively, it is conceivable that the input side of the amplifier that generates relatively little heat is the first semiconductor element 2 and the output side of the amplifier that generates much heat is the second semiconductor element 10.
[0040]
In addition, as shown in FIG. 4, a plurality of thermal vias 15 as heat dissipation via holes having a metal plating layer formed on a side surface are provided in place of the heat diffusion plate 14 formed on the wiring board 13 of the semiconductor module shown in FIG. The formed heat radiation area may be formed.
[0041]
As compared with the case where the heat diffusion plate 14 is formed, when the heat generated in the second semiconductor element 10 passes through the second wiring board 13 in the thickness direction, a region having a high thermal conductivity is cut off. Since the area is reduced, the effect of reducing the thermal resistance is reduced. However, unlike the thermal diffusion plate 14, the thermal via 15 can be built in the manufacturing process of the second wiring board 13, so that the number of steps and the number of parts can be reduced. The cost can be reduced by the reduction.
[0042]
Also in this case, as described above, the heat dissipation bump electrode 11a may be a single bump covering the heat dissipation area as shown in the drawing, or may be a structure in which a plurality of bumps fulfill the function of the heat dissipation bump electrode 11a. Absent. In the above-described embodiment, the case where the semiconductor elements 2 and 10 are flip-chip mounted via the bump electrodes 9 and 11 has been described. However, the same applies to cases other than flip-chip mounting by applying the present invention. The effect of can be expected.
[0043]
For example, in the example shown in FIG. 5, the first semiconductor element 2 is joined to the first wiring board 1 by a conductive joining member 3 such as a solder or a conductive metal paste, and The second semiconductor element 10 is electrically connected to the second wiring board 13 by a conductive joining member 12 such as a solder or a conductive metal paste, and electrically connected to the wiring board 13 through the bonding wires 6. Connected. In this semiconductor module, heat generated from the second semiconductor element 10 is radiated to the outside of the module through the conductive bonding member 12 and the second wiring board 13.
[0044]
In the examples shown in FIGS. 1 and 4, the semiconductor elements 2 and 10 are mounted by a so-called flip chip method in which the circuit forming surface where heat is generated by the bump electrodes 9 and 11 is directed toward the wiring boards 1 and 13. In the example shown in FIG. 1, the semiconductor elements 2 and 10 are mounted on the wiring boards 1 and 13 with the side opposite to the circuit forming surface on which heat is generated by the conductive bonding member 3, but the mounting methods may be mixed. I do not care. In addition, the conductive bonding member 12 for connecting the first wiring board 1 and the second wiring board 13 provides a structural, electrical, and thermal connection between the first wiring board 1 and the second wiring board 13. As long as they are electrically connected, the bumps need not be shaped as shown in the figure, and for example, an anisotropic conductive film may be used.
[0045]
In the above-described embodiment of the present invention, the heat radiation path of the heat generated from the second semiconductor element 10 does not include the first wiring board 1 and the heat radiation path of the heat generated from the first semiconductor element 2 Does not include the heat generated by the second semiconductor element 10. In other words, it is important that independent heat radiating paths are formed and the heat is radiated from the second wiring substrate 13 to a mounting substrate such as a motherboard outside the module.
[0046]
Therefore, in the thermal design of a semiconductor module, it is possible to independently design each heat radiation path as compared with a conventional semiconductor module having a common heat radiation path, and the simulation is simplified because the number of parameters is reduced. You. Further, when one semiconductor element is changed, the heat radiation path of the other semiconductor element is not affected, so that the design can be easily changed.
[0047]
Note that the first semiconductor element 2 and the second semiconductor element 10 are thermally independent, but the electrical connection between the second semiconductor element 10 and the first semiconductor element 2 or the circuit component 8 is made. Such a signal is transmitted from the second wiring board 13 via the conductive bonding member 12 such as a solder bump, the via hole wiring 7 formed on the first wiring board 1, and the like.
[0048]
In this case, when it is desired to sufficiently secure the grounding property or the heat radiation property of the first semiconductor element 2, as shown in FIG. 6, the grounding from the first semiconductor element 2 to the outside of the second wiring board 13 is performed. It is effective to form the thermal via 7a and the ground wiring 5a for enhancing the heat radiation function. However, the structure of the thermal via 7a and the ground wiring 5a in FIG. 6 does not necessarily have to be as shown in the figure as long as sufficient heat dissipation and grounding can be ensured.
[0049]
(Embodiment 2)
Another embodiment of the present invention will be described with reference to FIG. In the present embodiment, for a plurality of semiconductor elements arranged at different positions in the thickness direction of the wiring board, an element having a small allowable value of temperature is arranged downstream of the heat radiation path, or an element having a small allowable value of temperature is arranged. The thermal resistance of the heat dissipation path of
[0050]
In this embodiment, the semiconductor elements 17 to 21 are stacked and mounted on one surface of a wiring board 16 by a conductive bonding member 22, and the semiconductor elements 17 to 21 are molded with a sealing body 23 such as a resin. The external electrode 24 is formed in an array on the other surface of the wiring board 16, and most of the heat generated in the uppermost semiconductor element 17 is located between the semiconductor element 17 and the wiring board 16. Heat is radiated from the external electrode 24 to the outside of the module via the other semiconductor elements 18 to 21. Therefore, for example, in the lowermost semiconductor element 21, heat generated in the upper semiconductor elements 18 to 20 is integrated.
[0051]
In the present embodiment, the function and the method of use are controlled so that the amount of heat generated by the semiconductor elements 17 to 21 becomes smaller as the semiconductor element is mounted on an upper layer that is farther away from the wiring board 16, or the temperature tolerance is higher. The element is mounted on an upper layer that is farther away from the wiring board 16 as the element becomes.
[0052]
With this configuration, it is possible to suppress the temperature rise of the semiconductor elements 17 to 21 to an allowable value or less. This structure, whether all or a part of the semiconductor elements 17 to 21 is flip-chip mounted, or a structure in which an interposer is inserted in the middle, as described above, based on the heat generation amount or the allowable temperature value. By setting the arrangement of the semiconductor elements 17 to 21, the temperature rises of the semiconductor elements 17 to 21 can all be suppressed to the allowable values or less, and the reliability of the elements can be improved.
[0053]
As described above, the present invention has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the scope of the invention. It is.
[0054]
【The invention's effect】
The effects obtained by the typical inventions among the inventions disclosed in the present application will be briefly described as follows.
[0055]
According to the present invention, since the heat radiation paths of a plurality of three-dimensionally mounted heating elements are made independent, the thermal resistance of each element can be reduced, and the temperature rise of the element can be suppressed to an allowable value or less. Further, according to the present invention, since the second semiconductor element, which is a heating element, is not directly connected to a motherboard or the like outside the module, reliability in a manufacturing process can be improved.
[Brief description of the drawings]
FIG. 1 is a sectional structural view showing a semiconductor module according to an embodiment of the present invention.
FIG. 2 is a sectional structural view showing a conventional semiconductor module.
FIG. 3 is a sectional structural view showing a conventional semiconductor module.
FIG. 4 is a sectional structural view showing a modification of the semiconductor module according to one embodiment of the present invention;
FIG. 5 is a sectional structural view showing a modification of the semiconductor module according to one embodiment of the present invention;
FIG. 6 is a sectional structural view showing a modification of the semiconductor module according to one embodiment of the present invention;
FIG. 7 is a sectional structural view showing a semiconductor module according to another embodiment of the present invention.
[Explanation of symbols]
1, 13 wiring board, 2, 10 semiconductor element, 3, 12 conductive bonding member, 4 insulating layer, 5, 5a wiring, 6 bonding wire, 7 via hole wiring, 7a, 15 thermal via , 8 ... circuit parts, 9, 11, 11a ... bump electrodes, 14 ... heat diffusion plates, 16 ... wiring boards, 17, 18, 19, 20, 21 ... semiconductor elements, 22 ... conductive bonding materials, 23 ... sealing Body, 24 ... External electrodes.

Claims (7)

一方の面に配線と回路部品或いは第１の半導体素子が搭載され、他方の面にキャビティが形成された第１の配線基板の前記キャビティ内に第２の半導体素子或いは回路部品が収容される半導体モジュールにおいて、前記第２の半導体素子は配線を有する第２の配線基板に搭載され、前記第１の配線基板と第２の配線基板は電気的、熱的に接合され、第２の半導体素子から発生した熱をモジュール外部に放熱する放熱経路を前記第２の配線基板に形成したことを特徴とする半導体モジュール。A semiconductor in which a wiring and a circuit component or a first semiconductor element are mounted on one surface, and a second semiconductor element or a circuit component is accommodated in the cavity of the first wiring substrate having a cavity formed on the other surface. In the module, the second semiconductor element is mounted on a second wiring board having a wiring, and the first wiring board and the second wiring board are electrically and thermally joined to each other. A semiconductor module, wherein a heat radiation path for radiating generated heat to the outside of the module is formed in the second wiring board. 前記第２の半導体素子の発熱損失が前記第１の半導体素子の発熱損失より大きい、もしくは第２の半導体素子に許容される熱抵抗の上限が前記第１の半導体素子に許容される熱抵抗の上限より小さいことを特徴とする請求項１に記載の半導体モジュール。The heat loss of the second semiconductor element is larger than the heat loss of the first semiconductor element, or the upper limit of the heat resistance allowed for the second semiconductor element is the upper limit of the heat resistance allowed for the first semiconductor element. The semiconductor module according to claim 1, wherein the value is smaller than the upper limit. 第１の半導体素子或いは第２の半導体素子の少なくとも何れかがフリップチップ実装されることを特徴とする請求項１又は請求項２に記載の半導体モジュール。3. The semiconductor module according to claim 1, wherein at least one of the first semiconductor element and the second semiconductor element is flip-chip mounted. 4. 前記第２の半導体素子から発生した熱をモジュール外部に放熱するための放熱経路が、第２の半導体素子の接地配線であることを特徴とする請求項１乃至請求項３の何れか一項に記載の半導体モジュール。4. The heat radiation path for radiating heat generated from the second semiconductor element to the outside of the module is a ground wiring of the second semiconductor element, 5. The semiconductor module as described in the above. 配線基板の厚さ方向の異なる位置に夫々半導体素子が搭載された半導体モジュールにおいて、許容される温度の上限が小さい半導体素子をモジュールの放熱経路の下流側に配置する、あるいは許容される温度の上限が小さい半導体素子の放熱経路の出口までの熱抵抗が小さくなるよう放熱経路を形成したことを特徴とする半導体モジュール。In a semiconductor module in which semiconductor elements are mounted at different positions in the thickness direction of the wiring board, a semiconductor element having a small upper limit of allowable temperature is arranged downstream of the heat radiation path of the module, or an upper limit of allowable temperature. A semiconductor module, wherein a heat dissipation path is formed so as to reduce the thermal resistance of the semiconductor element having a small heat dissipation to the exit of the heat dissipation path. 配線基板の厚さ方向の異なる位置に夫々半導体素子が搭載された半導体モジュールにおいて、許容される温度もしくは熱抵抗の上限が小さい素子の温度が、他の素子から発生する熱の影響を受けない構造を有することを特徴とする半導体モジュール。In a semiconductor module in which semiconductor elements are mounted at different positions in the thickness direction of a wiring board, a structure in which the allowable temperature or the temperature of an element having a small upper limit of thermal resistance is not affected by heat generated from other elements. A semiconductor module comprising: 配線基板の厚さ方向の異なる位置に夫々半導体素子が搭載された半導体モジュールにおいて、個々の半導体素子からモジュール外部への放熱経路が実質的に独立していることを特徴とする半導体モジュール。A semiconductor module in which semiconductor elements are mounted at different positions in a thickness direction of a wiring board, wherein a heat radiation path from each semiconductor element to the outside of the module is substantially independent.
JP2002224486A 2002-08-01 2002-08-01 Semiconductor module Pending JP2004071597A (en)

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