JP2004064443A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a semiconductor device having a digital / analog input / output circuit capable of supporting an external digital power supply system of 5 V or 3.3 V.
Kind Code: A1 In a semiconductor device having a digital / analog dual-purpose terminal P1 that serves both as a digital output and an analog output, a digital output circuit CR1 connected to a first power supply voltage and an analog output circuit CR1 connected to a second power supply voltage are provided. An n-channel MOS transistor having a gate connected to the second power supply voltage between the output circuit CR3 and a connection point between the digital / analog shared terminal P1 and the digital output circuit CR1 and the analog output circuit CR3; M9.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device provided with a digital and analog input / output terminal that functions as a digital signal terminal and an analog signal terminal.
[0002]
[Prior art]
2. Description of the Related Art In recent years, integration of LSIs has been advanced, and some terminals have one terminal functioning as a terminal for digital signals and a terminal for analog signals. The terminal functions as a terminal for a digital signal when used in a digital system, and functions as a terminal for an analog signal when used in an analog system. This makes it possible to support both digital and analog systems with a single LSI, eliminating the need to develop an LSI for each system.
[0003]
Further, in order to reduce the gate length of the transistor, reduce power consumption, and reduce noise, the LSI operates at a low power supply voltage. However, the power supply voltage of a semiconductor product outside the LSI is not always the same as that of the LSI, and a power supply voltage of 5 V system semiconductor product and a 3 V system semiconductor product are mixedly mounted on a device board, and a 5 V amplitude is used. May be input to an input / output terminal of a 3V semiconductor product. For this reason, the logic portion inside the LSI is operated at a voltage of 3 V, and the voltage level of the external circuit is adjusted at the interface with the external circuit.
[0004]
A conventional digital / analog I / O circuit of an LSI will be described below with reference to FIG.
[0005]
As shown in FIG. 1, the conventional digital / analog input / output circuit of the LSI includes a digital output circuit CR31, a digital input circuit CR32, an analog output circuit CR33, and a digital / analog shared terminal P3.
[0006]
When the digital / analog input / output circuit is used in a digital system, the digital output circuit CR31 and the digital input circuit CR32 operate, and at this time, the analog output circuit CR33 does not operate. When the digital / analog input / output circuit is used in an analog system, the analog output circuit CR33 operates, and at this time, the digital output circuit CR31 and the digital input circuit CR32 do not operate.
[0007]
The digital output circuit CR31 includes a p-channel MOS transistor (hereinafter simply referred to as “pMOS transistor”) M31, an n-channel MOS transistor (hereinafter simply referred to as “nMOS transistor”) M32, and level converters LC31 and LC32. . The drains of the pMOS transistor M31 and the nMOS transistor M32 are commonly connected to a digital / analog shared terminal P3.
[0008]
In the digital output mode, when the digital output signals DOUT31 and DOUT32 both become "H", the pMOS transistor M31 is turned off and the nMOS transistor M32 is turned on, so that "L" is output to the digital / analog shared terminal P3. . When the digital output signal DOUT31 becomes "H" and the digital output signal DOUT32 becomes "L", both the pMOS transistor M31 and the nMOS transistor M32 are turned off, so that the digital / analog shared terminal P3 enters a high impedance state. When the digital output signals DOUT31 and DOUT32 both become "L", the pMOS transistor M31 is turned on and the nMOS transistor M32 is turned off, so that "H" is output to the digital / analog shared terminal P3.
[0009]
At this time, the voltage level of “H” output to the digital / analog shared terminal P3 is determined by the voltage level of the interface unit power supply VDD-IF connected to the source of the pMOS transistor M31. The interface section power supply VDD-IF is supplied from outside the LSI. Therefore, the voltage level of "H" output to the digital / analog dual-purpose terminal P3 becomes 5V when the circuit outside the LSI operates on the 5V system, and the circuit outside the LSI operates on the 3.3V system. In this case, the voltage is 3.3 V, and the signal level can be adjusted to an external circuit.
[0010]
As the pMOS transistor M31 and the nMOS transistor M32, those having a withstand voltage of 5 V are used according to the case where the voltage outside the LSI is high. Since the digital output signals DOUT31 and DOUT32 from the logic portion inside the LSI are at 3.3V level, the level converters LC31 and LC32 perform level conversion to 5V by driving the gates of the pMOS transistor M31 and the nMOS transistor M32. .
[0011]
In the digital output mode, the analog signal output control signal ACNT3 of the analog output circuit CR33 remains "H", the pMOS transistor M37 is turned off, the nMOS transistor M38 is turned off, and the analog / digital combined terminal P3 is No signal is output.
[0012]
The digital input circuit CR32 includes a complementary MOS inverter including a pMOS transistor M33 and an nMOS transistor M34, an nMOS transistor M35, a pMOS transistor M36, and a level converter LC33. The gates of the pMOS transistor M33 and the nMOS transistor M34 are commonly connected to the digital / analog shared terminal P3, and the drains are commonly connected to the level converter LC33.
[0013]
In order for the digital input circuit CR32 to operate, the condition is that the digital input control signal DCNT3 becomes "H", the nMOS transistor M35 is turned on, and the pMOS transistor M36 is turned off. In the digital output mode, the digital input control signal DCNT3 is set to "L" so that the digital input circuit CR32 does not operate.
[0014]
Next, in the digital input mode, the digital input control signal DCNT3 of the digital input circuit CR32 is set to "H" to operate the digital input circuit CR32. When the digital / analog shared terminal P3 becomes "H", the pMOS transistor M33 is turned off, the nMOS transistor M34 is turned on, and the drains of the pMOS transistor M33 and the nMOS transistor M34 become "L". When the digital / analog shared terminal P3 becomes "L", the pMOS transistor M33 is turned on, the nMOS transistor M34 is turned off, and the drains of the pMOS transistor M33 and the nMOS transistor M34 become "H".
[0015]
At this time, the voltage level of the drains of the pMOS transistor M33 and the nMOS transistor M34 is determined by the voltage level of the interface power supply VDD-IF connected to the source of the pMOS transistor M33.
[0016]
As the pMOS transistor M33 and the nMOS transistor M34, those having a withstand voltage of 5 V are used according to the case where the voltage outside the LSI is high.
[0017]
When the voltage level of the drain of the pMOS transistor M33 and the drain of the nMOS transistor M34 is 5V, the level converter LC33 converts the voltage to 3.3V, and when the voltage level is 3.3V, it propagates as the digital input signal DIN3.
[0018]
Note that the analog signal output control signal ACNT3 of the analog output circuit CR33 remains "H", and no analog signal is output to the digital / analog shared terminal P3. Further, the digital output signal DOUT31 of the digital output circuit CR31 is "H" and the digital output signal DOUT32 is "L", and no digital signal is output.
[0019]
The analog output circuit CR33 includes a transfer gate including a pMOS transistor M37 and an nMOS transistor M38, and an inverter INV3. The drain of the pMOS transistor M37 and the source of the nMOS transistor M38 are connected to the digital / analog shared terminal P3. The analog output signal AOUT3 is input to the source of the pMOS transistor M37 and the drain of the nMOS transistor M38. The inverted signal of the analog signal output control signal ACNT3 input to the gate of the pMOS transistor M37 is input to the gate of M38.
[0020]
When the analog signal output control signal ACNT3 is "H", the pMOS transistor M37 is turned off, the nMOS transistor M38 is turned off, and the digital / analog dual-purpose terminal P3 enters a high impedance state. When the analog signal output control signal ACNT3 becomes "L", the pMOS transistor M37 is turned on, the nMOS transistor M38 is turned on, and the analog output signal AOUT3 is output to the digital / analog shared terminal P3.
[0021]
At this time, since the digital output signal DOUT31 of the digital output circuit CR31 is "H" and the digital output signal DOUT32 is "L", and the pMOS transistor M31 and the nMOS transistor M32 are turned off, no digital signal is output. Further, the digital input control signal DCNT3 of the digital input circuit CR32 is "L", the nMOS transistor M35 is turned off, the pMOS transistor M36 is turned on, and the digital input signal DIN3 is not input.
[0022]
[Problems to be solved by the invention]
The power supply of the digital output circuit, the digital input circuit, and the analog output circuit is common, and the interface power supply VDD-IF is used. The VDD-IF is also used as a power supply for an interface section of another digital circuit in the LSI, and takes in a power supply external to the LSI in order to match a signal level with an external circuit.
[0023]
Since the analog signal is in the range of 0 to 3 V, it is preferable to use a transistor with a withstand voltage of 3 V for the transfer gate that handles the analog signal and to set the power supply voltage supplied to the transistor to 3.3 V. However, when the power supply of the external circuit is a 5 V system, 5 V is commonly supplied to the power supply VDD-IF, so that the power supply of the analog output circuit also becomes 5 V. For this reason, it is necessary to use a transistor having a withstand voltage of 5 V for the transfer gate that handles the analog signal. The thickness of the gate oxide film of the 5V withstand voltage transistor is increased so that the transistor structure can withstand a higher voltage than the 3.3V withstand voltage transistor.
[0024]
As shown in FIG. 6, the characteristics of the transistor having the increased gate oxide film have a high threshold value (Vth), and when the gate is controlled by a 3.3 V signal, the transistor is used particularly as a transfer gate circuit that handles an analog signal. In such a case, the impedance becomes very high, which is not practical.
[0025]
That is, since a transistor having a withstand voltage of 5 V cannot be used as a transfer gate for handling an analog signal in the range of 0 to 3 V, the present LSI can be used only in a system with an external voltage of 3.3 V.
[0026]
SUMMARY OF THE INVENTION It is an object of the present invention to provide an LSI having a digital / analog input / output circuit capable of supporting a 5 V or 3.3 V digital power supply system outside the LSI.
[0027]
[Means for Solving the Problems]
The above-mentioned object is to insert a transfer gate M9 for withstand voltage protection between a common connection point between the digital / analog shared terminal P1 and the digital output circuit CR1 and the analog output circuit, and further to connect a power supply of the digital input / output circuit section. This is achieved by dividing the power supply system of the analog output circuit section. As a result, a digital / analog input / output circuit can be realized that can handle either a 5 V system or a 3.3 V system outside the LSI.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
[First embodiment]
A circuit according to an embodiment of the present invention will be described with reference to FIGS.
[0029]
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 shows source-drain voltage characteristics of an nMOS transistor M9.
[0030]
As shown in FIG. 1, the digital / analog input / output circuit of this embodiment includes a digital output circuit CR1, a digital input circuit CR2, an analog output circuit CR3, and a digital / analog shared terminal P1.
[0031]
When the digital / analog input / output circuit is used in a digital system, the digital output circuit CR1 and the digital input circuit CR2 operate, and the analog output circuit CR3 does not operate at this time. When the digital / analog input / output circuit is used in an analog system, the analog output circuit CR3 operates, and at this time, the digital output circuit CR1 and the digital input circuit CR2 do not operate.
[0032]
The digital output circuit CR1 includes a pMOS transistor M1, an nMOS transistor M2, and level converters LC1 and LC2. The drains of the pMOS transistor M1 and the nMOS transistor M2 are commonly connected to the digital / analog shared terminal P1.
[0033]
In the digital output mode, when the digital output signals DOUT1 and DOUT2 both become "H", the pMOS transistor M1 turns off and the nMOS transistor M2 turns on, so that "L" is output to the digital / analog shared terminal P1. . When the digital output signal DOUT1 becomes "H" and DOUT2 becomes "L", both the pMOS transistor M1 and the nMOS transistor M2 are turned off, so that the digital / analog shared terminal P1 is in a high impedance state. When the digital output signals DOUT1 and DOUT2 both become "L", the pMOS transistor M1 is turned on and the nMOS transistor M2 is turned off, so that "H" is output to the digital / analog shared terminal P1.
[0034]
At this time, the voltage level of "H" output to the digital / analog shared terminal P1 is determined by the voltage level of the digital power supply VDD-D connected to the source of the pMOS transistor M1. The digital power supply VDD-D is supplied from a digital circuit outside the LSI. Therefore, the voltage level of “H” output to the digital / analog dual-purpose terminal P1 is 5 V when the digital circuit outside the LSI is operating in the 5 V system, and the digital circuit outside the LSI is in the 3.3 V system. When operating, the voltage is 3.3 V, and the signal level can be adjusted to an external circuit.
[0035]
As the pMOS transistor M1 and the nMOS transistor M2, those having a withstand voltage of 5 V are used according to the case where the voltage outside the LSI is high. Since the digital output signals DOUT1 and DOUT2 from the logic portion inside the LSI are at 3.3V level, the level converters LC1 and LC2 perform level conversion to 5V by driving the gates of the pMOS transistor M1 and the nMOS transistor M2. .
[0036]
In this digital output mode, the analog signal output control signal ACNT1 of the analog output circuit CR3 remains at "H", the pMOS transistor M7 is turned off, the nMOS transistor M8 is turned off, and the analog / digital combined terminal P1 receives the analog signal. No signal is output.
[0037]
The digital input circuit CR2 includes a complementary MOS inverter including a pMOS transistor M3 and an nMOS transistor M4, an nMOS transistor M5, a pMOS transistor M6, and a level converter LC3. The gates of the pMOS transistor M3 and the nMOS transistor M4 are commonly connected as a digital / analog shared terminal P1, and the drain is commonly connected to the level converter LC3.
[0038]
For the digital input circuit CR2 to operate, the condition is that the digital input control signal DCNT1 becomes "H", the nMOS transistor M5 is turned on, and the pMOS transistor M6 is turned off. In the digital output mode, the digital input control signal DCNT1 is set to "L" so that the digital input circuit CR2 does not operate.
[0039]
Next, in the digital input mode, the digital input control signal DCNT1 of the digital input circuit CR2 is set to “H” to operate the digital input circuit CR2. When the digital / analog shared terminal P1 becomes "H", the pMOS transistor M3 is turned off, the nMOS transistor M4 is turned on, and the drains of the pMOS transistor M3 and the nMOS transistor M4 become "L". When the digital / analog shared terminal P1 becomes "L", the pMOS transistor M3 is turned on, the nMOS transistor M4 is turned off, and the drains of the pMOS transistor M3 and the nMOS transistor M4 become "H".
[0040]
At this time, the voltage level of the drains of the pMOS transistor M3 and the nMOS transistor M4 is determined by the voltage level of the digital power supply VDD-D connected to the source of the pMOS transistor M3.
[0041]
As the pMOS transistor M3 and the nMOS transistor M4, those having a withstand voltage of 5 V are used according to the case where the voltage outside the LSI is high.
[0042]
The level converter LC3 converts the voltage of the drain of the pMOS transistor M3 and the drain of the nMOS transistor M4 to 3.3V when the voltage level is 5V, and propagates the digital input signal DIN1 at the same level when the voltage level is 3.3V.
[0043]
The analog signal output control signal ACNT1 of the analog output circuit CR3 remains at "H", and no analog signal is output to the digital / analog shared terminal P1. The digital output signal DOUT1 of the digital output circuit CR1 is "H" and DOUT2 is "L", and no digital signal is output.
[0044]
The analog output circuit CR3 includes a transfer gate including a pMOS transistor M7 and an nMOS transistor M8, a transfer gate M9 for withstand voltage protection, and an inverter INV1. The analog output signal AOUT1 is input to the source of the pMOS transistor M7 and the drain of the nMOS transistor M8, and the drain of the pMOS transistor M7 and the source of the nMOS transistor M8 are connected to the drain of the transfer gate M9. The source of the transfer gate M9 is connected to the digital / analog shared terminal P1, and the gate is connected to the analog power supply VDD-A. A 3.3 V power supply is supplied to the analog power supply VDD-A from outside the LSI.
[0045]
The inverted signal of the analog signal output control signal ACNT1 input to the gate of the pMOS transistor M7 is input to the gate of the nMOS transistor M8.
[0046]
When the analog signal output control signal ACNT1 is "H", the pMOS transistor M7 is turned off, the nMOS transistor M8 is turned off, and the digital / analog shared terminal P1 enters a high impedance state. When the analog signal output control signal ACNT1 becomes "L", the pMOS transistor M7 is turned on, the nMOS transistor M8 is turned on, and the analog output signal AOUT1 is output to the digital / analog shared terminal P1.
[0047]
At this time, since the digital output signal DOUT1 of the digital output circuit CR1 is "H" and DOUT2 is "L", and the pMOS transistor M1 and the nMOS transistor M2 are turned off, no digital signal is output. Further, the digital input control signal DCNT1 of the digital input circuit CR2 is "L", the nMOS transistor M5 is turned off, the pMOS transistor M6 is turned on, and the digital input signal DIN1 is not input.
[0048]
In this embodiment, the power supply for the analog output circuit and the power supply for the digital input / output circuit are separated. As a result, since a 5V power supply is not used for the transfer gate for analog signals including the pMOS transistor M7 and the nMOS transistor M8, a transistor having a 3V breakdown voltage can be used. Therefore, the problem of impedance when a transistor having a withstand voltage of 5 V is used for the transfer gate for analog signals can be avoided.
[0049]
The transfer gate M9 provided between the transfer gate composed of the pMOS transistor M7 and the nMOS transistor M8 and the digital / analog dual-purpose terminal P1 is used when the digital / analog input / output circuit is used in a digital system. It functions to protect the output circuit CR3.
[0050]
As the transfer gate M9, an nMOS transistor with a withstand voltage of 3V is used, and the gate is connected to a 3.3V power supply.
[0051]
According to FIG. 2A, when the source voltage of the transfer gate M9 rises to around 3.3 V, the voltage on the drain side of M9 is changed from the gate voltage of M9 of 3.3 V to M9 due to the characteristics of the nMOS transistor. Is applied only up to the voltage reduced by the threshold voltage. For example, assuming that the threshold value of M9 is 0.5 V, even if an amplitude signal of 5 V is input to the digital / analog shared terminal P1, the analog transfer gate composed of the pMOS transistor M7 and the nMOS transistor M8 is 3.3V-0. Since only 5V = 2.8V is applied, the destruction of the pMOS transistor M7 and the nMOS transistor M8 can be prevented.
[0052]
FIG. 2B shows the source-drain voltage characteristics of the depletion type nMOS transistor. The depletion type nMOS transistor has a smaller threshold value than the enhancement type nMOS transistor. When this depletion type nMOS transistor is used for the transfer gate M9, when an amplitude signal of 5 V is input to the digital / analog dual-purpose terminal P1, the analog transfer gate including the pMOS transistor M7 and the nMOS transistor M8 has the enhancement type nMOS transistor. Although a higher voltage is applied than at the time, the pMOS transistor M7 and the nMOS transistor M8 can be prevented from being destroyed. FIG. 2B shows a case where the threshold value is 0V.
[0053]
Naturally, even when an amplitude signal of 3.3 V is input to the digital / analog dual-purpose terminal P1, the pMOS transistor M7 and the nMOS transistor M8 can be prevented from being destroyed for the above-described reason.
[0054]
As described above, according to the present embodiment, the transfer gate for withstand voltage protection is inserted between the analog output circuit and the common connection point between the digital / analog dual-purpose terminal and the digital output circuit, and the digital input / output circuit By separating the power supply system of the unit and the power supply system of the analog output circuit unit, it is not necessary to use a transistor having a withstand voltage of 5 V as a transistor of the transfer gate unit that handles an analog signal of 0 to 3 V. This makes it possible to use one terminal for both the input and output of the digital signal and the output of the analog signal.
[0055]
[Second embodiment]
Next, a second embodiment will be described with reference to FIGS.
[0056]
The analog output circuit included in the digital / analog input / output circuit of the second embodiment is a circuit for controlling the gradation of the liquid crystal display panel. The digital output circuit and the digital input circuit are equivalent to those in the first embodiment, and in this embodiment, only the operation as an analog circuit will be described.
[0057]
FIG. 3 is a connection diagram between the LSI of this embodiment and a liquid crystal display panel. In the figure, terminals I / O-0 to I / 0-3 are digital / analog dual-purpose terminals. FIG. 4 is a circuit diagram of the I / 0-1 terminal, which is one of the digital / analog shared terminals I / 0-0 to I / 0-3 in FIG.
[0058]
The display on the liquid crystal panel is normally controlled by four gradation voltages of 3V, 2V, 1V and 0V. 3V generated by dividing the voltage applied to both ends of the liquid crystal panel resistor ladder R1 is connected to the pMOS transistor M11 and the nMOS transistor M12 through a voltage dividing circuit VD. Similarly, voltages 2V, 1V and 0V divided by the gradation voltage resistance ladder R1 are connected to three pairs of pMOS transistors and nMOS transistors through a voltage dividing circuit VD. The gates of the pMOS transistor M11 and the nMOS transistor M12 are controlled by a liquid crystal panel voltage selection signal SEL3 from the voltage selector -VSEL. When the liquid crystal panel voltage selection signal SEL3 becomes "H", the gates of the pMOS transistor M11 and the nMOS transistor M12 are changed. The gate opens, and a 3 V signal is output to the digital / analog dual-purpose terminal I / O-1 through the transfer gate M19. As the transfer gate M19, an nMOS transistor with a withstand voltage of 3 V is used.
[0059]
Similarly, the gates of the pMOS transistor and the nMOS transistor are opened by the SEL2, 1, 0 signals from the voltage selector, and the 2V, 1V, 0V signals are applied to the digital / analog shared terminal I / O-1 through the transfer gate M19. Is output.
[0060]
In this embodiment, the digital / analog dual-purpose terminals I / O-0 to I / O-3 are used for controlling the liquid crystal panel, and thus are used for analog signal output. However, in another system, they function as digital input / output terminals. I do.
[0061]
【The invention's effect】
As described above, according to the present invention, it is possible to provide an LSI having a digital / analog input / output circuit that can handle either a 5 V system or a 3.3 system digital power supply system outside the LSI. This eliminates the need to develop two types of LSIs in accordance with the external power supply voltage, thereby shortening the development period and reducing development costs.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment of the present invention.
FIG. 2 is a diagram showing characteristics of a source / drain voltage of an nMOS transistor.
FIG. 3 is a connection diagram when a liquid crystal panel is controlled in a second embodiment of the present invention.
FIG. 4 is a circuit diagram of a second embodiment of the present invention.
FIG. 5 is a conventional input / output circuit.
FIG. 6 is a diagram showing a resistance value of an analog transfer gate.
[Explanation of symbols]
CR1 ... Digital output circuit
CR2: Digital input circuit
CR3: Analog output circuit
M1, M3, M6, M7, M11, M17 ... pMOS transistors
M2, M4, M5, M8, M12, M18 ... nMOS transistors
M9, M19 ... Transfer gate
LC1, LC2, LC3, LC10, LC11 ... Level converter
P1, I / O-0, I / 0-1, I / O-2, I / O-3 ... Digital / analog shared terminal
TG11, TG12 ... Digital transfer gate
INV1, INV11, INV14 ... Inverter
DOUT1, DOUT2, DOUT11 ... Digital output signal
DIN1, DIN11 ... Digital input signal
DCNT1, DCNT11 ... Digital input control signal
AOUT1 ... Analog output signal
ACNT1 ... analog signal output control signal
SEL1, SEL2, SEL3, SEL4 ... Liquid crystal panel voltage selection signal
VDD-A: Analog power supply
VDD-D: Digital power supply
R1 ... Resistance ladder for liquid crystal panel
VD: voltage dividing circuit
VSEL: Voltage selector
CR31 ... Digital output circuit
CR32: Digital input circuit
CR33: Analog output circuit
M31, M33, M36, M37 ... pMOS transistors
M32, M34, M35, M38 ... nMOS transistors
LC31, LC32, LC33 ... Level converter
P3: Digital / analog shared terminal
INV3… Inverter
DOUT31, DOUT32 ... Digital output signal
DIN3: Digital input signal
DCNT3: Digital input control signal
AOUT3: Analog output signal
ACNT3: Analog signal output control signal
VDD-IF: Interface section power supply

Claims (5)

In a semiconductor device having a digital / analog dual-purpose terminal for both digital output and analog output,
A digital output circuit connected to the first power supply voltage;
An analog output circuit connected to the second power supply voltage;
An n-channel MOS transistor connected between the connection point between the digital / analog shared terminal and the digital output circuit and the analog output circuit and having a gate connected to the second power supply voltage; Semiconductor device. 2. The semiconductor device according to claim 1, wherein the breakdown voltage of the transistor of the analog output circuit and the breakdown voltage of the n-channel MOS transistor are lower than the breakdown voltage of the transistor of the digital output circuit. 3. The semiconductor device according to claim 1, wherein the first power supply voltage is higher than the second power supply voltage. 4. 4. The semiconductor device according to claim 1, wherein said n-channel MOS transistor is a depression type. 5. The semiconductor device according to claim 1, wherein the first power supply voltage and the second power supply voltage are the same voltage.

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