JP2004064053A - Dualdamascene structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a dualdamascene structure without failure in positioning. <P>SOLUTION: A semiconductor chip 20 comprises a substrate, a conductive layer 22, a protective layer 24, a dielectric layer 26, and a trench carved in the dielectric layer. A photo-resist layer 32 is deposited on the surface of the dielectric layer to fill in the trench. A limited aperture 32a is carved through the photo-resist layer approximately on the trench to expose the dielectric layer. A capping layer 34, which reduces the caliber of the aperture to a size within the trench, is deposited on the photo-resist layer. With a mask of the capping layer, the dielectric layer 26 and the protective layer 24 are etched to remove them until the conductive layer is exposed and then a contact hole is formed. The contact hole is filled with metal material to form the dualdamascene structure. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a dual damascene structure, and more particularly to a method of manufacturing a dual damascene structure that avoids misalignment.
[0002]
[Prior art]
The dual damascene process is a method of simultaneously forming a stacked structure in which a metal conductor and a metal plug are vertically arranged in a dielectric layer. The dual damascene structure mainly includes an upper trench and a lower contact hole (via), and is used as a connection between a different device between each layer and a conductor in a semiconductor chip, and furthermore, a surrounding intermediate layer dielectric material. To separate from other devices. As the precision and complexity of integrated circuits develop, how to maintain the yield of the dual damascene structure is an important issue in semiconductor processing.
[0003]
Referring to FIGS. 1 to 3, FIGS. 1 to 3 are explanatory views showing a method of manufacturing a dual damascene structure on a semiconductor chip according to the related art. As shown in FIG. 1, a semiconductor chip 10 includes a substrate 11, a conductive layer 12 formed in the substrate 11, a protective layer 13 sequentially deposited on the surfaces of the substrate 11 and the conductive layer 12, and a first dielectric layer. 14, an etch stop layer 15, a second dielectric layer 16, and a first photoresist layer 17. Further, a first photolithography step is performed to form a plurality of first openings 17 a in the first photoresist layer 17.
[0004]
Subsequently, as shown in FIG. 2, a first etching process is performed to form a plurality of trenches in the second dielectric layer 16 by removing the second dielectric layer 16 not covering the first photoresist layer 17. I do. Then, a second photoresist layer 18 is applied on the second dielectric layer 16, and the plurality of trenches are buried. Subsequently, a second photolithography process is performed, and a plurality of second photoresist layers 18 are formed in the second photoresist layer 18. The second opening 18a is formed. Under ideal circumstances, the second opening 18a is completely within the trench of the second dielectric layer 16. However, when defining the second opening 18a, misalignment may occur due to process technology limitations or other causes, and the second opening 18a may be partially formed outside the trench of the second dielectric layer 16.
[0005]
As shown in FIG. 3, along the second opening 18a, the etch stop layer 15, the first dielectric layer 14, and the protective layer 13 are removed in this order, and the second photoresist layer 18 is further removed to form a dual damascene structure. A metal is buried in the formed dual damascene structure, and a flattening process is performed by a chemical mechanical polishing process, thereby completing the manufacture of the metal conductor 19 and the metal plug 19a.
[0006]
As described above, when forming the second opening 18a in the second photoresist layer 18, misalignment occurs due to a process (for example, a photomask defect or an uneven photoresist thickness). A portion of the second opening 18a is formed outside the trench in the second dielectric layer 16. This condition reduces the contact area between the metal plug 19 and the conductive layer 12, and further increases the resistance of the metal plug 19.
[0007]
[Problems to be solved by the invention]
An object of the present invention is to provide a method for manufacturing a dual damascene structure that avoids misalignment.
[0008]
[Means for Solving the Problems]
Therefore, the present inventor has conducted extensive studies in view of the drawbacks found in the prior art, and as a result, the semiconductor chip is covered on the substrate, the conductive layer provided on the surface of the substrate, and the substrate and the conductive layer. A protective layer, a dielectric layer provided on the protective layer, and a trench formed in a surface layer of the dielectric layer, a photoresist layer filling the trench is formed on a surface of the dielectric layer. Forming a limited opening for exposing the dielectric layer at a position in the photoresist layer substantially corresponding to the opening of the trench, and forming a diameter of the limited opening on the surface of the photoresist layer by a diameter of the trench; Forming a cap layer to reduce the size within the range, etching the dielectric layer and the protective layer until the conductive layer is exposed using the cap layer as a mask, the cap layer and the photoresist layer The present inventors have found that the problem can be solved by a method of forming a dual damascene structure by removing a contact hole having a dual damascene structure, filling a metal material in the contact hole having the dual damascene structure, and forming a dual damascene structure. Based on the above, the present invention has been completed.
[0009]
Hereinafter, the present invention will be described specifically.
[0010]
2. A method for forming a dual damascene structure on a surface of a semiconductor chip according to claim 1, wherein the semiconductor chip includes a substrate, a conductive layer provided on a surface of the substrate, and a conductive layer provided on the substrate and the conductive layer. Forming a photoresist layer on the surface of the dielectric layer, the photoresist layer including a protective layer to cover, a dielectric layer provided on the protective layer, and a trench formed in a surface layer of the dielectric layer. A limited opening that exposes the dielectric layer is formed at a position in the photoresist layer that roughly corresponds to the opening of the trench, and the aperture of the limited opening is formed on the surface of the photoresist layer. Forming a cap layer for reducing the diameter of the cap layer within the range of the diameter, etching the dielectric layer and the protective layer until the conductive layer is exposed using the cap layer as a mask, Removing the Torejisuto layer, a contact hole is formed in a dual damascene structure, embedding a metallic material into the contact hole of the dual damascene structure, forming a dual damascene structure.
[0011]
3. The method according to claim 2, wherein the trench is formed in the photoresist by forming a photoresist layer on a surface of the dielectric layer and performing a photolithography process. Forming an opening defining the location of the substrate, performing an etching process, removing a predetermined depth in the dielectric layer through the opening, forming the trench in the dielectric layer; Remove the layer.
[0012]
According to a third aspect of the present invention, the protective layer in the first aspect is made of silicon nitride.
[0013]
According to a fourth aspect, in the first aspect, the dielectric layer comprises silicon oxide.
[0014]
According to a fifth aspect of the present invention, in the first aspect, the dielectric layer is made of fluorosilicate glass.
[0015]
According to a sixth aspect, in the first aspect, the dielectric layer is made of a dielectric material having a dielectric coefficient lower than 3.
[0016]
The method according to claim 7, wherein the cap layer according to claim 1 is formed by a low-temperature chemical vapor deposition process, and the low-temperature chemical vapor deposition process is performed in a high-density plasma etching apparatus, and the process parameters are: (1) The ratio of carbon to fluorine in the gas (C / F) is greater than or equal to 0.25, (2) the process temperature is lower than 100 ° C., (3) the pressure range is 1 to 100 (m torr). Yes, (4) the source power range is 500-2000 watts, and (5) the bias power range is 0-1200 watts.
[0017]
The method according to claim 8, the gas chosen at a low temperature chemical vapor deposition process in claim _7, the _{C 4 F 8, CF 2 H} 2, C 3 F 8, C 4 F 6 and _C 5 _{F 8} Including.
[0018]
In the method according to the ninth aspect, the gas selected in the low temperature chemical vapor deposition step according to the eighth aspect further includes carbon monoxide and argon.
[0019]
The method according to claim 10, wherein a dual damascene structure is formed on a surface of a semiconductor chip, wherein a substrate provided with a conductive layer, a protective layer, and a dielectric layer in order on the surface is provided. Forming a first photoresist layer on the surface, performing a first photolithography step, forming a first opening defining a position of a trench in the first photoresist layer, performing a first etching step, Removing, through an opening, a predetermined depth in the dielectric layer, forming the trench in the dielectric layer, and thereafter removing the first photoresist layer; Applying a second photoresist layer, further filling the trench, performing a second photolithography step, exposing the dielectric layer at a position in the second photoresist layer generally corresponding to the opening of the trench Forming a second opening, performing a low-temperature chemical vapor deposition process, depositing a cap layer on the inner wall of the second photoresist layer and the second opening, the cap layer is within the diameter range of the trench The diameter of the second opening is reduced, a second etching step is performed, and the dielectric layer and the protective layer are sequentially etched through the second opening until the surface of the conductive layer is exposed, and the cap layer And removing the second photoresist layer, forming a contact hole having a dual damascene structure, and burying a metal layer in the contact hole having the dual damascene structure to form a dual damascene structure.
[0020]
According to a eleventh aspect of the present invention, the protective layer in the tenth aspect is made of silicon nitride.
[0021]
In a twelfth aspect, the dielectric layer in the tenth aspect is made of silicon oxide.
[0022]
A method according to claim 13 wherein the dielectric layer according to claim 10 comprises fluorosilicate glass.
[0023]
According to a fourteenth aspect, in the tenth aspect, the dielectric layer is made of a dielectric material having a dielectric constant lower than 3.
[0024]
In the method according to claim 15, the low temperature chemical vapor deposition step in claim 10 is performed in a high-density plasma etching apparatus, and the process parameters are (1) the ratio of carbon to fluorine in the gas is 0.25. Greater or equal, (2) process temperature below 100 ° C., (3) pressure range from 1 to 100 (m torr), (4) source power range from 500 to 2000 watts, (5) The bias power range is 0-1200 watts.
[0025]
In the method according to a sixteenth aspect, the gas selected in the low-temperature chemical vapor deposition step in the fifteenth aspect is C ₄ F ₈ , CF ₂ H ₂ , C ₃ F ₈ , C ₄ F _6, and C ₅ F ₈ . Including.
[0026]
In the method described in claim 17, the gas selected in the low-temperature chemical vapor deposition step in claim 16 further includes carbon monoxide and argon.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention relates to a method for manufacturing a dual damascene structure, and more particularly to a method for manufacturing a dual damascene structure that avoids misalignment, wherein a semiconductor chip includes a substrate, a conductive layer provided on a surface of the substrate, Including a protective layer overlying a conductive layer, a dielectric layer provided on the protective layer, and a trench formed in a surface layer of the dielectric layer, filling the trench on the surface of the dielectric layer Forming a photoresist layer, forming a limited opening exposing the dielectric layer at a position in the photoresist layer substantially corresponding to the opening of the trench, and forming the limited opening on the surface of the photoresist layer; Forming a cap layer for reducing the diameter to within the diameter range of the trench, and using the cap layer as a mask, exposing the conductive layer to expose the dielectric layer and the protective layer. Forming a dual damascene structure by removing the cap layer and the photoresist layer, forming a contact hole having a dual damascene structure, and embedding a metal material in the contact hole having the dual damascene structure. I do.
[0028]
In order to describe the manufacturing method of such a dual damascene structure in detail, a specific embodiment will be described below with reference to the drawings.
[0029]
【Example】
Referring to FIGS. 4 to 9, FIGS. 4 to 9 are explanatory views showing a method of manufacturing a dual damascene structure on a semiconductor chip according to the present invention. As shown in FIG. 4, the semiconductor chip 20 includes a conductive layer substrate 22, a protective layer 24 formed on the conductive layer substrate 22, and a dielectric layer 26 formed on the protective layer 24. First, a photoresist layer 28 is applied to the surface of the dielectric layer 26, and an opening 28a is formed in the photoresist layer 28 through a photolithography process including procedures such as exposure, development, and cleaning. Define a trench in the structure. In a preferred embodiment according to the present invention, the conductive layer substrate 22 is made of copper and the dielectric layer 26 is made of silicon oxide, fluorosilicate glass (FSG), or a dielectric material having a dielectric constant lower than 3 (for example, SiLK ^™ ). And the protective layer 24 is made of silicon nitride.
[0030]
As shown in FIG. 5, subsequently, an etching process is performed by using a photoresist layer 28 serving as an etching mask, and the dielectric layer 26 is etched along the opening 28a in the photoresist layer 28. A trench 30 is formed therein, after which the photoresist layer 28 is removed. Next, as shown in FIG. 6, a photoresist layer 32 is applied to the surface of the dielectric layer 26, the photoresist layer 32 fills the trench 30, and a photolithography process including procedures such as exposure, development, and cleaning is performed. , An opening 32a is formed in the photoresist layer 32, and the opening 32a is used to define the position of the contact hole of the dual damascene structure, and the diameter of the opening 32a at this time is required in the process. Slightly larger than size.
[0031]
Next, as shown in FIG. 7, a low-temperature chemical vapor deposition process is performed, and a cap layer 34 is deposited on the photoresist layer 32 and the inner wall of the opening 32a, and the opening diameter of the opening 32a is reduced to a size required in the process. Used to reduce to. In a preferred embodiment according to the present invention, the cap layer 34 is a polymer thin film containing carbon and fluorine.
[0032]
Next, as shown in FIG. 8, an etching process is performed using a cap layer 34 serving as an etching mask, the dielectric layer 26 and the protective layer 24 are removed along the opening 32a, and the contact hole 36 is removed. 26 and the protective layer 24. Next, the cap layer 34 and the photoresist layer 32 are removed, and finally a dual damascene structure is completed. Finally, as shown in FIG. 9, a metal layer 38 is embedded in the dual damascene structure, and is further subjected to a full planarization process by a chemical mechanical polishing process. Is completely removed, and the upper end of the metal layer 38 in the dual damascene structure is almost as high as the surface of the dielectric layer 26.
[0033]
The low-temperature chemical vapor deposition process described above is a method based on DiRECT (Dielectric Resolution Enhancement Coating Technology) low-temperature chemical vapor deposition. This low-temperature chemical vapor deposition process is performed in a high-density plasma etching apparatus. The process parameters are such that the ratio of carbon to fluorine in gas (C / F) is greater than or equal to 0.25, and the process temperature is 100 °. C, the pressure range is 1-100 (m torr), the source power range is 500-2000 watts, and the bias power range is 0-1200 watts. Gas chosen in this low-temperature chemical vapor deposition process _{includes C 4 F 8, CF 2 H} 2, C 3 F 8, C 4 F 6 and _C 5 _{F 8,} further comprising carbon monoxide and argon.
[0034]
【The invention's effect】
Compared to the prior art, the present invention forms an opening 32a slightly larger than the opening diameter required in the process by a photolithography process, defines the position of the contact hole in the dual damascene structure, and furthermore, By the phase growth process, the cap layer 34 is deposited on the photoresist layer 32 and the inner wall of the opening 32a, and the diameter of the opening 32a is reduced to a size required in the process. That is, the position of the opening 32a is finely adjusted by the cap layer 34 so that the opening 32a can completely enter the trench 30 of the dielectric layer 26, and the occurrence of misalignment when the contact hole is defined is avoided. Alternatively, the alignment margin in the photolithography process is increased. In addition, in the photolithography process, by defining a contact hole with a relatively large exposure amount, generated scum is reduced, and no misalignment occurs. In addition, since the temperature of the low temperature chemical vapor deposition process is lower than 100 ° C., a thin film can be deposited on the defined photoresist layer 32, and a smaller pattern can be formed on the semiconductor chip, and at the same time, the photolithography can be performed. Do not destroy resist.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a method of manufacturing a dual damascene structure on a semiconductor chip according to a conventional technique.
FIG. 2 is an explanatory view showing a method of manufacturing a dual damascene structure on a semiconductor chip according to a conventional technique.
FIG. 3 is an explanatory view showing a method of manufacturing a dual damascene structure on a semiconductor chip according to a conventional technique.
FIG. 4 is an explanatory view illustrating a method of manufacturing a dual damascene structure on a semiconductor chip according to the present invention.
FIG. 5 is an explanatory view showing a method of manufacturing a dual damascene structure on a semiconductor chip according to the present invention.
FIG. 6 is an explanatory view showing a method of manufacturing a dual damascene structure on a semiconductor chip according to the present invention.
FIG. 7 is an explanatory view illustrating a method of manufacturing a dual damascene structure on a semiconductor chip according to the present invention.
FIG. 8 is an explanatory view illustrating a method of manufacturing a dual damascene structure on a semiconductor chip according to the present invention.
FIG. 9 is an explanatory view showing a method of manufacturing a dual damascene structure on a semiconductor chip according to the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 10 semiconductor chip 11 substrate 12 conductive layer 13 protective layer 14 first dielectric layer 15 etching stop layer 16 second dielectric layer 17 first photoresist layer 17a first opening 18 second photoresist layer 18a second opening 19 metal conductor 19a metal Plug 20 Semiconductor chip 22 Conductive layer substrate 24 Protective layer 26 Dielectric layer 28 Photoresist layer 28a Opening 30 Trench 32 Photoresist layer 32a Opening 34 Cap layer 36 Contact hole 38 Metal layer

Claims (17)

In a method of forming a dual damascene structure on a surface of a semiconductor chip,
The semiconductor chip includes a substrate, a conductive layer provided on a surface of the substrate, a protective layer covering the substrate and the conductive layer, a dielectric layer provided on the protective layer, and a surface of the dielectric layer. A trench formed in the layer;
Forming a photoresist layer filling the trench on the surface of the dielectric layer;
Forming a limited opening exposing the dielectric layer at a position substantially corresponding to the opening of the trench in the photoresist layer;
Forming a cap layer on the surface of the photoresist layer to reduce the diameter of the limited opening within the diameter range of the trench,
Etching the dielectric layer and the protective layer until the conductive layer is exposed using the cap layer as a mask,
Removing the cap layer and the photoresist layer to form a contact hole having a dual damascene structure,
A method comprising burying a metal material in a contact hole of the dual damascene structure to form a dual damascene structure. In the method of forming the trench,
Forming a photoresist layer on the surface of the dielectric layer,
Performing a photolithography process, forming an opening in the photoresist that defines the location of the trench,
Performing an etching process, removing a predetermined depth in the dielectric layer through the opening, forming the trench in the dielectric layer;
The method of claim 1, wherein said photoresist layer is removed. The method of claim 1, wherein said protective layer comprises silicon nitride. The method of claim 1, wherein the dielectric layer comprises silicon oxide. The method of claim 1, wherein the dielectric layer is comprised of fluorosilicate glass. The method of claim 1, wherein the dielectric layer comprises a dielectric material having a dielectric constant less than three. The cap layer is formed by a low-temperature chemical vapor deposition process, and the low-temperature chemical vapor deposition process is performed in a high-density plasma etching apparatus.
(1) the ratio of carbon to fluorine in the gas (C / F) is greater than or equal to 0.25,
(2) the process temperature is lower than 100 ° C.
(3) The pressure range is 1 to 100 (m torr),
(4) the source power range is 500-2000 watts,
The method of claim 1, wherein the bias power range is from 0 to 1200 watts. Gas selected by said cold chemical vapor deposition _process, according to claim 7, characterized in that it comprises a _{C 4 F 8, CF 2 H} 2, C 3 F 8, C 4 F 6 and _C 5 _{F 8} Method. 9. The method according to claim 8, wherein the gas selected in the low temperature chemical vapor deposition step further includes carbon monoxide and argon. In a method of forming a dual damascene structure on a surface of a semiconductor chip,
Providing a substrate on which a conductive layer, a protective layer, and a dielectric layer are sequentially provided on the surface,
Forming a first photoresist layer on the surface of the dielectric layer,
Performing a first photolithography step, forming a first opening defining a location of the trench in the first photoresist layer,
Performing a first etching step, removing a predetermined depth in the dielectric layer through the first opening, forming the trench in the dielectric layer, and thereafter, forming the first photoresist layer And remove
Applying a second photoresist layer on the surface of the dielectric layer, further filling the trench,
Performing a second photolithography step, forming a second opening exposing the dielectric layer at a position in the second photoresist layer approximately corresponding to the opening of the trench,
Performing a low-temperature chemical vapor deposition process, depositing a cap layer on the inner wall of the second photoresist layer and the second opening, and the cap layer reduces the diameter of the second opening within the diameter range of the trench. Let
Performing a second etching step, etching the dielectric layer and the protective layer in order until the surface of the conductive layer is exposed through the second opening,
Removing the cap layer and the second photoresist layer to form a contact hole having a dual damascene structure,
A method of forming a dual damascene structure by burying a metal layer in the contact hole of the dual damascene structure. The method of claim 10, wherein the protective layer is comprised of silicon nitride. The method of claim 10, wherein the dielectric layer comprises silicon oxide. The method of claim 10, wherein the dielectric layer comprises fluorosilicate glass. The method of claim 10, wherein the dielectric layer comprises a dielectric material having a dielectric constant less than three. The low-temperature chemical vapor deposition process is performed in a high-density plasma etching apparatus, and the process parameters include:
(1) the ratio of carbon to fluorine in the gas is greater than or equal to 0.25,
(2) the process temperature is lower than 100 ° C.
(3) The pressure range is 1 to 100 (m torr),
(4) the source power range is 500-2000 watts,
The method of claim 10, wherein the bias power range is 0-1200 watts. Gas selected by said cold chemical vapor deposition _process, according to claim 15, characterized in that it comprises a _{C 4 F 8, CF 2 H} 2, C 3 F 8, C 4 F 6 and _C 5 _{F 8} Method. 17. The method of claim 16, wherein the gas selected in the low temperature chemical vapor deposition step further comprises carbon monoxide and argon.

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