JP2004056363A - Cryptographic processing device and power leveling control method - Google Patents

Abstract

An object of the present invention is to provide a power leveling control method and a cryptographic processing device for reducing power consumption and preventing decryption by measuring power fluctuation.
In a cryptographic processing device including a plurality of hardware, a cryptographic processing device is divided into a plurality of predetermined operation periods based on the operation of the plurality of hardware, and the power required by each hardware in each operation period is reduced. Power detection means for detecting, and the respective hardware based on the power of each hardware detected by the power detection means, and such that the total power of each hardware is the same in the plurality of predetermined operation periods. Power adjusting means for adjusting the power of the wear.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technique for preventing an external process from being decrypted, which is a problem in a cryptographic processing device.
[0002]
[Prior art]
If there is power fluctuation in the processing device including the encryption process, the internal operation status can be determined by measuring the current fluctuation of the device power line. As a result, the encryption algorithm can be decrypted and important information can be stolen. Conventionally, in order to prevent this, for example, as described in Japanese Patent Application Laid-Open No. 2001-5731, a power consuming circuit is provided to prevent the processing pattern from being decoded by generating noise.
[0003]
[Problems to be solved by the invention]
In the conventional method, since power is generated due to noise, the overall power consumption tends to increase, and there is a problem that application to a low-power device is difficult. In addition, when there is a pattern in the noise generation method, there is a problem that the power pattern of the encryption process can be extracted by filtering the noise pattern.
[0004]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and eliminates unnecessary power generation means by suppressing fluctuations in power consumption at all times to reduce power consumption and measure power fluctuations. It is an object of the present invention to provide a power leveling control method and a cryptographic processing device that prevent decryption due to the above.
[0005]
[Means for Solving the Problems]
An encryption device according to the present invention is a cryptographic processing device having a plurality of hardware, wherein the cryptographic device is divided into a plurality of predetermined operation periods based on the operation of the plurality of hardware, and each hardware is required in each operation period. Power detection means for detecting the power to be, based on the power of each hardware detected by the power detection means, and so that the total power of each hardware is the same in the predetermined plurality of operation periods, Power adjusting means for adjusting the power of the respective hardware.
[0006]
In addition, a processor, a cache, a main memory, and a peripheral circuit are provided as the plurality of hardware, and the power detection unit includes a cache miss period, a cache hit period, a peripheral circuit operation as the predetermined plurality of operation periods. Are divided into periods.
[0007]
In addition, a processor and an encryption circuit are provided as the plurality of hardware, and the power detection unit divides the predetermined plurality of operation periods into an operation period of the encryption circuit and a non-operation period of the encryption circuit.
[0008]
The power adjusting means adjusts the power of the hardware by increasing or decreasing a clock frequency.
[0009]
Further, the power adjusting means increases or decreases the clock frequency by thinning out clock pulses.
[0010]
Further, when thinning out the clock pulses, the power adjusting means thins out the high potential and the low potential in a balanced manner.
[0011]
The power adjusting means adjusts the power of the hardware by increasing or decreasing a power supply voltage.
[0012]
The power adjusting means adjusts the power of the hardware by increasing or decreasing a threshold voltage.
[0013]
Further, the power adjusting means includes an adjusting register for adjusting, by the processor, a predetermined clock frequency value used when adjusting the power of the hardware by increasing or decreasing a clock frequency.
[0014]
Further, the power adjusting means includes an adjusting register for adjusting, by the processor, a predetermined voltage value used when adjusting the power of the hardware by increasing or decreasing a power supply voltage.
[0015]
Further, the power detection means detects power required by the respective hardware during the respective operation periods, based on a current value.
[0016]
Further, the power detection means detects power required by the respective hardware during the respective operation periods, based on a voltage value.
[0017]
The power leveling control method according to the present invention is a power leveling control method in a cryptographic processing device including a plurality of hardware, and is divided into a plurality of predetermined operation periods based on the operation of the plurality of hardware, In each operation period, the power required by each hardware is detected, and based on the detected power of each hardware, the total power of each hardware is the same in the predetermined plurality of operation periods. Thus, the power of each of the hardware is adjusted.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is an explanatory diagram illustrating a configuration of the cryptographic processing device according to Embodiment 1 of the present invention. In FIG. 1, 1 is a CPU core, 2 is a main memory, 3 is a peripheral circuit, 4 is a power fluctuation detecting means, 5 is a control means, and 6 is a bus. The CPU core 1 includes a processor 11, a cache controller 12, and a cache memory 13, and the control unit 5 includes a voltage conversion unit 51 and a clock conversion unit 52. In the first embodiment, a case will be described in which encryption processing is performed as a program.
The power fluctuation detecting means 4 corresponds to a power detecting means, and the power fluctuation detecting means 4 and the control means 5 correspond to a power adjusting means.
[0019]
The processor 11 controls the operation and the activation of the peripheral circuit 3 in accordance with the instructions and data stored in the main memory 2. The code required by the processor 11 is temporarily received by the cache controller 12 and checks whether or not the code is included in the cache memory 13. If it is included in the cache memory 13, it is determined to be a cache hit, and the data is extracted from the cache memory 13 and returned to the processor 11. Otherwise, it is retrieved from the main memory 2, returned to the processor 11, and stored in the cache memory 13 in preparation for the next access. Generally, the access performance of the cache memory 13 is high, and if the code required by the processor 11 is stored in the cache memory 13, the processor 11 can process at high speed.
[0020]
On the other hand, the processor 11 manages the operation of the peripheral circuit 3. The processor 11 performs pre-setting necessary for the operation of the peripheral circuit 3 and starts up. The peripheral circuit 3 operates in accordance with the setting, and when the operation is completed, the operation state is left in the register so that the processor 11 can recognize the end of the processing, or an interrupt signal is generated to notify the processor 11.
[0021]
FIG. 2 is an explanatory diagram showing a power transition of a general cryptographic processing apparatus. In the operation of the apparatus described above, the power transitions as shown in FIG. That is, when the processor 11 executes a new program, the cache memory 13 does not initially contain the corresponding code, so that the cache controller 12 determines that a cache miss has occurred and goes to the main memory 2 to retrieve data. During this time, the processor 11 suspends the processing, so that the internal arithmetic circuit does not operate and the access to the cache memory 13 is stopped. Since only the clock and a part of the state machine are operating, the power consumption of the CPU core 1 including the processor 11, the cache controller 12, and the cache memory 13 is low. On the other hand, since the main memory 2 is frequently accessed, the power consumption is high. (Period of cache miss in FIG. 2)
[0022]
After some time, processor 11 will re-execute the previously read code. At this time, if a code remains in the cache memory 13, a high-speed operation is performed as a cache hit. Since the processor 11 and the cache memory 13 operate at high speed, the power consumption of the CPU core increases. On the other hand, since the access frequency of the main memory 2 decreases, the power decreases. (Period of cache hit in Fig. 2)
[0023]
Next, the processor 11 starts a peripheral circuit start-up process. Although the power consumption of the peripheral circuit 3 that has not been operating so far is low, the processing is started by the access from the processor 11, and the power consumption increases. If there is no other processing, the processor 11 periodically accesses the register of the peripheral circuit 3 to monitor the operation status, or stops operating until a completion interrupt of the peripheral circuit 3 itself is generated. At this time, the power consumption of the CPU core 1 and the main memory 2 is low. (Period of peripheral circuit operation in FIG. 2)
[0024]
Generally, since the power of the CPU core 1, the power of the main memory 2, and the power consumption of the peripheral circuit 3 are independent of each other, the total power consumption of the chip changes in each phase of the above operation. That is, there is a danger that the size of the code and the number of loops can be known from the power fluctuation due to the cache miss, and the operation frequency of the cryptographic circuit can be known when performing cryptographic processing as a program due to the power fluctuation during the operation of the peripheral circuit. The surface becomes weak.
[0025]
Therefore, in the first embodiment, the cache hit / miss determination information and the bus information of the cache controller 12 are incorporated into the power fluctuation detecting means 4.
FIG. 3 is an explanatory diagram showing the configuration of the internal circuit of the power fluctuation detecting means 4. The above information is stored in the peripheral circuit power register 42, the CPU power register 43, and the main memory power register 44. Reference numeral 41 denotes an address decoder.
FIG. 4 is an explanatory diagram showing a power transition of the cryptographic processing apparatus according to the first embodiment. In all states of cache miss, cache hit, and peripheral circuit operation, the power value is the CPU core power of the cache hit in FIG. The figure shows a case where the value is adjusted to be a value obtained by adding the value and the main memory power value.
[0026]
The operation will be described with reference to FIGS.
In the case of the above-mentioned initial cache miss, the CPU power register 43 remains set to 1, the main memory power register 44 is set to 1, and the peripheral circuit power register 42 is set to 0. This indicates that the CPU power is intermediate, the main memory power is high, and the power of peripheral circuits is low. The contents of each register are notified to the control means 5. The set information of the main storage power register 44 is notified to the voltage conversion unit 51 as a voltage change notification indicating the large main storage power. Upon receiving the voltage change notification indicating that the main memory power is high, the voltage conversion unit 51 notifies the main memory 2 of a voltage value corresponding to the high main memory power, and increases the power supply voltage of the main memory 2. The set information of the peripheral circuit power register 42 is notified to the clock conversion unit 52 as a peripheral clock change notification indicating that the peripheral circuit power is low. When receiving the peripheral clock change notification indicating that the peripheral circuit power is low, the clock conversion unit 52 notifies the peripheral circuit 3 of the peripheral clock frequency corresponding to the peripheral circuit power low, and stops or reduces the peripheral clock of the peripheral circuit 3. . As described above, as for the chip power, the power consumption of the main memory 2 increases, and the power consumption of the peripheral circuit 3 decreases. The voltage value notified from the voltage conversion means 51 and the peripheral clock frequency notified from the clock conversion means 52 are adjusted in advance so that the total power of the chip becomes a predetermined power value, and set in the voltage conversion means 51 and the clock conversion means 52. Keep it. (Period of cache miss in FIG. 4)
[0027]
Next, at the time of a cache hit, the CPU power register 43 is set to 2, the main memory power register 44 is set to 0, and the peripheral circuit power register 42 remains set to 0. This indicates that the CPU power is high, the main memory power is low, and the peripheral circuit power is low. The contents of each register are similarly notified to the control means 5. The set information of the CPU power register 43 is notified to the clock conversion unit 52 as a CPU clock change notification indicating that the CPU power is high. When receiving the CPU clock change notification indicating that the CPU power is high, the clock conversion unit 52 notifies the CPU core 1 of the CPU clock frequency corresponding to the high CPU power, and increases the frequency of the CPU clock of the CPU core 1. The set information of the main memory power register 44 is notified to the voltage conversion means 51 in the same manner as in the above case, and the power conversion means 51 notifies the main memory 2 of the voltage value corresponding to the low main memory power, and The voltage of the memory 2 is decreased. As described above, as for the chip power, the power consumption of the CPU core 1 increases and the power consumption of the main memory 2 decreases. The voltage value of the voltage converting means 51 and the CPU clock frequency of the clock converting means 52 are adjusted in advance so that the total power of the chip becomes a predetermined power value, that is, the same power value as that of the cache miss period. The voltage conversion means 51 and the clock conversion means 52 are set in advance. (Period of cache hit in FIG. 4)
[0028]
When the peripheral circuit operates, the CPU power register 43 is set to 0, the peripheral circuit power register 42 is set to 1, and the main memory power register 44 remains set to 0. This indicates that the CPU power is low, the main memory power is low, and the peripheral circuit power is high. The contents of each register are similarly notified to the control means 5. The set information of the CPU power register 43 is notified to the clock conversion means 52 in the same manner as described above, and the clock conversion means 52 notifies the CPU core 1 of the CPU clock frequency corresponding to the low CPU power. Stop or reduce the frequency. Further, the set information of the peripheral circuit power register 42 is notified to the clock conversion means 52 as in the above case, and the clock conversion means 52 notifies the peripheral circuit 3 of the peripheral clock frequency corresponding to the large peripheral circuit power, and 3. Increase the frequency of the peripheral clock. As described above, in the chip power, the power consumption of the CPU core 1 decreases, and the power consumption of the peripheral circuit 3 increases. The CPU clock frequency and the peripheral clock frequency of the clock conversion means 52 are adjusted in advance so that the total power of the chip becomes a predetermined power value, that is, the same power value as that during the cache miss period. Set to. (Period of peripheral circuit operation in FIG. 4)
[0029]
As described above, in each of the cache miss period, the cache hit period, and the peripheral circuit operation period, the power required by each of the CPU core 1, the main memory 2, and the peripheral circuit 3 is detected, and the total chip amount is detected. By setting the power to a predetermined power value, it is possible to prevent the decryption by measuring the power fluctuation with low power.
[0030]
In the first embodiment, three values are used as the CPU clock change notification, two values are used as the peripheral clock change notification, and two values are used as the voltage change notification. However, the present invention is not limited to this. The effect of can be obtained.
[0031]
Embodiment 2 FIG.
In the first embodiment, the voltage conversion unit 51 or the clock conversion unit 52 receives a notification from a register such as the peripheral circuit power register 42, and stores the clock frequency or voltage value corresponding to the notification in the CPU core 1 or the main memory. In the second embodiment, the case where the clock frequency or the voltage value to be notified to the CPU core 1 or the like is finely adjusted will be described.
[0032]
As described with reference to FIG. 3, for example, in the case of the peripheral circuit 3, the peripheral clock frequencies corresponding to the large and small peripheral circuit powers are adjusted by the clock conversion means 52 in advance so that the total power of the chip becomes a predetermined power value. The clock conversion means 52 notifies the peripheral circuit 3 of an appropriate peripheral clock frequency based on the notification from the peripheral circuit power register 42. However, in this case, since the peripheral clock frequencies corresponding to the large and small peripheral circuit powers have already been set to certain values in the clock conversion means 52, the total power of the chip has deviated from the predetermined power value due to a change in the operating environment or the like. In such cases, there was a problem that readjustment was difficult.
[0033]
Thus, in the second embodiment, a case will be described in which a clock frequency and a voltage value can be finely adjusted even after a chip is manufactured by providing an adjustment register. FIG. 5 is an explanatory diagram showing a configuration of an internal circuit of the power fluctuation detecting means 4 according to the second embodiment. In FIG. 5, reference numeral 45 denotes an adjustment register including a peripheral circuit change frequency register 45a, a CPU change frequency register 45b, and a main memory change power 45c, and 46 denotes a selector including 46a to 46c. The standard frequencies and standard voltage values input to the selectors 46a to 46c are the same as the values set in advance in the voltage conversion means 51 and the clock conversion means 52 in FIG. 1 of the first embodiment. The other components denoted by the same reference numerals are the same as those in FIG.
[0034]
The operation will be described with reference to FIG. For example, a case where fine adjustment is performed by lowering the peripheral clock when the power of the peripheral circuit is high because the total power of the chip becomes higher than a predetermined power value during the operation of the peripheral circuit will be described. It is assumed that the CPU core 1 monitors whether or not the total power of the chip has deviated from a predetermined power value.
Since the chip total power has become higher than the predetermined power value, the CPU core 1 notifies the peripheral circuit change frequency register 45a of the information that the peripheral clock is reduced when the peripheral circuit power is high. The peripheral circuit change frequency register 45a outputs the change frequency to the selector 46a based on the notification from the CPU core 1. For example, the peripheral circuit change frequency register 45a holds the frequency of plus and minus two steps at a frequency width of αHz, that is, holds the frequencies of −2αHz, −αHz, + αHz, and + 2αHz. Based on this, the change frequency is selected and output to the selector 46a.
[0035]
On the other hand, the set information of the peripheral circuit power register 42 is notified to the selector 46a as a peripheral clock change notification indicating that the peripheral circuit power is high. The selector 46a also receives the standard frequency before the change, and also receives the change frequency from the peripheral circuit change frequency register 45a. The selector 46a uses the input from the peripheral circuit power register 42 and the input from the peripheral circuit change frequency register 45a and the standard frequency to determine the changed frequency including the change of the change frequency with respect to the standard frequency corresponding to the large peripheral circuit power, The clock converter 52 is notified as a peripheral clock change notification. The clock conversion unit 52 notifies the peripheral circuit 3 of the notified frequency after the change, and increases the peripheral clock of the peripheral circuit 3 to the frequency after the change. Other operations are the same as those in the first embodiment, and a description thereof will not be repeated.
[0036]
As described above, a register that holds a plurality of voltage values for fine adjustment is provided, and when the total power of the chip deviates from a predetermined power value, by selecting an appropriate register from among the registers, the total power of the chip is reduced. Even when the power value deviates from the predetermined value, readjustment can be easily performed.
[0037]
In the second embodiment, a case has been described in which the total power of the chip is higher than a predetermined power value during the period of the peripheral circuit operation, so that the peripheral clock when the peripheral circuit power is high and the peripheral clock is reduced to perform the fine adjustment. The same applies to the case where the fine adjustment is made high or the peripheral circuit power is low, and the same effect can be obtained when the clock or voltage value of the CPU core 1 or the main memory 2 is finely adjusted.
[0038]
The power control of the main memory can be performed by changing the threshold voltage in addition to the power supply voltage. In this case, when the main memory power register 44 in the power fluctuation detecting means 4 is set to 1, activation and power increase are performed by lowering the threshold voltage, and deactivation and power reduction are performed by increasing the threshold voltage. be able to.
[0039]
In the second embodiment, the case where the adjustment register 45 is provided in the power fluctuation detecting means 4 has been described. However, the power fluctuation detecting means 4 may be provided separately from the power fluctuation detecting means 4 as shown in FIG. Absent.
[0040]
Embodiment 3 FIG.
In the first embodiment, the case of a cryptographic processing device that performs cryptographic processing as a program has been described. In the third embodiment, a case of a cryptographic processing device including a cryptographic circuit will be described.
[0041]
FIG. 7 is an explanatory diagram illustrating the configuration of the cryptographic processing device according to the third embodiment. In FIG. 7, 11 is a bus, 7 is a CPU core, 8 is a clock oscillator, 9 is control means, and 10 is an encryption circuit. The control means 9 includes a sequence control circuit 91, a thinning control circuit 92, a thinning pattern register 93, and a delay register 94.
Note that the control unit 9 corresponds to a power detection unit and a power adjustment unit.
[0042]
The clock oscillator 8 supplies a basic clock to the control means 9, and the control means 9 supplies a clock to the CPU core 7. The CPU core 7 controls the control means 9 and the encryption circuit 10 via the bus 6.
As in the first embodiment, the operation is performed so that the total chip power is always a predetermined power value.
[0043]
When an operation start of the encryption circuit 10 is instructed by the CPU core 7 via the bus 6, the encryption circuit 10 validates a request signal for starting the encryption processing operation to the sequence control circuit 91. The sequence control circuit 91 that has received the request to start the cryptographic processing operation outputs a permission signal to the cryptographic circuit 10 and, at the same time, instructs the thinning control circuit 92 to lower the clock in order to reduce the power of the CPU core 7, for example, Instruct thinning processing. The thinning control circuit 92 having received the thinning instruction outputs a clock thinned to a predetermined value to the CPU core 7. As a result, the power of the CPU core 7 is reduced to a predetermined value. When ending the encryption processing operation, the encryption circuit 10 invalidates the request signal. The sequence control circuit 91 instructs the thinning control circuit 92 to end the thinning based on the operation of the encryption circuit 10, and the thinning control circuit 92 returns to the clock without thinning.
Note that the thinning control circuit 92 which has received the thinning instruction outputs a clock thinned to a predetermined value to the CPU core 7, and the thinning clock having the predetermined value is adjusted in advance so that the total power of the chip becomes a predetermined power value. Then, it is set in the thinning control circuit 92.
[0044]
As described above, by thinning out the clock of the CPU core based on the request for starting the cryptographic processing operation from the cryptographic circuit, it is possible to prevent decryption at low power and by measuring power fluctuation.
[0045]
In the third embodiment, the case has been described where the thinning-out clock of the predetermined value is adjusted in advance so that the total power of the chip becomes the predetermined power value and set in the thinning-out control circuit 92. As in the case of the second embodiment, a thinning pattern register 93 may be provided to finely adjust the value of the thinning clock.
For example, the values of a plurality of thinning clocks as shown in FIG. 8 are held in the thinning pattern register 93, and the values of the thinning clocks are finely adjusted. Thus, accurate power control can be realized.
[0046]
In the third embodiment, the sequence control circuit 91 outputs a permission signal to the encryption circuit 10 based on the activation request of the encryption processing operation from the encryption circuit 10, and simultaneously performs the clock thinning process to the thinning control circuit 92. Although the case where the instruction is given has been described, the delay register 94 may be provided in consideration of the fall (rise) of the CPU core 7 and the rise (fall) of the encryption circuit 10. Similarly to the above-described fine adjustment of the value of the thinning clock, a combination of the timing of outputting the permission signal to the encryption circuit 10 and the timing of instructing the thinning control circuit 92 to perform the thinning processing of the clock is held in the multiple delay register 94. The instruction timing of the process is finely adjusted so that the total chip power at the time of the falling (rising) of the CPU core 7 and the rising (falling) of the encryption circuit 10 approaches a predetermined voltage value. Thus, accurate power control can be realized.
It is assumed that the CPU core 1 monitors which timing should be selected in order to bring the total power of the chip closer to the predetermined power value.
[0047]
8 is an example in which the clock pulse is extracted at the same ratio as W-4, but the high potential side is maintained during the period in which the clock pulse is extracted. W-4 maintains the low potential side while the clock pulse is removed, but uses the W-4 format and the W-5 format alternately to make the high potential period and low potential period uniform. This has the effect of eliminating the DC component of the clock.
[0048]
Further, in the third embodiment, a case has been described where the clock output to the CPU core 7 is thinned out to a predetermined value in order to reduce the power of the CPU core 7 to a predetermined value. The present invention is not limited to this as long as it can be reduced to a predetermined value, and the same effect can be obtained by performing processing such as lowering the frequency or stopping the clock.
[0049]
Embodiment 4 FIG.
In the third embodiment, the case where the clock of the CPU core 7 is thinned out based on the request for starting the encryption processing operation from the encryption circuit 10 has been described. However, in the fourth embodiment, the CPU core 7 is thinned based on the current value. Will be described.
FIG. 9 is an explanatory diagram illustrating the configuration of the cryptographic processing device according to the fourth embodiment. In FIG. 9, 21 is a power supply terminal, and 22 is a current monitoring circuit. The other components denoted by the same reference numerals are the same as those in FIG.
Note that the current monitoring circuit 22 corresponds to power detection means, and the control means 9 corresponds to power adjustment means.
[0050]
As in the third embodiment, the operation is performed so that the total chip power is always a predetermined power value.
When the encryption processing is started by the encryption circuit 10, the current value becomes higher than before the encryption circuit 10 operates. Therefore, when the current value is monitored by the current monitoring circuit 22 and an excess current is detected, the current monitoring circuit 22 instructs the thinning control circuit 92 to perform a clock thinning process. The thinning control circuit 92 having received the thinning instruction outputs a clock thinned to a predetermined value to the CPU core 7. As a result, the power of the CPU core 7 is reduced to a predetermined value.
Further, when the encryption processing by the encryption circuit 10 is completed, the current value becomes lower than during the operation of the encryption circuit 10. Therefore, when the current value is monitored by the current monitoring circuit 22 and a current value lower than the predetermined current value is detected, the current monitoring circuit 22 instructs the thinning control circuit 92 to return to a clock without thinning. As a result, the power value of the CPU core 7 returns to before the encryption processing by the encryption circuit 10 starts, and the total power of the chip is always kept at the predetermined power value.
[0051]
In addition, a voltage monitoring circuit is provided instead of the current monitoring circuit 22. When the current increases, it is detected that the voltage temporarily drops due to the delay of the power supply circuit, and the CPU clock pulse is thinned out to reduce the total chip amount. The power can always be kept at a predetermined power value.
[0052]
As described above, by thinning out the clock of the CPU core based on the change in the current value or the voltage value, it is possible to prevent decryption at low power and by measuring power fluctuation.
[0053]
As in the third embodiment, by providing the thinning pattern register 93 and finely adjusting the value of the thinning clock, accurate power control can be realized.
[0054]
In the fourth embodiment, a case has been described in which the clock output to the CPU core 7 is thinned out to a predetermined value in order to reduce the power of the CPU core 7 to a predetermined value. The present invention is not limited to this as long as it can be reduced to a predetermined value, and the same effect can be obtained by performing processing such as lowering the frequency or stopping the clock.
[0055]
In the first to fourth embodiments, the cryptographic processing apparatus capable of preventing decryption by measuring power fluctuation has been described. The same effect can be obtained not only in the processing apparatus but also in other apparatuses.
[0056]
【The invention's effect】
As described above, in a cryptographic processing device including a plurality of hardware, the power required by each hardware is divided into a plurality of predetermined operation periods based on the operation of the plurality of hardware. Power detection means for detecting the power of each hardware detected by the power detection means, and so that the total power of each hardware is the same in the predetermined plurality of operation periods, The provision of the power adjusting means for adjusting the power of the hardware has an effect that the decryption can be prevented with low power and by measuring the power fluctuation.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a configuration of a cryptographic processing device according to a first embodiment.
FIG. 2 is an explanatory diagram showing a power transition of a general cryptographic processing device.
FIG. 3 is an explanatory diagram showing a configuration of an internal circuit of the power fluctuation detecting means 4;
FIG. 4 is an explanatory diagram showing a power transition of the cryptographic processing device according to the first embodiment.
FIG. 5 is an explanatory diagram showing a configuration of an internal circuit of a power fluctuation detecting unit 4 according to the second embodiment.
FIG. 6 is an explanatory diagram showing a configuration of a cryptographic processing device according to a second embodiment.
FIG. 7 is an explanatory diagram showing a configuration of a cryptographic processing device according to a third embodiment.
FIG. 8 is an explanatory diagram showing an example of a thinning pattern of a CPU clock.
FIG. 9 is an explanatory diagram showing a configuration of a cryptographic processing device according to a fourth embodiment.
[Explanation of symbols]
1 CPU core
2 Main memory
3 Peripheral circuit
4 Power fluctuation detection means
5 control means
6 bus
7 CPU core
8 Clock oscillator
9 Control means
10 Cryptographic circuit
11 processor
12 Cache controller
13 Cache memory
21 Power supply terminal
22 Current monitoring circuit
41 address decoder
42 Peripheral circuit power register
43 CPU power register
44 Main Memory Power Register
45 Adjustment register
46 Selector
51 Voltage conversion means
52 Clock conversion means
91 Sequence control circuit
92 Thinning-out control circuit
93 Thinning-out pattern register
94 Delay Register

Claims (13)

In a cryptographic processing device having a plurality of hardware,
Power detection means for dividing into a plurality of predetermined operation periods based on the operation of the plurality of hardware, and detecting power required by each hardware in each operation period,
Power for adjusting the power of each hardware based on the power of each hardware detected by the power detection means and so that the total power of each hardware is the same during the predetermined plurality of operation periods An encryption processing device comprising an adjustment unit. As the plurality of hardware, a processor, a cache, a main memory, a peripheral circuit,
2. The cryptographic processing apparatus according to claim 1, wherein the power detection unit divides the predetermined plurality of operation periods into a cache miss period, a cache hit period, and a peripheral circuit operation period. A processor and a cryptographic circuit are provided as the plurality of hardware,
2. The encryption processing device according to claim 1, wherein the power detection unit divides the predetermined plurality of operation periods into an operation period of an encryption circuit and a non-operation period of the encryption circuit. 2. The cryptographic processing apparatus according to claim 1, wherein the power adjusting unit adjusts the power of the hardware by increasing or decreasing a clock frequency. 5. The cryptographic processing apparatus according to claim 4, wherein the power adjusting unit increases or decreases the clock frequency by thinning out clock pulses. 6. The cryptographic processing apparatus according to claim 5, wherein the power adjusting unit balances the high potential and the low potential when thinning out the clock pulse. 2. The cryptographic processing apparatus according to claim 1, wherein the power adjusting unit adjusts the power of the hardware by increasing or decreasing a power supply voltage. 2. The cryptographic processing apparatus according to claim 1, wherein the power adjustment unit adjusts the power of the hardware by increasing or decreasing a threshold voltage. 3. The power adjustment unit according to claim 2, further comprising an adjustment register that adjusts, by the processor, a predetermined clock frequency value used when adjusting the power of the hardware by increasing or decreasing a clock frequency. 3. The encryption processing device according to any one of 3. 4. The power adjustment unit according to claim 2, further comprising an adjustment register that adjusts a predetermined voltage value used when adjusting power of the hardware by increasing or decreasing a power supply voltage by the processor. The cryptographic processing device according to any one of the above. 2. The cryptographic processing apparatus according to claim 1, wherein the power detection unit detects power required by the respective hardware during the respective operation periods based on a current value. 2. The cryptographic processing apparatus according to claim 1, wherein the power detection unit detects power required by the respective hardware during the respective operation periods based on a voltage value. A power leveling control method in a cryptographic processing device having a plurality of hardware,
Dividing into a plurality of predetermined operation periods based on the operation of the plurality of hardware, detecting power required by each hardware in each operation period,
The power of each of the hardware is adjusted based on the detected power of each of the hardware and such that the total power of each of the hardware is the same in the plurality of predetermined operation periods. Power leveling control method.

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