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JP2004055684A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2004055684A
JP2004055684A JP2002208643A JP2002208643A JP2004055684A JP 2004055684 A JP2004055684 A JP 2004055684A JP 2002208643 A JP2002208643 A JP 2002208643A JP 2002208643 A JP2002208643 A JP 2002208643A JP 2004055684 A JP2004055684 A JP 2004055684A
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semiconductor device
metal layer
semiconductor substrate
protective film
semiconductor
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JP4286497B2 (en
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Naohiro Mashino
真篠 直寛
Takashi Kurihara
栗原 孝
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Abstract

【課題】高密度化及び薄型化を意図した半導体装置を製造するにあたり、薄化された半導体基板の取扱いを容易に行えるようにすると共に、その半導体基板のダイシングを短時間で行えるようにする。
【解決手段】半導体装置として分割されるべき各素子形成領域が画定されている側の面に保護フィルム22が貼着された保護フィルム付半導体基板20を治具11〜13に固定保持し、この保護フィルム付半導体基板20の露出している側の全面に金属層23,24を形成した後、レーザにより、金属層23,24の、各素子形成領域を区分けする境界部分に対応する部分を除去し、さらにプラズマエッチング等により、金属層の除去された部分に沿って半導体基板21を各半導体装置30に分割(ダイシング)する。
【選択図】 図4
In manufacturing a semiconductor device intended to have a high density and a low thickness, a thinned semiconductor substrate can be easily handled, and dicing of the semiconductor substrate can be performed in a short time.
SOLUTION: A semiconductor substrate 20 with a protective film having a protective film 22 adhered to the surface on the side where each element formation region to be divided as a semiconductor device is defined is fixed and held on jigs 11 to 13. After the metal layers 23 and 24 are formed on the entire exposed side of the semiconductor substrate 20 with a protective film, a portion of the metal layers 23 and 24 corresponding to a boundary portion separating each element formation region is removed by laser. Then, the semiconductor substrate 21 is divided (diced) into the semiconductor devices 30 along the portion where the metal layer is removed by plasma etching or the like.
[Selection diagram] Fig. 4

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法に係り、特に、LSIチップ等の半導体装置を製造するにあたり薄化されたシリコンウエハ等の半導体基板の取扱いを容易に行うのに有用な技術に関する。
【0002】
【従来の技術】
従来、半導体装置の製造においてその基板として用いられているシリコンウエハは、その厚さが200μm程度以上と比較的厚かったため、その取扱い(めっき加工やスパッタリング、蒸着等による金属層の形成、各チップ単位に分割する処理(「ダイシング」ともいう。)など)も比較的容易であり、また、特定の用途(アンテナ効果を有するシリコンチップ等)に供する場合には、当該チップにシールド機能をもたせるためにシリコンウエハの裏面に金属層を形成した加工も可能であった。
【0003】
その一方で、最近の半導体装置(デバイス)の高密度化及び薄型化の要求に伴い、これに応えるために様々な方法が提案されている。その1つの方法として、例えば、シリコンウエハのそれぞれデバイスとして分割されるべき各領域毎に、所要の深さで穴を明けてこの穴をめっき等により導体で充填し、さらにシリコンウエハの表面に、当該導体に電気的に接続されるように所望のデバイスパターン(回路パターン、配線パターン等を含む)を形成した後、当該デバイスパターンをポリイミド樹脂等からなる絶縁膜で被覆し、次にシリコンウエハの裏面をバックグラインド法等により研磨し、当該ウエハを所定の厚さ(50μm程度)に薄化する一方で、当該導体を露出させた後、当該ウエハを各チップ単位にダイシングして個々のデバイスとする方法がある。この方法では、ダイシングを行う前の段階で、シリコンウエハの裏面(導体が露出している側の面)に金属バンプ等の外部接続端子が接合されたり、あるいは、当該デバイスにシールド機能をもたせるためにシリコンウエハの裏面に金属層が形成されたりする。
【0004】
また、ダイシングを行うに際しては、通常、ダイサー等の機械的な手段が用いられる。
【0005】
【発明が解決しようとする課題】
上述したように従来のシリコンウエハの厚さは比較的厚かったためその取扱いも比較的容易であったが、最近の薄型化の要求に伴いシリコンウエハを薄化する処理が行われるようになってくると、薄化されたシリコンウエハをそのままの状態で取扱うことは、技術的に非常に難しい。薄化されたシリコンウエハの取扱い中にクラックが生じたり、場合によっては割れてしまったり、あるいはシリコンウエハが反ってしまったりするおそれがあるからである。
【0006】
つまり、薄化されたシリコンウエハに損傷を与えることなくその取扱い(めっき加工等による金属層の形成や、各チップ単位のダイシングなど)を行うことが非常に困難であるといった課題があった。
【0007】
また、従来の技術ではダイサー等の機械的な手段によってダイシングを行っていたため、例えばマイクロチップ等のサブミリオーダーの極小デバイスを製造する場合、そのシリコンウエハにおける各デバイス間のダイシング間隔が非常に狭いこともあって、ダイシングを完了するまでに相当の時間がかかり、またコストアップにつながるため、現実的ではなかった。
【0008】
この場合、シリコンウエハの厚さが比較的厚ければ、その厚い分だけダイシングに要する時間が更に長くなるといった不利があり、一方、シリコンウエハが所定の厚さに薄化されていれば、ダイシングの最中にその機械的衝撃によってシリコンウエハにクラックが生じたり、あるいは割れてしまったりするおそれがあるため、ダイシングに際しては細心の注意を必要とし、技術的に難しいといった不利がある。
【0009】
本発明の目的は、上記の従来技術における課題に鑑み、高密度化及び薄型化を意図した半導体装置を製造するにあたり、薄化された半導体基板の取扱いを容易に行えるようにすると共に、その半導体基板のダイシングを短時間で行えるようにすることにある。
【0010】
【課題を解決するための手段】
上記の従来技術の課題を解決するため、本発明の一形態によれば、半導体基板のそれぞれ半導体装置として分割されるべき各素子形成領域が画定されている側の面に保護フィルムが貼着された保護フィルム付半導体基板を、該保護フィルムが貼着されている側と反対側の面のみを露出させて治具に固定保持する工程と、前記治具によって固定保持された保護フィルム付半導体基板の露出している側の全面に金属層を形成する工程と、レーザにより、前記金属層の、前記各素子形成領域を区分けする境界部分に対応する部分を除去する工程と、ドライエッチング又はウエットエッチングにより、前記金属層の除去された部分に沿って前記半導体基板をそれぞれ1つの素子形成領域が含まれるように各半導体装置に分割する工程とを含むことを特徴とする半導体装置の製造方法が提供される。
【0011】
この形態に係る半導体装置の製造方法によれば、半導体基板の取扱い(裏面への金属層の形成や、各半導体装置(チップ)単位のダイシングなど)を行うに先立ち、半導体基板の各素子形成領域が画定されている側の面を保護フィルムで覆った保護フィルム付半導体基板を治具に固定保持しているので、その半導体基板が所定の厚さに薄化されている場合でも、その薄化された半導体基板に損傷を与えることなくその取扱いを容易に行うことができる。
【0012】
また、各半導体装置(チップ)単位のダイシングを、従来の技術において用いられていたようなダイサー等の機械的な手段ではなく、レーザによって除去されていない部分(つまり、各チップ単位に分割されるべき各素子形成領域に対応する部分)の金属層をエッチングレジストとして用いたドライエッチングによって行っているので、短時間で一括ダイシングを行うことが可能となる。
【0013】
このように、薄化された半導体基板を短時間で一括ダイシングすることが可能になることで、マイクロチップなど今後の新しい半導体チップ製造技術に拍車がかかることが期待される。
【0014】
また、本発明の他の形態によれば、上述した形態に係る半導体装置の製造方法において、前記レーザにより前記金属層の所定の部分を除去する工程及び前記ドライエッチング又はウエットエッチングにより前記半導体基板を各半導体装置に分割する工程に代えて、レーザにより、前記金属層の、前記各素子形成領域を区分けする境界部分に対応する部分を除去し、さらに、該金属層の除去された部分に沿って前記半導体基板をそれぞれ1つの素子形成領域が含まれるように各半導体装置に分割する工程を含むことを特徴とする半導体装置の製造方法が提供される。
【0015】
この形態に係る半導体装置の製造方法によれば、上記の形態に係る半導体装置の製造方法によって得られた効果に加えて、更に、金属層の所定の部分を除去する処理と半導体基板のダイシング処理を1回の工程で行うようにしているので、プロセスの簡素化を図ることができる。
【0016】
また、本発明の更に他の形態によれば、上述した各形態に係る半導体装置の製造方法において、前記半導体基板を各半導体装置に分割する工程の後に、レーザにより、各半導体装置の露出している各金属層をそれぞれ所要の回路素子の形状にパターニングする工程を含むことを特徴とする半導体装置の製造方法が提供される。
【0017】
この形態に係る半導体装置の製造方法によれば、上記の各形態に係る半導体装置の製造方法によって得られた効果に加えて、更に、ダイシングを行った後にレーザにより各半導体装置の金属層をそれぞれ所要の形状にパターニングするようにしているので、パターニングする形状に応じてインダクタンスやアンテナ等として利用することができる。このことは、各半導体装置内に形成されるパターン面積を減らすことにつながる。
【0018】
さらに、本発明の他の形態によれば、上述した各形態に係る半導体装置の製造方法によって製造されたことを特徴とする半導体装置が提供される。
【0019】
【発明の実施の形態】
図1は本発明に係る半導体装置の製造方法を実施する際に使用する治具の一構成例を模式的に示したものである。
【0020】
図示のように、治具10は、処理対象物を載せて保持する下側パーツ11と、この下側パーツ11と協働して処理対象物を上方から押えて保持する上側パーツ12と、処理対象物を挟み込んで保持する両パーツ11,12をその周面方向から固定する治具クランプ13とから構成されている(図1(c)参照)。
【0021】
ここでいう処理対象物とは、後述するように、シリコンウエハ21(図中、破線で示す部分)の回路パターン、配線パターン等のデバイスパターンが作り込まれている側の面(すなわち、最終的に半導体装置(チップ)として分割されるべき各々の素子形成領域が画定されている側の面)に保護フィルムを貼着したもの(以下、便宜上、「保護フィルム付ウエハ」という。)を指す。
【0022】
下側パーツ11及び上側パーツ12は、それぞれステンレス鋼(SUS)等からなり、各々の表面はテフロン[登録商標]加工されている。下側パーツ11は、図1(a)に示すように円形状に成形されており、その周面に沿って近傍にシリコーンゴムやテフロン等からなるパッキンP1がリング状に配設されている。このパッキンP1(リング)の大きさは、シリコンウエハ21のサイズよりも若干大きめに選定されている。一方、上側パーツ12は、図1(b)に示すようにリング状に成形されており、そのリングの外径は下側パーツ11の外径と同じであり、またリングの内径によって画定される開口部の大きさは、シリコンウエハ21のサイズよりも小さめに選定されている。さらに、上側パーツ12の内周面に沿って近傍に同様の材料からなるパッキンP2がリング状に配設されている。
【0023】
このように構成された治具10(11〜13)に保護フィルム付ウエハをセットする方法について、図2を参照しながら説明する。
【0024】
先ず、図2(a)に示すように、下側パーツ11のパッキンP1が形成されている側の面に粘着剤(図示せず)を塗布し、保護フィルム付ウエハ20の保護フィルム22が貼着されている側の面を下にして、粘着剤により下側パーツ11の所定の位置に保護フィルム付ウエハ20を固定化する。このように粘着剤を使用して保護フィルム付ウエハ20を固定化することで、保護フィルム付ウエハ20の両面(シリコンウエハ21側と保護フィルム22側)の熱膨張係数の違いに起因して当該ウエハが反ってしまう可能性を排除することができる。
【0025】
次に、上側パーツ12のパッキンP2がシリコンウエハ21の周面に当接し、かつ、下側パーツ11のパッキンP1が上側パーツ12の周面に当接するように両パーツ11,12の位置合せを行った後、保護フィルム付ウエハ20を保持した両パーツ11,12を周面方向から挟み込むようにして複数個(図2(b)の例示では4個)の治具クランプ13で堅固に固定保持する。これによって、保護フィルム付ウエハ20は、シリコンウエハ21の裏面(デバイスパターンが作り込まれている側の面と反対側の面)のみが外部に露出する。つまり、保護フィルム付ウエハ20は、そのシリコンウエハ21の裏面を除き、両パーツ11,12の各パッキンP1,P2によって外部から気密封止されたことになる。
【0026】
以下、第1の実施形態に係る半導体装置の製造方法について、その製造工程を順に示す図3及び図4を参照しながら説明する。
【0027】
先ず最初の工程では(図3(a)参照)、50μm程度の厚さに薄化されたシリコンウエハ21のデバイスパターンが作り込まれている側の面(図示の例では下側の面)に、厚さが100μm〜1mm程度の保護フィルム22を貼着した保護フィルム付ウエハ20を、図2を参照して説明した方法により治具11〜13にセットする。
【0028】
保護フィルム22には、例えば、エポキシ樹脂やポリイミド樹脂等からなる樹脂フィルム、あるいはPET(ポリエチレンテレフタレート)等のプラスチックフィルムなどで構成されるシート状の支持体の片面に、アクリル系、ゴム系などの粘着剤(未硬化状態にある樹脂)を塗布したものが用いられる。あるいは、保護フィルム22の別の形態として、100μm〜300μm程度の比較的厚いシリコンウエハをバックグラインド法等の機械研磨によって薄化する際にシリコンウエハを保護するためにその片面(研磨される側と反対側の面)に貼着されるバックグラインド保護テープ(以下、「BGテープ」ともいう。)をそのまま用いてもよい。
【0029】
この保護フィルム22は、薄化されたシリコンウエハ21の本工程以降での取扱いを行い易くするためのものであり、また、取扱い中のシリコンウエハ21の破損を防ぐためのものである。
【0030】
次の工程では(図3(b)参照)、保護フィルム付ウエハ20の露出しているシリコンウエハ21の裏面に、無電解めっきにより、金属層23を形成する。
【0031】
すなわち、図示のようにめっき槽41に無電解ニッケル(Ni)めっき液42(Niイオンと還元剤を含む溶液)を入れたものを用意し、前の工程で治具11〜13にセットされた保護フィルム付ウエハ20をめっき槽41中に浸漬し、無電解Niめっき液42の中で酸化還元反応を起こさせ、還元剤が酸化されると同時にNiイオンがNiに還元されるようにして、Niをシリコンウエハ21の裏面上に析出させることで、無電解Niめっき層(金属層23)を厚さ0.2μm〜0.4μm程度に形成する。無電解Niめっき液42としては、例えば、メルテックス社製の無電解Niめっき液:メルプレートNI−867が好適に用いられる。
【0032】
なお、この無電解Niめっき層23は、下地のシリコン(Si)ウエハ21と次の工程で形成する金属層との密着性を高めるために形成されるものである。
【0033】
金属層23(無電解Niめっき層)を形成した後、保護フィルム付ウエハ20を治具にセットした状態でめっき槽41から取り出す。
【0034】
次の工程では(図3(c)参照)、前の工程で形成された金属層23(無電解Niめっき層)上に、無電解めっきにより、さらに金属層24を形成する。この金属層24の形成は、下地層の金属(この場合、Ni)との置換による「置換めっき」処理によって行う。
【0035】
すなわち、図示のようにめっき槽43に無電解金(Au)めっき液44(Auイオンと還元剤を含む溶液)を入れたものを用意し、前の工程で保護フィルム付ウエハ20のシリコンウエハ21の裏面に無電解Niめっき層23を形成したものをめっき槽43中に浸漬し、下地金属イオン(Niイオン)が酸化溶解するのと交換に、無電解Auめっき液44中のAuイオンがAuに還元されるようにして、Auを無電解Niめっき層23上に析出させることで、無電解Auめっき層(金属層24)をごく薄く(0.05μm以下に)形成する。無電解Auめっき液44としては、例えば、メルテックス社製の無電解Auめっき液:メルプレートAU−601が好適に用いられる。
【0036】
なお、この無電解Auめっき層24は、シリコンウエハ21の裏面に形成する金属層(Ni/Au)全体としての電気抵抗を下げるために形成されるものである。
【0037】
また、本工程では0.05μm以下のごく薄い金属層24(無電解Auめっき層)を置換めっき処理によって形成しているが、さらに厚く形成する場合には、別途、図3(c)の工程で行ったような無電解Auめっき処理を施す。
【0038】
金属層24(無電解Auめっき層)を形成した後、保護フィルム付ウエハ20を治具にセットした状態でめっき槽43から取り出す。
【0039】
次の工程では(図4(a)参照)、レーザによるトリミングにより、2層構造の金属層(無電解Niめっき層23/無電解Auめっき層24)のパターニングを行う。すなわち、レーザにより、金属層23,24の所定の部分を除去する。この除去すべき所定の部分は、最終的に半導体装置(チップ)として分割されるべきシリコンウエハ21の各素子形成領域を区分けする境界部分に対応する部分(図6(b)においてSPで示す部分)である。レーザとしては、例えばUV−YAGレーザ、エキシマレーザ等が用いられる。
【0040】
次の工程では(図4(b)参照)、ドライエッチング(本実施形態ではプラズマエッチング)により、前の工程で除去された金属層23,24の所定の部分、すなわち各素子形成領域を区分けする境界部分に沿ってシリコンウエハ21をそれぞれ1つの素子形成領域が含まれるように個々の半導体装置(チップ)単位に分割する(ダイシング)。プラズマ放電に供するガスとしては、主として酸素(O2 )、窒素(N2 )、水素(H2 )等が用いられるが、エッチングレートを上げるためには、上記のガスにCF4 、SF6 等の反応性ガスを混合したものが用いられる。
【0041】
これによって、各半導体装置(チップ)が保護フィルム22に貼着された状態で分離されたことになる。
【0042】
なお、本工程では各半導体装置単位のダイシングをプラズマエッチングによって行っているが、このプラズマエッチング以外にも、例えばアルゴン(Ar)イオン等のイオンビームを用いたエッチング(イオンビームエッチング)によってダイシングを行うことも可能である。あるいは、かかるドライエッチングに代えて、酸、アルカリ、有機溶剤などの溶液を用いたウエットエッチングによってダイシングを行うことも可能である。
【0043】
この場合、留意すべき点は、各半導体装置単位のダイシングを行うにあたり、各半導体装置を保持している保護フィルム22が分割される前に(つまり、保護フィルム22が完全に切断された状態となる前の段階で)、プラズマエッチング等の処理を終了させることである。
【0044】
本工程の後、各半導体装置単位にダイシングされた保護フィルム付ウエハ20を、治具11〜13から取り外す。
【0045】
最後の工程では(図4(c)参照)、各半導体装置単位にダイシングされた保護フィルム付ウエハ20から保護フィルム22を剥離する。つまり、保護フィルム22から各半導体装置(チップ)30を取り外す。各々の半導体装置30は、それぞれ対応する素子形成領域を含むシリコン基板21aと、このシリコン基板21aの裏面に形成されたNi/Auの金属層23a,24aとから構成されている。なお、シリコンウエハの周囲部分から作製された半導体装置(図中、31で示す部分)については、不良チップとして取り除く。
【0046】
以上説明したように、第1の実施形態に係る半導体装置の製造方法によれば、薄化されたシリコンウエハ21の取扱い(ウエハの裏面への金属層23,24の形成や、各半導体装置(チップ)30単位のダイシングなど)を行うに先立ち、図3(a)に示したようにシリコンウエハ21のデバイスパターンが作り込まれている側の面を保護フィルム22で覆った保護フィルム付ウエハ20を治具11〜13に固定保持しているので、その薄化されたシリコンウエハ21に損傷を与えることなくその取扱いを容易に行うことができる。
【0047】
また、各半導体装置(チップ)30単位のダイシングを、従来の技術において用いられていたようなダイサー等の機械的な手段ではなく、図4(a),(b)に示したようにレーザトリミングによって除去されていない部分(各チップ単位に分割されるべき各素子形成領域に対応する部分)の金属層23,24をエッチングレジストとして用いたプラズマエッチングによって行っているので、短時間で大量に一括ダイシングを行うことが可能となる。このように、薄化されたシリコンウエハ21の大量一括ダイシングが可能になることで、マイクロチップなど今後の新しいシリコンチップ製造技術に拍車がかかることが期待される。
【0048】
また、プラズマエッチングによってダイシングを行っているので、従来の機械的な手段によるダイシングでは行うことができなかった、曲線状のダイシング加工も可能となる。
【0049】
また、保護フィルム22として、シリコンウエハの薄化時に用いるバックグラインド保護テープ(BGテープ)を剥がさずにそのまま用いた場合には、シリコンウエハ21に新たに保護フィルムを貼着する必要が無くなるので、プロセスの簡素化を図ることができる。
【0050】
また、シリコンウエハ21の裏面に金属層23,24が存在することで、例えばアンテナ効果を有するシリコンチップ等に供する場合には、当該チップにシールド機能を持たせることができる。
【0051】
また、レーザトリミングによって金属層23,24のパターニング(金属層23,24の所定の部分の除去)を行っているので、従来の技術において用いられていたようなパターニング用のレジスト(ドライフィルム等)を使用する必要が無くなり、またレジストの剥離を行う必要も無くなる。これによって、プロセスの簡素化を図ることができ、また、従来用いられていたようなレジスト剥離液によるBGテープへの損傷を無くすことができる。
【0052】
さらに、保護フィルム付ウエハ20を治具11〜13に固定保持することで、無電解めっき処理(図3(b),(c)参照)を行う際のめっき液42,44中での揺動等にも耐えることができる。
【0053】
また、従来の技術ではシリコンウエハに金属層を形成するのに蒸着やスパッタリング等を行っており、このような処理は処理室内から空気を抜いて真空状態を維持しながら行われるため、このとき、シリコンウエハに貼着されたBGテープから好ましくないガスが発生する。
【0054】
これに対し本実施形態では、無電解めっき処理(図3(b),(c)参照)によって金属層23,24を形成しており、しかも、保護フィルム22(BGテープ)は治具の各パーツ11,12のパッキンP1,P2によってめっき液42,44から完全に遮断されているので、この保護フィルム22(BGテープ)からガスが発生するのを防止することができる。
【0055】
次に、第2の実施形態に係る半導体装置の製造方法について、その製造工程の一部を示す図5を参照しながら説明する。
【0056】
この第2の実施形態に係る半導体装置の製造方法は、第1の実施形態に係る半導体装置の製造方法(図3,図4)と比べて、図4(a)及び(b)の工程で行った処理に代えて、図5(a)に示すようにレーザ(UV−YAGレーザ、エキシマレーザ等)により、金属層23,24の所定の部分(シリコンウエハ21の各素子形成領域を区分けする境界部分に対応する部分)を除去し、さらに当該レーザにより、金属層23,24の除去された部分に沿ってシリコンウエハ21をそれぞれ1つの素子形成領域が含まれるように個々の半導体装置(チップ)単位にダイシングするようにした点で相違する。他の工程については、第1の実施形態の場合と同じであるので、その説明は省略する。
【0057】
このように本実施形態に係る半導体装置の製造方法は、金属層23,24のパターニング処理とシリコンウエハ21のダイシング処理とを1回の工程で行うようにしたことを特徴とする。
【0058】
この第2の実施形態に係る半導体装置の製造方法によれば、第1の実施形態において得られた効果に加えて、更に、金属層23,24のパターニング処理及びシリコンウエハ21のダイシング処理を1回の工程(図5(a)参照)で行うようにしているので、プロセスの簡素化を図ることができる。
【0059】
更に、シリコンウエハ21の裏面に金属層23,24が形成されているので、レーザによるダイシングの際に、レーザによる熱を金属層23,24を介して有効に放散することができ、これによって、シリコンウエハ21の回路への熱によるダメージを防止することができる。
【0060】
次に、第3の実施形態に係る半導体装置の製造方法について、図6を参照しながら説明する。
【0061】
図6において、(a)は本実施形態に係る半導体装置の製造工程の一部を示したものであり、(b)は(a)の工程において形成されるパターンの一例を模式的に示したものである。
【0062】
この第3の実施形態に係る半導体装置の製造方法は、第1,第2の実施形態に係る半導体装置の製造方法(図3,図4,図5)と比べて、図4(b)の工程と図4(c)の工程の間、又は図5(a)の工程と図5(b)の工程の間に、図6(a)に示すようにレーザ(UV−YAGレーザ、エキシマレーザ等)によるトリミングにより、ダイシング後の各半導体装置の金属層23,24を所要の形状にパターニングする処理を追加した点で相違する。他の工程については、第1,第2の実施形態の場合と同じであるので、その説明は省略する。
【0063】
このように本実施形態に係る半導体装置の製造方法は、シリコンウエハ21のダイシングを行った後に各半導体装置(チップ)の金属層23,24を所要の回路素子(図6(b)においてEPで示す部分)の形状にパターニングするようにしたことを特徴とする。パターニングされる回路素子としては、図6(b)に示すようなコイル状のインダクタンス素子EPの他に、アンテナやSAWフィルタなどがある。なお、SPは、最終的に各チップ単位に分割されるべきシリコンウエハ21の各素子形成領域を区分けする境界部分に対応する部分を示す。
【0064】
この第3の実施形態に係る半導体装置の製造方法によれば、第1,第2の実施形態において得られた効果に加えて、更に、各半導体装置(チップ)単位にダイシングを行った後で各々の金属層23,24を所要の回路素子の形状にパターニングするようにしているので、パターニングする形状に応じてインダクタンス、アンテナ、SAWフィルタ等として利用することができ、これによって、各チップ内に形成されるパターン面積を減らすことが可能となる。
【0065】
なお、レーザトリミング(図6(a))をダイシング後に行っている理由は、ダイシングを行う前に金属層23,24を所要の回路素子の形状にパターニングしてしまうと、プラズマダイシング(図4(b))またはレーザダイシング(図5(a))の際に金属層23,24をダイシング保護膜として活用できない(つまり、回路素子パターンが損傷を受けるおそれがある)からである。
【0066】
【発明の効果】
以上説明したように本発明によれば、高密度化及び薄型化を意図した半導体装置を製造するにあたり、薄化された半導体基板の取扱いを容易に行うことができると共に、その半導体基板のダイシングを短時間で行うことが可能となる。
【図面の簡単な説明】
【図1】本発明に係る半導体装置の製造方法を実施する際に使用する治具の一構成例を示す図である。
【図2】図1の治具に保護フィルム付ウエハをセットする方法を説明するための図である。
【図3】本発明の第1の実施形態に係る半導体装置の製造工程を示す断面図である。
【図4】図3の製造工程に続く製造工程を示す断面図である。
【図5】本発明の第2の実施形態に係る半導体装置の製造工程の一部を示す断面図である。
【図6】本発明の第3の実施形態に係る半導体装置の製造工程の一部と、当該工程において形成されるパターンの一例を模式的に示す図である。
【符号の説明】
10…治具、
11…下側パーツ、
12…上側パーツ、
13…治具クランプ、
20…保護フィルム付ウエハ、
21…シリコンウエハ(半導体基板)、
21a…シリコン基板、
22…保護フィルム(BGテープ等)、
23,23a…無電解Niめっき層(第1の金属層)、
24,24a…無電解Auめっき層(第2の金属層)、
30…半導体装置(チップ)、
41,43…無電解めっき槽、
42…無電解Niめっき液、
44…無電解Auめっき液、
EP…金属層のレーザトリミングによって形成されたパターン(回路素子)、
P1,P2…パッキン、
SP…各素子形成領域(半導体装置)を区分けする境界部分に対応する部分。
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique useful for easily handling a semiconductor substrate such as a thinned silicon wafer when manufacturing a semiconductor device such as an LSI chip.
[0002]
[Prior art]
Conventionally, a silicon wafer used as a substrate in the manufacture of a semiconductor device has a relatively large thickness of about 200 μm or more. (Such as "dicing") is relatively easy, and when used for a specific application (such as a silicon chip having an antenna effect), the chip must have a shielding function. Processing in which a metal layer was formed on the back surface of a silicon wafer was also possible.
[0003]
On the other hand, with recent demands for higher density and thinner semiconductor devices (devices), various methods have been proposed in order to meet the demands. As one method, for example, for each region to be divided as a device on a silicon wafer, a hole is drilled at a required depth, and the hole is filled with a conductor by plating or the like. After forming a desired device pattern (including a circuit pattern, a wiring pattern, etc.) so as to be electrically connected to the conductor, the device pattern is covered with an insulating film made of a polyimide resin or the like. The back surface is polished by a back grinding method or the like, and the wafer is thinned to a predetermined thickness (about 50 μm), while the conductor is exposed, and then the wafer is diced into each chip unit to make individual devices. There is a way to do that. In this method, an external connection terminal such as a metal bump is bonded to the back surface (the surface where the conductor is exposed) of the silicon wafer before the dicing is performed, or the device has a shielding function. In some cases, a metal layer is formed on the back surface of the silicon wafer.
[0004]
When dicing is performed, mechanical means such as a dicer is usually used.
[0005]
[Problems to be solved by the invention]
As described above, the conventional silicon wafer was relatively thick, so that its handling was relatively easy. However, with the recent demand for thinning, a process of thinning the silicon wafer has been performed. It is technically very difficult to handle the thinned silicon wafer as it is. This is because cracks may occur during handling of the thinned silicon wafer, and in some cases, the silicon wafer may be broken or the silicon wafer may be warped.
[0006]
That is, there is a problem that it is very difficult to handle the thinned silicon wafer without damaging it (formation of a metal layer by plating or the like, dicing for each chip).
[0007]
In addition, in the conventional technology, dicing is performed by a mechanical means such as a dicer.For example, when manufacturing a sub-millimeter-order ultra-small device such as a microchip, a dicing interval between devices on a silicon wafer is extremely narrow. For this reason, dicing takes a considerable amount of time to complete and increases the cost, which is not practical.
[0008]
In this case, if the thickness of the silicon wafer is relatively thick, there is a disadvantage that the time required for dicing is further increased by the thicker. On the other hand, if the silicon wafer is thinned to a predetermined thickness, During the process, the silicon wafer may be cracked or broken by the mechanical impact, so that dicing requires great care and is technically difficult.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that is intended to have a higher density and a smaller thickness in view of the above-mentioned problems in the prior art. An object of the present invention is to enable dicing of a substrate in a short time.
[0010]
[Means for Solving the Problems]
According to one embodiment of the present invention, a protective film is attached to a surface of a semiconductor substrate on a side where each element formation region to be divided as a semiconductor device is defined. Fixing the semiconductor substrate with the protective film to the jig by exposing only the surface opposite to the side to which the protective film is attached, and the semiconductor substrate with the protective film fixed and held by the jig. Forming a metal layer on the entire surface on the exposed side of the metal layer; removing a portion of the metal layer corresponding to a boundary portion separating each of the element formation regions by laser; and dry etching or wet etching. Dividing the semiconductor substrate into the respective semiconductor devices so as to include one element formation region along the portion where the metal layer is removed. The method of manufacturing a semiconductor device according to is provided.
[0011]
According to the method of manufacturing a semiconductor device according to this aspect, prior to handling the semiconductor substrate (forming a metal layer on the back surface, dicing each semiconductor device (chip), etc.), each element formation region of the semiconductor substrate is formed. Since the semiconductor substrate with the protective film whose surface on which is defined is covered with a protective film is fixedly held on a jig, even if the semiconductor substrate is thinned to a predetermined thickness, the thickness of the semiconductor substrate is reduced. The handled semiconductor substrate can be easily handled without damaging it.
[0012]
Further, the dicing of each semiconductor device (chip) is not performed by a mechanical means such as a dicer as used in the conventional technology, but by a portion which is not removed by a laser (that is, divided into each chip). Since the metal layer of a portion corresponding to each element formation region to be formed) is dry-etched using an etching resist, batch dicing can be performed in a short time.
[0013]
As described above, since it becomes possible to collectively dice the thinned semiconductor substrate in a short time, it is expected that a new semiconductor chip manufacturing technology such as a microchip will be spurred.
[0014]
According to another aspect of the present invention, in the method of manufacturing a semiconductor device according to the above-described aspect, the step of removing a predetermined portion of the metal layer by the laser and the step of dry-etching or wet-etching the semiconductor substrate. In place of the step of dividing the semiconductor device, the laser is used to remove a portion of the metal layer corresponding to a boundary portion that divides each of the element formation regions, and further along the removed portion of the metal layer. A method of manufacturing a semiconductor device is provided, comprising a step of dividing the semiconductor substrate into each semiconductor device so as to include one element formation region.
[0015]
According to the method of manufacturing a semiconductor device according to this embodiment, in addition to the effects obtained by the method of manufacturing a semiconductor device according to the above-described embodiment, a process of removing a predetermined portion of a metal layer and a dicing process of a semiconductor substrate are further performed. Is performed in one step, so that the process can be simplified.
[0016]
According to still another aspect of the present invention, in the method of manufacturing a semiconductor device according to each of the above-described embodiments, after the step of dividing the semiconductor substrate into the respective semiconductor devices, the respective semiconductor devices are exposed by a laser. A step of patterning each of the metal layers into a required circuit element shape.
[0017]
According to the method of manufacturing a semiconductor device according to this embodiment, in addition to the effects obtained by the method of manufacturing a semiconductor device according to each of the above-described embodiments, the metal layers of each semiconductor device are further separated by laser after dicing. Since the pattern is formed into a required shape, it can be used as an inductance or an antenna according to the shape to be patterned. This leads to a reduction in the pattern area formed in each semiconductor device.
[0018]
Further, according to another aspect of the present invention, there is provided a semiconductor device manufactured by the method of manufacturing a semiconductor device according to each of the above-described embodiments.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 schematically shows a configuration example of a jig used when carrying out a method of manufacturing a semiconductor device according to the present invention.
[0020]
As shown in the drawing, a jig 10 includes a lower part 11 for placing and holding a processing object, an upper part 12 for pressing and holding the processing object from above in cooperation with the lower part 11, It comprises a jig clamp 13 for fixing the two parts 11, 12 for sandwiching and holding the object from the circumferential direction thereof (see FIG. 1 (c)).
[0021]
As will be described later, the object to be processed is a surface on the side of the silicon wafer 21 (indicated by a broken line in the figure) on which a device pattern such as a circuit pattern and a wiring pattern is formed (that is, a final surface). (Hereinafter referred to as a "wafer with a protective film" for convenience) on the surface on the side where each element formation region to be divided as a semiconductor device (chip) is defined.
[0022]
The lower part 11 and the upper part 12 are each made of stainless steel (SUS) or the like, and their surfaces are Teflon (registered trademark) processed. The lower part 11 is formed in a circular shape as shown in FIG. 1A, and a packing P1 made of silicone rubber, Teflon, or the like is arranged in a ring shape in the vicinity along a peripheral surface thereof. The size of the packing P1 (ring) is selected to be slightly larger than the size of the silicon wafer 21. On the other hand, the upper part 12 is formed in a ring shape as shown in FIG. 1B, and the outer diameter of the ring is the same as the outer diameter of the lower part 11 and is defined by the inner diameter of the ring. The size of the opening is selected to be smaller than the size of the silicon wafer 21. Further, a packing P2 made of a similar material is arranged in a ring shape in the vicinity along the inner peripheral surface of the upper part 12.
[0023]
A method for setting a wafer with a protective film on the jig 10 (11 to 13) configured as described above will be described with reference to FIG.
[0024]
First, as shown in FIG. 2A, an adhesive (not shown) is applied to the surface of the lower part 11 on which the packing P1 is formed, and the protective film 22 of the protective film-attached wafer 20 is attached. The wafer 20 with the protective film is fixed to a predetermined position of the lower part 11 with an adhesive, with the surface on which it is attached facing down. By fixing the protective film-attached wafer 20 using the adhesive in this way, the difference in the thermal expansion coefficient between both surfaces (the silicon wafer 21 side and the protective film 22 side) of the protective film-attached wafer 20 causes the difference. The possibility that the wafer is warped can be eliminated.
[0025]
Next, the two parts 11, 12 are aligned so that the packing P2 of the upper part 12 contacts the peripheral surface of the silicon wafer 21 and the packing P1 of the lower part 11 contacts the peripheral surface of the upper part 12. After that, the two parts 11, 12 holding the wafer 20 with the protective film are firmly fixed and held by a plurality of (four in the example of FIG. 2B) jig clamps 13 so as to be sandwiched from the circumferential direction. I do. As a result, in the wafer 20 with a protective film, only the back surface (the surface opposite to the surface on which the device pattern is formed) of the silicon wafer 21 is exposed to the outside. In other words, the wafer 20 with the protective film is hermetically sealed from the outside by the packings P1, P2 of both parts 11, 12, except for the back surface of the silicon wafer 21.
[0026]
Hereinafter, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.
[0027]
First, in the first step (see FIG. 3A), the surface of the silicon wafer 21 thinned to a thickness of about 50 μm (on the lower side in the illustrated example) on which the device pattern is formed is formed. The protection film-equipped wafer 20 to which the protection film 22 having a thickness of about 100 μm to 1 mm is attached is set on the jigs 11 to 13 by the method described with reference to FIG.
[0028]
The protective film 22 includes, for example, a resin film made of an epoxy resin, a polyimide resin, or the like, or a sheet-shaped support made of a plastic film such as PET (polyethylene terephthalate), on one surface of which an acrylic or rubber-based material is used. What applied the adhesive (resin in an unhardened state) is used. Alternatively, as another form of the protection film 22, one side (the side to be polished and the other side) is used to protect the silicon wafer when the silicon wafer having a relatively large thickness of about 100 μm to 300 μm is thinned by mechanical polishing such as a back grinding method. The back-grinding protection tape (hereinafter, also referred to as “BG tape”) attached to the opposite surface) may be used as it is.
[0029]
This protective film 22 is for facilitating the handling of the thinned silicon wafer 21 after this step, and also for preventing the silicon wafer 21 from being damaged during the handling.
[0030]
In the next step (see FIG. 3B), a metal layer 23 is formed by electroless plating on the exposed back surface of the silicon wafer 21 of the wafer 20 with a protective film.
[0031]
That is, as shown in the figure, a plating tank 41 containing an electroless nickel (Ni) plating solution 42 (a solution containing Ni ions and a reducing agent) was prepared, and was set in the jigs 11 to 13 in the previous step. The wafer 20 with the protective film is immersed in the plating bath 41 to cause an oxidation-reduction reaction in the electroless Ni plating solution 42 so that the reducing agent is oxidized and Ni ions are reduced to Ni at the same time. By depositing Ni on the back surface of the silicon wafer 21, an electroless Ni plating layer (metal layer 23) is formed to a thickness of about 0.2 μm to 0.4 μm. As the electroless Ni plating solution 42, for example, an electroless Ni plating solution manufactured by Meltex Co., Ltd .: Melplate NI-867 is preferably used.
[0032]
The electroless Ni plating layer 23 is formed to increase the adhesion between the underlying silicon (Si) wafer 21 and the metal layer formed in the next step.
[0033]
After the formation of the metal layer 23 (electroless Ni plating layer), the wafer 20 with the protective film is taken out of the plating tank 41 while being set in a jig.
[0034]
In the next step (see FIG. 3C), a metal layer 24 is further formed by electroless plating on the metal layer 23 (electroless Ni plating layer) formed in the previous step. The formation of the metal layer 24 is performed by a “substitution plating” process by substitution with a metal (in this case, Ni) of the underlayer.
[0035]
That is, as shown in the figure, a plating tank 43 containing an electroless gold (Au) plating solution 44 (a solution containing Au ions and a reducing agent) is prepared, and the silicon wafer 21 of the protective film-attached wafer 20 is prepared in the previous step. The electroless Ni plating layer 23 formed on the back surface is immersed in a plating bath 43, and the Au ions in the electroless Au plating solution 44 are replaced with Au in exchange for the underlying metal ions (Ni ions) being oxidized and dissolved. By depositing Au on the electroless Ni plating layer 23 so as to reduce the thickness of the electroless Ni plating layer 23, the electroless Au plating layer (metal layer 24) is formed to be extremely thin (less than 0.05 μm). As the electroless Au plating solution 44, for example, an electroless Au plating solution: Melplate AU-601 manufactured by Meltex Corporation is preferably used.
[0036]
The electroless Au plating layer 24 is formed to reduce the electric resistance of the entire metal layer (Ni / Au) formed on the back surface of the silicon wafer 21.
[0037]
Further, in this step, a very thin metal layer 24 (electroless Au plating layer) having a thickness of 0.05 μm or less is formed by the displacement plating process. The electroless Au plating treatment as performed in the above is performed.
[0038]
After the formation of the metal layer 24 (electroless Au plating layer), the wafer 20 with the protective film is taken out of the plating tank 43 while being set in a jig.
[0039]
In the next step (see FIG. 4A), the metal layer having a two-layer structure (electroless Ni plating layer 23 / electroless Au plating layer 24) is patterned by laser trimming. That is, predetermined portions of the metal layers 23 and 24 are removed by laser. The predetermined portion to be removed is a portion corresponding to a boundary portion for dividing each element formation region of the silicon wafer 21 to be finally divided as a semiconductor device (chip) (portion indicated by SP in FIG. 6B). ). As the laser, for example, a UV-YAG laser, an excimer laser, or the like is used.
[0040]
In the next step (see FIG. 4B), predetermined portions of the metal layers 23 and 24 removed in the previous step, that is, each element formation region, are separated by dry etching (plasma etching in this embodiment). The silicon wafer 21 is divided into individual semiconductor devices (chips) along the boundary portion so as to include one element formation region (dicing). The gas used for plasma discharge is mainly oxygen (O 2 2 ), Nitrogen (N 2 ), Hydrogen (H 2 ) Is used, but in order to increase the etching rate, CF 4 , SF 6 A mixture of such reactive gases is used.
[0041]
As a result, each semiconductor device (chip) is separated while being attached to the protective film 22.
[0042]
In this step, dicing of each semiconductor device unit is performed by plasma etching. In addition to the plasma etching, dicing is performed by etching using an ion beam such as argon (Ar) ions (ion beam etching). It is also possible. Alternatively, dicing can be performed by wet etching using a solution of an acid, an alkali, an organic solvent, or the like instead of the dry etching.
[0043]
In this case, it should be noted that when dicing each semiconductor device, before dicing the protective film 22 holding each semiconductor device (that is, the state in which the protective film 22 is completely cut). (Before) the process such as plasma etching is terminated.
[0044]
After this step, the wafer 20 with the protective film diced for each semiconductor device is removed from the jigs 11 to 13.
[0045]
In the last step (see FIG. 4C), the protection film 22 is peeled off from the wafer 20 with the protection film diced for each semiconductor device. That is, each semiconductor device (chip) 30 is removed from the protective film 22. Each semiconductor device 30 includes a silicon substrate 21a including a corresponding element formation region, and Ni / Au metal layers 23a and 24a formed on the back surface of the silicon substrate 21a. Note that a semiconductor device (a portion indicated by 31 in the drawing) manufactured from a peripheral portion of the silicon wafer is removed as a defective chip.
[0046]
As described above, according to the method for manufacturing a semiconductor device according to the first embodiment, the handling of the thinned silicon wafer 21 (the formation of the metal layers 23 and 24 on the back surface of the wafer, the formation of each semiconductor device ( Prior to performing dicing (chips) of 30 units, the silicon wafer 21 with the protective film 22 is covered with a protective film 22 on the surface of the silicon wafer 21 on which the device pattern is formed, as shown in FIG. Is fixedly held on the jigs 11 to 13, so that the thinned silicon wafer 21 can be easily handled without damaging it.
[0047]
Further, dicing of 30 units of each semiconductor device (chip) is performed by laser trimming as shown in FIGS. 4 (a) and 4 (b) instead of mechanical means such as a dicer used in the prior art. Is performed by plasma etching using the metal layers 23 and 24 of the portions not removed by the plasma etching using the metal layers 23 and 24 as etching resists (portions corresponding to the respective element forming regions to be divided into each chip unit), and thus a large number of batches can be performed in a short time Dicing can be performed. As described above, it is expected that a large-scale batch dicing of the thinned silicon wafer 21 will be used to accelerate a new silicon chip manufacturing technology such as a microchip.
[0048]
In addition, since dicing is performed by plasma etching, curved dicing, which cannot be performed by conventional mechanical dicing, can be performed.
[0049]
When the back-grinding protection tape (BG tape) used for thinning the silicon wafer is used as the protection film 22 without peeling it off, there is no need to attach a new protection film to the silicon wafer 21. The process can be simplified.
[0050]
Further, the presence of the metal layers 23 and 24 on the back surface of the silicon wafer 21 allows the chip to have a shielding function when used for, for example, a silicon chip having an antenna effect.
[0051]
Further, since the metal layers 23 and 24 are patterned (removal of predetermined portions of the metal layers 23 and 24) by laser trimming, a resist for patterning (such as a dry film) used in the related art is used. Need not be used, and there is no need to remove the resist. Thereby, the process can be simplified, and the BG tape can be prevented from being damaged by the resist stripping solution as conventionally used.
[0052]
Further, the wafer 20 with the protective film is fixed and held on the jigs 11 to 13 so as to swing in the plating solutions 42 and 44 when performing the electroless plating process (see FIGS. 3B and 3C). And so on.
[0053]
In addition, in the related art, vapor deposition or sputtering is performed to form a metal layer on a silicon wafer, and such processing is performed while evacuating air from a processing chamber and maintaining a vacuum state. Undesirable gas is generated from the BG tape attached to the silicon wafer.
[0054]
On the other hand, in the present embodiment, the metal layers 23 and 24 are formed by electroless plating (see FIGS. 3B and 3C), and the protection film 22 (BG tape) is Since the parts 11 and 12 are completely shielded from the plating solutions 42 and 44 by the packings P1 and P2, generation of gas from the protective film 22 (BG tape) can be prevented.
[0055]
Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIG. 5 showing a part of the manufacturing process.
[0056]
The method of manufacturing the semiconductor device according to the second embodiment differs from the method of manufacturing the semiconductor device according to the first embodiment (FIGS. 3 and 4) in the steps of FIGS. 4A and 4B. Instead of the performed processing, predetermined portions of the metal layers 23 and 24 (each element formation region of the silicon wafer 21) are separated by a laser (UV-YAG laser, excimer laser, or the like) as shown in FIG. The portions corresponding to the boundary portions) are removed, and the laser is used to separate the silicon wafer 21 along the removed portions of the metal layers 23 and 24 so that each of the semiconductor devices (chips) includes one element formation region. The difference is that dicing is performed in units. Other steps are the same as those in the first embodiment, and a description thereof will be omitted.
[0057]
As described above, the method of manufacturing the semiconductor device according to the present embodiment is characterized in that the patterning of the metal layers 23 and 24 and the dicing of the silicon wafer 21 are performed in one step.
[0058]
According to the method of manufacturing the semiconductor device according to the second embodiment, in addition to the effects obtained in the first embodiment, the patterning process of the metal layers 23 and 24 and the dicing process of the silicon wafer 21 are further performed in one step. Since the process is performed in a single process (see FIG. 5A), the process can be simplified.
[0059]
Further, since the metal layers 23 and 24 are formed on the back surface of the silicon wafer 21, heat generated by the laser can be effectively dissipated through the metal layers 23 and 24 during dicing by the laser. The circuit of the silicon wafer 21 can be prevented from being damaged by heat.
[0060]
Next, a method for manufacturing a semiconductor device according to the third embodiment will be described with reference to FIG.
[0061]
6A shows a part of a manufacturing process of the semiconductor device according to the present embodiment, and FIG. 6B schematically shows an example of a pattern formed in the process of FIG. Things.
[0062]
The method for manufacturing a semiconductor device according to the third embodiment is different from the method for manufacturing a semiconductor device according to the first and second embodiments (FIGS. 3, 4, and 5) in FIG. As shown in FIG. 6A, a laser (UV-YAG laser, excimer laser) is used between the process and the process of FIG. 4C or between the process of FIG. 5A and the process of FIG. Etc.) in that a process of patterning the metal layers 23 and 24 of each semiconductor device after dicing into a required shape by trimming according to the above method is added. The other steps are the same as those in the first and second embodiments, and a description thereof will be omitted.
[0063]
As described above, in the method of manufacturing a semiconductor device according to the present embodiment, after dicing the silicon wafer 21, the metal layers 23 and 24 of each semiconductor device (chip) are replaced with required circuit elements (EP in FIG. 6B). (Part shown in the figure). As the circuit element to be patterned, there are an antenna, a SAW filter, and the like, in addition to the coil-shaped inductance element EP as shown in FIG. SP indicates a portion corresponding to a boundary portion that divides each element formation region of the silicon wafer 21 to be finally divided into each chip unit.
[0064]
According to the method of manufacturing a semiconductor device according to the third embodiment, in addition to the effects obtained in the first and second embodiments, after dicing is performed for each semiconductor device (chip), Since each of the metal layers 23 and 24 is patterned into a required circuit element shape, it can be used as an inductance, an antenna, a SAW filter, or the like according to the patterning shape. The area of the formed pattern can be reduced.
[0065]
The reason why laser trimming (FIG. 6A) is performed after dicing is that if the metal layers 23 and 24 are patterned into required circuit element shapes before dicing, plasma dicing (FIG. This is because the metal layers 23 and 24 cannot be used as a dicing protective film during b)) or laser dicing (FIG. 5A) (that is, the circuit element pattern may be damaged).
[0066]
【The invention's effect】
As described above, according to the present invention, in manufacturing a semiconductor device intended for high density and thinning, the thinned semiconductor substrate can be easily handled, and dicing of the semiconductor substrate can be performed. This can be performed in a short time.
[Brief description of the drawings]
FIG. 1 is a view showing one configuration example of a jig used when carrying out a method of manufacturing a semiconductor device according to the present invention.
FIG. 2 is a view for explaining a method of setting a wafer with a protective film on the jig of FIG. 1;
FIG. 3 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a manufacturing process following the manufacturing process of FIG. 3;
FIG. 5 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the second embodiment of the present invention.
FIG. 6 is a diagram schematically illustrating a part of a manufacturing process of a semiconductor device according to a third embodiment of the present invention and an example of a pattern formed in the manufacturing process.
[Explanation of symbols]
10 ... Jig,
11 ... lower part,
12 Upper part,
13 ... Jig clamp,
20: wafer with protective film,
21: silicon wafer (semiconductor substrate),
21a: silicon substrate,
22 ... Protective film (BG tape etc.),
23, 23a ... electroless Ni plating layer (first metal layer),
24, 24a ... electroless Au plating layer (second metal layer),
30 ... semiconductor device (chip),
41, 43 ... electroless plating tank,
42 ... Electroless Ni plating solution,
44 ... Electroless Au plating solution,
EP: pattern (circuit element) formed by laser trimming of the metal layer,
P1, P2 ... packing,
SP: a part corresponding to a boundary part that divides each element formation region (semiconductor device).

Claims (9)

半導体基板のそれぞれ半導体装置として分割されるべき各素子形成領域が画定されている側の面に保護フィルムが貼着された保護フィルム付半導体基板を、該保護フィルムが貼着されている側と反対側の面のみを露出させて治具に固定保持する工程と、
前記治具によって固定保持された保護フィルム付半導体基板の露出している側の全面に金属層を形成する工程と、
レーザにより、前記金属層の、前記各素子形成領域を区分けする境界部分に対応する部分を除去する工程と、
ドライエッチング又はウエットエッチングにより、前記金属層の除去された部分に沿って前記半導体基板をそれぞれ1つの素子形成領域が含まれるように各半導体装置に分割する工程とを含むことを特徴とする半導体装置の製造方法。
A semiconductor substrate with a protective film having a protective film adhered to the surface of the semiconductor substrate on which the element forming regions to be divided as semiconductor devices are defined is opposite to the side on which the protective film is adhered. A step of exposing only the side surface and fixing and holding the jig,
A step of forming a metal layer on the entire exposed side of the semiconductor substrate with a protective film fixed and held by the jig,
Removing a portion of the metal layer, which corresponds to a boundary portion that divides each of the element formation regions, with a laser;
Dividing the semiconductor substrate into each semiconductor device along the portion where the metal layer is removed by dry etching or wet etching so that each semiconductor device includes one element formation region. Manufacturing method.
前記半導体基板を各半導体装置に分割する工程において、各半導体装置を保持している前記保護フィルムが分割される前に前記ドライエッチング又はウエットエッチングを終了させることを特徴とする請求項1に記載の半導体装置の製造方法。The method according to claim 1, wherein in the step of dividing the semiconductor substrate into the semiconductor devices, the dry etching or the wet etching is terminated before the protective film holding each semiconductor device is divided. A method for manufacturing a semiconductor device. 前記レーザにより前記金属層の所定の部分を除去する工程及び前記ドライエッチング又はウエットエッチングにより前記半導体基板を各半導体装置に分割する工程に代えて、
レーザにより、前記金属層の、前記各素子形成領域を区分けする境界部分に対応する部分を除去し、さらに、該金属層の除去された部分に沿って前記半導体基板をそれぞれ1つの素子形成領域が含まれるように各半導体装置に分割する工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
Instead of the step of removing a predetermined portion of the metal layer by the laser and the step of dividing the semiconductor substrate into each semiconductor device by the dry etching or wet etching,
By using a laser, a portion of the metal layer, which corresponds to a boundary portion that divides each of the element formation regions, is removed, and further, one semiconductor device formation region is formed along the semiconductor substrate along the removed portion of the metal layer. 2. The method according to claim 1, further comprising the step of dividing the semiconductor device into semiconductor devices so as to be included.
前記半導体基板を各半導体装置に分割する工程において、各半導体装置を保持している前記保護フィルムが分割される前に前記レーザの照射を終了させることを特徴とする請求項3に記載の半導体装置の製造方法。4. The semiconductor device according to claim 3, wherein, in the step of dividing the semiconductor substrate into the respective semiconductor devices, the laser irradiation is terminated before the protective film holding each semiconductor device is divided. Manufacturing method. 前記半導体基板を各半導体装置に分割する工程の後に、
レーザにより、各半導体装置の露出している各金属層をそれぞれ所要の回路素子の形状にパターニングする工程を含むことを特徴とする請求項1から4のいずれか一項に記載の半導体装置の製造方法。
After the step of dividing the semiconductor substrate into each semiconductor device,
5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of patterning each exposed metal layer of each semiconductor device into a required circuit element shape by using a laser. Method.
前記金属層を形成する工程は、
前記治具に固定保持された保護フィルム付半導体基板を第1の無電解金属めっき液中に浸漬し、酸化還元反応により当該金属を析出させて第1の金属層を形成する工程と、
前記第1の金属層が形成された保護フィルム付半導体基板を第2の無電解金属めっき液中に浸漬し、前記第1の金属層の金属との置換による置換めっき処理によって第2の金属層を形成する工程とを含むことを特徴とする請求項1から5のいずれか一項に記載の半導体装置の製造方法。
The step of forming the metal layer,
Immersing the semiconductor substrate with a protective film fixed and held in the jig in a first electroless metal plating solution, and depositing the metal by an oxidation-reduction reaction to form a first metal layer;
The semiconductor substrate with a protective film on which the first metal layer is formed is immersed in a second electroless metal plating solution, and the second metal layer is subjected to a displacement plating process by replacing the first metal layer with a metal. Forming a semiconductor device. 6. The method according to claim 1, further comprising the step of:
前記半導体基板は、前記各素子形成領域が一方の面に画定された比較的厚い半導体基板を、該各素子形成領域が画定されている側と反対側の面から研磨して所定の厚さに薄化することによって得られることを特徴とする請求項1から5のいずれか一項に記載の半導体装置の製造方法。The semiconductor substrate is formed by polishing a relatively thick semiconductor substrate in which each of the element formation regions is defined on one surface from a surface opposite to the side on which each of the element formation regions is defined to a predetermined thickness. The method for manufacturing a semiconductor device according to claim 1, wherein the method is obtained by thinning. 半導体基板のそれぞれ半導体装置として分割されるべき各素子形成領域が画定されている面と反対側の面に金属層を形成する工程と、
該金属層の、前記各素子形成領域を区分けする境界部分に対応する部分を除去する工程と、
ドライエッチング又はウエットエッチングにより、前記金属層の除去された部分に沿って前記半導体基板をエッチングし、分割する工程とを含むことを特徴とする半導体装置の製造方法。
A step of forming a metal layer on a surface of the semiconductor substrate opposite to a surface on which each element formation region to be divided as a semiconductor device is defined;
Removing a portion of the metal layer corresponding to a boundary portion that divides each of the element formation regions;
Etching the semiconductor substrate along a portion from which the metal layer has been removed by dry etching or wet etching, and dividing the semiconductor substrate.
請求項1から8のいずれか一項に記載の半導体装置の製造方法によって製造されたことを特徴とする半導体装置。A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.
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