JP2004053276A - Semiconductor device and semiconductor integrated circuit - Google Patents

Abstract

A semiconductor device on which a plurality of chips having different test conditions are mounted is surely subjected to a burn-in test.
[Means for Solving the Problems]
The control circuit of the first chip generates a control signal for operating the second chip. The first chip and the second chip are manufactured by mutually different manufacturing processes, and are mounted on one package. The test control circuit of the first chip inhibits transmission of a control signal to the second chip during testing of the first chip. For this reason, for example, during the burn-in test of the first chip, it is possible to prevent the transistors and the like of the second chip from being stressed. As a result, in a semiconductor device in which the first chip and the second chip having different test conditions are mounted, a test can be performed by applying stress only to the first chip.
[Solution]
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a plurality of semiconductor chips are mounted in the same package and a system is configured with one package.
In particular, the present invention relates to a test circuit mounted on the semiconductor device.
[0002]
[Prior art]
Recently, a semiconductor device that operates as a system by housing a logic chip, a memory chip, and the like having different process technologies in one package has been developed. This type of semiconductor device is called a multi-chip package (hereinafter, referred to as MCP) or a multi-chip module (hereinafter, referred to as MCM).
Generally, a burn-in test is performed on a semiconductor device in a test process. The burn-in test is an accelerated test in which a plurality of semiconductor devices mounted on a test substrate are operated at a high temperature and a high voltage for a predetermined time and an initial failure of a transistor or the like is removed in a short time.
[0003]
The test conditions for the burn-in test must be set optimally for each manufacturing process in order to reliably remove the initial failure. For this reason, the conditions of the burn-in test are different between the logic chip and the memory chip. For example, a burn-in test is performed at 125 ° C. for a logic chip, and a burn-in test is performed at 100 ° C. for a memory chip.
[0004]
[Problems to be solved by the invention]
However, in an MCP in which a logic chip and a memory chip are mounted in one package, the logic chip and the memory chip must be burned in under the same test conditions. When the burn-in test of the semiconductor device is performed under a loose test condition among the test conditions of each chip, there is a possibility that the initial failure of the chip under severe test conditions cannot be sufficiently removed. When the burn-in test of the semiconductor device is performed under severe test conditions among the test conditions of each chip, excessive stress is applied to the chip under the loose test conditions, and the defect rate may increase.
[0005]
In order to prevent the above problem, conventionally, for example, a logic chip manufactured by a proven manufacturing process and requiring no burn-in test is mounted on the MCP. In this case, the initial failure of the memory chip mounted on the MCP can be removed by performing the burn-in test at 100 ° C.
An object of the present invention is to reliably perform a burn-in test on a semiconductor device on which a plurality of chips having different test conditions are mounted.
[0006]
It is another object of the present invention to test a plurality of chips mounted on a semiconductor device under optimum test conditions.
[0007]
[Means for Solving the Problems]
In the semiconductor device of the first aspect and the semiconductor integrated circuit of the tenth aspect, the control circuit of the first chip (semiconductor integrated circuit) generates a control signal for operating the second chip (semiconductor chip). The first chip and the second chip are manufactured by mutually different manufacturing processes, and are mounted on one package. The test control circuit of the first chip inhibits transmission of a control signal to the second chip during testing of the first chip. That is, when the first chip is tested, the operation of the second chip is prevented. For this reason, for example, during the burn-in test of the first chip, it is possible to prevent the transistors and the like of the second chip from being stressed. As a result, in the semiconductor device on which the first chip and the second chip are mounted, a burn-in test can be performed by applying stress to only the first chip.
[0008]
For example, the first chip is a logic chip, and the second chip is a memory chip. Generally, a memory chip has a more complicated manufacturing process than a logic chip. For this reason, the temperature of the burn-in test in the memory chip is set lower than that of the logic chip. According to the present invention, in a semiconductor device on which a plurality of semiconductor chips having different test conditions are mounted, each of the chips can be tested under optimum conditions.
[0009]
In the semiconductor device according to the second aspect, the semiconductor device has a first power supply terminal for the first chip and a second power supply terminal for the second chip. That is, the power supply is independent for the first chip and the second chip. The test control circuit controls output of all control signals supplied to the second chip. Therefore, for example, when the supply of the power supply voltage to the second power supply terminal is stopped at the time of the burn-in test of the first chip, the second chip is brought into a state equivalent to being left at a high temperature. As a result, during the test of the first chip, it is possible to reliably prevent the transistor and the like of the second chip from being stressed by the electric field.
[0010]
In the semiconductor device of the third aspect, the semiconductor device has a common power supply terminal for the first chip and the second chip. The test control circuit prohibits the output of the enable signal for activating the second chip when the first chip is tested. Therefore, when testing the first chip, the second chip receives the power supply voltage but does not receive the enable signal. Therefore, the second chip is inactivated, and stress is prevented from being applied to the second chip.
[0011]
In the semiconductor device according to the fourth aspect, the first chip shifts to the test mode when receiving the test signal at the test terminal. The test activation circuit of the first chip is activated when receiving the test signal, and outputs a test activation signal according to the logic of the signal input to the input terminal of the first chip. Here, the input terminal is a terminal that receives an input signal used in a normal operation. The test control circuit prohibits transmission of the control signal to the second chip when receiving the test start signal. Therefore, a desired test among a plurality of tests can be performed by using the input terminal used in the normal operation.
[0012]
In the semiconductor device according to the fifth aspect, the first chip and the second chip manufactured by different manufacturing processes are mounted in one package. The semiconductor device includes a first power supply terminal for an internal circuit of the first chip, a second power supply terminal for an internal circuit of the second chip, and a third power supply terminal for input / output circuits of the first and second chips. Have. That is, the power supply is independent of the internal circuit of the first chip, the internal circuit of the second chip, and the input / output circuits of the first and second chips. The control circuit of the first chip generates a control signal for operating the second chip.
[0013]
The test control circuit is formed on the second chip instead of the first chip. The test control circuit operates by the power supply voltage supplied to the third power supply terminal, and prohibits transmission of a control signal to the internal circuit of the second chip when testing the first chip. For this reason, for example, during the burn-in test of the first chip, the power supply voltage is supplied to the first and third power supply terminals and the supply of the power supply voltage to the second power supply terminal is stopped, so that the second chip is left at a high temperature. Is equivalent to Since the test control circuit is formed on the second chip, stress can be easily prevented from being applied to the second chip even when a general-purpose chip is used as the first chip.
[0014]
In the semiconductor device according to the sixth aspect, the test activation terminal receives a test activation signal for testing the first chip. The test control circuit prohibits transmission of the control signal when receiving the test start signal. Therefore, the first chip can be easily tested only by supplying a predetermined voltage to the test start terminal.
In the semiconductor device according to the seventh aspect, the output inhibition circuit of the test control circuit sets the output node of the control signal to high impedance when testing the first chip. Therefore, for example, at the time of a burn-in test, the second chip can be easily and reliably left at a high temperature.
[0015]
In the semiconductor device according to the eighth aspect, the high-level fixing circuit of the test control circuit fixes an output node of a control signal to the second chip to a high level when the first chip is tested. For example, by connecting the output of the high-level fixed circuit to the input terminal of the second chip that indicates an active state at the time of the low level, the second chip is reliably deactivated during the test of the first chip. Can be in a state.
[0016]
In the semiconductor device according to the ninth aspect, the low-level fixing circuit of the test control circuit fixes the output node of the control signal to the second chip to a low level when the first chip is tested. For example, by connecting the output of the low-level fixed circuit to the input terminal of the second chip that indicates an active state at the time of a high level, the second chip is reliably deactivated during the test of the first chip. Can be in a state.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a first embodiment of the semiconductor device of the present invention. This embodiment corresponds to claims 1, 2, 6, 7, and 10. This semiconductor device is formed as an MCP by mounting a logic chip (first chip) and an SDRAM (second chip) on a package substrate BRD. The SDRAM manufacturing process uses a semiconductor element having characteristics different from those of a logic chip, and is configured by adding a memory cell forming process. That is, the manufacturing processes of the SDRAM and the logic chip are different from each other. Usually, the burn-in test of a single logic chip is performed at 125 ° C., and the burn-in test of a single SDRAM is performed at 100 ° C.
[0018]
The package substrate BRD includes a first power supply terminal VDD1 and a first ground terminal GND1 connected to a power supply terminal and a ground terminal of the logic chip, respectively, and a second power supply terminal VDD2 and a second power supply terminal connected to the power supply terminal and the ground terminal of the SDRAM, respectively. It has two ground terminals GND2, a test control terminal BIZ connected to a test control terminal of the logic chip, and a terminal connected to an input terminal and an output terminal of the logic chip.
[0019]
The logic chip includes a logic circuit (control circuit) 10 that generates a plurality of control signals CNT for operating the SDRAM and receives data from the SDRAM, and a test control circuit 12. The logic circuit 10 has a predetermined function such as data processing in addition to the control function of the SDRAM. The test control circuit 12 receives the control signal CNT for the SDRAM output from the logic circuit 10 and transmits the control signal CNT to the SDRAM when the test start signal BIZ is at a low level. The test control circuit 12 prohibits transmission of the control signal CNT to the SDRAM when the test start signal BIZ is at a high level. All control signals CNT supplied from the logic chip to the SDRAM are output to the SDRAM via the test control circuit 12.
[0020]
The SDRAM has a memory cell array 14, a control circuit for operating the memory cell array 14, an input / output circuit, and the like (not shown). The external terminals of the SDRAM are all connected to the logic chip. That is, the SDRAM operates in response to the control signal CNT from the logic chip. Data read from the memory cell array 14 is output to the outside of the MCP via the logic chip.
[0021]
FIG. 2 shows the structure of the MCP shown in FIG. In this embodiment, an SDRAM and a logic chip are stacked on a package substrate BRD. The package substrate BRD, the SDRAM, and the logic chip are connected to each other via bonding wires. The present invention is not limited to the MCP having a laminated structure. For example, the present invention may be applied to an MCM in which a logic chip and an SDRAM are arranged in parallel on a package substrate.
[0022]
FIG. 3 shows details of the test control circuit 12 shown in FIG.
The test control circuit 12 has a clocked inverter 12a (output inhibition circuit) for each control signal CNT (CNT1,..., CNTn) for operating the SDRAM. When receiving the low-level test start signal BIZ, the clocked inverter 12a outputs a signal obtained by inverting the control signal CNT to the IO cell 14, respectively. When receiving the high-level test control terminal BIZ, the clocked inverter 12a sets the output to high impedance, thereby inhibiting the output of the control signal CNT to the IO cell 14.
[0023]
The IO cell 14 has a pull-down resistor 14a and an output buffer 14b. When the clocked inverter 12a is off, the input terminals MIN1,. . . , MINn are supplied with a low level by a pull-down resistor 14a. Here, the buffer 14b may be formed in an SDRAM instead of a logic chip.
Next, the burn-in test of the MCP will be described. The burn-in test of the MCP is performed separately for the logic chip and the SDRAM.
[0024]
First, a plurality of MCPs are mounted on a test board. The test substrate is placed in a test furnace (125 ° C.). Next, only the first power supply terminal VDD1 and the first ground terminal GND1 connected to the logic chip are connected to the power supply line, and a predetermined voltage is supplied to these terminals VDD1 and GND1. The second power supply terminal VDD2 and the second ground terminal GND2 connected to the SDRAM are not connected to a power supply line.
[0025]
Thereafter, a high level is supplied to the test control terminal BIZ, and the clocked inverter 12a of the test control circuit 10 is deactivated. Next, when a test signal is supplied to the input terminal of the logic chip, the logic circuit 10 shown in FIG. 1 operates, and a burn-in test of the logic chip is performed. At this time, no power is supplied to the SDRAM. Further, all the input terminals MIN1,. . . , MINn are supplied with a low level. Therefore, the SDRAM is in a state equivalent to being left at a high temperature. In general, the high temperature storage standard for SDRAM is higher than 125 ° C. For this reason, during the burn-in test of the logic chip, the transistors and the like in the SDRAM are not stressed and deteriorated. That is, in the present invention, the burn-in test is performed only on a desired chip among a plurality of semiconductor chips mounted on the MCP.
[0026]
After the burn-in test of the logic chip, the burn-in test of the SDRAM is performed in a test furnace at 100 ° C. At this time, the first power terminal VDD1, the first ground terminal GND1, the second power terminal VDD2, and the second ground terminal GND2 are connected to the power line, and a predetermined voltage is supplied to these terminals VDD1, GND1, VDD2, and GND2. You. That is, power is supplied to both the logic chip and the SDRAM.
[0027]
The test start terminal BIZ is set to low level, and the clocked inverter 12a of the test control circuit 12 is activated. The logic circuit 10 operates when a test signal is supplied to the input terminal of the logic chip. The control signal CNT (test pattern) generated by the logic circuit 10 is transmitted to the SDRAM via the clocked inverter 12a. Then, a burn-in test of the SDRAM is performed.
[0028]
Note that the internal circuit of the logic chip also operates during the burn-in test of the SDRAM. For this reason, the above-described burn-in test of the logic chip at 125 ° C. may be performed, if necessary, under the condition that the stress applied to the logic chip at the time of the burn-in test of the SDRAM at 100 ° C. is subtracted.
As described above, in the present embodiment, during the burn-in test of the logic chip, the test control circuit 12 inhibits the transmission of the control signal CNT to the SDRAM, thereby preventing the SDRAM from operating. Therefore, it is possible to prevent stress from being applied to the transistors and the like of the SDRAM. As a result, in a semiconductor device such as an MCP on which a plurality of semiconductor chips having different test conditions are mounted, each chip can be tested under optimum conditions.
[0029]
Since the power supplies VDD1 and GND1 of the logic chip and the power supplies VDD2 and GND2 of the SDRAM are made independent, the SDRAM can be brought into a state equivalent to being left at a high temperature during a burn-in test of the logic chip. As a result, stress due to an electric field can be reliably prevented from being applied to the transistors and the like of the SDRAM, and deterioration of the elements can be prevented.
A test start terminal BIZ for receiving a test start signal for performing a burn-in test of the logic chip was formed. Therefore, the burn-in test can be easily performed only by supplying a high-level voltage to the test start terminal BIZ.
[0030]
At the time of the burn-in test of the logic chip, the output node of the control signal CNT was set to high impedance by the clocked inverter 12a of the test control circuit 12. Therefore, the SDRAM can be easily and reliably brought into a state equivalent to being left at a high temperature.
FIG. 4 shows a main part of a second embodiment of the semiconductor device of the present invention. This embodiment corresponds to claims 1, 2, 6, 7, and 10. The same elements as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0031]
In this embodiment, the output of the test control circuit 12 is connected to an IO cell 14 having a pull-down resistor 14a or an IO cell 16 having a pull-up resistor 16a. Other configurations are the same as those of the first embodiment. Note that the buffers 14b and 16b may be formed in an SDRAM instead of a logic chip.
The IO cell 14 having a pull-down resistor is connected to an input terminal (for example, a clock enable terminal CKE) that indicates an activated state when it is at a high level. The IO cell 16 having a pull-up resistor is connected to input terminals (for example, a chip select signal / CS, a row address strobe terminal / RAS, a column address strobe terminal / CAS, and a write enable signal / WE) indicating an activated state at a low level. It is connected. One of the IO cells 14 and 16 is connected to an input terminal (for example, an address terminal) to which a low level and a high level are selectively supplied according to specifications. Other configurations are the same as those of the first embodiment.
[0032]
In this embodiment, a burn-in test of the logic chip is performed as in the first embodiment. At this time, no voltage is supplied to the power supply terminal VDD2 and the ground terminal GND2 of the SDRAM. A low level or a high level is supplied to one of the IO cells 14 and 16 to the input terminal of the SDRAM, and the SDRAM is reliably kept in the inactive state. Therefore, during the burn-in test of the logic chip, the SDRAM is in a state equivalent to being left at a high temperature, and no stress is applied to the SDRAM.
[0033]
In this embodiment, the same effects as in the first embodiment can be obtained.
FIG. 5 shows a main part of a third embodiment of the semiconductor device of the present invention. This embodiment corresponds to claims 1, 2, 6, 8, 9, and 10. The same elements as those in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0034]
In this embodiment, a test control circuit 18 is formed instead of the test control circuit 12 of the first embodiment. The output of the test control circuit 18 is connected to the IO cell 16 having a pull-up resistor or the IO cell 14 having a pull-down resistor. The IO cell 16 having a pull-up resistor is connected to an input terminal that indicates an activated state when it is at a high level. The IO cell 14 having a pull-down resistor is connected to an input terminal that is activated when the level is low, contrary to the first embodiment. Note that the buffers 14b and 16b may be formed in an SDRAM instead of a logic chip. Other configurations are the same as those of the first embodiment.
[0035]
The test control circuit 18 includes an nMOS transistor 18a (low-level fixed circuit) and a pMOS for forcibly setting the transmission node of the control signal CNT output from the logic circuit 10 of the logic chip shown in FIG. It has a transistor 18b (high-level fixed circuit). The source of the nMOS transistor 18a is connected to the first ground terminal GND1, and the source of the pMOS transistor 18a is connected to the first power supply terminal VDD1. The nMOS transistor 18a and the pMOS transistor 18b are turned on when the test start signal BIZ is at a high level. The transmission node to which the nMOS transistor 18a is connected is connected to the IO cell 16 having a pull-up resistor. The transmission node to which the pMOS transistor 18b is connected is connected to the IO cell 14 having a pull-down resistor.
[0036]
In this embodiment, no voltage is supplied to the power supply terminal VDD2 and the ground terminal GND2 of the SDRAM during the burn-in test of the logic chip. In addition, when the nMOS transistor 18a is turned on, a low level which is an inactive level is supplied to the input terminal MIN1 which is activated when the SDRAM is at a high level. When the pMOS transistor 18b is turned on, a high level which is an inactive level is supplied to the input terminal MINn which is activated when the SDRAM is at a low level. Therefore, during the burn-in test of the logic chip, the SDRAM is in a state equivalent to being left at a high temperature. That is, no stress is applied to the SDRAM during the burn-in test of the logic chip.
[0037]
In this embodiment, the same effects as in the first embodiment can be obtained. Further, at the time of the burn-in test of the logic chip, the drain of the nMOS transistor 18a of the test control circuit 18 was connected via the IO cell 16 to a terminal (MIN1 or the like) indicating an activated state when the SDRAM was at a high level. Alternatively, the drain of the pMOS transistor 18b of the test control circuit 18 is connected via the IO cell 14 to a terminal (MINn or the like) which is activated when the SDRAM is at a low level. Therefore, the SDRAM can be reliably inactivated during the burn-in test of the logic chip.
[0038]
FIG. 6 shows a fourth embodiment of the semiconductor device of the present invention. This embodiment corresponds to claims 1, 3, 7, 8, and 10. The same elements as those in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the package substrate BRD of the MCP includes a power supply terminal VDD and a ground terminal GND connected to a power supply terminal and a ground terminal of the logic chip and the SDRAM, respectively, and a test control terminal BIZ connected to a test control terminal of the logic chip. And a terminal connected to the input terminal and the output terminal of the logic chip. That is, the logic chip and the SDRAM are connected to the common power supply terminal VDD and the ground terminal GND. Therefore, at the time of the burn-in test of the logic chip, the power supply voltage is supplied not only to the logic chip but also to the SDRAM.
[0039]
The logic chip has a logic circuit 10 and a test control circuit 20. The test control circuit 20 has a plurality of clocked inverters 12a (not shown) for inhibiting transmission of a signal corresponding to the clock enable signal CKE among the control signals CNT to the SDRAM. The clocked inverter 12a is deactivated when the test start signal BIZ is at a high level, as in the first embodiment (FIG. 3).
[0040]
As described above, in the present embodiment, only the control signal CNT corresponding to the clock enable signal CKE is transmitted to the SDRAM via the test control circuit 20. The clock signal CLK, the chip select signal / CS, the write enable signal / WE, the address signal AD, and the like are transmitted directly from the logic circuit 10 to the SDRAM.
In the logic chip, an IO cell (not shown) that outputs the clock enable signal CKE has a pull-down resistor. Therefore, when the clocked inverter 12a of the test control circuit 20 is inactivated, the clock enable signal CKE output from the logic chip is fixed at a low level.
[0041]
During the burn-in test of the logic chip, power is supplied to the SDRAM. Therefore, the internal circuit of the SDRAM is in an operable state. When receiving a high-level clock enable signal CKE, the SDRAM activates a clock buffer and transmits a clock signal CLK to an internal circuit. Input buffers for the chip select signal / CS, the address signal AD and the like operate upon receiving the clock signal CLK. When receiving the low-level clock enable signal CKE, the SDRAM inactivates the clock buffer and inhibits transmission of the clock signal CLK to the internal circuit. At this time, the input buffer is deactivated. Therefore, the SDRAM enters a standby state (more precisely, a low power consumption state in which the clock buffer does not operate).
[0042]
In the standby state, the memory cell array 14 of the SDRAM does not operate. Therefore, no stress is applied to the memory cell array 14 during the burn-in test of the logic chip.
In this embodiment, the same effects as in the first embodiment can be obtained. Further, when the power supply of the logic chip and the power supply of the SDRAM are common, the supply of the clock enable signal CKE to the SDRAM is stopped during the burn-in test of the logic chip. Therefore, the operation of the memory cell array 14 of the SDRAM can be prevented, and the stress applied to the memory cell array 14 can be prevented.
[0043]
FIG. 7 shows a fifth embodiment of the semiconductor device of the present invention. This embodiment corresponds to claims 5, 6, 8, and 9. The same elements as those in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.
In this embodiment, the package substrate BRD of the MCP is connected to the first power supply terminal VDD1 and the first ground terminal GND1, respectively connected to the power supply terminal and the ground terminal of the logic chip, and to the power supply terminal and the ground terminal of the SDRAM, respectively. A second power supply terminal VDD2 and a second ground terminal GND2, a third power supply terminal VDD3 and a third ground terminal GND3 connected to a power supply terminal and a ground terminal of an input / output unit (IO cell unit) of the logic chip and the SDRAM, and a test. It has a test control terminal BIZ connected to the control circuit 22 and terminals connected to input terminals and output terminals of the logic chip.
[0044]
The test control circuit 22 is formed not in the logic chip but in the input / output unit of the SDRAM. The power supply terminal and the ground terminal of the test control circuit 22 are connected to the third power supply terminal VDD3 and the third ground terminal GND3.
In this embodiment, at the time of a burn-in test of the logic chip, the first power supply terminal VDD1 and the first ground terminal GND1 connected to the logic chip, and the third power supply terminal VDD3 connected to the input / output unit of the logic chip and the SDRAM. And third ground terminal GND3 are connected to a power supply line. The second power supply terminal VDD2 and the second ground terminal GND2 connected to the SDRAM are not connected to a power supply line. Therefore, during the burn-in test of the logic chip, only the logic chip, the input / output unit of the SDRAM, and the test control circuit 22 operate.
[0045]
FIG. 8 shows details of the test control circuit 22 shown in FIG.
The test control circuit 22 has the same logic as the first embodiment (FIG. 3). That is, the test control circuit 22 has the clocked inverter 22a (output inhibit circuit) activated in response to the test start signal BIZ for each control signal CNT (CNT1,... CNTn) for operating the SDRAM. ing. Each clocked inverter 22a receives a control signal CNT (CNT1,..., CNTn) from the logic chip via the IO cell 24, and receives the signal when the test start signal BIZ is at a low level (not in the burn-in test mode). The input signals MIN1,. . . , MINn to the internal circuit of the SDRAM.
[0046]
For example, the input signal MIN1 corresponding to the IO cell 14 having a pull-down resistor is a signal indicating an activated state when it is at a high level. The input signal MINn corresponding to the IO cell 16 having a pull-up resistor is a signal that indicates an activated state when it is at a low level.
When performing the burn-in test of the logic chip, the second power supply terminal VDD2 and the second ground terminal GND2 connected to the SDRAM are not connected to the power supply line. A high level is supplied to the test activation terminal BIZ, and the clocked inverter 22a is inactivated. Therefore, the SDRAM internal circuit (memory cell array 14) does not operate. Therefore, no stress is applied to the memory cell array 14 during the burn-in test of the logic chip.
[0047]
In this embodiment, the same effects as those of the first and second embodiments can be obtained. Further, the test control circuit 22 was connected to dedicated power supplies VDD3 and GND3 supplied to the logic chip and the input / output unit of the SDRAM. Therefore, the test control circuit 22 can be formed in the SDRAM. As a result, even when the logic chip is a general-purpose chip, the burn-in test can be performed only on the logic chip.
[0048]
FIG. 9 shows a sixth embodiment of the semiconductor device of the present invention. This embodiment corresponds to claims 1, 2, 5, 6, 8, 9, and 10. The same elements as those in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.
In this embodiment, the logic chip has a plurality of test modes. For this reason, a test activation circuit 26a is formed in the logic circuit 26 of the logic chip. The test activation circuit 26a is activated when the test terminal TEST receives a high level, and changes the test activation signal BIZ to a high level when the logic of the signal supplied to the address terminals AD0 and AD1 is, for example, "10". To change. Address terminals AD0 and AD1 receive an address signal for selecting a register of a logic chip and a memory cell of an SDRAM during a normal operation. Due to the high level of the test start signal BIZ, the clocked inverter 12a (not shown) of the test control circuit 12 is inactivated.
[0049]
The test activation circuit 26a activates for performing a built-in self test (BIST; Built-in Self Test) when receiving a high level at the test terminal TEST and receiving, for example, logic “00” at the address terminals AD0 and AD1. Output a signal.
In this embodiment, the same effects as in the first embodiment can be obtained. Further, the clocked inverter 12a of the test control circuit 22 was deactivated according to a combination of input signals used in the normal operation. Therefore, a plurality of tests can be performed with a small number of terminals.
[0050]
FIG. 10 shows a seventh embodiment of the semiconductor device of the present invention. This embodiment corresponds to claims 1, 2, 5, 6, 8, 9, and 10. The same elements as those in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.
In this embodiment, the logic chip has a plurality of test modes. Therefore, a test activation circuit 28a is formed in the logic circuit 28 of the logic chip. The test activation circuit 28a changes the test activation signal BIZ to a high level when the logic combination of the signals input to the command terminals CMD1, CMD2, and CMD3 is a predetermined combination. Command terminals CMD1, CMD2, and CMD3 receive command signals for operating the logic chip and the SDRAM during normal operation. A combination of command signals for changing the test start signal BIZ to a high level is a combination that is not input in normal operation. When receiving a signal of another combination that is not used in normal operation, the test activation circuit 26a outputs, for example, an activation signal for performing a built-in self-test (BIST; Built-in Self Test).
[0051]
In this embodiment, the same effects as in the first embodiment can be obtained. Further, the test start signal BIZ was set to a high level using only the input terminals used in the normal operation. Therefore, a test terminal can be made unnecessary.
In the above-described embodiment, an example has been described in which the present invention is applied to an MCP including one logic chip and one SDRAM. The present invention is not limited to such an embodiment. For example, the present invention may be applied to an MCP including one logic chip and a plurality of memory chips.
[0052]
The inventions described in the above embodiments are arranged and disclosed as additional notes.
(Supplementary Note 1) A semiconductor device in which a first chip and a second chip manufactured by mutually different manufacturing processes are mounted in one package.
The first chip includes:
A control circuit for generating a control signal for operating the second chip;
A test control circuit for inhibiting transmission of the control signal to the second chip when the first chip is tested.
[0053]
(Supplementary Note 2) In the semiconductor device according to Supplementary Note 1,
A first power terminal for the first chip;
A second power supply terminal for the second chip;
The semiconductor device, wherein the test control circuit controls output of all the control signals supplied to the second chip.
[0054]
(Supplementary Note 3) In the semiconductor device according to Supplementary Note 1,
A power supply terminal common to the first chip and the second chip;
The semiconductor device, wherein the test control circuit controls an output of an enable signal for activating the second chip among the control signals supplied to the second chip.
[0055]
(Supplementary Note 4) In the semiconductor device according to Supplementary Note 1,
The first chip includes:
A test terminal for receiving a test signal for transitioning the first chip to a test mode;
An input terminal for receiving an input signal used in normal operation,
A test activation circuit that is activated when the test signal is received, and outputs a test activation signal in accordance with the logic of a signal input to the input terminal;
The semiconductor device, wherein the test control circuit inhibits transmission of the control signal when receiving the test start signal.
[0056]
(Supplementary Note 5) In the semiconductor device according to Supplementary Note 1,
The first chip includes:
An input terminal for receiving an input signal used in normal operation,
A test activation circuit that outputs a test activation signal according to a combination of logics of signals input to the input terminal a plurality of times,
The semiconductor device, wherein the test control circuit inhibits transmission of the control signal when receiving the test start signal.
[0057]
(Supplementary Note 6) A semiconductor device in which a first chip and a second chip manufactured by different manufacturing processes are mounted in one package,
A first power supply terminal for an internal circuit of the first chip;
A second power supply terminal for an internal circuit of the second chip;
A third power supply terminal for an input / output circuit of the first and second chips;
The first chip includes:
A control circuit for generating a control signal for operating the second chip,
The second chip comprises:
A test control circuit that operates by a power supply voltage supplied to the third power supply terminal and that inhibits transmission of the control signal to an internal circuit of the second chip when testing the first chip. Semiconductor device.
[0058]
(Supplementary Note 7) In the semiconductor device according to Supplementary Note 1 or 6,
A test start terminal for receiving a test start signal for testing the first chip;
The semiconductor device, wherein the test control circuit inhibits transmission of the control signal when receiving the test start signal.
(Supplementary Note 8) In the semiconductor device according to Supplementary Note 1 or 6,
The semiconductor device according to claim 1, wherein the test control circuit includes an output prohibition circuit that sets an output node of the control signal to high impedance when testing the first chip.
[0059]
(Supplementary Note 9) In the semiconductor device according to Supplementary Note 1 or 6,
The semiconductor device according to claim 1, wherein the test control circuit includes a high-level fixing circuit that fixes an output node of the control signal to a high level when the first chip is tested.
(Supplementary Note 10) In the semiconductor device according to Supplementary Note 1 or 6,
The semiconductor device according to claim 1, wherein the test control circuit includes a low-level fixing circuit that fixes an output node of the control signal to a low level when the first chip is tested.
[0060]
(Supplementary Note 11) In the semiconductor device according to Supplementary Note 1 or 6,
The first chip is a logic chip,
The semiconductor device according to claim 2, wherein the second chip is a memory chip.
(Supplementary Note 12) A control circuit that generates a control signal for operating another semiconductor chip having a different manufacturing process mounted on the same package,
A test control circuit that operates in a test mode and inhibits output of the control signal.
[0061]
(Supplementary Note 13) In the semiconductor integrated circuit according to supplementary note 12,
A test start terminal for receiving a test start signal;
The semiconductor integrated circuit, wherein the test control circuit inhibits output of the control signal when receiving the test start signal.
(Supplementary Note 14) In the semiconductor integrated circuit according to supplementary note 12,
The semiconductor integrated circuit according to claim 1, wherein the test control circuit includes an output prohibition circuit that sets an output node of the control signal to high impedance in the test mode.
[0062]
(Supplementary Note 15) In the semiconductor integrated circuit according to supplementary note 12,
The semiconductor device according to claim 1, wherein the test control circuit includes a high-level fixing circuit that fixes an output node of the control signal to a high level in the test mode.
(Supplementary Note 16) In the semiconductor integrated circuit according to supplementary note 12,
The semiconductor integrated circuit according to claim 1, wherein the test control circuit includes a low-level fixing circuit that fixes an output node of the control signal to a low level in the test mode.
[0063]
In the semiconductor device according to Supplementary Note 5, the test activation circuit of the first chip outputs a test activation signal according to a combination of logics of signals input to the input terminal of the first chip a plurality of times. Here, the input terminal is a terminal that receives an input signal used in a normal operation. The test control circuit prohibits transmission of the control signal to the second chip when receiving the test start signal. Therefore, a desired test among a plurality of tests can be performed by using the input terminal used in the normal operation.
[0064]
As described above, the present invention has been described in detail. However, the above-described embodiment and its modifications are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the present invention.
[0065]
【The invention's effect】
In the semiconductor device according to the first aspect and the semiconductor integrated circuit according to the tenth aspect, in a semiconductor device on which a plurality of semiconductor chips having different test conditions are mounted, each chip can be tested under optimum conditions. For example, during the burn-in test of the first chip, it is possible to prevent stress from being applied to the transistors and the like of the second chip. As a result, in the semiconductor device on which the first chip and the second chip are mounted, a burn-in test can be performed by applying stress to only the first chip.
[0066]
According to the semiconductor device of the second aspect, it is possible to reliably prevent a stress due to an electric field from being applied to the transistors and the like of the second chip during the test of the first chip.
In the semiconductor device according to the third aspect, the second chip can be inactivated at the time of testing the first chip, thereby preventing stress from being applied to the second chip.
According to the semiconductor device of the fourth aspect, a desired test among a plurality of tests can be performed by using the input terminal used in the normal operation.
[0067]
In the semiconductor device according to the fifth aspect, in a semiconductor device on which a plurality of semiconductor chips having different test conditions are mounted, each of the chips can be tested under optimum conditions. In particular, even when a general-purpose chip is used as the first chip, stress can be easily prevented from being applied to the second chip.
In the semiconductor device according to the sixth aspect, the test can be easily performed only by supplying a predetermined voltage to the test start terminal.
[0068]
In the semiconductor device according to the seventh aspect, for example, the second chip can be easily and reliably left at a high temperature during a burn-in test.
9. The semiconductor device according to claim 8, wherein an output of the high-level fixed circuit is connected to a terminal which is activated when the input terminal of the second chip is at a low level, thereby enabling the second chip to be tested at the time of testing the first chip. Can be reliably inactivated.
[0069]
In the semiconductor device according to the ninth aspect, the output of the low-level fixed circuit is connected to the input terminal of the input terminal of the second chip that indicates an active state at the time of the high level, so that the second chip is tested during the test of the first chip. Can be reliably inactivated.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 2 is a perspective view showing the structure of the MCP shown in FIG.
FIG. 3 is a circuit diagram showing details of a test control circuit of FIG. 1;
FIG. 4 is a circuit diagram showing a main part of a second embodiment of the present invention.
FIG. 5 is a circuit diagram showing a main part of a third embodiment of the present invention.
FIG. 6 is a block diagram showing a fourth embodiment of the present invention.
FIG. 7 is a block diagram showing a fifth embodiment of the present invention.
FIG. 8 is a circuit diagram showing details of a test control circuit of FIG. 7;
FIG. 9 is a block diagram showing a sixth embodiment of the present invention.
FIG. 10 is a block diagram showing a seventh embodiment of the present invention.
[Explanation of symbols]
10 Logic circuit
12 Test control circuit
14 Memory cell array
12a Clocked inverter
14 IO cell
14a pull-down resistor
14b output buffer
16 IO cells
16a pull-up resistor
18 Test control circuit
20 Test control circuit
22 Test control circuit
22a Clocked inverter
24 IO cells
26 Logic circuit
26a Test start circuit
28 Logic circuit
28a Test start circuit
BIZ test control terminal
BRD package substrate
CNT control signal
GND1 First ground terminal
GND2 Second ground terminal
GND3 Third ground terminal
TEST test terminal
VDD1 First power supply terminal
VDD2 Second power supply terminal
VDD3 Third power supply terminal

Claims (10)

A semiconductor device in which a first chip and a second chip manufactured by different manufacturing processes are mounted in one package,
The first chip includes:
A control circuit for generating a control signal for operating the second chip;
A test control circuit for inhibiting transmission of the control signal to the second chip when the first chip is tested. The semiconductor device according to claim 1,
A first power terminal for the first chip;
A second power supply terminal for the second chip;
The semiconductor device, wherein the test control circuit controls output of all the control signals supplied to the second chip. The semiconductor device according to claim 1,
A power supply terminal common to the first chip and the second chip;
The semiconductor device, wherein the test control circuit controls an output of an enable signal for activating the second chip among the control signals supplied to the second chip. The semiconductor device according to claim 1,
The first chip includes:
A test terminal for receiving a test signal for transitioning the first chip to a test mode;
An input terminal for receiving an input signal used in normal operation,
A test activation circuit that is activated when the test signal is received, and outputs a test activation signal in accordance with the logic of a signal input to the input terminal;
The semiconductor device, wherein the test control circuit inhibits transmission of the control signal when receiving the test start signal. A semiconductor device in which a first chip and a second chip manufactured by different manufacturing processes are mounted in one package,
A first power supply terminal for an internal circuit of the first chip;
A second power supply terminal for an internal circuit of the second chip;
A third power supply terminal for an input / output circuit of the first and second chips;
The first chip includes:
A control circuit for generating a control signal for operating the second chip,
The second chip comprises:
A test control circuit that operates by a power supply voltage supplied to the third power supply terminal and that inhibits transmission of the control signal to an internal circuit of the second chip when testing the first chip. Semiconductor device. The semiconductor device according to claim 1 or 5,
A test start terminal for receiving a test start signal for testing the first chip;
The semiconductor device, wherein the test control circuit inhibits transmission of the control signal when receiving the test start signal. The semiconductor device according to claim 1 or 5,
The semiconductor device according to claim 1, wherein the test control circuit includes an output prohibition circuit that sets an output node of the control signal to high impedance when testing the first chip. The semiconductor device according to claim 1 or 5,
The semiconductor device according to claim 1, wherein the test control circuit includes a high-level fixing circuit that fixes an output node of the control signal to a high level when the first chip is tested. The semiconductor device according to claim 1 or 5,
The semiconductor device according to claim 1, wherein the test control circuit includes a low-level fixing circuit that fixes an output node of the control signal to a low level when the first chip is tested. A control circuit for generating a control signal for operating another semiconductor chip having a different manufacturing process mounted on the same package;
A test control circuit that operates in a test mode and inhibits output of the control signal.

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