JP2004053261A - Circuit for testing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time required for determining defective and non-defective semiconductor integrated circuits. <P>SOLUTION: This test circuit is provided with a signature (N vector) 17 when a test pattern is an N vector (N is a natural number), and a signature (M vector) 16 when the test pattern is an M vector (M is a natural number, and M<N). A comparator 15 performs comparison determination on both a compression value of an output signal value, outputted from a core_logic/memory 13 to which the test pattern of the M vector is inputted and held in an MISR (Multiple Input Signature Register) 14, and the signature (N vector) 16. In the case that the result of the comparison determination is non-defective, comparison determination is performed on both a compression value of an output signal value, outputted from the core_logic/memory 13 to which the test pattern of the N vector is successively inputted and held in the MISR 14, and the signature (N vector ) 17. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a test circuit for determining a good / defective product of a semiconductor integrated circuit, and more particularly to a test circuit for a semiconductor integrated circuit incorporated in the semiconductor integrated circuit.
[0002]
[Prior art]
As a test method of a semiconductor integrated circuit, there is a method called a stored test method in which a test pattern is input from the outside to a chip of the semiconductor integrated circuit, an output value is taken out, and compared with an expected value, and a semiconductor test method is used. There is a method called a BIST (Build In Self Test) method in which a self-diagnosis is performed by a test pattern generation circuit and a test determination unit incorporated in a chip of an integrated circuit. In recent years, the degree of integration of semiconductor integrated circuits has also increased, and the BIST method has become mainstream from the viewpoint of shortening the time required to judge good / bad of a large-scale semiconductor integrated circuit.
[0003]
In the BIST system, a circuit called a memory BIST circuit or a logic BIST circuit is used depending on what is a circuit to be tested in the semiconductor integrated circuit. For example, a memory BIST circuit is used to test a memory circuit such as an SRAM or a DRAM, and a logic BIST circuit is used to test a logic circuit such as a random logic or a core logic.
[0004]
FIG. 4 is a block diagram showing a schematic configuration of a test circuit of a semiconductor integrated circuit according to the related art. 101 is a pseudo random pattern generator (PRPG) that generates a pseudo random test pattern, 102 is an n-bit bundle that is a transmission line for transmitting an n-bit signal, 103 is a Core_Logic / Memory that is a circuit to be tested, and 104 is a shift register. , A Multiple Input Signature Register (MISR) composed of a counter, etc., 105 is a comparator which is a comparison circuit, 106 is a signature (N vector) holding an expected value which has been compressed in advance, 107 is a PRPG 101, a MISR 104, a comparator 105, etc. BIST_Controllers are shown.
[0005]
In FIG. 4, a pseudo random test pattern generated by the PRPG 101 under the control of the BIST_Controller 107 is input to the test target circuit Core_Logic / Memory 103 through the n-bit bundle 102. In the Core_Logic / Memory 103, an output signal of the Core_Logic / Memory 103 based on the input of the pseudo random test pattern is output to the MISR 104. The MISR 104 compresses the output and holds the compressed value. The BIST_Controller 107 enables the comparator 105 in response to a control output of the signal N (N vector completion signal), and in this enabled state, a Signature (N vector) in which a compressed value output from the MISR 104 and an expected value compressed in advance are held. Compare with the output value of 106. At this time, if all the compared values match, the test target circuit Core_Logic / Memory 103 is determined to be a non-defective product. If any of the comparison values do not match, the core_logic / Memory 103 is determined to be a defective product. finish.
[0006]
The “vector” of “N vector” (N is a natural number) described above is a word meaning “quantity” or “period (cycle)”. Therefore, “N vector” means that the number of test cycles of the pseudo random test pattern generated by the PRPG 101 is N. The "N vector" is the number of test cycles required to determine a non-defective / defective product of the circuit to be tested, that is, "all vectors".
[0007]
[Problems to be solved by the invention]
As described above, the test circuit built in the conventional semiconductor integrated circuit compares the compressed value of the output series of the test target circuit with the expected value held in the Signature, and determines whether or not the two values match each other. When the test was completed, a single comparison was performed to determine a good / defective product. Therefore, even if a defective portion is detected immediately after the start of the test operation, the test cannot be stopped halfway and the test time cannot be reduced.
[0008]
The present invention has been made in view of the above, and an object of the present invention is to provide a test circuit for a semiconductor integrated circuit incorporated in a semiconductor integrated circuit, which can shorten a test time for determining a good / defective product.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a test circuit for a semiconductor integrated circuit according to the present invention includes: a test pattern generation unit configured to generate a test pattern to be input to a semiconductor integrated circuit to be tested; A signal holding unit for holding a compressed value of an output signal value output from the semiconductor integrated circuit, and when the test pattern is input to the semiconductor integrated circuit to be tested, the semiconductor integrated circuit to be tested is normal A signature holding unit that holds a signature that is a compressed value of the output signal value expected in the case; andcomparing the compressed value of the output signal value held by the signal holding unit with the signature held by the signature holding unit. Controlling the comparing and judging means, the test pattern generating means, the signal holding means and the comparing and judging means In the test circuit of a semiconductor integrated circuit and a test control unit that, the signature holding means comprising a plurality of said signatures that correspond respectively to the plurality of different test patterns.
[0010]
According to the present invention, the signature holding means includes a plurality of signatures respectively corresponding to a plurality of different test patterns, and performs comparison / determination based on the plurality of signatures. The number can be increased.
[0011]
In the test circuit for a semiconductor integrated circuit according to the next invention, in the above-mentioned invention, the signature holding means is a first signature which is the signature when the test pattern is an N vector (N cycles) (N is a natural number). And a second signature, which is the signature when the test pattern is an M vector (M cycles) (M is a natural number having a relationship of M <N), and the comparing and judging means includes: A comparison between a compressed value of an output signal value output from the semiconductor integrated circuit to be tested and held in the signal holding means and the second signature based on the test pattern of the M vector input to the semiconductor integrated circuit And if the result of the comparison is good, the test pattern of the N vector continuously input to the semiconductor integrated circuit under test is Is output from the semiconductor integrated circuit of the test object based on the emission and performs a comparison determination of the compression value and the first signature of the output signal value held in the signal holding unit.
[0012]
According to the present invention, the signature holding unit includes the first signature, which is a signature when the test pattern is an N vector (N cycles) (N is a natural number), and an M vector (M cycles) (M: A second signature that is a signature when M <N (a natural number having a relationship of N <N), and the comparison and determination unit is configured to execute the test target semiconductor integrated circuit based on the test pattern of the M vector input to the test target semiconductor integrated circuit. A comparison judgment is made between the compressed value of the output signal value output from the circuit and held in the signal holding means and the second signature, and if the result of the comparison judgment is good, the input is continued to the semiconductor integrated circuit to be tested. The compressed value of the output signal value output from the test target semiconductor integrated circuit based on the N-vector test pattern and held by the signal holding means and the first signal And to perform the comparison and determination of the turbocharger. That is, since the intermediate test is performed in the middle of the test pattern without completing the entire test at one time, the time required to test from the M vector to the N vector can be reduced or shortened. it can. Further, since comparison / judgment is performed based on a plurality of signatures, the number of good / bad judgments can be increased.
[0013]
In the test circuit for a semiconductor integrated circuit according to the next invention, in the above-mentioned invention, the test control means may be configured such that the test control means is based on the test pattern of the M vector input to the semiconductor integrated circuit to be tested. Along with the determination of the output signal value output from the controller, a comparable signal is output to the comparison / determination means, and the test is terminated when the result of the comparison / determination is bad, and when the result of the comparison / determination is good. The determination signal output from the test target semiconductor integrated circuit based on the N vector test pattern continuously input to the test target semiconductor integrated circuit, It is characterized by outputting.
[0014]
According to the present invention, the test control means, when the output signal value output from the test target semiconductor integrated circuit is determined based on the test pattern of the M vector input to the test target semiconductor integrated circuit, A comparison possible signal is output. If the result of the comparison is poor, the test is ended. If the result of the comparison is good, the test pattern of the N vector continuously input to the semiconductor integrated circuit to be tested is output. When a value of an output signal output from the semiconductor integrated circuit to be tested is determined, a comparable signal is output to the comparison determination means. That is, since the intermediate test is performed in the middle of the test pattern without completing the entire test at one time, the time required to test from the M vector to the N vector can be reduced or shortened. it can.
[0015]
A test circuit for a semiconductor integrated circuit according to the next invention includes a test pattern generating means for generating a test pattern to be input to the semiconductor integrated circuit to be tested, and a test pattern output from the test target semiconductor integrated circuit to which the test pattern is input. Signal holding means for holding a compressed value of an output signal value to be output, and when the output signal value held in the signal holding means and the test pattern are input to the semiconductor integrated circuit to be tested, Comparison and determination means for comparing and determining a signature which is a compression value of an output signal value expected when the integrated circuit is normal, and a test for controlling the test pattern generation means, the signal holding means and the comparison and determination means A test circuit for controlling a semiconductor integrated circuit, the control circuit comprising: And further comprising a signature generator for generating a plurality of said signatures corresponding to each of the test pattern.
[0016]
According to the present invention, there is further provided a signature generating means for generating a plurality of signatures respectively corresponding to a plurality of different test patterns based on the control of the test control means, and performing the comparison / determination based on the plurality of signatures. Therefore, the number of times of good / bad determination can be increased.
[0017]
A test circuit for a semiconductor integrated circuit according to the next invention includes a test pattern generating means for generating a test pattern to be input to the semiconductor integrated circuit to be tested, and a test pattern output from the test target semiconductor integrated circuit to which the test pattern is input. Signal holding means for holding a compressed value of an output signal value to be output, and when the output signal value held in the signal holding means and the test pattern are input to the semiconductor integrated circuit to be tested, Comparison and determination means for comparing and determining a signature which is a compression value of an output signal value expected when the integrated circuit is normal, and a test for controlling the test pattern generation means, the signal holding means and the comparison and determination means And a control circuit for controlling a plurality of different test patterns. Characterized by inputting a plurality of said signatures from the external terminal.
[0018]
According to the present invention, a plurality of signatures respectively corresponding to a plurality of different test patterns are input from an external terminal, and comparison / judgment is performed based on the plurality of signatures. Can be increased.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of a test circuit for a semiconductor integrated circuit according to the present invention will be described below in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited by the embodiment.
[0020]
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a schematic configuration of a test circuit of the semiconductor integrated circuit according to the first embodiment of the present invention. Reference numeral 11 denotes a PRPG (Pseudo Random Pattern Generator) for generating a pseudo-random test pattern, 12 denotes an n-bit bundle as a transmission medium for an n-bit signal, 13 denotes a Core_Logic / Memory that is a circuit to be tested, 14 denotes a shift register, and a counter. MISR (Multiple Input Signature Register) composed of, for example, a comparator 15 as a comparison circuit, 16 and 17 a Signature (M vector) and a Signature (N vector) each holding a previously compressed expected value, and 18 a PRPG11, BIST_Controllers that control the MISR 14, the comparator 15, and the like are shown respectively.
[0021]
In FIG. 1, a pseudo random test pattern generated by the PRPG 11 under the control of the BIST_Controller 18 is input to the test target circuit Core_Logic / Memory 13 through the n-bit bundle 12. In the Core_Logic / Memory 13, an output signal of the Core_Logic / Memory 13 based on the input of the pseudo random test pattern is output to the MISR 14. The MISR 14 compresses the output signal value and holds the compressed value. The BIST_Controller 18 enables the comparator 15 by the control output of the signal M (M vector completion signal) (M is a natural number having a relationship of M <N with the previous N), and is output from the MISR 14 in this enabled state. A comparison (intermediate judgment) is made between the compressed value up to the M vector and the output value of the Signature (M vector) 16 which is an expected value that is compressed and held in advance.
[0022]
At this time, if the compared values match, the compression and comparison processing up to the N vector is performed as before. That is, the BIST_Controller 18 enables the comparator 15 in response to the control output of the signal N (N vector completion signal), and in this enabled state, the compressed value up to the N vector output from the MISR 14 is compressed and held in advance. The value is compared with the output value of the Signature (N vector) 17 to determine a non-defective / defective product.
[0023]
On the other hand, in the above-described intermediate determination, if even part of the compared values does not match, the circuit to be tested, Core_Logic / Memory 13, is determined to be defective, and the test ends. That is, it is possible to reduce or shorten the time required for the test from the M vector to the N vector.
[0024]
Note that the Signature (M vector) 16 has an n-bit configuration like the Signature (N vector) 17, and differs only in the value held.
[0025]
As described above, according to the first embodiment, as shown in FIG. 1, a signature (M vector) 16 and a signature (N vector) 17 are provided, and the result of the comparison determination (intermediate determination) based on the test pattern of the M vector is obtained. When the test is good, the comparison and determination based on the test pattern of the N vector are continuously performed, so that the test time from the M vector to the N vector can be reduced or shortened. Test time for non-defective products can be reduced. In addition, an effect that the number of times of determining good / defective products can be increased can be obtained.
[0026]
In the first embodiment, the signature is configured to have two signatures, a signature (M vector) 16 and a signature (N vector) 17, but the configuration is not limited to two, and three or more signatures are used. May be provided. For example, if a natural number L having a relationship of L <M <N is provided with a signature (L vector), a non-defective / defective product can be determined at an earlier stage. The test time for defective products can be further reduced.
[0027]
In the first embodiment, the signal transmission medium between the blocks is connected by an n-bit bundle. However, the present invention is not limited to the n-bit bundle, and each block is connected by a single line. It is also possible. In this case, the configuration may be such that the value is shifted in the circuit, and the same effect as in the case of the configuration using the n-bit bundle can be obtained.
[0028]
Embodiment 2 FIG.
FIG. 2 is a block diagram showing a schematic configuration of a test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that a plurality of signatures to be compared with the value of the MISR 14 by the comparator 15 are generated by the signature generator 20. Other configurations are the same as those of the first embodiment, and the same portions are denoted by the same reference numerals.
[0029]
The Signature_Generator 20 is configured by combining a well-known shift register, counter, LFSR (Linear Feedback Shift Register), and the like, and is a circuit capable of generating a plurality of Signatures corresponding to the number of compressed vectors. .
[0030]
In FIG. 2, up to the point where the output signal of Core_Logic / Memory 13 due to the input of the pseudo-random test pattern is output to the MISR 14, it is the same as in the first embodiment, and the description is omitted. The MISR 14 compresses the output signal and holds the compressed value. The BIST_Controller 18 enables the comparator 15 by the signal A (Comparator enable signal), and instructs the Signature_Generator 20 to generate a Signature by the signal B (Signature control signal). In the enable state, the compression value output from the MISR 14 is compared with the output value of the Signature generated by the Signature_Generator 20, and a non-defective / defective product of the test target circuit is determined.
[0031]
If the test target circuit is determined to be defective in the above-described test, the test ends. On the other hand, if the test target circuit is determined to be non-defective, the test is continued. In the subsequent operation, a new Signature is generated by the Signature_Generator 20 according to the Signature control signal from the BIST_Controller 18, and the above-described non-defective / defective determination is repeatedly performed.
[0032]
In the second embodiment, a plurality of Signatures are generated by the Signature_Generator 20 by the control signal of the BIST_Controller 18 and the test is performed a plurality of times. Therefore, similarly to the first embodiment, the test target circuit is a defective product. In some cases, the test time can be reduced.
[0033]
In addition, since the Signature_Generator 20 is built in, in the case where a large number of tests are performed in stages, the generation of the Signature is easier as compared with the first embodiment in which it is necessary to prepare a predetermined number of Signatures in advance. It has the advantage of becoming.
[0034]
As described above, according to the second embodiment, as shown in FIG. 2, a Signature_Generator 20 that generates a plurality of Signatures respectively corresponding to a plurality of different test patterns is provided, and the comparison / generation based on the plurality of Signatures generated by the Signature_Generator 20 is performed. Since the determination is performed, the test time when the test target circuit is defective can be reduced. In addition, an effect that the number of times of determining good / defective products can be increased can be obtained.
[0035]
In the second embodiment, the signal transmission medium between the blocks is connected by an n-bit bundle. However, the present invention is not limited to the n-bit bundle, and the blocks are connected by a single line. It is also possible. In this case, the configuration may be such that the value is shifted in the circuit, and the same effect as in the case of the configuration using the n-bit bundle can be obtained.
[0036]
Further, in the second embodiment, the configuration is provided with the Signature_Generator that generates a plurality of Signatures. However, the configuration can be combined with the first embodiment having a plurality of Signatures in advance, and the same effect can be obtained in this case.
[0037]
Embodiment 3 FIG.
FIG. 3 is a block diagram showing a schematic configuration of a test circuit of a semiconductor integrated circuit according to a third embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that the comparator 15 has a signature 21 for externally inputting a signature for comparison with the value of the MISR 14 and holding the input signal value. . The other configuration is the same as that of the first embodiment, and the same portions are denoted by the same reference numerals.
[0038]
In FIG. 3, up to the point where the output signal of Core_Logic / Memory 13 due to the input of the pseudo-random test pattern is output to the MISR 14, it is the same as the first embodiment, and the description is omitted. The MISR 14 compresses the output signal and holds the compressed value. The BIST_Controller 18 enables the comparator 15 in response to the signal A (Comparator enable signal). A signal B (Signature input signal) from an external input terminal (not shown) is input to the Signature 21, and the Signature is held. In the enable state, the compression value output from the MISR 14 is compared with the output value of the Signature held by the Signature 21 to determine whether the test target circuit is good or defective.
[0039]
If the test target circuit is determined to be defective in the above-described test, the test ends. On the other hand, if the test target circuit is determined to be non-defective, the test is continued. In the subsequent operation, the signature of Signature 21 is updated by a signal B (Signature input signal) from a test pin (not shown), and the above-described non-defective / defective determination is repeatedly performed.
[0040]
In the third embodiment, the signature is updated each time by the input of the signature from the outside, and the test is performed a plurality of times. Therefore, similar to the first embodiment, when the circuit to be tested is defective. Test time can be reduced.
[0041]
As described above, according to the third embodiment, as shown in FIG. 3, a plurality of signatures respectively corresponding to a plurality of different test patterns are input from an external terminal, and comparison / determination based on the plurality of signatures is performed. As a result, it is possible to reduce the test time when the test target circuit is defective. In addition, an effect that the number of times of determining good / defective products can be increased can be obtained.
[0042]
In the third embodiment, the signal transmission medium between the blocks is connected by an n-bit bundle. However, the present invention is not limited to the n-bit bundle, and each block is connected by a single line. It is also possible. In this case, the configuration may be such that the value is shifted in the circuit, and the same effect as in the case of the configuration using the n-bit bundle can be obtained.
[0043]
Further, in the third embodiment, a configuration is employed in which a Signature input from the outside is held. However, the third embodiment is combined with the first embodiment having a plurality of Signatures in advance and / or the second embodiment having a Signature_Generator for generating a plurality of Signatures. The same effect can be obtained in this case.
[0044]
【The invention's effect】
As described above, according to the present invention, the signature holding unit includes a plurality of signatures respectively corresponding to a plurality of different test patterns, and performs the comparison / determination based on the plurality of signatures. And the number of good / bad determinations can be increased. In addition, since the intermediate determination is performed using a test pattern at an intermediate stage without completing the entire test at one time, the time required for the test can be reduced or shortened.
[0045]
According to the next invention, the signature holding means includes a first signature that is a signature when the test pattern is an N vector (N cycles) (N is a natural number), and an M vector (M cycles) (M , A natural signature having a relationship of M <N), and a second signature which is a signature when M <N. The comparison / determination means includes a semiconductor device to be tested based on a test pattern of an M vector input to the semiconductor integrated circuit to be tested. A comparison decision is made between the compressed value of the output signal value output from the integrated circuit and held by the signal holding means and the second signature, and if the result of the comparison judgment is good, the test is continued with the semiconductor integrated circuit to be tested. The compressed value of the output signal value output from the semiconductor integrated circuit to be tested based on the input N vector test pattern and held by the signal holding means and the first sig. In this case, the intermediate test is performed using the test pattern at an intermediate stage without completing the entire test at one time. This has the effect of reducing and shortening. In addition, since comparison / judgment is performed based on a plurality of signatures, the number of good / bad judgments can be increased.
[0046]
According to the next invention, the test control unit is configured to determine the output signal value output from the test target semiconductor integrated circuit based on the M vector test pattern input to the test target semiconductor integrated circuit, The test is terminated when the result of the comparison and determination is bad, and the test pattern of the N vector continuously input to the semiconductor integrated circuit to be tested is output when the result of the comparison and determination is good. Along with the determination of the output signal value output from the semiconductor integrated circuit to be tested based on the test signal, a comparable signal is output to the comparison and determination means, and the entire test is performed in a halfway stage without ending the entire test at once. Since the intermediate judgment is performed, the effect of reducing or shortening the time required to test from the M vector to the N vector can be obtained. In addition, since comparison / judgment is performed based on a plurality of signatures, the number of good / bad judgments can be increased.
[0047]
According to the next invention, there is further provided a signature generating means for generating a plurality of signatures respectively corresponding to a plurality of different test patterns based on the control of the test control means, and performing comparison / determination based on the plurality of signatures. Thus, the number of good / bad determinations can be increased. In addition, since the intermediate determination is performed using a test pattern at an intermediate stage without completing the entire test at one time, the time required for the test can be reduced or shortened.
[0048]
According to the next invention, a plurality of signatures respectively corresponding to a plurality of different test patterns are input from an external terminal, and comparison / judgment is performed based on the plurality of signatures. This has the effect that the number of times can be increased. In addition, since the intermediate determination is performed using a test pattern at an intermediate stage without completing the entire test at one time, the time required for the test can be reduced or shortened.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention;
FIG. 2 is a block diagram illustrating a schematic configuration of a test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention;
FIG. 3 is a block diagram illustrating a schematic configuration of a test circuit of a semiconductor integrated circuit according to a third embodiment of the present invention;
FIG. 4 is a block diagram showing a schematic configuration of a test circuit of a semiconductor integrated circuit according to a conventional technique.
[Explanation of symbols]
11, 101 PRPG, 12, 102 n-bit bundle, 13, 103 Core_Logic / Memory, 14, 104 MISR, 15, 105 Comparator, 16 Signature (M vector), 17, 106
Signature (N vector), 18, 107 BIST_Controller, 20 Signature_Generator, 21 Signature.

Claims (5)

Test pattern generating means for generating a test pattern to be input to a semiconductor integrated circuit to be tested, and signal holding means for holding a compressed value of an output signal value output from the semiconductor integrated circuit to be tested to which the test pattern has been input And when the test pattern is input to the test target semiconductor integrated circuit, a signature holding that holds a signature that is a compressed value of an output signal value expected when the test target semiconductor integrated circuit is normal. Means for comparing and judging the compressed value of the output signal value held in the signal holding means and the signature held in the signature holding means; and the test pattern generating means, the signal holding means and A test circuit for a semiconductor integrated circuit, comprising:
A test circuit for a semiconductor integrated circuit, wherein the signature holding means includes a plurality of signatures respectively corresponding to a plurality of different test patterns. The signature holding means,
A first signature that is the signature when the test pattern is an N vector (N cycles) (N is a natural number);
A second signature, which is the signature when the test pattern is an M vector (M cycles) (M is a natural number having a relation of M <N);
With
The comparing and judging means,
The compressed value of the output signal value output from the semiconductor integrated circuit to be tested and held in the signal holding means based on the test pattern of the M vector input to the semiconductor integrated circuit to be tested and the second signature When the result of the comparison is good, the output is output from the semiconductor integrated circuit to be tested based on the test pattern of the N vector continuously input to the semiconductor integrated circuit to be tested. 2. The test circuit according to claim 1, wherein a comparison between the compressed value of the output signal value held in the signal holding means and the first signature is performed. The test control means,
Along with the determination of the output signal value output from the test target semiconductor integrated circuit based on the test pattern of the M vector input to the test target semiconductor integrated circuit, a comparison enable signal is output to the comparison determination unit;
If the result of the comparison is poor, the test is terminated,
When the result of the comparison determination is good, the output signal value output from the test target semiconductor integrated circuit based on the test pattern of the N vector continuously input to the test target semiconductor integrated circuit is determined. 3. The test circuit for a semiconductor integrated circuit according to claim 2, wherein a comparison signal is output to said comparison determination means. Test pattern generating means for generating a test pattern to be input to a semiconductor integrated circuit to be tested, and signal holding means for holding a compressed value of an output signal value output from the semiconductor integrated circuit to be tested to which the test pattern has been input When the output signal value held in the signal holding means and the test pattern are input to the semiconductor integrated circuit to be tested, an output signal expected when the semiconductor integrated circuit to be tested is normal In a test circuit of a semiconductor integrated circuit, comprising: a comparison / judgment unit for comparing and judging a signature which is a compressed value of a value; and a test control unit for controlling the test pattern generation unit, the signal holding unit and the comparison / judgment unit.
A test circuit for a semiconductor integrated circuit, further comprising signature generation means for generating a plurality of signatures respectively corresponding to a plurality of different test patterns based on control of the test control means. Test pattern generating means for generating a test pattern to be input to a semiconductor integrated circuit to be tested, and signal holding means for holding a compressed value of an output signal value output from the semiconductor integrated circuit to be tested to which the test pattern has been input When the output signal value held in the signal holding means and the test pattern are input to the semiconductor integrated circuit to be tested, an output signal expected when the semiconductor integrated circuit to be tested is normal In a test circuit of a semiconductor integrated circuit, comprising: a comparison / judgment unit for comparing and judging a signature which is a compressed value of a value; and a test control unit for controlling the test pattern generation unit, the signal holding unit and the comparison / judgment unit.
A test circuit for a semiconductor integrated circuit, wherein a plurality of signatures respectively corresponding to a plurality of different test patterns are input from an external terminal.

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