JP2004048429A - Power-on reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-on reset circuit capable of being stably operated regardless of the rise speed of a power voltage without needing any steady state current and suitable for a portable apparatus especially needing low power consumption. <P>SOLUTION: This power-on reset circuit is provided with a charging circuit 1, a CMOS inverter 2 to which the charging voltage of the capacitor of the charging circuit 1 is inputted, a flip flop 4 to be operated with the output signal of the CMOS inverter 2 as a clock, a transistor 5 to be conduction-controlled according to the output signal of the flip flop 4, and a reset pulse generating circuit 6 for generating a reset pulse until a power supply voltage exceeds a predetermined value. When a power is supplied, the voltage of the capacitor of the charging circuit 1 exceeds a predetermined voltage so that steady currents running through the reset pulse generating circuit 6 can be interrupted. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a latch circuit with reset and the like, and more particularly to a power-on reset circuit used for generating a reset pulse for setting an initial value of a latch when power is turned on.
[0002]
[Prior art]
FIG. 4 is a circuit diagram showing an example of a conventional power-on reset circuit. A CMOS circuit that outputs a reset pulse that includes a charging circuit 31 composed of a resistor R11 and a capacitor C11 connected in series, and a PMOS transistor P11 and an NMOS transistor N11 each of which receives a voltage charged in the capacitor C11 of the charging circuit 31 at its gate. It is composed of an inverter 32.
[0003]
When the power supply voltage is started at a speed sufficiently faster than the time constant determined by the resistor R11 and the capacitor C11, the charging voltage of the capacitor C11 is low immediately after the power is turned on, and the output of the CMOS inverter 32 becomes a high level. This High level becomes a reset signal, and reset of a latch circuit and the like in the semiconductor device is performed. When the time elapses and the capacitor C11 is charged and exceeds a half of the power supply voltage, the output of the CMOS inverter 32 becomes Low level and the reset is released.
[0004]
However, if the rising speed of the power supply voltage is slower than the time constant determined by the resistor R11 and the capacitor C11, the charging voltage of the capacitor C11 rises at the same time following the rising of the power supply voltage. Since the source-to-source voltage cannot exceed the threshold value and is always in the off state, the output of the CMOS inverter 32 does not output the High level, and the reset operation is not performed.
[0005]
Therefore, it is necessary to design the values of the resistor R11 and the capacitor C11 each time according to the rising speed of the power supply voltage of the device. Further, if the value is designed to be an unnecessarily large value, the time until the reset is released becomes long, and there is a problem that it takes time until the normal operation starts.
[0006]
To solve this problem, FIG. 5 shows another example of a conventional power-on reset circuit.
[0007]
A resistor circuit 41, which includes resistors R21 and R22 and generates a voltage proportional to the power supply voltage at point A, and a transistor Q15 which is diode-connected to the resistor R23 and applies a constant reference voltage to point B regardless of the power supply voltage. A power-on reset comprising a reference voltage circuit 42 for generating a voltage and a comparison circuit 43 composed of resistors R24 and R25 and transistors Q11, Q12, Q13 and Q14 and outputting a comparison result between points A and B to point C. Circuit. FIG. 6 shows the operation at points A, B and C with respect to the power supply voltage. Until the power supply voltage reaches the predetermined voltage, the output voltage at the point C is equal to the power supply voltage and is at the high level, but when the power supply voltage exceeds the predetermined value, it becomes low level. That is, a high-level reset pulse is output during the rising process at power-on, and the output goes low after the power supply voltage has settled to a steady value. In order for the output at the point C to be at the Low level, the transistor Q14 is on and the current must continue to flow through the resistor R25, and unlike the power-on reset circuit composed of CMOS in FIG. 4, a reset pulse is output. Later, a steady current is required.
[0008]
[Problems to be solved by the invention]
Conventionally, in the power-on reset circuit shown in FIG. 4, when the rise of the power supply voltage is slow, a reset pulse is not output, and there is a possibility that a stable operation is prevented. Further, in the power-on reset circuit shown in FIG. 5, there is a problem that power consumption increases because current continues to flow even in a steady state.
[0009]
The present invention has been made to solve the above-mentioned conventional problems, and can perform a stable operation irrespective of a rising speed of a power supply voltage, does not require a steady current consumption, and is particularly a portable device that requires a low power consumption. It is an object of the present invention to provide a power-on reset circuit that is suitable for:
[0010]
[Means for Solving the Problems]
In order to achieve this object, in a power-on reset circuit according to the present invention, a charging circuit in which a resistor and a capacitor are connected in series, a CMOS inverter to which a charging voltage of a capacitor in the charging circuit is input, and an output of the CMOS inverter A flip-flop that operates using a signal as a clock, a transistor whose conduction is controlled by an output signal of the flip-flop, and an operation current supplied through the transistor to generate a reset pulse until a power supply voltage exceeds a predetermined value And wherein the transistor is turned off when the charging voltage of the capacitor in the charging circuit exceeds a predetermined value when the power is turned on, and the steady current flowing to the reset pulse generating circuit is cut off. It is.
[0011]
With this configuration, a stable operation can be performed irrespective of the rising speed of the power supply voltage, and a power-on reset circuit that does not require steady current consumption can be obtained.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
The invention according to claim 1 of the present invention operates a charging circuit in which a resistor and a capacitor are connected in series, a CMOS inverter to which a charging voltage of a capacitor in the charging circuit is input, and an output signal of the CMOS inverter as a clock. A flip-flop, a transistor whose conduction is controlled by an output signal of the flip-flop, and a reset pulse generation circuit that is supplied with an operating current through the transistor and generates a reset pulse until a power supply voltage exceeds a predetermined value, When the charging voltage of the capacitor in the charging circuit exceeds a predetermined value when the power is turned on, the transistor is turned off and the steady current flowing to the reset pulse generating circuit is cut off.
[0013]
According to a second aspect of the present invention, there is provided a resistor circuit whose output voltage changes according to a power supply voltage, a reference voltage circuit that outputs a constant voltage regardless of the power supply voltage, and an output of each of the resistor circuit and the reference voltage circuit. Equipped with a reset pulse generation circuit consisting of a comparison circuit that compares the voltage, and has the function of reliably generating a reset pulse until the power supply voltage exceeds a predetermined value, regardless of the power supply voltage startup speed at power-on. Have.
[0014]
According to a third aspect of the present invention, the charging circuit includes an OR gate between the CMOS inverter and the flip-flop, wherein a sleep control signal is input to one input of the OR gate. Even if the time required for the rise of the sleep control signal has not elapsed, the fall of the sleep control signal cuts off the steady current flowing through the reset pulse generation circuit.
[0015]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
FIG. 1 is a circuit diagram of a power-on reset circuit according to the first embodiment. In FIG. 1, reference numeral 1 denotes a charging circuit including a resistor R1 and a capacitor C1, reference numeral 2 denotes a CMOS inverter to which the charging voltage of the capacitor C1 in the charging circuit 1 is input, and reference numeral 3 denotes a signal from the CMOS inverter 2 or a sleep control terminal SLEEP. 4 is a D flip-flop that operates using the output signal of the OR gate 3 as a clock, 5 is a PMOS transistor whose conduction is controlled by the output signal of the D flip-flop 4, and 6 is reset until the power supply voltage exceeds a predetermined value. This is a reset pulse generating circuit that generates a pulse. The reset pulse generating circuit 6 includes a resistor circuit 41, a reference voltage circuit 42, and a comparison circuit 43, similarly to the conventional power-on reset circuit of FIG. The output signal of the comparison circuit 43 of the reset pulse generation circuit 6 is output to the reset output terminal RESET via the AND gate A1.
[0017]
The operation of the power-on reset circuit according to the first embodiment configured as described above will be described below with reference to the drawings. FIG. 2 shows response waveforms of the voltage and the power supply current at each point when the power supply voltage is raised while the sleep control terminal SLEEP is fixed at a low level. After the power supply voltage terminal Vcc rises, the voltage at the point D of the charging circuit 1 slowly rises according to a time constant determined by the values of the resistor R1 and the capacitor C1. Until the voltage at the point D exceeds the switching voltage of the CMOS inverter 2, the points E and F are at the high level, the D flip-flop 4 is reset, and the point G is maintained at the low level, so that the PMOS transistor 5 is turned on. Yes, a current flows through the reset pulse generation circuit 6. The voltages at points A, B, and C inside the reset pulse generating circuit 6 operate exactly the same as in FIG. 6 referred to in the conventional example. Therefore, the reset output terminal RESET shows the same response as at the point C, and the output voltage of the reset output terminal RESET is equal to the power supply voltage and is at the High level until the power supply voltage reaches the predetermined voltage, but when the power supply voltage exceeds the predetermined value. It becomes Low level. That is, a high-level reset pulse is output during the rising process at power-on, and the output goes low after the power supply voltage has settled to a steady value. In addition, since the reset pulse is generated without depending on the rising speed of the power supply voltage and is performed until the power supply voltage reaches the predetermined voltage, a stable operation is guaranteed.
[0018]
The current Icc flowing through the power supply voltage terminal Vcc is the current consumed by the reset pulse generation circuit 6, and continues to flow even after the power supply voltage has settled to a steady value. However, if the voltage at the point D of the charging circuit 1 exceeds the switching voltage of the CMOS inverter 2 after a sufficient time has elapsed since the rise of the power supply voltage terminal Vcc, the points E and F become Low level and the D flip-flop 4 Since the point G, which is the output of the above, goes high, the PMOS transistor 5 is turned off, and no current flows to the reset pulse generating circuit 6. That is, when the power supply voltage rises, a reset pulse is obtained at the reset output terminal RESET by the action of the reset pulse generation circuit 6, and the current flowing through the reset pulse generation circuit 6 can be cut off after a sufficient time has elapsed.
[0019]
Next, FIG. 3 shows a response waveform of the voltage and the power supply current at each point when the sleep control terminal SLEEP is set to the High level immediately after the power supply voltage is started.
[0020]
The sleep control means that unnecessary current flowing in a circuit whose function is stopped according to an operation state is cut off every time in order to reduce power consumption in a portable device. Normally, after the power supply voltage of the internal circuit of the semiconductor device rises and enters a standby state, the sleep control terminal rises and the circuit operation starts. Regardless of the presence or absence of a power-on reset circuit, a semiconductor device for a portable device generally has a sleep control terminal.
[0021]
As shown in FIG. 3, in the power-on reset circuit of the present embodiment, by raising the sleep control terminal SLEEP to a high level, the voltage at the point D of the charging circuit 1 becomes higher than the switching voltage of the CMOS inverter 2 before the voltage at the point D exceeds the switching voltage of the CMOS inverter 2. The point becomes Low level, and the current flowing through the reset pulse generation circuit 6 can be cut off. That is, as compared with the case where the sleep control terminal SLEEP shown in FIG. 2 is fixed at the Low level, the period during which the current flows through the reset pulse generating circuit 6 can be shortened, so that further lower power consumption is achieved. Can be achieved.
[0022]
When the current flowing through the reset pulse generation circuit 6 is cut off after the power supply voltage has risen to a steady value, a high-level voltage is generated at the point C for a short period. The AND gate A1 has an effect of preventing a malfunction such that this signal is not output as a reset pulse to the reset output terminal RESET.
[0023]
In the present embodiment, the reference voltage circuit 42 is composed of the transistor Q15 which is diode-connected with the resistor R23. A voltage source may be used.
[0024]
【The invention's effect】
As described above, the present invention can reliably generate a reset pulse and operate stably until the power supply voltage exceeds a predetermined value, irrespective of the power supply voltage rising speed at the time of power-on. An excellent power-on reset circuit that does not require a current can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a power-on reset circuit according to a first embodiment of the present invention; FIG. 2 is a diagram illustrating the operation of FIG. 1 (when there is no sleep control);
FIG. 3 is a diagram for explaining the operation of FIG. 1 (when sleep control is performed)
FIG. 4 is a circuit diagram of a conventional power-on reset circuit. FIG. 5 is a circuit diagram of another conventional power-on reset circuit. FIG. 6 is a diagram for explaining the operation of FIG.
1, 31 charging circuit 2, 32 CMOS inverter 3 OR gate 4 D flip-flop 5 PMOS transistor 6 reset pulse generation circuit 41 resistance circuit 42 reference voltage circuit 43 comparison circuit

Claims (3)

A charging circuit in which a resistor and a capacitor are connected in series, a CMOS inverter to which a charging voltage of the capacitor in the charging circuit is input, a flip-flop that operates using an output signal of the CMOS inverter as a clock, and an output signal of the flip-flop A transistor whose conduction is controlled, and a reset pulse generating circuit that is supplied with an operating current through the transistor and generates a reset pulse until a power supply voltage exceeds a predetermined value. A power-on reset circuit, wherein the transistor is turned off when a charging voltage exceeds a predetermined value, and a steady current flowing through the reset pulse generation circuit is cut off. The reset pulse generation circuit includes a resistance circuit whose output voltage changes according to a power supply voltage, a reference voltage circuit that outputs a constant voltage regardless of the power supply voltage, and a comparison circuit that compares output voltages of the resistance circuit and the reference voltage circuit. 2. The power-on reset circuit according to claim 1, comprising a circuit. 3. The power-on reset circuit according to claim 2, further comprising an OR gate between the CMOS inverter and the flip-flop, wherein a sleep control signal is input to one input of the OR gate.

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