JP2004048008A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method that can prevent diffusion of the impurities contained in the gate electrode and improve the reliability of the gate insulation film and the durability of the hot carriers. <P>SOLUTION: A gate oxide film 36 and a P<SP>+</SP>-gate electrode 35 are formed on a N-type silicon substrate 1. A source/drain region 6 is formed at both sides of the P<SP>+</SP>-gate electrode 35. Nitrogen is doped in the gate oxide film 36 and P<SP>+</SP>-gate electrode 35, and a nitrogen doped region 30 is formed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of improving element characteristics by a nitrogen implantation technique and a method of manufacturing the same.
[0002]
[Prior art]
Conventionally, it has been known to form a source / drain junction surface of a MOS transistor shallowly in order to suppress a short channel effect of the MOS transistor. In order to suppress the short-channel effect of a P-channel MOS transistor (hereinafter, referred to as a PMOS transistor), it is effective to use a P-type or N-type doped electrode as an electrode material of the PMOS transistor. In order to suppress the short-channel effect of an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor), it is effective to use an N-doped electrode as an electrode material of the NMOS transistor. Further, utilizing this fact, in a CMOS (Complementary MOS) transistor including an NMOS transistor and a PMOS transistor, an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor) uses an N-type doped gate electrode. As a PMOS transistor, a dual gate CMOS transistor using a P-doped gate electrode has been proposed.
[0003]
Next, a method of forming a shallow source / drain junction surface of a PMOS transistor by a conventional technique will be described with reference to FIGS. 145 # to 147 # are diagrams showing a conventional PMOS transistor. 145 # to 147 #, 1 is an N-type silicon substrate, 2 is a gate oxide film formed on the N-type silicon substrate 1, 3 is a gate electrode formed on the gate oxide film 2, 4 is a gate electrode 3 5 is a side wall oxide film formed on the side wall of the gate electrode 3, 6 is a P-type source / drain region formed on the N-type silicon substrate 1 with a channel region 10 interposed therebetween, 7 Is an element isolation oxide film formed on the N-type silicon substrate 1. Conventionally, in order to form the junction surface of the source / drain region 6 shallowly, as shown in FIG.⁺) Boron fluoride ion (BF₂ ⁺) Was implanted into the source / drain regions 6. Alternatively, in order to prevent the boron ion channeling phenomenon, as shown in FIG.⁺) Or germanium ion (Ge⁺) Is implanted into the source / drain regions 6 to make the N-type silicon substrate 1 amorphous, and then, as shown in FIG.⁺) Was implanted into the source / drain regions 6.
[0004]
When the source / drain junction surface is formed shallow, a problem occurs in that the sheet resistance of the source / drain region increases. Therefore, as shown in FIG. It has been proposed to provide a silicide 8.
[0005]
FIG. 148 # shows an example of a conventional dual gate CMOS transistor. 148 #, 11 is a P-type silicon substrate, 12 is an element isolation oxide film formed on the P-type silicon substrate 11, 13 is an N well formed in the P-type silicon substrate 11, and 14 is a P-type silicon substrate 11. A P-well 15 formed therein is a gate oxide film formed on the P-type silicon substrate 11, and 16 is a polysilicon film formed on the gate oxide film 15, which is P-type doped. Reference numeral 17 denotes a polysilicon film formed on the gate oxide film 15, which is N-type doped. Reference numeral 18 denotes a tungsten silicide film provided on the polysilicon film 16 and the polysilicon film 17. By providing the tungsten silicide film 18 on the polysilicon film 16, a gate electrode having a polycide gate structure of the PMOS transistor is formed. Further, by providing the tungsten silicide film 18 on the polysilicon film 17, a gate electrode having a polycide gate structure of the NMOS transistor is formed. Reference numeral 19 denotes an oxide film provided on the gate electrodes of the PMOS transistor and the NMOS transistor, reference numeral 20 denotes a sidewall oxide film provided on the side walls of the gate electrodes of the PMOS transistor and the NMOS transistor, and reference numeral 21 denotes a P-type doped PMOS transistor. The source / drain regions are formed in the N well 13 with the gate electrode interposed therebetween. Reference numeral 22 denotes a source / drain region of an N-type doped NMOS transistor, which is formed in the P well 14 with a gate electrode interposed therebetween.
[0006]
Next, a method of manufacturing the dual gate CMOS transistor shown in FIG. First, an element isolation oxide film 12 is formed on the main surface of a P-type silicon substrate 11, and an N well 13 serving as a PMOS transistor formation region and a P well 14 serving as an NMOS transistor formation region are formed (FIG. 149). Next, an oxide film 15a # is formed, a polysilicon film 9 is deposited by a CVD method, and then a tungsten silicide film 18a # is deposited by a sputtering method (FIG. 150). Next, the formation region of the PMOS transistor is covered with a resist 25, and arsenic ions (As⁺) Is injected (FIG. 151１５). Next, as shown in FIG. 152 #, after removing the resist 25, the formation region of the NMOS transistor is covered with the resist 26, and boron fluoride ions are implanted into the polysilicon film 9 in the formation region of the PMOS transistor (FIG. 152 #). Next, after removing the resist 26, an oxide film is deposited by a CVD method (not shown), and the oxide film, the tungsten silicide film 18a # and the polysilicon film 9 are formed by photolithography and anisotropic etching to form a gate electrode. Then, an oxide film 19, a tungsten silicide film 18, and polysilicon films 16a # and 17a # are formed, respectively (FIG. 153 #). Next, an oxide film is deposited by a CVD method (not shown), and is etched back to form a sidewall oxide film 20 on the side wall of the gate electrode (FIG. 154). Next, the formation region of the PMOS transistor is covered with the resist 27, and arsenic ions are implanted into the formation region of the NMOS transistor (FIG. 155). Next, after removing the resist 27, the formation region of the NMOS transistor is covered with the resist 28, and boron fluoride ions are implanted into the formation region of the PMOS transistor (FIG. 156). Next, after the resist 28 is removed, the implanted ions are activated by performing a heat treatment, and the N-type doped polysilicon film 16, the P-type doped polysilicon film 17,⁺-Type source / drain regions 22 and P⁺Type source / drain regions 21 are formed to complete a dual gate CMOS transistor having a polycide gate structure (FIG. 157).
[0007]
FIG. 158 # shows another example of a conventional dual-gate CMOS transistor. In FIG. 158 #, reference numerals 11-17 and 20-22 are the same as or correspond to the conventional example shown in FIG. 148 #. Reference numeral 23 denotes a titanium silicide film formed on the source / drain regions 21 and 22 and the polysilicon films 16 and 17 in a self-aligned manner. In this manner, the structure obtained by silicidizing the surfaces of the polysilicon film and the source / drain regions serving as the gate electrode in a self-aligned manner is called a salicide (SALIDE: Self Aligned Silicide) structure, and has a source / drain junction surface. This is effective in suppressing the sheet resistance of the source / drain region, which becomes a problem when the layer is formed shallow. In particular, titanium silicide has a low specific resistance even among metal silicides and has good adhesiveness, and thus is a promising material for high heat-resistant wiring of semiconductor devices.
[0008]
Next, a method of manufacturing the dual gate CMOS transistor shown in FIG. First, an element isolation oxide film 12 is formed on the main surface of a P-type silicon substrate 11, and an N well 13 serving as a region for forming a PMOS transistor and a P well 14 serving as a region for forming an NMOS transistor are formed (FIG. 159). Next, after an oxide film 15a # and a polysilicon film are sequentially deposited on the N well 13 and the P well 14 (not shown), as shown in FIG. 160 #, the polysilicon film is formed by photolithography and anisotropic etching. Is patterned into the shape of a gate electrode to form a polysilicon film 8. Next, as shown in FIG. 161, after forming a sidewall oxide film 20 on the side wall of the polysilicon film 8, the formation region of the PMOS transistor is covered with a resist 25, and the source / drain region of the NMOS transistor and the polysilicon film 8 are formed. Arsenic ions are implanted (FIG. 161). Next, as shown in FIG. 162 #, after removing the resist 25, the formation region of the NMOS transistor is covered with the resist 26, and boron fluoride ions are implanted into the source / drain regions of the PMOS transistor and the polysilicon film 8 (FIG. 162). ). Next, after the resist 26 is removed, titanium is sputtered on the entire surface, and heat treatment is applied to cause a reaction between silicon and titanium, and a titanium silicide film 23 is formed on the source / drain regions 21 and 22 and the polysilicon films 16 and 17. Is formed (FIG. 163).
[0009]
As described above, in the dual gate CMOS transistor, in order to connect two gate electrodes made of different materials, that is, the P-type doped polysilicon film 16 and the N-type doped polysilicon film 17, A method is employed in which the gate electrode has a polycide gate structure of a polysilicon film and a tungsten silicide film, or the gate electrode is silicided. In particular, when a salicide structure is incorporated in a dual gate CMOS transistor, an increase in sheet resistance in a source / drain region which is problematic when a source / drain junction surface is formed shallow to suppress a short channel effect can be reduced. it can.
[0010]
In addition, as one of the semiconductor devices, there is a thin film transistor (hereinafter, referred to as a TFT) using polysilicon, which is an important device as a load transistor of a highly integrated SRAM or a driving transistor for a liquid crystal display. However, demands for higher integration and higher performance of TFT application elements require TFTs to be miniaturized, improved in electrical characteristics, and improved in reliability.
[0011]
Important issues for miniaturization of a TFT are suppression of a short channel effect caused by diffusion of impurity ions forming source / drain regions into a channel region, and improvement of hot carrier resistance.
[0012]
Next, the structure of a conventional TFT will be described. Here, for convenience, a P-channel MOS-TFT (hereinafter referred to as a PMOS-TFT) will be described as an example. FIG. 164 # is a sectional structural view showing a conventional PMOS-TFT. In the figure, 101 # is a semiconductor substrate, 102 # is an insulating film formed on the semiconductor substrate, 103 # is formed on the insulating film, a P-type doped gate electrode, and 104 # is formed on the gate electrode. A gate insulating film, 105 # is a polysilicon layer formed on the gate insulating film, 105a is a channel region formed in the polysilicon layer 105 #, 105b is a P-type source region formed in the polysilicon layer 105 #, 105c is a P-type drain region formed in the polysilicon layer. FIG. 165 # is a bird's eye view of the upper part of the TFT gate electrode 103 # shown in FIG.
[0013]
Next, a method of manufacturing the TFT shown in FIG. First, a high-temperature oxide film is deposited on the semiconductor substrate 101 by a CVD method or the like to form an insulating film 102 #. Next, a non-doped polysilicon layer 103a is deposited on the insulating film 102 # by a CVD method or the like, and a P-type doped polysilicon layer 103a is implanted by implanting P-type ions such as boron (B) @ ions. Is formed (FIG. 166). Next, resist 107 # is patterned in the shape of the gate electrode, and polysilicon layer 103a is anisotropically etched to form gate electrode 103b (FIG. 167 #). Next, after removing the resist 107 #, a gate insulating film 104 # is formed by gate oxidation, a non-doped polysilicon layer is deposited on the gate insulating film 104 # by a CVD method or the like, and then arsenic ( As) is ion-implanted (not shown). Next, after depositing a resist and performing patterning using a photoengraving process so as to leave a region to be a channel region, a source region, and a drain region, anisotropic etching is performed using the resist as a mask to obtain a desired shape. A polysilicon layer 105 # is formed (FIG. 168 #). Next, after removing the resist formed in the previous step, a resist 108 # is formed again on the channel region, and boron fluoride (FB2 #) is ion-implanted using the resist 108 # as a mask (FIG. 169 #). Next, a heat treatment for activating the implanted impurities is performed to form the gate electrode 103 #, the source region 105b, and the drain region 105c, and the TFT shown in FIG. 164 # is completed.
[0014]
In addition, there is a nonvolatile semiconductor memory device as one of the semiconductor devices. Among them, an EEPROM (Electrically-Erasable and Programmable-Read-Only-Only Memory) that can freely program data and that can electrically write and erase data is known. ing. This EEPROM has the advantage that both writing and erasing can be performed electrically, but it has the disadvantage that high integration is difficult because two transistors are required for the memory cells. Therefore, a flash EEPROM has conventionally been proposed in which a memory cell is formed of one transistor, and in which written information charges can be collectively erased. These are disclosed, for example, in US Pat. No. 4,868,619.
[0015]
FIG. 170 is a sectional view showing a conventional stacked gate type flash EEPROM. The structure of a conventional flash EEPROM will be described with reference to FIG.
[0016]
Referring to FIG. 170 #, a drain region 208 and a source region 209 # are formed on a main surface of a P-type silicon substrate 201 # so as to sandwich a channel region 215 # at a predetermined interval. A floating gate electrode 203 # is formed on channel region 215 # via a thin oxide film 202 # having a thickness of about 100%. A control gate electrode 205 # is formed on floating gate electrode 203 # via an interlayer insulating film 204 # so as to be electrically separated from floating gate electrode 203 #. Floating gate electrode 203 # and control gate electrode 205 # are formed of a polysilicon layer, and are formed by implantation of boron (B) or the like.⁺Is doped. Thermal oxide film 216 # is formed to cover P-type silicon substrate 201 #, floating gate electrode 203 # made of a polysilicon layer, and control gate electrode 205 #. A smooth coat film 212 # made of an oxide film or the like is formed on thermal oxide film 216 #. Reference numeral 214 denotes a wiring layer made of an aluminum alloy or the like.
[0017]
Next, the operation of the flash EEPROM will be described with reference to FIG. First, in a write operation of a flash EEPROM using CHE (Channel \ Electron), a voltage V of 6V to 8V is applied to the drain region 208 #._D1. A voltage V of 10 V to 15 V is applied to the control gate electrode 205 #._G1Is applied. This voltage V_D1And V_G1, A portion of electrons having high energy generated near the drain region 208 # and the oxide film 202 # are attracted to and injected into the floating gate electrode 203 # by an electric field caused by the voltage VG1 applied to the control gate electrode 205 #. Is done. When electrons are accumulated in floating gate electrode 203 # in this manner, the threshold voltage V_THBecomes higher than a predetermined value. This threshold voltage V_THIs higher than a predetermined value, is a written state, and is referred to as a "0" state.
[0018]
A write operation of a flash EEPROM using SHE (Substrate \ Hot \ Electron) will be described with reference to FIG. For example, in an N-channel type flash EEPROM formed in a P well 222 # in an N-type silicon substrate 221 #, a drain region 208 # and a source region 209 # are grounded, and a voltage V of 10V to 15V is applied to a control gate electrode 205 #._G2Is applied. Further, a voltage V of -5V to -10V is applied to the substrate electrode 223 #._B2Is applied. This voltage V_G2And V_B2, A forward bias is applied to the PN junction formed by the N-type silicon substrate 221 # and the P-well 222 #, and an on-current is generated. Some of the electrons are applied to the voltage V applied to the control gate gate electrode 205 #._G2Is attracted to the floating gate electrode 203 # and injected.
[0019]
A write operation of a flash EEPROM using FN (Fowler-Nordheim) tunnel phenomenon will be described with reference to FIG. For example, in the FN writing at the drain end, the voltage V of −10 V to −12 V is applied to the drain region 208 #._D3Is applied, control gate electrode 205 # is held at ground potential, and source region 209 # is held in a floating state. Voltage V applied to drain region 208 #_D3, Electrons in floating gate electrode 203 # pass through thin oxide film 202 # by FN tunnel phenomenon. By accumulating electrons in floating gate electrode 203 # in this manner, threshold voltage V_THWill be higher.
[0020]
Next, the erasing operation will be described. A voltage V of 10 V to 12 V is applied to the source region 209 #._SIs applied, the control gate electrode 205 # is kept at the ground potential, and the drain region 208 # is kept in a floating state. Voltage V applied to source region 209 #_S, Electrons in the floating gate electrode 203 # pass through the thin oxide film 202 # by the FN tunnel phenomenon. The electrons in the floating gate electrode 203 are extracted in this manner, so that the threshold voltage V_THBecomes lower. The state where the threshold voltage VTH becomes lower than the predetermined value is the erased state and is called the state of "1".
[0021]
Further, in the read operation, a voltage V of 5 V is applied to the control gate electrode 205 #._G4, A voltage V of 1V to 2V is applied to the drain region 208 #._D4Is applied. At this time, the above-described determination of “1” or “0” is performed depending on whether a current flows through the channel region of the control gate transistor, that is, whether the control gate transistor is on or off. Thus, information is read.
[0022]
Further, a coupling ratio in the flash EEPROM will be described with reference to FIG. Since the flash EEPROM has a two-layer gate electrode, the voltage applied to the control gate electrode 205 # is applied to the channel region via the floating gate electrode 203 #. That is, even if the same potential is applied to each terminal while the amount of charge stored in floating gate electrode 203 # is the same, the potential of floating gate electrode 203 # differs depending on the structure of interlayer insulating film 204 # or oxide film 202. Potential V of floating gate electrode 203 #_FGIs the control gate voltage V_CG, Source voltage V_SAnd drain voltage V_DIn addition to the potential applied to each terminal such as, the threshold voltage V_TH, The capacitance of floating gate electrode 203 # and control gate electrode 205 # (C_FC), The capacitance between floating gate electrode 203 # and substrate 201 # (C_FB), The capacitance between floating gate electrode 203 # and source region 209 # (C_FS) And the capacitance between floating gate electrode 203 and drain region 208 # (C_FD) And is approximately given by:
[0023]
V_FG= C_FCV_CG/ C_TOTAL+ C_FDV_D/ C_TOTAL+ (C_FD+ C_FB) V_S/ C_TOTAL+ C_FBV_TH/ C_TOTAL+ Q_FG/ C_TOTAL… (1)
Q_FG= C_FC(V_FG-V_CG) + C_FD(V_FG-V_D) + C_FS(V_FG-V_S) + C_FB(V_FG-V_TH-V_S)
Where C_TOTAL= C_FC+ C_FD+ C_FS+ C_FB
From the equation (1), the potential V of the control gate electrode 203 # is obtained._CGIs C, called the coupling ratio_FC/ C_TOTALMultiplied by affects potential VFG of floating gate electrode 203. That is, when the coupling ratio is increased, the potential of floating gate electrode 203 # is increased even if the potential applied to control gate electrode 205 # is the same. Therefore, when the coupling ratio is large, the potential of floating gate electrode 203 # is increased even if the same potential is applied to control gate electrode 205 #. Therefore, as the coupling ratio increases, it becomes easier to control the transistor operation by the potential applied to control gate electrode 205 #.
[0024]
In the above-described semiconductor device, when data is written and erased by using the FN tunnel phenomenon, the oxide film 202 # is broken at a certain probability, so that the reliability of the element is reduced. Further, by tunneling electrons through the oxide film 202 #, electrons injected into the oxide film 202 # are trapped in the oxide film 202 # with a certain probability, and an interface state is generated at the interface between the silicon substrate 201 # and the oxide film 202 #. I do. Due to the generated interface states, the reliability of the oxide film 202 # is reduced, and the threshold voltage is changed and the current driving capability is reduced. In addition, since a high potential is applied to the floating gate electrode 203 #, the source region 209 #, or the drain region 208 # when data is written or erased, a high potential is applied to the interface between the drain region 208 # and the oxide film 202 # or between the source region 209 and the oxide film 202 #. An electric field is generated. In particular, since adjacent memory cells share the drain region 208 #, a potential is also applied to the drain region 208 # of the non-selected cell at the time of writing data. Since control gate electrode 205 # in a cell non-selected state is held at the ground potential, a high electric field is generated between floating gate electrode 203 # and drain region 208 # in such a non-selected cell, and this high electric field 175. Tunneling between bands occurs as shown in FIG. 175 #, and electron / hole pairs are generated. The generated holes are injected into the oxide film 202 # with a certain probability, and form an interface level at the interface between the silicon substrate 201 # and the oxide film 202 #, thereby lowering the reliability of the oxide film 202 #.
[0025]
In order to prevent such a decrease in reliability of oxide film 202 #, there has been proposed a method of suppressing generation of interface states at the interface between silicon substrate 201 # and oxide film 202 #. After the oxide film is formed, an RTN (Rapid Thermal Nitridation) process is performed so that nitrogen is contained in the oxide film 202. Since nitrogen terminates dangling bonds in the oxide film 202, electric charges are trapped in the oxide film 202 #. Can be prevented. RTN processing refers to, for example, ammonia (NH₃This is a process in which annealing is performed for a very short time in a reactive gas atmosphere containing nitrogen, such as). Thereby, nitrogen is taken into silicon substrate 201 # and oxide film 202 #.
[0026]
FIG. 176 # shows a conventional embedded channel type flash EEPROM. In FIG. 176 #, 201 # to 205 #, 208 #, 209 #, 215 #, 216 # indicate the same or corresponding parts as in FIG. 170 #. 217 # is an N-type impurity layer formed in the channel region 215 #, and 218 # is a P-type impurity layer formed below the N-type impurity layer 217 #. The N-type impurity layer 217 # and the P-type impurity layer 218 # form a buried channel layer. In such a buried channel type flash EEPROM, unlike the surface channel type flash EEPROM, a high electric field is not applied between the source region 209 # or the drain region 208 # and the oxide film 202 #. The occurrence of tunneling can be suppressed. Therefore, at the time of data writing or erasing, generation of holes due to band-to-band tunneling can be prevented, and injection of holes into oxide film 202 # can be prevented.
[0027]
[Patent Document 1]
JP-A-3-46238
[0028]
[Patent Document 2]
JP-A-3-44075
[0029]
[Patent Document 3]
JP-A-62-177919
[0030]
[Problems to be solved by the invention]
The conventional MOS transistor has the following problems.
[0031]
Conventionally, a source / drain region of a PMOS transistor has been formed by implanting boron fluoride ions to form a shallow source / drain junction surface. Therefore, there has been a problem that fluorine contained in boron fluoride ions hinders the reaction between titanium and silicon at the time of forming titanium silicide, and a good titanium silicide film cannot be formed.
[0032]
Further, in the conventional method of forming the source / drain regions of the PMOS transistor, a high-temperature heat treatment for crystal recovery is required because the source / drain regions are pre-amorphized by silicon ions or germanium ions. Therefore, there is a problem that the reduction of the heat treatment, which is a condition for forming the source / drain junction surface shallow, causes insufficient recovery of the crystal and increases the junction leakage current.
[0033]
In addition, the heat treatment must be reduced in order to form the source / drain junction surface of the NMOS transistor shallowly. As a result, the recovery of the crystal becomes insufficient and the junction leakage current increases.
[0034]
Furthermore, the conventional method of forming source / drain regions has a problem in that impurities implanted by heat treatment for activation diffuse in both the PMOS transistor and the NMOS transistor, making it difficult to form a shallow junction. .
[0035]
Also, in the dual gate CMOS transistor, during the heat treatment process, boron ions penetrate through the gate oxide film from the P-type doped gate electrode of the PMOS transistor and enter the channel region, thereby changing the threshold voltage of the transistor. was there.
[0036]
In particular, in a dual gate CMOS transistor having a polycide gate structure, arsenic ions are diffused from the N-type doped gate electrode and boron ions are diffused from the P-type doped gate electrode through the silicide during the heat treatment process. Accordingly, there is a problem that the work function of the gate electrode is changed and the threshold voltage of the transistor is changed.
[0037]
Further, in conventional NMOS transistors and PMOS transistors, the gate electrodes are doped with impurities, so that the diffusion of the impurities during the heat treatment process deteriorates the gate oxide film. However, there was a problem that sufficient was not obtained.
[0038]
In addition, the conventional TFT has the following problems with recent miniaturization.
[0039]
Due to the heat treatment after the source / drain implantation, impurities in the source region and the drain region are thermally diffused and diffused into the channel region, so that punch-through occurs and the original transistor operation is not performed.
[0040]
When the electric field applied to the drain end is high in the off state, hot carriers are generated and the reliability of the device is degraded.
[0041]
The conventional flash EEPROM has the following problems.
Conventionally, RTN processing has been used as a method for introducing nitrogen into oxide film 202 #. Since the RTN process is often performed in an ammonia atmosphere, as shown in FIG. 177 #, the oxide film 202 # contains not only nitrogen but also hydrogen. There is a problem that the reliability of the oxide film 202 # is reduced by the doping of hydrogen. Further, there is a problem in that hydrogen and nitrogen are also injected into the silicon substrate 201 # due to the manufacturing method.
[0042]
Further, in the RTN process, the silicon substrate 201 # is exposed to a high temperature of about 1100 [deg.] C. Further, since the process is performed in a short time, the temperature around the silicon substrate 201 # is rapidly changed. For this reason, there has been a problem that a temperature distribution is generated in the plane of the silicon substrate 201, and a slit-like defect is generated due to a difference in expansion coefficient.
[0043]
In a conventional flash EEPROM, an impurity such as boron is implanted into the control gate electrode or the floating gate electrode. Therefore, the implanted impurity penetrates into the interlayer insulating film 204 # or the oxide film 202 # during the heat treatment process, and There is a problem that the film quality of the film 204 # or the oxide film 202 # is deteriorated.
[0044]
In particular, when boron penetrates oxide film 202 # and enters channel region 215 #, there is a problem that the threshold voltage of the flash EEPROM varies.
[0045]
Further, the potential applied to control gate electrode 205 # is applied to floating gate electrode 203 # in a form multiplied by the coupling ratio. Therefore, it is necessary to apply a potential to the control gate electrode 205 # in anticipation of a decrease in potential due to the coupling ratio. For example, when writing is performed in a device having a coupling ratio of 0.5%, the floating gate electrode 203 # If 5V is applied, a voltage of about 10V must be applied to the control gate electrode 205 #. In other words, in order to guarantee the same operation, it is necessary to apply a higher voltage to the control gate electrode 205 as the coupling ratio is smaller, and it is difficult to reduce the power supply voltage of the flash EEPROM.
[0046]
Conventionally, in order to improve the coupling ratio, a method of using a nitride film having a higher dielectric constant than an oxide film as the interlayer insulating film 204 # has been proposed. There is a problem that becomes large. In order to prevent the problem of the leakage current, a composite film of a nitride film and an oxide film may be used as the interlayer insulating film 204 #. However, the interlayer insulating film 204 # becomes thicker and the coupling ratio cannot be increased. was there.
[0047]
Further, when considering miniaturization of an element, it is difficult to form a shallow source / drain junction due to diffusion of impurities implanted by source / drain implantation, so that there is a problem of a short channel effect such as punch-through. there were.
[0048]
In a conventional buried channel type flash EEPROM, it is difficult to form a buried channel layer shallow due to diffusion of impurities implanted into the buried channel region. There is a problem in that it becomes impossible to control the drain-to-drain current, and the source-drain breakdown voltage characteristics such as punch-through deteriorate.
[0049]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is intended to form a shallow source / drain junction surface, prevent lateral diffusion of impurities implanted in a source / drain region, and dope a gate electrode. Device capable of suppressing penetration of boron ions, suppressing diffusion of impurities doped into the gate electrode, improving hot carrier resistance, improving reliability of oxide film and interlayer insulating film, and reducing power supply voltage and manufacturing thereof The aim is to provide a method.
[0050]
[Means for Solving the Problems]
The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first electrode of a first conductivity type provided on the first insulating film, A source / drain region provided on the semiconductor substrate with a first electrode interposed therebetween, wherein the first insulating film and the first electrode are doped with nitrogen.
[0051]
Further, the nitrogen concentration peak in a depth direction from the first electrode toward the semiconductor substrate exists at a position shallower than an interface between the semiconductor substrate and the first insulating film.
[0052]
Still another feature is that the nitrogen concentration peak exists in the first insulating film.
[0053]
Still further, the first conductivity type is a P-type or an N-type.
[0054]
Still another feature is that the inside of the source / drain region is doped with nitrogen.
[0055]
Still further, a second insulating film is provided on the first electrode, and a second electrode is provided on the second insulating film, wherein the second insulating film is doped with nitrogen. It is characterized by having.
[0056]
Still another feature is that the second electrode is doped with nitrogen.
[0057]
In addition, a semiconductor device according to the present invention includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first electrode formed on the first insulating film, The semiconductor device includes a source / drain region provided on the semiconductor substrate with an electrode interposed therebetween, and a region doped with nitrogen in the source / drain region.
[0058]
Further, a second insulating film is provided on the first electrode, and a second electrode is provided on the second insulating film.
[0059]
Still further, the source / drain region is provided from the main surface of the semiconductor substrate to the inside of the semiconductor substrate, and the nitrogen-doped region is provided from the main surface to the inside of the source / drain region. It is characterized by being provided.
[0060]
Further, a semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type, a first insulating film formed on the semiconductor substrate, and a first electrode formed on the first insulating film. A source / drain region of a second conductivity type provided on the semiconductor substrate with the first electrode interposed therebetween; and a first of a second conductivity type provided on the semiconductor substrate between the source / drain regions. An impurity region and a region containing nitrogen inside the first impurity region are provided.
[0061]
Further, a second insulating film is provided on the first electrode, and a second electrode is provided on the second insulating film.
[0062]
Still another feature is that an impurity region of a first conductivity type is provided below the first impurity region.
[0063]
Further, a semiconductor device according to the present invention includes a semiconductor substrate having a first conductivity type region and a second conductivity type region, a first gate insulating film formed on the first conductivity type region, A first gate electrode formed on a first gate insulating film and doped to a second conductivity type; and a second conductivity type formed in the region of the first conductivity type with the first gate electrode interposed therebetween. Source / drain regions, a second gate electrode formed on the second conductivity type region and doped with the first conductivity type, and the first conductivity type region sandwiching the second gate electrode. And a first conductivity type source / drain region formed in the first gate electrode, the first gate electrode, the second gate electrode, the first gate insulating film, and the second gate electrode are doped with nitrogen. It is characterized by the following.
[0064]
Further, the first conductivity type is P-type, and the second conductivity type is N-type.
[0065]
Further, a semiconductor device according to the present invention includes a semiconductor substrate having a first conductivity type region and a second conductivity type region, a first gate insulating film formed on the first conductivity type region, A first gate electrode formed on a first gate insulating film and having a laminated structure of a polysilicon film doped with a second conductivity type and a metal silicide film; and a first gate electrode sandwiching the first gate electrode. A second conductivity type source / drain region formed in the one conductivity type region, a second gate insulating film formed on the second conductivity type region, and formed on the second gate insulating film And a second gate electrode having a stacked structure of a polysilicon film doped with a first conductivity type and a metal silicide film, and formed in a region of the first conductivity type with the second gate electrode interposed therebetween. A source / drain region of a first conductivity type; The first gate electrode and the second gate electrode are doped with nitrogen, and the nitrogen concentration peaks in the first gate electrode and the second gate electrode are present at the interface between the polysilicon film and the metal silicide film. It is characterized by doing.
[0066]
Further, the first gate insulating film and the second gate insulating film are doped with nitrogen.
[0067]
Further, in the semiconductor device according to the present invention, an active layer in which a source / drain region is formed sandwiching a channel region, and a region doped with nitrogen including a junction surface between the channel region and the source / drain region is formed And an insulating film formed on the first surface of the active layer, and a gate electrode formed at a position facing the channel region via the insulating film.
[0068]
In addition, the semiconductor device according to the present invention includes an active layer having a source / drain region formed with a channel region interposed therebetween, an insulating film formed on a first surface of the active layer, A gate electrode formed at a position facing the channel region, wherein the active layer and the insulating film are doped with nitrogen.
[0069]
In addition, the semiconductor device according to the present invention includes an active layer having a source / drain region formed with a channel region interposed therebetween, an insulating film formed on a first surface of the active layer, A gate electrode formed at a position facing the channel region, wherein the gate electrode and the insulating film are doped with nitrogen.
[0070]
Further, the method for manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a semiconductor substrate, a step of forming an electrode layer on the insulating film, a step of ion-implanting nitrogen into the electrode, A step of injecting impurities into the electrode layer; a step of performing a heat treatment after the steps of injecting nitrogen into the electrode layer and the step of injecting impurities to deposit nitrogen in the insulating film. .
[0071]
Further, in the nitrogen ion implantation, the projected range RP of the nitrogen is set at a position where the distance from the interface between the insulating film and the electrode layer is 5 × {RP} or more, where the standard deviation is 偏差 RP. It is characterized by being set.
[0072]
Further, in the method for manufacturing a semiconductor device according to the present invention, a step of forming a first insulating film on a semiconductor substrate; a step of forming an electrode layer on the first insulating film; A step of implanting ions, a step of implanting impurities into the electrode layer, a step of forming a second insulating layer on the electrode layer after the steps of implanting nitrogen and the impurities, and a step of forming the second insulating layer A heat treatment after the step of forming nitrogen, and a step of depositing nitrogen in the first insulating layer and the second insulating layer.
[0073]
Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate electrode on a semiconductor substrate, implanting nitrogen ions into the semiconductor substrate, and forming a nitrogen-doped region in the semiconductor substrate with the gate electrode interposed therebetween And implanting impurity ions having a range greater than the range of the nitrogen ions into the semiconductor substrate to form source / drain regions including the nitrogen-doped region. .
[0074]
Further, the nitrogen ions are implanted into the semiconductor substrate at an angle smaller than 90 degrees with respect to the main surface of the semiconductor substrate.
[0075]
Further, in the method for manufacturing a semiconductor device according to the present invention, a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and the step of sandwiching the gate electrode and the gate electrode Implanting nitrogen ions into the semiconductor substrate, doping the gate electrode with nitrogen, and forming a nitrogen-doped region in the semiconductor substrate; and removing impurity ions having a range larger than the range of the nitrogen ions. Implanting the gate electrode and the gate electrode into the semiconductor substrate with the gate electrode interposed therebetween, doping the gate electrode with impurities, and forming source / drain regions including the nitrogen-doped region; and forming the gate electrode and the semiconductor substrate. Performing a heat treatment after the step of implanting impurities into the gate insulating film. And butterflies.
[0076]
In the method of manufacturing a semiconductor device according to the present invention, a gate insulating film is formed on a semiconductor substrate having a first conductivity type region and a second conductivity type region, and a gate electrode layer is formed on the gate insulating film. In the method for manufacturing a semiconductor device according to the present invention, a step of ion-implanting nitrogen into the entire surface of the gate electrode layer and a step of introducing a second conductivity type impurity into the gate electrode layer formed on the first conductivity type region. Introducing a first conductivity type impurity into the gate electrode layer formed on the second conductivity type region; and introducing nitrogen and impurities into the gate electrode layer and then performing a heat treatment to form the gate insulating layer. And depositing nitrogen in the film.
[0077]
In the method of manufacturing a semiconductor device according to the present invention, a gate insulating film is formed on a semiconductor substrate having a first conductivity type region and a second conductivity type region, and a polysilicon film is formed on the gate insulating film. A method of manufacturing a semiconductor device in which a metal silicide film is formed on the polysilicon film, wherein nitrogen is ion-implanted at an interface between the polysilicon film and the metal silicide film; Introducing a second conductivity type impurity into the polysilicon film formed on the substrate; and introducing a first conductivity type impurity into the polysilicon film formed on the second conductivity type region. A step of performing a heat treatment after the step of introducing nitrogen and impurities into the polysilicon film to precipitate nitrogen in the gate insulating film.
[0078]
Further, in the method of manufacturing a semiconductor device according to the present invention, it is preferable that a polysilicon film to be an active layer, a first insulating film formed on a first surface of the active layer, and the first insulating film be interposed. A method of manufacturing a semiconductor device having a gate electrode formed by performing a step of implanting nitrogen ions into the polysilicon film by an oblique rotation implantation method; and a step of implanting nitrogen ions into the polysilicon film. / Implanting impurities into the drain region.
[0079]
The method for manufacturing a semiconductor device according to the present invention may further include a step of implanting nitrogen into a gate electrode, a step of forming a gate insulating film on the gate electrode after the step of implanting nitrogen ions, A step of forming a polysilicon film to be an active layer on the insulating film; and a step of performing a heat treatment after the step of forming the polysilicon film to deposit nitrogen in the gate insulating film. And
[0080]
In the semiconductor device according to the present invention, since the gate electrode is doped with nitrogen, when introducing the impurity into the gate electrode, the nitrogen first occupies the holes that are diffusion paths of the impurity. Spreading is suppressed. Therefore, the impurity is prevented from entering the gate insulating film or penetrating the gate insulating film.
[0081]
Further, since nitrogen is precipitated in the gate insulating film, the interface state between the gate insulating film and the semiconductor substrate is reduced, and the reliability and hot carrier resistance of the gate insulating film of the semiconductor device are improved. In the case where the semiconductor device is a semiconductor memory device capable of electrically writing and erasing data, holes generated by band-to-band tunneling are injected into a gate insulating film during data writing or erasing, or electrons are emitted. Tunneling the insulating film can prevent generation of an interface level at the interface between the gate insulating film and the semiconductor substrate.
[0082]
Further, when nitrogen is implanted into the gate electrode and a heat treatment is performed after an interlayer insulating film is formed over the gate electrode, nitrogen also precipitates in the interlayer insulating film. This nitrogen prevents the formation of a level in the interlayer insulating film during the operation of the element, so that the reliability of the interlayer insulating film can be improved. Since the film quality of the interlayer insulating film can be reduced by improving the film quality, the coupling ratio can be improved and the potential applied to the control gate electrode can be reduced.
[0083]
In the semiconductor device according to the present invention, since the source / drain regions are doped with nitrogen, the junction surface between the source / drain regions is formed shallow due to the effect of preventing diffusion of nitrogen impurities. Therefore, a short channel effect such as punch-through can be suppressed, and the element can be miniaturized. Further, by providing the nitrogen doping region so as to include the junction surface between the channel region and the source / drain region, the lateral diffusion of impurities can be further suppressed. In the case where the semiconductor device is a semiconductor memory device which can be electrically written and erased, diffusion of impurities for forming source / drain regions is suppressed, so that the source / drain regions and the gate electrode overlap. Therefore, the capacitance between the control gate electrode and the source / drain regions can be reduced. Therefore, the coupling ratio can be increased, and the potential applied to the control gate electrode can be reduced.
[0084]
In the semiconductor device according to the present invention, nitrogen is doped into a gate electrode having a two-layer structure of a metal silicide film and a polysilicon film, and a nitrogen concentration peak exists at an interface between the polysilicon film and the metal silicide film. Therefore, diffusion of impurities doped into the polysilicon film into the metal silicide film is suppressed. Therefore, a change in the work function of the gate electrode in the positive or negative direction is suppressed, and a change in the threshold voltage due to a change in the work function is suppressed.
[0085]
Further, when nitrogen is doped into the channel region of the semiconductor substrate, diffusion of impurities for forming a buried channel is suppressed. Therefore, since the buried channel layer can be formed thin, punch-through caused by the buried channel layer having a large thickness is suppressed. Also, by forming a region to be doped with nitrogen inside the buried channel layer, defects caused by the implantation of nitrogen cannot be formed at the bonding surface between the buried channel layer and the semiconductor substrate. It does not occur.
[0086]
Further, in the method of manufacturing a semiconductor device according to the present invention, nitrogen is ion-implanted into a gate electrode, and then heat treatment is performed to precipitate nitrogen in the gate insulating film. That is, nitrogen can be injected into the gate insulating film without damaging the gate insulating film, and hydrogen is not contained in the gate insulating film. Therefore, a nitrogen effect can be provided without being adversely affected by hydrogen.
[0087]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
Next, an embodiment of the present invention will be described. FIG. 1 is a sectional view showing a PMOS transistor according to a first embodiment of the present invention. In FIG. 1, reference numerals 1, 4 to 7, and 10 are the same as or correspond to those of the conventional FIG. The shaded area 30 indicates a nitrogen doping region, and P⁺It exists in the -shaped gate electrode 35 and the gate oxide film 36. FIG. 2 shows the PMOS transistor P shown in FIG.⁺FIG. 4 is a diagram showing profiles in the depth direction of a -shaped gate electrode 35 and a gate oxide film 36. FIG. 2 shows that nitrogen is deposited in the gate oxide film 36. Here, the precipitation of nitrogen refers to a state where nitrogen is trapped at a certain position and the concentration increases.
[0088]
Next, a manufacturing process of the PMOS transistor shown in FIG. 1 will be described. First, after an element isolation oxide film 7 is formed on the N-type silicon substrate 1 by a normal element isolation step, an oxide film 36a # of about 100 DEG is formed by thermal oxidation, and a polysilicon film 35a # of about 2000 DEG is formed by a CVD method. (FIG. 3). Next, nitrogen ions are applied at 20 keV and 4 × 10 so that the range center is located above the polysilicon film 35a #.^Fifteen/ Cm²Inject under the conditions of (FIG. 4). Next, boron ions are applied to the polysilicon film 35a # at 20 keV and 4 × 10^Fifteen/ Cm²Inject under the conditions of (FIG. 5). Next, an oxide film of about 2000 ° is deposited by a CVD method (not shown), and the oxide film and the polysilicon film 35a ′ are patterned into the shape of the gate electrode by using photolithography and anisotropic etching. 4 and a gate electrode 35b # are formed (FIG. 6). Next, an oxide film of about 800 ° is deposited by a CVD method (not shown), and the side wall oxide film 5 and the gate oxide film 36b # are formed by etching back. 20 keV, 4 × 10^Fifteen/ Cm²Inject under the condition of (FIG. 7). Then, the source / drain region 6 and the gate electrode 35 shown in FIG. 1 are formed by activating the implanted impurities by applying a heat treatment at 850 ° C. for about 20 minutes. At the time of this heat treatment, nitrogen doped above gate electrode 35b # is thermally diffused, but nitrogen is segregated in gate oxide film 36b #, and as shown in FIG. A film 36 is formed.
[0089]
Here, the nitrogen injection conditions during the above manufacturing process will be described in more detail. The projected range RP of nitrogen is P, given its standard deviation as △ RP.⁺The gate electrode 35 is set so as to be located in the gate electrode 35 at a position above the position of 5 × {RP} from the interface between the gate electrode 35 and the gate oxide film 36 (FIG. 8). If the position is set below this condition, the gate oxide film 36 may be damaged by nitrogen implantation.
[0090]
In the above description, the doping of the gate electrode 35 and the doping of the source / drain region 6 are performed in separate steps. However, the doping of the gate electrode 35 is performed together with the doping of the source / drain region 6. No problem. For doping the gate electrode, boron fluoride may be ion-implanted. Further, in the above embodiment, the case where only the PMOS transistor is used has been described. However, the PMOS transistor may be added to a part of the CMOS transistor, or the manufacturing process of the PMOS transistor may be added to a part of the manufacturing process of the CMOS transistor. Good.
[0091]
Next, effects of the invention in the present embodiment will be described. Since the gate electrode 35 is doped with nitrogen, diffusion of boron is suppressed. In other words, since nitrogen has the same vacancy diffusion mechanism as boron and has a larger diffusion coefficient than boron, nitrogen occupies the vacancy that is the diffusion path first by interdiffusing nitrogen with boron. As a result, diffusion of boron can be suppressed, and as a result, penetration of boron into the channel region 10 can be suppressed, and fluctuation of the threshold voltage can be effectively suppressed. Further, by doping nitrogen using an ion implantation method, the depth and concentration distribution of nitrogen can be easily controlled.
[0092]
Further, by doping nitrogen on the upper portion of the gate electrode 35 and performing a heat treatment, nitrogen is deposited on the gate oxide film 36. As a result, the silicon oxide film / silicon interface level is reduced, the reliability of the gate oxide film 2 is improved, and the hot carrier resistance is effectively improved. Here, FIG. 9 shows the result of evaluating the reliability of the gate oxide film of the conventional MOS transistor and the MOS transistor in which nitrogen was implanted into the gate electrode by the constant current stress method. FIG. 9 is a diagram showing an improvement in the reliability of an oxide film by nitrogen implantation. FIG. 9 shows that when nitrogen is implanted into the gate electrode 35 and nitrogen is deposited on the gate oxide film 36, the dielectric breakdown resistance is improved and the reliability of the gate oxide film is improved. FIG. 10 shows the nitrogen injection amount dependency of the amount of change in the threshold voltage due to hot carrier injection of the PMOS transistor. FIG. 10 shows the change in threshold voltage after applying a constant stress voltage for 1000 seconds. Since the change in threshold voltage decreases when the amount of nitrogen implanted into the gate electrode 35 is increased, nitrogen is applied to the gate electrode. It is understood that the doping and the deposition of nitrogen on the gate oxide film 36 improve the hot carrier resistance of the PMOS transistor.
[0093]
The nitrogen concentration peak in the nitrogen doping region 30 inside the gate electrode 35 and the gate oxide film 36 is 10 to¹⁹/ Cm³From to²¹/ Cm³It is desirable to set within the range. Therefore, the injection amount of nitrogen ions during the manufacturing process is¹⁴/ Cm²To 〜１０¹⁶/ Cm²It should be set within the range of. Nitrogen concentration peak is ~ 10¹⁹/ Cm³If it is lower than the above, the above-described effect cannot be obtained, and the nitrogen concentration peak in the gate oxide film 36 becomes 10 to²¹/ Cm³If it is higher than, the mobility of the channel electrons deteriorates, and the MOS transistor characteristics deteriorate.
[0094]
(Embodiment 2)
Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a sectional view showing a PMOS transistor according to a second embodiment of the present invention. In FIG. 11, reference numerals 1 to 7, and 10 are the same as or correspond to those in the conventional FIG. Reference numeral 30 denotes a nitrogen doping region formed inside the source / drain region 6. FIG. 12 is a diagram showing a profile in the depth direction of the source / drain region 6 of the PMOS transistor shown in FIG. FIG. 12 shows that the junction surface of the source / drain region 6 is not doped with nitrogen, and that the nitrogen / doped region 30 exists inside the source / drain region 6 formed by doping with boron.
[0095]
Next, a manufacturing process of the PMOS transistor shown in FIG. 11 will be described. First, after an element isolation oxide film 7 is formed by a normal element isolation step, a 100 ° oxide film 2a is formed on the N-type silicon substrate 1 by thermal oxidation, and then 5 × 20 phosphorus is formed by a CVD method. / Cm³A polysilicon film 3a doped to a thickness of about 2000 is deposited for about 2000 °, and an oxide film 4a for about 2000 ° is deposited by CVD (FIG. 13). Next, the oxide film 4a and the polysilicon film 3a are patterned into the shape of the gate electrode by photolithography and anisotropic etching to form the oxide film 4 and the gate electrode 3, respectively (FIG. 14). Next, an oxide film of about 800 ° is deposited by a CVD method (not shown), and a sidewall oxide film 5 is formed by etching back (FIG. 15). Next, nitrogen ions were set to 10 keV and 2 × 10^Fifteen/ Cm²Inject under the conditions of (FIG. 16). Next, boron ions were set to 10 keV, 4 × 10^Fifteen/ Cm²注入 (FIG. 17), and a heat treatment at 850 ° C. for about 20 minutes is applied to activate the implanted impurities.⁺At the same time that the -type source / drain regions 6 are formed, the nitrogen doping region 30 is formed.
[0096]
Next, another manufacturing process of the PMOS transistor shown in FIG. 11 will be described. 13 to 15 are the same as those in the above-described manufacturing process, and thus the description is omitted. Next, while rotating the N-type silicon substrate 1 at an incident angle of 30 ° with nitrogen ions, 12 keV, 2.5 、 × 10^Fifteen/ Cm²(FIG. 18). Next, boron ions were set to 10 keV, 4 × 10^Fifteen/ Cm²注入 (FIG. 19) and a heat treatment at 850 ° C. for about 20 minutes to activate the implanted impurities, thereby obtaining the P shown in FIG.⁺At the same time that the -type source / drain regions 6 are formed, the nitrogen doping region 30 is formed.
[0097]
Here, the nitrogen implantation conditions during the above manufacturing process will be described. Nitrogen is implanted at such an energy that the projected range of nitrogen is smaller than the projected range of boron. This is to prevent a defect occurring at the time of implanting nitrogen from occurring at a junction surface between the source / drain region 6 and the N-type silicon substrate 1 and causing a junction leakage current at the time of device operation.
[0098]
In the above description, an N-type gate electrode is used as the gate electrode. However, a P-type gate electrode or a gate electrode having a stacked structure of metal silicide and polysilicon may be used to reduce the sheet resistance of the gate electrode. As shown in FIG. 20, a titanium silicide film 8 may be formed on source / drain region 6 by using a titanium salicide step after the step shown in FIG. 19 in order to reduce the resistance of source / drain region 6. . Further, in the above-described embodiment, boron is ion-implanted when the source / drain regions 6 are formed. However, when the titanium silicide film 8 as shown in FIG. Boron fluoride may be ion-implanted. In the above embodiment, the case where only the PMOS transistor is used has been described. However, the PMOS transistor may be added to a part of the CMOS transistor, or the manufacturing process of the PMOS transistor may be added to a part of the CMOS transistor. Good.
[0099]
Next, effects of the invention in the present embodiment will be described. P⁺Since the -type source / drain regions 6 are doped with nitrogen, diffusion of boron is suppressed. In other words, since nitrogen has the same vacancy diffusion mechanism as boron and has a larger diffusion coefficient than boron, nitrogen occupies the vacancy that is the diffusion path first by interdiffusing nitrogen with boron. As a result, diffusion of boron can be suppressed, and the junction surface of the source / drain region 6 can be formed shallow. Further, in the present embodiment, in order to prevent the harmful effects of nitrogen implantation, nitrogen is implanted with an energy such that the projected range of nitrogen is smaller than the projected range of boron. As shown in (2), even if the end of the nitrogen distribution at the time of nitrogen implantation is not deeper than the end of the boron distribution at the time of boron implantation, it can be sufficiently suppressed.
[0100]
Further, when nitrogen is doped by the ion implantation method, the N-type silicon substrate 1 is made amorphous, and the channeling phenomenon at the time of boron ion implantation performed thereafter can be suppressed, so that the junction surface of the source / drain region 6 is formed shallow. It becomes possible. In addition, since amorphization by nitrogen is not as amorphous as by ion implantation of germanium and silicon, high-temperature heat treatment for recovering crystals is not required, and it is more effective to form a shallow junction surface. Further, since the source / drain region 6 can be formed without implanting boron fluoride into the source / drain region 6, when the resistance of the source / drain region is reduced by using the salicide process, the fluorine in the boron fluoride is reduced. Hinders the silicidation reaction, and a good metal silicide film can be formed. Further, by doping nitrogen by oblique rotation ion implantation, the lateral diffusion of boron can be further suppressed, and as a result, the effective gate length of the transistor can be increased.
[0101]
The nitrogen concentration peak in the nitrogen doping region 30 inside the source / drain region 6 is 10 to¹⁹/ Cm³To 〜１０²¹/ Cm³It is desirable to set within the range of. Therefore, the injection amount of nitrogen ions during the manufacturing process is¹⁴/ Cm²To 〜１０¹⁶/ Cm²It should be set within the range. Nitrogen concentration peak is ~ 10¹⁹/ Cm³When the value is lower than, the above-mentioned effects cannot be obtained, and the nitrogen concentration peak becomes 〜１０10²¹/ Cm³If it becomes higher, the activation rate of boron decreases, and the resistance of the source / drain region 6 increases.
[0102]
(Embodiment 3)
Next, another embodiment of the present invention will be described. FIG. 22 is a sectional view showing a PMOS transistor according to the third embodiment of the present invention. 22, 1, 2, 5 to 7, 10, 30, 35, and 36 are the same as or correspond to those shown in FIG. 1 or FIG. This embodiment is an invention in which Embodiment 1 and Embodiment 2 are combined.
[0103]
Next, a manufacturing process of the PMOS transistor shown in FIG. 22 will be described. First, after an element isolation oxide film 7 is formed on the N-type silicon substrate 1 by a normal element isolation process, an oxide film 36a of about 100 ° is formed by thermal oxidation, and a polysilicon film 35a of about 2000 ° is formed by a CVD method. Is formed (FIG. 23). Next, the polysilicon film 35a # and the oxide film 36a # are patterned into the shape of the gate electrode by photolithography and anisotropic etching to form the polysilicon film 35b # and the gate oxide film 2, respectively (not shown). Next, an oxide film of about 800 ° is deposited by a CVD method (not shown), and is etched back to form a sidewall oxide film 5 and a gate oxide film 36b ′ (FIG. 24). Next, nitrogen ions are applied to the polysilicon film 35b # and the source / drain regions at 10 keV and 2 × 10^Fifteen/ Cm²The injection is performed under the condition of (FIG. 25). Next, boron ions are applied to the polysilicon film 35b # and the source / drain regions at 10 keV,^Fifteen/ Cm²The injection is performed under the condition of (FIG. 26). Next, the source / drain region 6, the gate electrode 35 and the nitrogen doping region 30 shown in FIG. 22 are formed by activating the implanted impurities by applying a heat treatment at 850 ° C. for about 20 minutes. At the time of this heat treatment, nitrogen doped above gate electrode 35b # is thermally diffused, but nitrogen is segregated in gate oxide film 36b #, and as shown in FIG. A film 36 is formed. The conditions for implanting nitrogen into the source / drain region 6 and the gate electrode 35 are as described in the first and second embodiments, respectively.
[0104]
Next, another manufacturing process of the PMOS transistor shown in FIG. 22 will be described. First, after an element isolation oxide film 7 is formed on the N-type silicon substrate 1 by a normal element isolation process, an oxide film 36a of about 100 ° is formed by thermal oxidation, and a polysilicon film 35a of about 2000 Is formed (FIG. 27). Then, nitrogen ions are applied at 20 keV and 4 × 10 4 so that the range center is located above the polysilicon film 35a #.^Fifteen/ Cm²The injection is performed under the condition of (FIG. 28). Next, boron ions are applied to the polysilicon film 35a # at 20 keV and 4 × 10^Fifteen/ Cm²Inject under the conditions of (FIG. 29). Next, the polysilicon film 35a # is patterned into the shape of a gate electrode by photolithography and anisotropic etching to form a gate electrode 35b # (not shown). Next, an oxide film of about 800 ° is deposited by a CVD method (not shown), and is etched back to form a sidewall oxide film 5 and a gate oxide film 36b ′ (FIG. 30). Next, nitrogen is applied to the source / drain regions at 10 keV and 2 × 10^Fifteen/ Cm²Ion implantation is performed under the condition of (FIG. 31). Next, boron ions were applied to the source / drain regions at 10 keV and 4 × 10^Fifteen/ Cm²Inject under the conditions of (FIG. 32). Finally, heat treatment is applied at 850 ° C. for about 20 minutes. The operation in this heat treatment has been described in detail in the first manufacturing process, and therefore the description thereof is omitted here.
[0105]
In the second manufacturing process, nitrogen and boron are implanted twice into the gate electrode 35. Before patterning the gate electrode 35, an oxide film of about 2000.degree. In this way, an oxide film serving as a stopper film for introducing impurities into the gate electrode 35 may be formed on the gate electrode, and in the subsequent ion implantation of nitrogen and boron, only the source / drain region 6 may be implanted. In this manufacturing process, boron ions are implanted before patterning the gate electrode 35. However, the process may be omitted and the gate electrode 35 may be doped by implanting boron ions into the source / drain regions 6.
[0106]
In the above embodiment, the case where only the PMOS transistor is used has been described. However, the PMOS transistor may be added to a part of the CMOS transistor, or the manufacturing process of the PMOS transistor may be added to a part of the CMOS transistor. As shown in FIG. 33, in order to reduce the resistance of the gate electrode 35 and the source / drain region 6, a titanium salicide process is used after the process shown in FIG. 26 or FIG. May be formed with titanium silicide 8.
[0107]
Next, effects of the invention in the present embodiment will be described. Since the gate electrode 35 is doped with nitrogen, the diffusion of boron is suppressed as described in detail in Embodiment 2, and the penetration of boron into the channel region 10 through the gate oxide film 36 can be suppressed. In addition, the fluctuation of the threshold voltage can be effectively suppressed. Further, by doping nitrogen on the upper portion of the gate electrode 35 and performing a heat treatment, nitrogen is deposited on the gate oxide film 36. As a result, the silicon oxide film / silicon interface level is reduced, the reliability of the gate oxide film 36 is improved, and the hot carrier resistance is effectively improved. Furthermore, since the source / drain region 6 is doped with nitrogen, the diffusion of boron is suppressed as described in detail in Embodiment 1, and the junction surface of the source / drain region 6 can be formed shallow. Become. In addition, although the number of steps increases, by separately performing the nitrogen doping step for the gate electrode 35 and the source / drain regions 6, it becomes possible to change and optimize the respective nitrogen profiles, and to perform the gate oxidation of boron. The penetration of the film 36 and the diffusion in the source / drain region 6 are more effectively suppressed.
[0108]
(Embodiment 4)
Next, another embodiment of the present invention will be described. FIG. 34 is a sectional view showing the NMOS transistor according to the fourth embodiment of the present invention. In the figure, 4, 5, 7, and 10 are the same as or correspond to those shown in FIG. Numeral 40 indicates a P-type silicon substrate, shaded portions 30 indicate nitrogen doping regions, and N⁺It exists in the -shaped gate electrode 41 and the gate oxide film 42. 43 denotes an N formed with the channel region 10 interposed therebetween.⁻Type source / drain regions, 44 is N⁻N formed adjacent to the -type source / drain regions⁺These are type source / drain regions. N⁻Type source / drain region 43 and N⁺The -type source / drain regions 44 constitute an NMOS transistor having an LDD (Lightly-DopedｐDrain) structure. FIG. 35 is a diagram showing the NMOS transistor N shown in FIG.⁺FIG. 4 is a diagram illustrating profiles of a -shaped gate electrode 41 and a gate oxide film 42 in a depth direction. FIG. 35 shows that nitrogen is deposited in the gate oxide film 42. Here, the precipitation of nitrogen refers to a state where nitrogen is trapped at a certain position and the concentration increases.
[0109]
Next, a manufacturing process of the NMOS transistor shown in FIG. 34 will be described. First, after an element isolation oxide film 7 is formed on a P-type silicon substrate 40 by an ordinary element isolation structure, an oxide film 42a of about 100 ° is formed by thermal oxidation, and a polysilicon film 41a of about 2000 Is formed (FIG. 36). Next, nitrogen ions are applied at 20 keV and 1 × 10 2 so that the range center is located above the polysilicon film 41a #.¹⁶/ Cm²Inject under the conditions of (FIG. 37). Next, arsenic ions are applied to the polysilicon film 41a # at 30 keV, 4 × 10^Fifteen/ Cm²The injection is performed under the condition of (FIG. 38). Next, the polysilicon film 41a # is patterned into the shape of a gate electrode by photolithography and anisotropic etching to form a gate electrode 41b # (not shown). Next, arsenic ions are introduced into the N-type source / drain regions at 50 keV, 4 × 10¹³/ Cm²Inject under the conditions of (FIG. 39). Next, an oxide film of about 800 ° is deposited by a CVD method (not shown), and is etched back to form a sidewall oxide film 5 and a gate oxide film 42b (FIG. 40). Next, N⁺Arsenic ions in the -type source / drain regions at 50 keV, 4 × 10^Fifteen/ Cm²The injection is performed under the condition of (FIG. 41).
[0110]
Finally, the implanted impurities are activated by applying a heat treatment at 850 ° C. for about 20 minutes, and the N shown in FIG.⁻Type source / drain region 43, N⁺A ソ ー ス -type source / drain region 44, a gate electrode 41, and a nitrogen doping region 30 are formed. Further, during this heat treatment, the nitrogen doped above the gate electrode 41b # is thermally diffused, but the nitrogen segregates in the gate oxide film 42b #, and as shown in FIG. A film 36 is formed. Also in this embodiment, the conditions for injecting nitrogen into gate electrode 41 are as described in the second embodiment. In other words, the projected range RP of nitrogen is NRP, where the standard deviation is {RP}.⁺The gate electrode 41 is set so as to be in the gate electrode 41 at a position higher than 5 × {RP} from the interface between the gate electrode 44 and the gate oxide film 42.
[0111]
In the above description, the N-type doped gate electrode 41 is formed by implanting arsenic ions into the polysilicon film.²⁰/ Cm³The N-type doped gate electrode 41 may be formed using a doped polysilicon film doped to a degree of. In this embodiment, the case where only the NMOS transistor is used has been described. However, the NMOS transistor may be added to a part of the CMOS transistor, or the manufacturing process of the NMOS transistor may be added to a part of the CMOS transistor. Good.
[0112]
Next, effects of the invention in the present embodiment will be described. Since nitrogen is doped on the gate electrode 41, nitrogen is deposited on the gate oxide film 42 by the subsequent heat treatment. As a result, the silicon oxide film / silicon interface level is reduced, the reliability of the gate oxide film 42 is improved, and the hot carrier resistance is effectively improved. The evaluation of the reliability of the gate oxide film 42 is as described with reference to FIG. 9 in the first embodiment. FIG. 42 shows the dependency of the threshold voltage on the amount of nitrogen injected by hot carrier injection of the NMOS transistor. FIG. 42 shows a change in the threshold voltage after applying a constant stress voltage for 1000 seconds. Since the change in the threshold voltage decreases when the amount of nitrogen implanted into the gate electrode 41 is increased, nitrogen is applied to the gate electrode. It is understood that the doping and the deposition of nitrogen on the gate oxide film 42 improve the hot carrier resistance of the NMOS transistor.
[0113]
The nitrogen concentration peak in the nitrogen doping region 30 inside the gate electrode 41 and the gate oxide film 42 is 10 to¹⁹/ Cm³From to²¹/ Cm³It is desirable to set within the range of. Therefore, the injection amount of nitrogen ions during the manufacturing process is¹⁴/ Cm²To 〜１０¹⁶/ Cm²It should be set within the range of. Nitrogen concentration peak is ~ 10¹⁹/ Cm³If it is lower than the above, the above-mentioned effect cannot be obtained, and the nitrogen concentration peak in the gate oxide film 42 becomes 10 to²¹/ Cm³If it is higher than, the mobility of the channel electrons deteriorates, and the MOS transistor characteristics deteriorate.
[0114]
(Embodiment 5)
Next, another embodiment of the present invention will be described. FIG. 43 is a sectional view showing an NMOS transistor according to a fifth embodiment of the present invention. In the figure, 2, 3, 4, 5, 7, 10, 30, 40, 43, and 44 are the same as or correspond to those shown in FIG. That is, in the NMOS transistor of the present embodiment, N⁺The nitrogen doping region 30 is formed inside the -type source / drain region 43. FIG. 44 shows N of the NMOS transistor.⁺FIG. 4 is a diagram illustrating a profile of a -type source / drain region 43 in a depth direction. According to FIG.⁺The junction surface of the -type source / drain region 43 is not doped with nitrogen, and is formed by doping N with arsenic.⁺It can be seen that the nitrogen doping region 30 exists inside the -type source / drain region 43.
[0115]
Next, a manufacturing process of the NMOS transistor shown in FIG. 43 will be described. First, after an element isolation oxide film 7 is formed on a P-type silicon substrate 40 by a normal element isolation step, an oxide film 2a having a thickness of about 100 ° is formed by thermal oxidation, and phosphorus is applied on the oxide film by 5 × phosphorus by CVD. 10²⁰/ Cm³A polysilicon film doped to about is formed to about 2000Å, and an oxide film about 2000 の is formed on the polysilicon film (not shown). Next, the oxide film and the polysilicon film are patterned into the shape of the gate electrode by photolithography and anisotropic etching to form the oxide film 4 and the gate electrode 3 respectively (FIG. 45). Next, N⁻Arsenic ions are introduced into the -type source / drain regions at an incident angle of 45 ° while rotating the P-type silicon substrate 40 at 50 keV, 4 × 10¹³/ Cm²The injection is performed under the condition of (FIG. 46). Next, an oxide film of about 800 ° is deposited by a CVD method (not shown), and a sidewall oxide film 5 and a gate oxide film 2 are formed by etching back.⁺10 keV, 2 × 10 nitrogen ions in １０-type source / drain regions^Fifteen/ Cm²Inject under the conditions of (FIG. 47). Next, N⁺Arsenic ions in the -type source / drain regions at 50 keV, 4 × 10^Fifteen/ Cm²Inject under the condition of (FIG. 48). Next, the implanted impurities are activated by applying a heat treatment at 850 ° C. for about 20 minutes, and the N shown in FIG.⁻Type source / drain region 43, N⁺A ソ ー ス -type source / drain region 44 and a nitrogen doping region 30 are formed.
[0116]
Here, the conditions for injecting nitrogen during the above manufacturing process are as described in the first embodiment. That is, the nitrogen implantation condition is that the nitrogen is implanted at an energy such that the projection range of nitrogen is smaller than the projection range of arsenic.
[0117]
In the above description, the gate electrode is formed by depositing phosphorus-doped polysilicon, but the gate electrode may be formed by implanting N-type impurities after depositing non-doped polysilicon. Further, a gate electrode having a stacked structure of metal silicide and polysilicon may be used to reduce the sheet resistance of the gate electrode. As shown in FIG. 49, in order to reduce the resistance of the source / drain regions, a titanium salicide process is used after the process shown in FIG.⁺Titanium silicide 8 may be formed on -type source / drain region 44. In the above embodiment, the case where only the NMOS transistor is used has been described. However, the NMOS transistor may be added to a part of the CMOS transistor, or the manufacturing process of the NMOS transistor may be added to a part of the CMOS transistor. Good.
[0118]
Next, effects of the invention in the present embodiment will be described. N⁺Since the -type source / drain region 44 is doped with nitrogen, diffusion of arsenic is suppressed. That is, since the relationship between boron and nitrogen is described in detail in Embodiment 1, the relationship between arsenic and nitrogen can also be said. By interdiffusion between nitrogen and arsenic, diffusion of arsenic can be suppressed, and the / Drain region can be formed shallowly.
[0119]
Also, N⁺The nitrogen concentration peak in the nitrogen doping region 30 of the -type source / drain region 44 is 10 to¹⁹/ Cm³From to²¹/ Cm³It is desirable to set within the range. Therefore, the injection amount of nitrogen ions during the manufacturing process is¹⁴/ Cm²To 〜１０¹⁶/ Cm²It should be set within the range of. Nitrogen concentration peak is ~ 10¹⁹/ Cm³When the value is lower than, the above-mentioned effects cannot be obtained, and the nitrogen concentration peak becomes 〜１０10²¹/ Cm³Above which the activation rate of arsenic decreases and N⁺The resistance of the -type source / drain region 44 increases.
[0120]
(Embodiment 6)
Next, another embodiment of the present invention will be described. FIG. 50 is a sectional view showing the structure of a dual gate CMOS transistor according to the sixth embodiment of the present invention. In FIG. 50, reference numerals 10 to 14, 20, 21, and 23 are the same as or correspond to the conventional FIG. The hatched portion 30 indicates a nitrogen doping region. In a PMOS transistor, the inside of the source / drain region 21 is⁺It exists in the -type polysilicon film 50 and the gate oxide film 47, and is N in the NMOS transistor.⁺It exists in the -type polysilicon film 51 and the gate oxide film 48. Reference numeral 52 denotes an N formed in the P well 14 with the channel region 10 interposed therebetween.⁻Type source / drain regions, 53 is N⁻N formed adjacent to the -type source / drain regions⁺These are type source / drain regions. P⁺Type polysilicon film 50, N⁺Type polysilicon film 51, P⁺Type source / drain regions 21 and N⁺A titanium silicide film 23 is formed on the -type source / drain regions 53 to form a gate electrode having a two-layer structure and to reduce the resistance of the source / drain regions.
[0121]
Next, a manufacturing process of the dual gate CMOS transistor shown in FIG. 50 will be described. First, after forming an N well 13 and a P well 14 on a P-type silicon substrate 11, an element isolation oxide film 12 is formed on the P-type silicon substrate 11 by a normal element isolation process. Next, an oxide film 49 of about 100 ° is formed by thermal oxidation, and a polysilicon film 55 of about 2000 ° is deposited by CVD (FIG. 51). Next, nitrogen ions are applied at 20 keV and 4 × 10 4 so that the range center is located above the polysilicon film 55.^Fifteen/ Cm²Inject under the conditions of (FIG. 52). Next, the PMOS transistor formation region is covered with a resist 60, and arsenic ions are applied to the polysilicon film 55 in the NMOS transistor formation region at 30 keV, 4 × 10 4^Fifteen/ Cm²(FIG. 53). Next, after removing the resist 60, the NMOS transistor formation region is covered with a resist 61, and boron ions are applied to the polysilicon film 55 in the PMOS transistor formation region at 20 keV and 4 × 10 4.^Fifteen/ Cm²The injection is performed under the condition of (FIG. 54). Next, after removing the resist 61, the polysilicon film 55 is patterned into the shapes of the gate electrodes of the PMOS transistor and the NMOS transistor by photolithography and anisotropic etching to form a polysilicon film 50a # and a polysilicon film 51a # ( (FIG. 55). Next, the PMOS transistor formation region is covered with a resist 62, and N⁻Arsenic ions are introduced into the ソ ー ス -type source / drain regions at 50 keV while rotating the P-type silicon substrate 11 at an incident angle of 45 °, 4 × 10 4¹³/ Cm²Inject under the condition of (FIG. 56). Next, after removing the resist 62, an oxide film of 800 ° is deposited by a CVD method (not shown), and etched back to form a sidewall oxide film 20, a gate oxide film 47a ′ and a gate oxide film 48a #. (FIG. 57). Next, the PMOS transistor formation region is covered with a resist 63, and N⁺Arsenic ions in the -type source / drain regions at 50 keV, 4 × 10^Fifteen/ Cm²Inject under the conditions of (FIG. 58). Next, after removing the resist 63, the NMOS transistor formation region is covered with a resist 64, and nitrogen ions are applied to the source / drain region on the N well 13 at 10 keV, 2 × 10 4^Fifteen/ Cm²After implanting under the condition of, boron ions are 10 keV, 4 × 10^Fifteen/ Cm²(FIG. 59).
[0122]
Next, after removing the resist 64, the implanted impurities are activated by applying a heat treatment at 850 ° C. for about 20 minutes, and the source / drain regions 21 and P shown in FIG.⁺Type polysilicon film 50, N⁻Type source / drain region 52, N⁺Type source / drain region 53, N⁺A -type gate electrode 51 and a nitrogen doping region 30 are formed. At the time of this heat treatment, nitrogen doped on the polysilicon film 50a # and the polysilicon film 51a # is thermally diffused. However, nitrogen is segregated in the gate oxide film 47a # and the gate oxide film 48a #, and the nitrogen concentration peaks. An existing gate oxide film 47 and gate oxide film 48 are formed (not shown). Next, titanium of about 500 ° is deposited by a sputtering method, and heat treatment is performed at 700 ° C. for about 30 seconds to form P.⁺Type polysilicon films 50, 51, P⁺Type source / drain regions 21 and N⁺The titanium silicide film 23 is formed on the -type source / drain regions 53, and unreacted titanium on the oxide film is removed (not shown), thereby forming the dual gate CMOS transistor shown in FIG.
[0123]
Next, another manufacturing process of the dual gate CMOS transistor shown in FIG. 50 will be described. First, it is formed up to FIG. 51 by the above-described manufacturing process. Next, the PMOS transistor formation region is covered with a resist 60, and nitrogen ions are applied at 25 keV and 1 × 10 5 so that the range center is located above the polysilicon film 55.¹⁶/ Cm²(FIG. 60). Next, arsenic ions are applied to the polysilicon film 55 at 30 keV, 4 × 10^Fifteen/ Cm²The injection is performed under the condition of (FIG. 61). Next, after removing the resist 60, the NMOS transistor formation region is covered with the resist 61, and nitrogen ions are applied at 15 keV and 4 × 10 4 so that the range center is located above the polysilicon film 55.^Fifteen/ Cm²The injection is performed under the condition of (FIG. 62). Next, leaving the resist 61 as it is, boron ions are applied to the polysilicon film 55 at 20 keV, 4 × 10 4^Fifteen/ Cm²The injection is performed under the condition of (FIG. 63). Next, after removing the resist 61, the polysilicon film 55 is patterned into the shapes of the gate electrodes of the PMOS transistor and the NMOS transistor by using photolithography and anisotropic etching, and the polysilicon film 50a # and the polysilicon film 51a # are respectively formed. (FIG. 64). The following steps are the same as the above-described manufacturing steps (FIGS. 56 to 59 correspond to the drawings), and a description thereof will be omitted.
[0124]
In the above two manufacturing steps, the step of doping the polysilicon film 50a # with boron and the step of doping the source / drain region with boron are performed in separate steps. However, the doping of the polysilicon film 50a # is performed in the source / drain region. May be performed also in the doping step to the semiconductor. Also, the step of doping the polysilicon film with arsenic is N⁻Type source / drain region or N⁺The step may be performed also in the step of doping arsenic into the -type source / drain regions.
[0125]
Next, effects of the present embodiment will be described. In the PMOS transistor region, P⁺Since the n-type polysilicon film 50 and the P-type source / drain regions 21 are doped with nitrogen, the effects described in detail in the first and second embodiments can be obtained. In the transistor region, N⁺Since the -type polysilicon film 51 is doped with nitrogen, the effects described in detail in the fourth embodiment can be obtained. A step of implanting nitrogen ions into the polysilicon film 50a # and a step of⁺In the manufacturing method in which the step of implanting into the polysilicon film 51a # and the step of implanting into the polysilicon film 51a # are performed in separate steps, the respective nitrogen profiles may be optimized according to the properties of the ions implanted into the polysilicon film 50a # and the polysilicon film 51a #. And P in the PMOS transistor region⁺The penetration of boron from the -type polysilicon film 50 and the generation of the interface state between the gate oxide film and the silicon substrate in the NMOS transistor region are more effectively suppressed.
[0126]
(Embodiment 7)
Next, another embodiment of the present invention will be described. FIG. 65 is a sectional view showing the structure of a dual gate CMOS transistor according to the seventh embodiment of the present invention. 65, reference numerals 10 to 14, 20, 21, and 50 to 53 are the same as or correspond to those of the embodiment shown in FIG. 70 is a tungsten silicide film, P⁺It is formed on the -type polysilicon film 50. Tungsten silicide film 70 and P⁺The gate electrode of the PMOS transistor is constituted by the two-layer structure of the -type polysilicon film 50, and the nitrogen-doped region 30 indicated by oblique lines exists in the gate electrode and the gate oxide film 47. On the tungsten silicide film 70, an oxide film 19 is formed. 71 is a tungsten silicide film, and N⁺It is formed on the -type polysilicon film 51. Tungsten silicide film 71 and N⁺The gate electrode of the NMOS transistor is constituted by the two-layer structure of the -type polysilicon film 51, and the nitrogen-doped region 30 indicated by oblique lines exists in the gate electrode and the gate oxide film 48. On the tungsten silicide film 71, an oxide film 19 is formed. FIG. 66 is a diagram showing the profile of the gate electrode of the PMOS transistor and the oxide film 47 in the depth direction, and FIG. 67 is a diagram showing the profile of the gate electrode of the NMOS transistor and the gate oxide film 48 in the depth direction. . According to FIG. 66, at the gate electrode of the PMOS transistor, P⁺It can be seen that a nitrogen concentration peak exists at the interface between the -type polysilicon film 50 and the tungsten silicide film 70, and that nitrogen is precipitated in the gate oxide film 47. Also, according to FIG. 67, N⁺It can be seen that a nitrogen concentration peak exists at the interface between the -type polysilicon film 51 and the tungsten silicide film 71, and that nitrogen is deposited in the gate oxide film 48.
[0127]
Next, a manufacturing process of the dual gate CMOS transistor shown in FIG. 65 will be described. First, after an N well 13 and a P well 14 are formed on a P-type silicon substrate 11, an element isolation oxide film 12 is formed on the P-type silicon substrate 11 by a normal element isolation process (not shown). Next, an oxide film 49 of about 100 ° is formed by thermal oxidation, and a polysilicon film 55 of about 2000 ° is deposited by CVD (FIG. 68). Next, a tungsten silicide film 72 of about 1000 ° is deposited by a sputtering method (FIG. 69). Next, nitrogen ions are applied at 40 keV and 1 × 10 4 so that the range center comes near the interface between the polysilicon film 55 and the tungsten silicide film 72.¹⁶/ Cm²(FIG. 70). Next, the PMOS transistor forming region is covered with a resist 60, and arsenic ions are applied to the polysilicon film 55 in the NMOS transistor forming region at 120 keV, 4 × 10 4^Fifteen/ Cm²The injection is performed under the condition of (FIG. 71). Next, after removing the resist 60, the NMOS transistor formation region is covered with a resist 61, and boron ions are applied to the polysilicon film 55 in the PMOS transistor formation region at 30 keV, 4 × 10 4^Fifteen/ Cm²(FIG. 72). Next, after removing the resist 61, an oxide film of about 2000 ° is deposited by a CVD method (not shown), and an oxide film, a tungsten silicide film 72 and a polysilicon film 55 are formed by photolithography and anisotropic etching. By patterning into a shape, an oxide film 19, a tungsten silicide film 70a #, a tungsten silicide film 71a #, a polysilicon film 50a #, and a polysilicon film 51a # are formed (FIG. 73). Next, the PMOS transistor formation region is covered with a resist 62,⁻Arsenic ions are introduced into the ソ ー ス -type source / drain regions at 50 keV while rotating the P-type silicon substrate 11 at an incident angle of 45 °, 4 × 10 4¹³/ Cm²(FIG. 74).
[0128]
Next, after removing the resist 62, an oxide film of 800 ° is deposited by the CVD method and etched back to form the sidewall oxide film 20, the gate oxide film 47a ′, and the gate oxide film 48a ′ (not shown). , The PMOS transistor formation region is covered with a resist 63,⁺Arsenic ions in the -type source / drain regions at 50 keV, 4 × 10¹³/ Cm²(FIG. 75). Next, after removing the resist 63, the NMOS transistor formation region is covered with the resist 64, and nitrogen is applied to the source / drain region of the PMOS transistor at 10 keV, 2 × 10^Fifteen/ Cm²After implanting under the condition of, boron ions are 10 keV, 4 × 10^Fifteen/ Cm²Inject under the conditions of (FIG. 76). Next, after removing the resist 64, the implanted impurities are activated by applying a heat treatment at 850 ° C. for about 20 minutes, and the tungsten silicide films 70, 71, P shown in FIG.⁺Type polysilicon film 50, N⁺Type polysilicon film 51, source / drain region 21, N⁻Type source / drain region 52, N⁺A ソ ー ス -type source / drain region 53 and a nitrogen doping region 30 are formed. During this heat treatment, nitrogen doped at the interface between the polysilicon film 50a # and the tungsten silicide film 70a # and the interface between the polysilicon film 51a # and the tungsten silicide film 71a # is thermally diffused, but the gate oxide film 47a # and the gate oxide film 48a In the inside, nitrogen segregates, and as shown in FIGS. 66 and 67, a gate oxide film 47 and a gate oxide film 48 having a nitrogen concentration peak are formed.
[0129]
Next, effects of the invention in the present embodiment will be described. P⁺Near the interface between the -type polysilicon film 50 and the tungsten silicide film 70 and N⁺Since nitrogen is doped near the interface between the -type polysilicon film 51 and the tungsten silicide film 71, diffusion of boron into the tungsten silicide film 70 and diffusion of arsenic into the tungsten silicide film 71 are suppressed. That is, since the diffusion coefficient of nitrogen is larger than that of boron or arsenic, nitrogen occupies the diffusion path first, so that diffusion of boron into the tungsten silicide film 70 and diffusion of arsenic into the tungsten silicide film 71 are prevented. This suppresses the fluctuation of the threshold voltage due to the change of the work function due to the interdiffusion of boron and arsenic, thereby effectively suppressing the fluctuation of the threshold voltage. In this embodiment, the nitrogen doping region 30 is formed inside the source / drain region 21. However, the source / drain region 21 is formed by applying boron fluoride ions at, for example, 20 keV, 4 × 10^Fifteen/ Cm²In the case of implanting under the condition of, the nitrogen doping region 30 inside the source / drain region 21 may not be formed.
[0130]
(Embodiment 8)
FIG. 77 is a sectional view showing the structure of a PMOS-TFT according to an eighth embodiment of the present invention. In the figure, reference numerals 101 # to 105 # denote the same or corresponding portions as those of the TFT shown in FIG. A hatched portion 110 # indicates a nitrogen-doped region which is a region doped with nitrogen. FIG. 78 shows an impurity profile in the depth direction on the a-a 'section in FIG. 77, and FIG. 79 shows an impurity profile in the depth direction on the b-b' section in FIG. From FIGS. 78 and 79, it can be seen that the nitrogen doping region 110 # is formed up to the channel region outside the source end face and the drain end face.
[0131]
Next, a manufacturing process of the TFT shown in FIG. 77 will be described. First, after forming an insulating film 102 # on a semiconductor substrate 101 #, a non-doped polysilicon layer is deposited to a thickness of about 2000 # by a CVD method. Next, boron is ion-implanted into the non-doped polysilicon layer to form a P-type doped polysilicon layer, and then the polysilicon layer is patterned into a gate electrode shape by a photolithography process and anisotropic etching. Then, a gate electrode 103 # is formed (not shown). Next, after forming a gate insulating film 104 of 100 ° by thermal oxidation, a non-doped polycrystalline silicon layer is deposited by about 2000 ° by a CVD method. Next, in order to control the threshold voltage, arsenic was added to the non-doped polysilicon layer at 50 keV, 1 × 10 4¹²~ 1 × 10¹³/ Cm²Ion implantation is performed under the condition of to form an N-type doped polysilicon layer. Next, the polycrystalline silicon layer is patterned using a photolithography process and anisotropic etching so as to leave regions serving as a channel region, a source region and a drain region, thereby forming a polycrystalline polysilicon layer 105 # having a desired shape. (FIG. 80). Next, a resist 107 is provided in the channel region using a photolithography process, and nitrogen is applied at 10 keV while rotating the semiconductor substrate 101 at an incident angle of 15 ° to 60 °.^Fifteen/ Cm²Ion implantation is performed under the condition of (FIG. 81). Next, 10 keV, 4 × 10^Fifteen/ Cm²Then, boron fluoride is ion-implanted under the conditions (FIG. 82), and a heat treatment at 850 ° C. for about 20 minutes is applied to activate the implanted impurities. As shown in FIG. 77, a P-type source region 105b and a drain region are formed. At the same time as the formation of 105c, a nitrogen doping region 110 # is formed.
[0132]
Here, the relationship between the nitrogen implantation conditions and the source / drain implantation conditions will be described. The nitrogen injection energy is set so that its range RP # is smaller than the range RP # of boron fluoride. If nitrogen doping region 110 # is formed deeper than the source / drain junction surface, crystal defects formed at the time of nitrogen implantation are included in the depletion layer formed at the source / drain junction surface, and the junction leakage current is reduced. This is because it is a factor that causes it to occur.
[0133]
In the above description, boron fluoride was ion-implanted into the gate electrode, but there is no problem if boron is used. There is no problem even if an N-type gate electrode is used instead of the P-type gate electrode. Although boron fluoride ions are used for the P-type source / drain regions, boron ions may be used. In the above embodiment, the case of the P-channel MOS thin film transistor is described. However, there is no problem if the P-channel MOS thin film transistor is added to a part of the CMOS thin film transistor or the above-described process is added to a part of the CMOS process.
[0134]
Next, effects of the invention in the present embodiment will be described. Since the source region 105b and the drain region 105c are doped with nitrogen, diffusion of boron is suppressed. In other words, since nitrogen has the same vacancy diffusion mechanism as boron and has a larger diffusion coefficient than boron, by interdiffusing nitrogen with boron, nitrogen occupies vacancies that are diffusion paths first. As a result, the diffusion of boron can be suppressed. Therefore, the lateral diffusion of boron into the channel region is suppressed by the action of nitrogen, the effective gate length can be increased, and the occurrence of punch-through due to the short channel effect can be prevented. Further, by injecting nitrogen obliquely, the lateral diffusion of boron is further suppressed.
[0135]
(Embodiment 9)
In the eighth embodiment, the case where the present invention is applied to a PMOS-TFT has been described. In the ninth embodiment, the present invention is applied to an N-channel MOS-TFT (hereinafter referred to as an NMOS-TFT). Will be described. In the case of forming an NMOS-TFT, the conductivity type of the impurity to be implanted in FIG. 77 may be reversed from that in the case of forming a PMOS-TFT. That is, gate electrode 103 #, source region 105b and drain region 105c are doped N-type, and channel region 105a is doped P-type. FIG. 83 shows an impurity profile in the depth direction in the a-a 'section when the TFT shown in FIG. 77 is formed in an N-channel type, and FIG. 84 shows an impurity profile in the depth direction in the b-b' section. 83 and 84 that the nitrogen doping region 110 # is formed up to the channel region outside the source end surface and the drain end surface.
[0136]
Next, the manufacturing process of the NMOS-TFT according to the present invention will be described. Since the manufacturing steps are basically the same as those of the PMOS-TFT described in the eighth embodiment, FIGS. 80 to 82 are used as drawings. However, since the impurity implantation conditions are different, if the impurity here differs from that in Embodiment 7, the one described in parentheses in the drawing is adopted. First, after forming an insulating film 102 # on a semiconductor substrate 101 #, a non-doped polysilicon layer is deposited to a thickness of about 2000 # by a CVD method. Next, arsenic is ion-implanted into the non-doped polysilicon layer to form an N-type doped polysilicon layer, and then the polysilicon layer is patterned into a shape of a gate electrode by a photolithography process and anisotropic etching. Then, a gate electrode 103 # is formed (not shown). Next, after forming a gate insulating film 104 of 100 ° by thermal oxidation, a non-doped polysilicon layer of about 2000 ° is deposited by a CVD method. Next, in order to control the threshold voltage, boron fluoride was added to the non-doped polysilicon layer at 20 keV, 1 × 10¹²~ 1 × 10¹³/ Cm²Ion implantation is performed under the condition of to form a P-type doped polysilicon layer. Next, the polysilicon layer is patterned using a photolithography process and anisotropic etching so as to leave regions serving as a channel region, a source region, and a drain region, thereby forming a polysilicon layer 105 # having a desired shape (FIG. 80). Next, a resist 107 is provided in the channel region using a photolithography process, and nitrogen is applied at 10 keV while rotating the semiconductor substrate 101 at an incident angle of 15 ° to 60 °.^Fifteen/ Cm²(FIG. 81). Next, 30 keV, 4 × 10^Fifteen/ Cm²Arsenic is ion-implanted under the conditions described above (FIG. 82), and a heat treatment is performed at 850 ° C. for about 20 minutes to activate the implanted impurities, thereby simultaneously forming the N-type source region 105b and the drain region 105c. A nitrogen doping region 110 # is formed (FIG. 82).
[0137]
Also in the present embodiment, the relationship between the nitrogen implantation conditions and the source / drain implantation conditions is the same as in the eighth embodiment. That is, the injection energy of nitrogen is set such that its range RP # is smaller than the range RP # of arsenic.
[0138]
In the above description, arsenic implantation is used for the gate electrode, but there is no problem if phosphorus is used. Further, there is no problem even if a P-type gate electrode is used instead of the N-type gate electrode. Although arsenic is used for the N-type source / drain regions, phosphorus ion implantation may be used. Further, in the above embodiment, the case of the N-channel MOS thin film transistor is described. However, there is no problem even if the above process is added to a part of the CMOS thin film transistor or to a part of the CMOS process.
[0139]
Next, effects of the invention in the present embodiment will be described. Also in the present embodiment, as in Embodiment 8, since the N-type source / drain regions are doped with nitrogen, diffusion of arsenic or phosphorus is suppressed. That is, since the relationship between boron and nitrogen is described in detail in Embodiment 8, the relationship between arsenic and nitrogen or between phosphorus and nitrogen can be said. Therefore, the diffusion of arsenic is suppressed by mutually diffusing nitrogen and arsenic. it can. Therefore, the lateral diffusion of arsenic or phosphorus into the channel region is suppressed by the action of nitrogen, the effective gate length can be increased, and punch-through due to the short channel effect can be prevented. Further, by injecting nitrogen obliquely, the lateral diffusion of phosphorus or arsenic is further suppressed.
[0140]
(Embodiment 10)
FIG. 85 is a sectional view showing the structure of a PMOS-TFT according to the tenth embodiment of the present invention. In the figure, 101 -103, 105, and 110 indicate the same or corresponding portions as the TFT shown in FIG. However, in this embodiment, the nitrogen-doped region 110 indicated by the hatched portion is formed not only in the source region 105b and the drain region 105c but also in the polysilicon layer 105 and the gate insulating film 111 #. FIG. 86 shows an impurity profile in the depth direction in the a-a ′ section of FIG. 85. The impurity profile in the depth direction in the section taken along line b-b 'of FIG. 85 is the same as that of FIG. FIG. 86 shows that nitrogen is deposited on the gate insulating film 111 #.
[0141]
Next, a manufacturing process of the PMOS-TFT according to the present embodiment will be described. In the process described in Embodiment 8, up to the gate electrode 103 # is formed. Next, after a gate insulating film 111a of 100 ° is formed by thermal oxidation, a non-doped polycrystalline silicon layer 106 # is deposited by about 2000 ° by a CVD method (not shown). Next, nitrogen is applied to the non-doped polycrystalline silicon layer 106 at an angle of incidence of 15 ° to 60 ° while rotating the semiconductor substrate 101 ° at 10 keV, 2 × 10^Fifteen/ Cm²(FIG. 87). Further, in order to control the threshold voltage, arsenic is applied to the polysilicon layer 106 # at 50 keV, 1 × 10¹²~ 1 × 10¹³/ Cm²(Not shown), and the polysilicon layer 106 # is patterned by using a photolithography process and anisotropic etching so as to leave regions to become a channel region, a source region, and a drain region. A polysilicon layer 105 # is formed (FIG. 88). Next, a resist 107 is provided in the channel region by using a photolithography process, and 30 keV, 4 × 10 4^Fifteen/ Cm²By implanting boron fluoride under the conditions (FIG. 89) and performing a heat treatment at 850 ° C. for about 20 minutes to activate the implanted impurities, the P-type source region 105b and the drain region shown in FIG. 105c and a nitrogen doping region 110 # are formed. At the time of this heat treatment, nitrogen injected into polysilicon film 105 # is thermally diffused, and nitrogen is segregated in gate insulating film 111a to form gate insulating film 111 # having nitrogen-doped region 110 #.
[0142]
Here, the relationship between the nitrogen implantation conditions and the source / drain implantation conditions is the same as in the first embodiment. That is, the injection energy of nitrogen is set such that its range RP # is smaller than the range RP # of boron fluoride.
[0143]
In the above manufacturing process, the rotation oblique injection method of nitrogen is used. However, vertical injection may be performed, and nitrogen may be diffused into the channel portion on the side wall of the gate electrode 3 by a later heat treatment.
[0144]
Next, effects of the invention according to the present embodiment will be described. Since nitrogen is segregated in the gate insulating film 111 #, the interface level of the polysilicon layer / silicon oxide film (gate insulating film) is reduced, and the reliability of the gate insulating film 111 # is improved. That is, it is possible to suppress the hot carriers generated at the drain end due to the decrease in the interface state from being trapped in the gate insulating film 111 #, and to effectively improve the hot carrier resistance. Further, since the source / drain regions are also doped with nitrogen, it is possible to prevent the effect described in detail in the eighth embodiment, that is, the occurrence of punch-through due to the diffusion of impurities constituting the source / drain regions.
[0145]
(Embodiment 11)
In the tenth embodiment, the case where the present invention is applied to a PMOS-TFT has been described. In the eleventh embodiment, a case where the present invention is applied to an NMOS-TFT will be described. In the case of forming an NMOS-TFT, the conductivity type of the impurity to be implanted in FIG. 85 may be reversed from that in the case of forming a PMOS-TFT. That is, gate electrode 103 #, source region 105b and drain region 105c are doped N-type, and channel region 105a is doped P-type. FIG. 90 shows an impurity profile in the depth direction in the a-a 'cross section when the TFT shown in FIG. 85 is formed in an N-channel type. The impurity profile in the depth direction in the b-b 'section is the same as that in FIG. From FIG. 90, it can be seen that nitrogen is deposited on the gate insulating film 111 #.
[0146]
Next, a manufacturing process of the NMOS-TFT according to the present embodiment will be described. Since the manufacturing process is basically the same as that of the PMOS-TFT described in the tenth embodiment, FIGS. 87 to 89 are used as drawings. However, since the impurity implantation conditions are different, if the impurity here is different from that of Embodiment 10, the one described in parentheses in the drawing is adopted. In the process described in Embodiment 8, up to the gate electrode 103 # is formed. Next, after forming a gate insulating film 111a of 100 ° by thermal oxidation, a non-doped polysilicon layer is deposited by about 2000 ° by a CVD method. Next, nitrogen was applied to the non-doped polysilicon layer at an incident angle of 15 ° to 60 ° while rotating the semiconductor substrate 101 ° at 10 keV, 2 × 10^Fifteen/ Cm²Ion implantation is performed under the conditions of (FIG. 87). Further, in order to control the threshold voltage, boron fluoride is applied to the polysilicon layer at 30 keV, 1 × 10¹²~ 1 × 10¹³/ Cm²Ion implantation is performed under the conditions of (not shown). Next, the polysilicon layer is patterned using a photolithography process and anisotropic etching so as to leave regions serving as a channel region, a source region, and a drain region, thereby forming a polycrystalline polysilicon layer 105 # having a desired shape ( (FIG. 88). Next, a resist 107 is provided in the channel region by using a photolithography process, and 30 keV, 4 × 10 4^Fifteen/ Cm²Arsenic is ion-implanted under the conditions (FIG. 89), and a heat treatment at 850 ° C. for about 20 minutes is applied to activate the implanted impurities, so that the N-type source region 105b, drain region 105c and nitrogen doping region 110 To form In addition, nitrogen injected into polysilicon film 105 # during this heat treatment is thermally diffused, and nitrogen is segregated in gate insulating film 111a to form gate insulating film 111 # having a nitrogen-doped region (FIG. 89). Through the above steps, the TFT shown in FIG. 85 is completed.
[0147]
Next, effects of the invention according to the present embodiment will be described. Since nitrogen is segregated in the gate insulating film 111a below the channel region, the interface state of the polysilicon layer / silicon oxide film (gate insulating film) is reduced, and the reliability of the gate insulating film 111 # is improved. That is, it is possible to suppress the hot carriers generated at the drain end due to the decrease in the interface state from being trapped in the gate insulating film 111 #, and to effectively improve the hot carrier resistance. Further, since the source / drain regions are also doped with nitrogen, it is possible to prevent the effect described in detail in the eighth embodiment, that is, the occurrence of punch-through due to the diffusion of impurities constituting the source / drain regions.
[0148]
(Embodiment 12)
FIG. 91 is a sectional structural view of a PMOS-TFT showing a twelfth embodiment of the present invention. In the figure, 101 #, 102 #, 105 #, 110 #, and 111 # indicate the same or corresponding portions as the TFT shown in FIG. However, in the present embodiment, nitrogen doping region 110 # is present in gate insulating film 111 # below gate electrode 120 # and channel region 105a. FIG. 92 shows an impurity profile in the a-a ′ cross section of FIG. 91. FIG. 92 shows that nitrogen is deposited in the channel region of the gate insulating film 111 #.
[0149]
Next, a method for manufacturing the TFT shown in FIG. 91 will be described. First, after forming an insulating film 102 # on a semiconductor substrate 101 #, a polysilicon layer 120a is deposited to a thickness of about 2000 # by a CVD method. Next, 10 keV, 2 × 10^Fifteen/ Cm²Nitrogen is ion-implanted under the condition of (FIG. 93). Next, boron fluoride is ion-implanted into the polysilicon layer 120a (FIG. 94). Next, the polysilicon layer is patterned into a shape of a gate electrode by a photolithography process and anisotropic etching to form a gate electrode 120b. Next, after a gate insulating film 111a of 100 ° is formed by thermal oxidation, a polysilicon layer is deposited by about 2000 ° by a CVD method, and arsenic is applied to the polysilicon layer at 30 keV, 1 × 10¹²~ 1 × 10¹³/ Cm²Ion implantation is performed under the conditions of (not shown). Next, the polysilicon layer is patterned by using a photolithography process and anisotropic etching so as to leave regions serving as a channel region, a source region, and a drain region, thereby forming a polysilicon layer 105 # having a desired shape (FIG. 95). . Next, a resist 107 is provided in the channel region by using a photolithography process, and 30 keV, 4 × 10 4^Fifteen/ Cm²By implanting boron fluoride under the conditions (FIG. 96) and applying a heat treatment at 850 ° C. for about 20 minutes to activate the implanted impurities, a P-type source region 105b and a drain region 105c are formed. . In addition, during this heat treatment, nitrogen injected into gate electrode 120 # is thermally diffused, and nitrogen is segregated in gate insulating film 111a to form gate insulating film 111 # having a nitrogen-doped region (FIG. 96).
[0150]
Next, effects of the invention according to the present embodiment will be described. Since nitrogen is doped in gate electrode 120 #, boron can be prevented from diffusing during heat treatment for activating impurities and penetrating through gate insulating film 111 # and entering channel region 105a. That is, as described in detail in the seventh embodiment, this is due to the effect of preventing diffusion of nitrogen. By doping nitrogen into gate electrode 120 # and then performing heat treatment, nitrogen is deposited in the gate insulating film. As a result, the effect described in the tenth embodiment, that is, the generation of interface states in the gate insulating film due to hot carrier injection is suppressed, and the reliability of gate insulating film 120 # is improved.
[0151]
(Embodiment 13)
In the twelfth embodiment, the case where the present invention is applied to a PMOS-TFT has been described. In the thirteenth embodiment, a case where the present invention is applied to an NMOS-TFT will be described. In the case of forming an NMOS-TFT, the conductivity type of the impurity to be implanted in FIG. 91 may be reversed from that in the case of forming a PMOS-TFT. In other words, gate electrode 120 #, source region 105b and drain region 105c are doped N-type, and channel region 105a is doped P-type. FIG. 97 shows an impurity profile in the depth direction in an a-a ′ cross section when the TFT shown in FIG. 91 is formed in an N-channel type. From FIG. 91, it can be seen that nitrogen is deposited in the gate insulating film 111 # below the channel region 105a.
[0152]
The manufacturing process of the NMOS-TFT according to the present embodiment is basically the same as the manufacturing process of the PMOS-TFT described in detail in the twelfth embodiment. May be used. The ion implantation conditions for forming the NMOS-TFT are described in the above embodiment mode, and the description of this embodiment mode is omitted here.
[0153]
Also in this embodiment, as in the twelfth embodiment, since nitrogen is doped in gate electrode 120 #, arsenic doped in the gate electrode diffuses during the heat treatment for activating the impurity, and the gate insulation It can be prevented from being injected into the film 111 #. Further, since nitrogen is precipitated in the gate insulating film 111 # during this heat treatment, generation of interface states in the gate insulating film 111 # due to hot carrier injection can be prevented, that is, the reliability of the gate insulating film can be improved. Can be.
[0154]
(Embodiment 14)
FIG. 98 is a bird's-eye view of a dual-gate CMOS-TFT according to a fourteenth embodiment of the present invention. FIG. 99 shows the A-A 'section of FIG. 98, that is, the sectional structure of the PMOS-TFT. FIG. 100' shows the B-B 'section of FIG. 98, that is, the sectional structure of the NMOS-TFT. 98 to 100 #, 101 # indicates a semiconductor substrate, and 102 # indicates an insulating film. A hatched portion 110 # is a nitrogen-doped region, 125 # is a non-doped polysilicon layer, 126 # is a tungsten silicide (WSi2 #) layer, 127 # is a P-type polysilicon layer, and a non-doped polysilicon layer 125 #, a tungsten silicide layer 126 #, and a P-type polysilicon layer. The gate electrode of the PMOS-TFT is formed in a three-layer structure of 127. 128 # is a gate insulating film, 129 # is a polysilicon layer having a channel region 129a, a P-type source region 129b and a drain region 129c. Reference numeral 130 denotes an N-type polysilicon layer, which has a three-layer structure of a non-doped polysilicon layer 125 #, a tungsten silicide layer 126 #, and an N-type polysilicon layer 130 #, and forms a gate electrode of the NMOS-TFT. 131 # is a gate insulating film, and 132 # is a polysilicon layer having a channel region 132a, an N-type source region 132b and a drain region 132c. Note that nitrogen doping region 110 # is present in tungsten silicide layer 126 #, P-type polysilicon layer 127 #, gate insulating film 128 #, N-type polysilicon layer 130 #, and gate insulating film 131 #. FIG. 101A shows an impurity profile in the a-a 'cross section of FIG. 99, and FIG. 102A shows an impurity profile in a b-b' cross section of FIG. As shown in FIG. 101, in the gate electrode of the PMOS-TFT, the peak of the nitrogen concentration distribution exists at the interface between the P-type polysilicon layer 127 # and the tungsten silicide layer 126 # and in the gate insulating film 128 #. In addition, as shown in FIG. 102, in the gate electrode of the NMOS-TFT, the peak of the nitrogen concentration distribution exists at the interface between the N-type polysilicon layer 130 and the tungsten silicide layer 126 # and in the gate insulating film 128 #.
[0155]
Next, a manufacturing process of the TFT shown in FIG. 98 will be described. First, after forming an insulating film 102 # on a semiconductor substrate 101 #, a polysilicon layer 125a is deposited to a thickness of about 500 # by a CVD method. Next, a 500 ° tungsten silicide layer 126a is deposited on the polysilicon layer 125a by sputtering, and a polysilicon layer 135 # is deposited about 1000 ° on the tungsten silicide layer 126a (FIG. 103). Next, nitrogen ions are implanted near the interface between the polysilicon layer 135 # and the tungsten silicide layer 126a. In the present embodiment, the nitrogen ion implantation conditions are 40 keV, 2 × 10^Fifteen/ Cm²It may be set to about (FIG. 104). Next, a region to be a PMOS-TFT is covered with a resist, and arsenic is ion-implanted into a region to be an NMOS-TFT. Conversely, a region to be an NMOS-TFT is covered with a resist, and boron fluoride is ion-implanted into a region to be a PMOS-TFT. FIG. 105 # is a sectional structural view of the TFT after the implantation. Next, after patterning the polysilicon film 135, the tungsten silicide layer 126a, and the non-doped polysilicon layer 125a into a shape of a gate electrode, a gate oxide film of 100 ° is formed by thermal oxidation, and a polysilicon layer is deposited by about 2000 ° by a CVD method. . Next, after ion implantation for threshold voltage control is performed for each region of the PMOS-TFT and the NMOS-TFT, the polysilicon layer is patterned to form a polysilicon layer 129 # and a polysilicon layer 132 # (FIG. 106 #). .
[0156]
Next, a resist 140 # other than the source region 132b and the drain region 132c of the NMOS-TFT is provided, and 30 keV, 4 × 10 4^Fifteen/ Cm²Arsenic is ion-implanted under the conditions described above. A top view of the TFT at this stage is shown in FIG. Further, a heat treatment at 850 ° C. for about 20 minutes is applied to activate arsenic ions, thereby forming the source region 132b and the drain region 132c of the NMOS-TFT. Next, the resist 140 # is removed, and a resist 141 # is provided in a region other than the source region 129b and the drain region 129c of the PMOS-TFT.^Fifteen/ Cm²Ion implantation of boron fluoride is performed under the condition of. A top view of the TFT at this stage is shown in FIG. Further, heat treatment is performed at 850 ° C. for about 20 minutes to activate boron ions, thereby forming a source region 129b of the PMOS-TFT and a drain region 129c of the NMOS-TFT.
[0157]
Incidentally, in the heat treatment step for activating the source / drain regions, impurities contained in the gate electrode are also diffused. However, due to the effect of nitrogen doped near the interface between tungsten silicide layer 126 # and polysilicon layer 127 # and near the interface between tungsten silicide layer 126 # and polycrystalline silicon layer 130 #, boron and arsenic are introduced into tungsten silicide layer 126 #. The diffusion is suppressed, and the fluctuation of the threshold voltage due to the change of the work function of the gate electrode is effectively suppressed.
[0158]
(Embodiment 15)
FIG. 109 # is a sectional structural view showing a stacked gate type flash EEPROM according to a fifteenth embodiment of the present invention. In FIG. 109 #, 201 #, 205 #, 208 #, 209 #, 212 #, 215 # indicate the same or corresponding parts as in FIG. 206 # is a sidewall oxide film provided on the side wall of the control gate electrode 205 # and the floating gate electrode 221 #, 212a is provided on the smooth coat film 212 #, and a contact hole for connecting to the drain region 208 #, 213 # is on the smooth coat film 212 # A titanium alloy film such as titanium nitride (TiN) provided on the wall surface of the contact hole 212a; 214 # is an aluminum alloy wiring layer provided on the titanium alloy film 213 #; and a hatched portion 219 # is a nitrogen doping region. 220 ° is an oxide film having a thickness of about 100 °. Reference numeral 221 denotes a floating gate electrode made of a polysilicon film and has a thickness of about 1000 °. 222 ° is an interlayer insulating film composed of a composite film of a nitride film and an oxide film, and has a thickness of about 200 °. The nitrogen doping region 219 # exists in the oxide film 220 #, the polysilicon film 221 #, and the interlayer insulating film 222 #. FIG. 110 # shows a nitrogen profile in the depth direction of control gate electrode 205 #, interlayer insulating film 222 #, floating gate electrode 221 #, and oxide film 220 # of the flash EEPROM shown in FIG. 109 #.
[0159]
Next, a manufacturing process of the flash EEPROM shown in FIG. 109 # will be described. First, after a well region and an element isolation oxide film are formed in a predetermined region of a P-type silicon substrate 201 # (not shown), an oxide film 220a of about 100% is formed on the entire surface, and 1000 Å is formed on the oxide film 220a. Polysilicon film 221a is formed to the extent of FIG. Next, nitrogen is applied to the polysilicon film 221a at 10 keV,^Fifteen/ Cm²(FIG. 112 条件). At this time, assuming that the standard deviation is {RP}, the projected range RP of nitrogen comes into the polysilicon film 221a at a position higher than the position of 5 × {RP} from the interface between the polysilicon film 221a and the oxide film 220a. (FIG. 113 #). If it is set at a position lower than this condition, the oxide film 220a may be damaged by nitrogen implantation.
[0160]
Next, boron is applied to the polysilicon film 221a at 20 keV and 4 × 10^Fifteen/ Cm²(FIG. 114 条件). Next, an interlayer insulating film 222a made of a composite film of an oxide film and a nitride film is formed on the polysilicon film 221a to a thickness of about 200 °. Thereafter, a polysilicon film 205a is formed on the interlayer insulating film 222a to a thickness of about 2500 ° (FIG. 115). Next, a resist 225 # is formed in a predetermined region on the polysilicon film 205a, and anisotropic etching is performed using the resist 225 # as a mask to form the polysilicon film 205a, the interlayer insulating film 222a, the polysilicon film 221a, and the oxide film 220a. Is patterned (FIG. 116). Thereby, control gate electrode 205 #, interlayer insulating film 222b, floating gate electrode 221b, and oxide film 220b are formed (FIG. 117 #). Next, after removing resist 225 #, a resist 226 # is formed so as to cover a portion to be a source region of the memory cell, and arsenic (As) is applied to the main surface of silicon substrate 201 # using resist 226 # and control gate electrode 205 # as a mask. 35 keV, 5 × 10^Fifteen/ Cm²(FIG. 118 条件). Thereafter, resist 226 # is removed.
[0161]
Then, a resist 227 # is formed so as to cover a portion to be a drain region of the memory cell, and arsenic is applied to the main surface of silicon substrate 201 # at 35 keV, 1 × 10¹⁶/ Cm²Ion implantation is performed under the condition of (FIG. 119). Thereafter, resist 227 # is removed. Next, an oxide film 206a is formed on the entire surface at about 2000 ° (FIG. 120 °), and a sidewall oxide film 206 # is formed by performing anisotropic reactive ion etching. The width of the sidewall oxide film 206a thus formed in the channel direction is 2000 °, which is almost the same as the thickness of the oxide film 206a shown in FIG. Therefore, by adjusting the thickness of oxide film 206a, the width of sidewall oxide film 206 # in the channel direction can be easily controlled. After the side wall oxide film 206 # is formed, the implanted impurities are activated by performing a heat treatment at 850 ° C for about 60 seconds to form the source region 209 # and the drain region 208. By this heat treatment, boron and nitrogen implanted into the floating gate electrode 221b are diffused, but nitrogen is diffused faster than boron, and only nitrogen is deposited in the oxide film 220b and the interlayer insulating film 222b. A nitrogen doping region 219 # is formed in floating gate electrode 221 # and interlayer insulating film 222 # (FIG. 121 #).
[0162]
Next, after a smooth coat film 212 # is formed in a thickness of about 5000-15000 ° using a CVD method, the surface of the smooth coat film 212 # is flattened by performing a heat treatment at a temperature of 800 ° -1000 ° C. by a reflow method. . The smooth coat film 212 # is formed of, for example, a PSG film, a BPSG film, a nitride film, a non-doped oxide film, or a laminated film of these (FIG. 122). Next, a contact hole 212a having a diameter of about 0.6 μm to 1.5 μm is provided in a portion of the smooth coat film 212 # located in the drain region (FIG. 123 #). Next, a titanium alloy film 213 # made of titanium nitride for electrically connecting to the drain region is formed on the side surface of the contact hole 212a and on the smooth coat film 212 # (FIG. 124 #). Finally, an aluminum alloy wiring layer 214 of about 10,000 is formed on the titanium alloy film 213 by using the sputtering method, and the titanium alloy film 213 and the aluminum alloy wiring layer 214 are patterned by using photolithography and dry etching. . Thereby, a bit line composed of titanium alloy film 213 # and aluminum alloy wiring layer 214 # and electrically connected to drain region 208 # is formed. Thus, the flash EEPROM shown in FIG. 109 is completed. Note that the source / drain implantation may be performed simultaneously with the resist 225 # as a mask in the step shown in FIG. 117 #.
[0163]
Next, the effect of the invention of the flash EEPROM according to the present embodiment will be described. In the present embodiment, nitrogen is ion-implanted into the floating gate electrode 221 #, and nitrogen is deposited in the oxide film 220 # and the interlayer insulating film 222 # by the subsequent thermal diffusion. Therefore, there is no doping of hydrogen as in the RTN process. . Therefore, when an operation such as writing or erasing is performed using FN tunneling due to a nitrogen effect in the oxide film 220 #, traps or interface states due to hot carrier injection and holes generated due to interband tunneling are generated. Occurrence of traps and interface states due to the above can be suppressed, and furthermore, the deterioration of the oxide film due to hydrogen doping does not occur, so that the reliability of the oxide film 220 # is improved and the probability of initial failure of the flash EEPROM is reduced. . At the same time, the reliability of interlayer insulating film 222 # is improved by the nitrogen effect in interlayer insulating film 222 #. Further, when the reliability of the interlayer insulating film 222 # is improved, the thickness of the interlayer insulating film 222 # can be reduced, so that the capacitance (C) between the control gate electrode 205 # and the floating gate electrode 221 can be reduced._FC) Can be increased. That is, even if the same potential is applied to the control gate electrode 205 #, an element having a higher coupling ratio applies a larger electric field to the channel and improves the current driving capability. Can be reduced, and a low power supply voltage can be achieved.
[0164]
Further, since the floating gate electrode 221 # is doped with nitrogen, diffusion of boron is suppressed. In other words, since nitrogen has the same vacancy diffusion mechanism as boron and has a larger diffusion coefficient than boron, nitrogen occupies the vacancy that is the diffusion path first by interdiffusing nitrogen and boron. As a result, diffusion of boron can be suppressed. Therefore, penetration of boron into channel region 215 # and injection into oxide film 220 # can be suppressed, and variation in threshold voltage can be effectively suppressed.
[0165]
Further, in the manufacturing process of the flash EEPROM of the present embodiment, since nitrogen is doped by the ion implantation method, unlike the RTN process, the silicon substrate 201 # is not exposed to a rapid temperature change. For this reason, the occurrence of stripe-like defects can also be suppressed.
[0166]
Further, in the RTN process, it is necessary to apply heat at the time of nitrogen doping, so that nitrogen may diffuse over a wide area of the silicon substrate 201 #. However, in the manufacturing process of the present embodiment, nitrogen is doped by ion implantation so that nitrogen is doped. There is no need to perform a heat treatment step at the time of implantation. Therefore, heat treatment can be performed after patterning of the gate electrode, which is effective when it is not desired to diffuse nitrogen into the source region 209 # and the drain region 208 #.
[0167]
(Embodiment 16)
FIG. 125 # is a sectional structural view showing the memory cell portion of the stacked gate type flash EEPROM according to the sixteenth embodiment of the present invention. In FIG. 125, reference numerals 201 to 203, 206, 208, 209, and 215 indicate the same or corresponding parts as in FIG. In addition, the configuration of a portion not described other than the memory cell portion is the same as that shown in FIG. A hatched portion 219 # indicates a nitrogen doping region. 222 ° is an interlayer insulating film composed of a composite film of a nitride film and an oxide film, and has a thickness of about 200 °. 223 ° is a control gate electrode made of a polysilicon film and has a thickness of about 2500 °. The nitrogen doping region exists in the interlayer insulating film 222 # and the control gate electrode 223 #.
[0168]
Next, a manufacturing process of the flash EEPROM shown in FIG. First, after a well region and an element isolation oxide film are formed in a predetermined region of a P-type silicon substrate 201 (not shown), an oxide film 202a of about 100 °, a polysilicon film 203a of about 1000 °, an oxide film Then, an interlayer insulating film 222a of about 200 ° made of a composite film of a nitride film and a polysilicon film 223a of about 2500 ° are formed in this order (FIG. 126). Next, nitrogen is applied to the polysilicon film 223a at 10 keV,^Fifteen/ Cm²(FIG. 127). At this time, as described with reference to FIG. 113 in the fifteenth embodiment, the projected range RP of nitrogen is 5 × {RP} from the interface between the polysilicon film 223a and the interlayer insulating film 222a, assuming that the standard deviation is {RP}. The position is set so as to be in the polysilicon film 223a at a position higher than the predetermined position.
[0169]
Next, boron is applied to the polysilicon film 223a at 20 keV and 4 × 10^Fifteen/ Cm²Ions are implanted under the conditions of (FIG. 128). Thereafter, the flash EEPROM shown in FIG. 125 is completed through the manufacturing steps after FIG. 116 in the fifteenth embodiment. However, in the heat treatment step for activating impurities in the present embodiment, nitrogen doped in control gate electrode 223 # is deposited on interlayer insulating film 222 #.
[0170]
Next, the effect of the invention of the flash EEPROM according to the present embodiment will be described. Also in the present embodiment, the effect shown in the fifteenth embodiment, that is, the improvement of the reliability of the interlayer insulating film 222 # and the reduction of the power supply voltage of the element accompanying the effect can be realized. Further, by implanting nitrogen into control gate electrode 223 #, diffusion of boron doped into the control gate electrode during heat treatment can be prevented, and boron can be prevented from being injected into interlayer insulating film 222 #.
[0171]
(Embodiment 17)
FIG. 129 # is a sectional structural view showing the memory cell portion of the stack gate type flash EEPROM according to the seventeenth embodiment of the present invention. In FIG. 129, 201, 206, 208, 209, 215, and 219 to 223 indicate the same or corresponding parts as in FIG. 109 or FIG. 125 of the embodiment. In addition, the configuration of a portion not described other than the memory cell portion is the same as that shown in FIG. This embodiment is an invention in which Embodiment 15 and Embodiment 16 are combined.
[0172]
Next, a manufacturing process of the flash EEPROM shown in FIG. After performing the manufacturing process shown in FIG. 115 # of the fifteenth embodiment, nitrogen is applied to the polysilicon film 223a at 10 keV, up to 4 × 10^Fifteen/ Cm²Ion implantation is performed under the condition of (FIG. 130). Next, boron is applied to the polysilicon film 223a at 20 keV, 4 × 10^Fifteen/ Cm²(FIG. 131 条件). Thereafter, the flash EEPROM shown in FIG. 129 is completed through the manufacturing steps shown in FIG. 116 # of the fifteenth embodiment. However, in the heat treatment step for activating impurities in the present embodiment, nitrogen doped in floating gate electrode 221b is deposited on oxide film 220b and interlayer insulating film 222b, and simultaneously doped on control gate electrode 223b. Nitrogen is also deposited on the interlayer insulating film 222b.
[0173]
The effects of the present invention according to the present embodiment are as described in detail in the fifteenth and sixteenth embodiments, and a description thereof will not be repeated.
[0174]
(Embodiment 18)
FIG. 132 # is a sectional view showing a memory cell portion of a buried channel type flash EEPROM according to the eighteenth embodiment of the present invention. In FIG. 132, 201 to 205, 208, 209, 215, 217, and 218 indicate the same or corresponding parts as in FIG. Reference numeral 206 # denotes a sidewall oxide film provided on the side wall of the control gate electrode 205 # and the floating gate electrode 203 #. A hatched portion 219 # is a nitrogen doping region and is formed inside the N-type impurity layer 217 #.
[0175]
Next, the manufacturing process of the embedded channel type flash EEPROM shown in FIG. First, a well region and an element isolation oxide film are formed in a predetermined region of a P-type silicon substrate 201 # (not shown). Next, nitrogen ions are implanted into the silicon substrate 201 # at a range such that the depth from the main surface of the silicon substrate 201 # becomes smaller than 500 [deg.] (FIG. 133 #). Next, an N-type impurity such as arsenic or phosphorus is implanted at a range such that the depth from the main surface becomes 500 ° or less (FIG. 134 °). Next, a P-type impurity such as boron is injected from the main surface. Is implanted in a range such that the depth becomes 500 ° or more (FIG. 135 °). That is, the nitrogen implantation condition is that the nitrogen is implanted at an energy such that the range of nitrogen is smaller than the range of arsenic. Next, an oxide film 202a of about 100 °, a polysilicon film 203a of about 1000 °, an interlayer insulating film 204a of about 200 ° made of a composite film of an oxide film and a nitride film, and a polysilicon film 205a of about 2500 ° are formed in this order. (FIG. 136). Subsequent manufacturing steps are the same as those shown in FIG. 116 # of the fifteenth embodiment and the description thereof is omitted here. However, in the present embodiment, the impurities implanted into N-type impurity layer 217 # and P-type impurity layer 218 # are activated by the heat treatment step in Embodiment 15, and nitrogen doping region 219 # is also formed at the same time. . The N-type impurity layer 217 # is formed so as to cover the nitrogen doping region 219 # according to the above-described impurity ion implantation conditions. Therefore, defects generated at the time of nitrogen ion implantation are caused by the N-type impurity layer 217 # and the P-type impurity layer 218 #. Since there is no occurrence at the junction surface and no increase in junction leakage current, there is no need to worry about the adverse effects of nitrogen implantation.
[0176]
Next, effects of the present invention according to the present embodiment will be described. Since the region shallower than N-type impurity layer 217 # is doped with nitrogen, arsenic diffusion is suppressed. That is, nitrogen has the same vacancy diffusion as arsenic in its diffusion mechanism and has a larger diffusion coefficient than arsenic, so that arsenic diffusion during the heat treatment step can be suppressed. Further, diffusion of boron in P-type impurity layer 218 # can be suppressed by the same mechanism. Therefore, since a thin N-type impurity layer 217 # can be formed, punch-through in a buried channel type flash EEPROM can be suppressed. Further, the thickness of N-type impurity layer 217 # can be controlled to a desired value by nitrogen implantation conditions.
[0177]
(Embodiment 19)
FIG. 137 # is a sectional view showing a stacked gate type flash EEPROM according to a nineteenth embodiment of the present invention. In FIG. 137, reference numerals 201 to 205, 208, 209, and 215 indicate parts that are the same as or correspond to those in FIG. Reference numeral 206 # denotes a sidewall oxide film provided on the side wall of the control gate electrode 205 # and the floating gate electrode 203 #. The shaded portion 230 # is a nitrogen doping region formed inside the drain region 208 #. FIG. 138 is a diagram showing a depth profile of a drain region 208 # of the flash EEPROM shown in FIG. 137 #. FIG. 138 # shows that nitrogen is not doped into the junction surface of the drain region 208 #, and that a nitrogen doping region 230 # exists inside the drain region 208 formed by doping with arsenic.
[0178]
Next, a manufacturing process of the stack gate type flash EEPROM shown in FIG. First, after a well region and an element isolation oxide film are formed in a predetermined region of a P-type silicon substrate 201 (not shown), an oxide film 202a of about 100 °, a polysilicon film 203a of about 1000 °, an oxide film Then, an interlayer insulating film 204a of about 200 ° made of a composite film of a nitride film and a polysilicon film 205a of about 2500 ° and an oxide film 207a of about 1000 ° are formed in this order (FIG. 139). Next, the oxide film 202a, the polysilicon film 203a, the interlayer insulating film 204a, the polysilicon film 205a, and the oxide film 207a are patterned into a gate electrode shape, and the oxide film 202 #, the floating gate electrode 203 #, the interlayer insulating film 204 #, the control gate An electrode 205 # and an oxide film 207 # are formed. Next, the source formation region is covered with a resist 225 #, and using the resist 225 # and the oxide film 207 # as a mask, nitrogen is applied to the drain formation region at 10 keV and 、 8 × 10^Fifteen/ Cm²(FIG. 140 条件). Next, arsenic was changed to 35 keV, 5 × 10^Fifteen/ Cm²Ion implantation is performed under the condition (1) (FIG. 141). That is, the nitrogen implantation condition is that the nitrogen is implanted at an energy such that the range of nitrogen is smaller than the range of arsenic. Thereafter, resist 225 # is removed. Subsequent manufacturing steps are the same as those shown in FIG. 119 # of the fifteenth embodiment and the description thereof is omitted here. However, in the present embodiment, the impurities implanted into source region 209 # and drain region 208 # are activated by the heat treatment process in Embodiment 15, and nitrogen doping region 230 # is also formed at the same time. Since the drain region 208 # is formed so as to cover the nitrogen doping region 230 # according to the above-described impurity ion implantation conditions, defects generated at the time of nitrogen ion implantation do not occur at the junction surface between the drain region 208 # and the silicon substrate 201 #. Also, since the junction leakage current does not increase, there is no need to worry about the adverse effects of nitrogen implantation.
[0179]
Next, effects of the present invention according to the present embodiment will be described. Since the drain region 208 # is doped with nitrogen, diffusion of arsenic implanted into the drain region 208 # during the heat treatment step can be prevented. Therefore, it becomes possible to form a shallow PN junction surface with silicon substrate 201 # in drain region 208 #, and it is possible to suppress short channel effects such as punch-through. Further, since the short channel effect can be suppressed, the element can be miniaturized.
[0180]
In addition, since the diffusion of arsenic implanted into drain region 208 # is suppressed by nitrogen doped into the drain region, the overlap region between oxide film 202 # and drain region 208 # due to arsenic diffusion in the lateral direction is reduced, The capacitance between the control gate electrode 205 # and the drain region 208 # (C_FS) Becomes smaller. Therefore, the coupling ratio (C_FC/ C_TOTAL) Can be increased, and the potential (V_CG) And the potential of floating gate electrode 203 # (V_FG) Becomes smaller. That is, even when the same potential is applied to control gate electrode 205 #, a device having a higher coupling ratio applies a larger electric field to channel region 215 #, and the current driving capability is improved. Therefore, to obtain the same effect, the larger the coupling ratio, the higher the applied voltage (V_CG) Can be small, and the power supply voltage can be reduced.
[0181]
(Embodiment 20)
FIG. 142 is a sectional view showing a stacked gate type flash EEPROM according to the twentieth embodiment of the present invention. In FIG. 142 #, 201 # to 205 #, 208 #, 209 #, 215 # indicate the same or corresponding parts as in FIG. Reference numeral 206 # denotes a sidewall oxide film provided on the side wall of the control gate electrode 205 # and the floating gate electrode 203 #. 231 # is a nitrogen doping region formed inside source region 209 #.
[0182]
In the method of manufacturing the stack gate type flash EEPROM described in this embodiment, the nitrogen doping step described in Embodiment 19 may be performed before the source implantation step. Also in this embodiment, nitrogen is implanted at such energy that the range of nitrogen is smaller than that of arsenic, as in the case of the nineteenth embodiment.
[0183]
Also in this embodiment, the same effect as the effect of the invention shown in the nineteenth embodiment can be obtained.
[0184]
(Embodiment 21)
FIG. 143 # is a sectional structural view of the stack gate type flash EEPROM shown in the twenty-first embodiment of the present invention. In FIG. 35, 201 -205, 206, 208, 209, 230, and 231 show the same or corresponding parts as those in the embodiment shown in FIG. 137 or 142. This embodiment is an invention in which the nineteenth embodiment and the twentieth embodiment are combined. That is, a nitrogen doping region 230 # is formed inside the drain region 208, and a nitrogen doping region 231 # is formed inside the source region 209 #.
[0185]
In the manufacturing process of the stack gate type flash EEPROM shown in this embodiment, the nitrogen doping process shown in the nineteenth embodiment may be performed after the process of patterning the gate electrode (FIG. 144 #).
[0186]
In this embodiment, since the nitrogen doping region 230 # and the nitrogen doping region 231 # are provided inside the drain region 208 # and the source region 209 #, respectively, the effect shown in the nineteenth or twentieth embodiment is more remarkable. appear. Further, in this embodiment, nitrogen may be implanted without providing oxide film 207 #, and control gate electrode 205 # may be doped with nitrogen.
[0187]
Note that a region to be doped with nitrogen may be selected in combination with the above embodiment depending on a desired effect.
[0188]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[0189]
In the semiconductor device according to the present invention, since the gate electrode is doped with nitrogen, the diffusion of the impurity introduced into the gate electrode can be suppressed, and the contamination of the impurity into the gate insulating film and the penetration of the impurity from the gate insulating film can be suppressed. it can. Further, since the gate insulating film is doped with nitrogen, the reliability and hot carrier resistance of the gate insulating film are improved.
[0190]
Since the semiconductor device according to the present invention includes the nitrogen doping region inside the source / drain region, diffusion of impurities introduced into the source / drain region can be suppressed, and the junction surface of the source / drain region is formed shallow. It is possible to do.
[0191]
In addition, the nitrogen doping region of the source / drain region can prevent diffusion of impurities in the lateral direction, so that the area where the first insulating film overlaps with the source / drain region can be reduced, so that the second gate The capacitance between the electrode and the source / drain region can be reduced. Therefore, the coupling ratio can be increased, and the voltage applied to the second gate electrode can be reduced.
[0192]
Further, in the semiconductor device according to the present invention, nitrogen is doped into the gate electrode having a stacked structure of the metal silicide film and the polysilicon film, and the nitrogen concentration peak exists at the interface between the polysilicon film and the metal silicide film. The diffusion of the impurity doped in the polysilicon film into the metal silicide film can be suppressed. Therefore, a change in the work function of the gate electrode in the positive or negative direction can be suppressed, and a change in the threshold voltage due to a change in the work function can be suppressed.
[0193]
Further, by implanting nitrogen ions into the semiconductor substrate main surface at an angle smaller than 90 °, the diffusion of impurities in the channel direction can be further controlled.
[0194]
In the method of manufacturing a semiconductor device according to the present invention, nitrogen ions are implanted, and impurity ions having a range larger than the range of the nitrogen ions are implanted to form the source / drain regions. A nitrogen doping region can be formed.
[0195]
Furthermore, in the method for manufacturing a semiconductor device according to the present invention, after nitrogen is ion-implanted into the gate insulating film, heat treatment is performed, and nitrogen is deposited in the gate insulating film. Therefore, without damaging the gate insulating film, A gate insulating film not doped with hydrogen can be formed.
[Brief description of the drawings]
FIG. 1 is a sectional structural view of a PMOS transistor according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a profile of a source / drain region in a depth direction.
FIG. 3 is a manufacturing process diagram of the PMOS transistor according to the first embodiment of the present invention.
FIG. 4 is a manufacturing process diagram of the PMOS transistor according to the first embodiment of the present invention.
FIG. 5 is a manufacturing process diagram of the PMOS transistor according to the first embodiment of the present invention.
FIG. 6 is a manufacturing process diagram of the PMOS transistor according to the first embodiment of the present invention.
FIG. 7 is a manufacturing process diagram of the PMOS transistor according to the first embodiment of the present invention.
FIG. 8 is a manufacturing process diagram of the PMOS transistor according to the first embodiment of the present invention.
FIG. 9 is a manufacturing process diagram of the PMOS transistor according to the first embodiment of the present invention.
FIG. 10 is a sectional structural view of a PMOS transistor of the present invention.
FIG. 11 is a diagram showing a profile of a source / drain region in a depth direction.
FIG. 12 is a sectional structural view of a PMOS transistor according to a second embodiment of the present invention.
FIG. 13 is a diagram showing a profile of a gate electrode and a gate oxide film in a depth direction.
FIG. 14 is a manufacturing process diagram of the PMOS transistor according to the second embodiment of the present invention.
FIG. 15 is a manufacturing step diagram of the PMOS transistor according to the second embodiment of the present invention.
FIG. 16 is a manufacturing process diagram of the PMOS transistor according to the second embodiment of the present invention.
FIG. 17 is a manufacturing step diagram of the PMOS transistor according to the second embodiment of the present invention.
FIG. 18 is a manufacturing step diagram of the PMOS transistor according to the second embodiment of the present invention.
FIG. 19 is a diagram illustrating nitrogen implantation conditions.
FIG. 20 is a diagram showing the result of evaluating the reliability of an oxide film.
FIG. 21 is a diagram showing a nitrogen injection amount dependency of a threshold voltage change amount due to hot carrier injection of a PMOS transistor.
FIG. 22 is a sectional structural view of a PMOS transistor according to a third embodiment of the present invention.
FIG. 23 is a manufacturing process diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 24 is a manufacturing process diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 25 is a manufacturing process diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 26 is a manufacturing step diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 27 is a manufacturing process diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 28 is a manufacturing process diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 29 is a manufacturing process diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 30 is a manufacturing step diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 31 is a manufacturing step diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 32 is a manufacturing step diagram of the PMOS transistor according to the third embodiment of the present invention.
FIG. 33 is a sectional structural view of a PMOS transistor of the present invention.
FIG. 34 is a sectional structural view of an NMOS transistor according to a fourth embodiment of the present invention.
FIG. 35 is a diagram showing a profile in a depth direction of a gate electrode and a gate oxide film.
FIG. 36 is a manufacturing step diagram of the NMOS transistor according to the fourth embodiment of the present invention.
FIG. 37 is a manufacturing step diagram of the NMOS transistor according to the fourth embodiment of the present invention.
FIG. 38 is a manufacturing step diagram of the NMOS transistor according to the fourth embodiment of the present invention.
FIG. 39 is a manufacturing step diagram of the NMOS transistor according to the fourth embodiment of the present invention.
FIG. 40 is a manufacturing step diagram of the NMOS transistor according to the fourth embodiment of the present invention;
FIG. 41 is a manufacturing step diagram of the NMOS transistor according to the fourth embodiment of the present invention;
FIG. 42 is a diagram showing the dependency of the amount of change in the threshold voltage due to hot carrier injection on the NMOS transistor on the amount of nitrogen injection.
FIG. 43 is a sectional structural view of an NMOS transistor according to a fifth embodiment of the present invention.
FIG. 44 is a diagram showing a profile of a source / drain region in a depth direction.
FIG. 45 is a manufacturing step diagram of the NMOS transistor according to the fifth embodiment of the present invention.
FIG. 46 is a manufacturing step diagram of the NMOS transistor according to the fifth embodiment of the present invention;
FIG. 47 is a view showing the manufacturing process of the NMOS transistor according to the fifth embodiment of the present invention;
FIG. 48 is a view showing the manufacturing process of the NMOS transistor according to the fifth embodiment of the present invention;
FIG. 49 is a sectional structural view of an NMOS transistor of the present invention.
FIG. 50 is a sectional structural view of a dual gate CMOS transistor according to a sixth embodiment of the present invention.
FIG. 51 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 52 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 53 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 54 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 55 is a manufacturing step diagram of the dual gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 56 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 57 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 58 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 59 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 60 is a view showing the manufacturing process of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 61 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 62 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 63 is a manufacturing step diagram of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 64 is a view showing the manufacturing process of the dual-gate CMOS transistor according to the sixth embodiment of the present invention;
FIG. 65 is a sectional structural view of a dual gate CMOS transistor according to a seventh embodiment of the present invention.
FIG. 66 is a diagram showing profiles of a gate electrode and a gate oxide film in a depth direction.
FIG. 67 is a diagram showing a profile of a gate electrode and a gate oxide film in a depth direction.
FIG. 68 is a view showing the manufacturing process of the dual-gate CMOS transistor according to the seventh embodiment of the present invention;
FIG. 69 is a view showing the manufacturing process of the dual-gate CMOS transistor according to the seventh embodiment of the present invention;
FIG. 70 is a manufacturing step diagram of the dual-gate CMOS transistor according to the seventh embodiment of the present invention;
FIG. 71 is a manufacturing step diagram of the dual-gate CMOS transistor according to the seventh embodiment of the present invention;
FIG. 72 is a manufacturing step diagram of the dual-gate CMOS transistor according to the seventh embodiment of the present invention;
FIG. 73 is a manufacturing step diagram of the dual-gate CMOS transistor according to the seventh embodiment of the present invention;
FIG. 74 is a view showing the manufacturing process of the dual-gate CMOS transistor according to the seventh embodiment of the present invention;
FIG. 75 is a manufacturing step diagram of the dual-gate CMOS transistor according to the seventh embodiment of the present invention;
FIG. 76 is a view showing the manufacturing process of the dual-gate CMOS transistor according to the seventh embodiment of the present invention;
FIG. 77 is a sectional structural view of a TFT according to an eighth embodiment of the present invention.
FIG. 78 is a diagram showing an impurity profile in the a-a ′ cross section of the PMOS-TFT.
FIG. 79 is a diagram showing an impurity profile in a section taken along the line b-b ′ of the PMOS-TFT.
FIG. 80 is a manufacturing step diagram of the TFT according to the eighth embodiment of the present invention;
FIG. 81 is a view showing the manufacturing process of the TFT according to the eighth embodiment of the present invention;
FIG. 82 is a view showing the manufacturing process of the TFT according to the eighth embodiment of the present invention;
FIG. 83 is a diagram showing an impurity profile in an a-a ′ cross section of the NMOS-TFT.
FIG. 84 is a diagram showing an impurity profile in a section taken along the line b-b ′ of the NMOS-TFT.
FIG. 85 is a sectional structural view of a TFT according to the tenth embodiment of the present invention;
FIG. 86 is a diagram showing an impurity profile in the a-a ′ cross section of the PMOS-TFT.
FIG. 87 is a view showing the manufacturing step of the TFT according to the tenth embodiment of the present invention;
FIG. 88 is a manufacturing step diagram of the TFT according to the tenth embodiment of the present invention;
FIG. 89 is a view showing the manufacturing process of the TFT according to the tenth embodiment of the present invention;
FIG. 90 is a diagram showing an impurity profile in an a-a ′ cross section of the NMOS-TFT.
FIG. 91 is a sectional structural view of a TFT according to an eleventh embodiment of the present invention;
FIG. 92 is a diagram showing an impurity profile in an a-a ′ section of a PMOS-TFT.
FIG. 93 is a manufacturing step diagram of the TFT according to the eleventh embodiment of the present invention;
FIG. 94 is a view showing the manufacturing process of the TFT according to the eleventh embodiment of the present invention;
FIG. 95 is a view showing the manufacturing step of the TFT according to the eleventh embodiment of the present invention;
FIG. 96 is a view showing the manufacturing process of the TFT according to the eleventh embodiment of the present invention;
FIG. 97 is a diagram showing an impurity profile in an a-a ′ cross section of the NMOS-TFT.
FIG. 98 is a bird's-eye view of the TFT according to the twelfth embodiment of the present invention;
FIG. 99 is a sectional view of the TFT, taken along the line A-A ′.
FIG. 100 is a B-B ′ cross-sectional view of the TFT.
FIG. 101 is a diagram showing an impurity profile in an a-a ′ cross section of a TFT.
FIG. 102 is a diagram showing an impurity profile in a section taken along the line b-b ′ of the TFT.
FIG. 103 is a manufacturing step diagram of the TFT according to the twelfth embodiment of the present invention;
FIG. 104 is a manufacturing step diagram of the TFT according to the twelfth embodiment of the present invention.
FIG. 105 is a manufacturing step diagram of the TFT according to the twelfth embodiment of the present invention.
FIG. 106 is a manufacturing step diagram of the TFT according to the twelfth embodiment of the present invention.
FIG. 107 is a manufacturing step diagram of the TFT according to the twelfth embodiment of the present invention;
FIG. 108 is a manufacturing step diagram of the TFT according to the twelfth embodiment of the present invention;
FIG. 109 is a sectional structural view of a flash EEPROM according to a thirteenth embodiment of the present invention;
FIG. 110 is a diagram showing a profile of a gate electrode in a depth direction.
FIG. 111 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 112 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 113 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 114 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 115 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 116 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 117 is a view showing the manufacturing process of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 118 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 119 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 120 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 121 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 122 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 123 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 124 is a manufacturing step diagram of the flash EEPROM according to the thirteenth embodiment of the present invention;
FIG. 125 is a sectional structural view of a flash EEPROM according to a fourteenth embodiment of the present invention;
FIG. 126 is a manufacturing step diagram of the flash EEPROM according to the fourteenth embodiment of the present invention;
FIG. 127 is a manufacturing step diagram of the flash EEPROM according to the fourteenth embodiment of the present invention;
FIG. 128 is a manufacturing step diagram of the flash EEPROM according to the fourteenth embodiment of the present invention;
FIG. 129 is a sectional structural view of a flash EEPROM according to a fifteenth embodiment of the present invention;
FIG. 130 is a manufacturing step diagram of the flash EEPROM according to the fifteenth embodiment of the present invention;
FIG. 131 is a manufacturing step diagram of the flash EEPROM according to the fifteenth embodiment of the present invention;
FIG. 132 is a sectional structural view of a flash EEPROM according to a sixteenth embodiment of the present invention;
FIG. 133 is a manufacturing step diagram of the flash EEPROM according to the sixteenth embodiment of the present invention;
FIG. 134 is a view showing the manufacturing process of the flash EEPROM according to the sixteenth embodiment of the present invention;
FIG. 135 is a manufacturing step diagram of the flash EEPROM according to the sixteenth embodiment of the present invention;
FIG. 136 is a manufacturing step diagram of the flash EEPROM according to the sixteenth embodiment of the present invention;
FIG. 137 is a sectional structural view of a flash EEPROM according to a seventeenth embodiment of the present invention;
FIG. 138 is a diagram showing a profile of a drain region in a depth direction.
FIG. 139 is a manufacturing step diagram of the flash EEPROM according to the seventeenth embodiment of the present invention;
FIG. 140 is a manufacturing step diagram of the flash EEPROM according to the seventeenth embodiment of the present invention;
FIG. 141 is a view showing the manufacturing process of the flash EEPROM according to the seventeenth embodiment of the present invention;
FIG. 142 is a sectional structural view of a flash EEPROM according to an eighteenth embodiment of the present invention;
FIG. 143 is a sectional structural view of a flash EEPROM according to a nineteenth embodiment of the present invention;
FIG. 144 is a sectional structural view of a flash EEPROM according to a nineteenth embodiment of the present invention;
FIG. 145 is a sectional structural view of a conventional PMOS transistor.
FIG. 146 is a sectional structural view of a conventional PMOS transistor.
FIG. 147 is a sectional structural view of a conventional PMOS transistor.
FIG. 148 is a sectional structural view of a conventional dual-gate CMOS transistor.
FIG. 149 is a view showing the manufacturing process of the conventional dual-gate CMOS transistor;
FIG. 150 is a view showing the manufacturing process of the conventional dual-gate CMOS transistor;
FIG. 151 is a view showing the manufacturing process of the conventional dual-gate CMOS transistor;
FIG. 152 is a view showing a manufacturing step of a conventional dual-gate CMOS transistor;
FIG. 153 is a manufacturing process diagram of a conventional dual-gate CMOS transistor.
FIG. 154 is a manufacturing process diagram of a conventional dual-gate CMOS transistor.
FIG. 155 is a view showing the manufacturing process of the conventional dual-gate CMOS transistor;
FIG. 156 is a manufacturing step diagram of the conventional dual-gate CMOS transistor;
FIG. 157 is a view showing the manufacturing step of the conventional dual-gate CMOS transistor;
FIG. 158 is a sectional structural view of a conventional dual-gate CMOS transistor.
FIG. 159 is a view showing the manufacturing step of the conventional dual-gate CMOS transistor;
FIG. 160 is a view showing the manufacturing process of the conventional dual-gate CMOS transistor;
FIG. 161 is a view showing the manufacturing process of the conventional dual-gate CMOS transistor;
FIG. 162 is a view showing the manufacturing process of the conventional dual-gate CMOS transistor;
FIG. 163 is a manufacturing step diagram of the conventional dual-gate CMOS transistor;
FIG. 164 is a sectional structural view of a conventional TFT.
FIG. 165 is a bird's-eye view of a conventional TFT.
FIG. 166 is a manufacturing process diagram of a conventional TFT.
FIG. 167 is a manufacturing process diagram of a conventional TFT.
FIG. 168 is a manufacturing process diagram of a conventional TFT.
FIG. 169 is a manufacturing process diagram of a conventional TFT.
FIG. 170 is a sectional structural view of a conventional flash EEPROM.
FIG. 171 is a sectional structural view for explaining the operation of the flash EEPROM.
FIG. 172 is a sectional structural view for explaining the operation of the flash EEPROM;
FIG. 173 is a sectional structural view for explaining the operation of the flash EEPROM;
FIG. 174 is a sectional structural view for explaining the coupling ratio of the flash EEPROM.
FIG. 175 is a cross-sectional structure diagram for describing band-to-band tunneling occurring in a flash EEPROM.
FIG. 176 is a sectional structural view of a conventional embedded channel type flash EEPROM.
FIG. 177 is a view illustrating the conventional method of manufacturing the semiconductor device;
[Explanation of symbols]
6 source / drain region, 8 titanium silicide film, 23 titanium silicide film, 30 nitrogen doping region, 35 gate electrode, 36 gate oxide film, 41 gate electrode, 42 gate oxide film, 44 N⁺-Type source / drain region, 43 N⁻Type source / drain regions, 47 gate oxide film, 48 gate oxide film, 50 polysilicon film, 51 polysilicon film, 52 N⁻-Type source / drain region, 53 N⁺Source / drain regions, 105 polysilicon layer, 105a channel region, 105b source region, 105c drain region, 110 nitrogen doping region, 111 gate insulating film, 120 gate electrode, 126 tungsten silicide layer, 128 gate insulating film, 131 gate insulating Film, 208 drain region, 209 source region, 217 N-type impurity layer, 218 P-type impurity layer, 219 nitrogen doping region, 220 oxide film, 222 interlayer insulating film, 223 control gate electrode, 230 nitrogen doping region, 231 nitrogen doping region .

Claims (6)

A semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
A first electrode formed on the first insulating film;
Source / drain regions provided on the semiconductor substrate with the first electrode interposed therebetween;
A semiconductor device having a region doped with nitrogen inside the source / drain region. A second insulating film on the first electrode;
The semiconductor device according to claim 1, further comprising a second electrode on the second insulating film. The source / drain region is provided from the main surface of the semiconductor substrate to the inside of the semiconductor substrate, and the region doped with nitrogen is provided from the main surface to the inside of the source / drain region. The semiconductor device according to claim 2, wherein: Forming a gate electrode on the semiconductor substrate;
Implanting nitrogen ions into the semiconductor substrate, forming a nitrogen doping region in the semiconductor substrate with the gate electrode in between,
Implanting impurity ions having a range greater than the range of the nitrogen ions into the semiconductor substrate to form source / drain regions including the nitrogen-doped region. Method. 5. The method according to claim 4, wherein the nitrogen ions are implanted into the semiconductor substrate at an angle smaller than 90 degrees with respect to a main surface of the semiconductor substrate. Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Implanting nitrogen ions into the semiconductor substrate with the gate electrode and the gate electrode interposed therebetween, and doping nitrogen into the gate electrode, and forming a nitrogen doping region in the semiconductor substrate;
Impurity ions having a range greater than the range of the nitrogen ions are implanted into the semiconductor substrate with the gate electrode and the gate electrode interposed therebetween, and the gate electrode is doped with impurities, and a source including the nitrogen-doped region is provided. / Forming a drain region;
Performing a heat treatment after the step of implanting impurities into the gate electrode and the semiconductor substrate to deposit nitrogen in the gate insulating film.

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