JP2004047919A - Manufacturing method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor integrated circuit whereby an operator can identify a present process by only watching a resist pattern. <P>SOLUTION: The manufacturing method includes a first process of coating a resist 2 onto a substrate 1; a second process of placing a mask 3 with a main body pattern 3a and a plurality of identification patterns 3b corresponding to a plurality of processes formed thereto above the resist 2, selectively exposing the resist with the main body pattern 3a and the identification pattern 3b of a process corresponding to the main body pattern 3a from the mask 3, and thereafter developing the exposed patterns to form the resist pattern of the main body pattern 3a and the resist pattern 4 of the identification pattern 3b on the resist 2; and a third process of identifying the process to be the second process on the basis of the resist pattern 4 of the identification pattern 3b. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor integrated circuit that can determine a current process based on a photoresist pattern formed on a semiconductor substrate even when a photomask is shared between processes.
[0002]
[Prior art]
In a semiconductor integrated circuit, a well formation step, a Si nitride film pattern formation step for LOCOS formation, a field transistor threshold voltage adjustment step are performed using a semiconductor substrate by an impurity diffusion method using photolithography, a film formation method and an etching method. LOCOS forming step, Si nitride film removing step, transistor threshold voltage adjusting step, gate electrode forming step, source / drain forming step, interlayer insulating film forming step, interlayer conductive hole forming step, and wiring forming step. Is done.
At this time, the determination of the process currently being performed is determined based on a photoresist pattern formed on the semiconductor substrate or a substrate pattern manufactured by etching or the like from the photoresist pattern.
[0003]
[Patent Document 1]
JP-A-5-275310 (pages 2-3, FIG. 1)
[0004]
[Problems to be solved by the invention]
However, from the viewpoint of cost reduction, since a mask is often shared between the steps, a similar photoresist pattern is formed on the semiconductor substrate. However, it was difficult to determine from which process to start next, only by looking at this photoresist pattern.
If performed by an unskilled worker, there is a possibility that a process error will occur.
[0005]
SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems involved, and an object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit that can determine a current process only by looking at a photoresist pattern.
[0006]
[Means for Solving the Problems]
The present invention provides a method of manufacturing a semiconductor integrated circuit manufactured through a plurality of steps of repeating impurity diffusion in a substrate by using a photolithography method,
A first step of applying a photoresist to the substrate or a layer laminated on the substrate,
Using a photomask in which a plurality of identification patterns corresponding to the plurality of steps are formed in a portion other than the main body pattern and the main body pattern, the photomask is arranged above the photoresist, and from above the photomask. After selectively exposing the body pattern and the identification pattern in a process corresponding to the body pattern, development is performed to form a photoresist pattern of the body pattern and a photoresist pattern of the identification pattern on the photoresist. A second step;
A third step of determining the second step from the photoresist pattern of the identification pattern;
And a method for manufacturing a semiconductor integrated circuit.
A second invention is a method for manufacturing a semiconductor integrated circuit, which is manufactured through a plurality of steps of repeating impurity diffusion in a substrate by using a photolithography method, wherein the first substrate or a layer laminated on the substrate has a first layer. A first step of applying a photoresist of
Using a photomask in which only a plurality of identification patterns corresponding to the plurality of processes are formed at an end, the photomask is disposed above the first photoresist, and the plurality of identification patterns are arranged on the photomask. After exposing the pattern, performing development, a second step of forming a first photoresist pattern of the plurality of identification patterns on the substrate or a layer laminated on the substrate,
Etching the substrate exposed from the first photoresist pattern to form a plurality of identification marks corresponding to the plurality of identification patterns on the substrate, and then removing the first photoresist pattern; Three steps,
A fourth step of forming a second photoresist on the substrate on which the plurality of identification marks are formed;
Using a photomask in which only the main body pattern is formed, after selectively exposing the main body pattern and the identification mark portion corresponding to the step in which the main body pattern is used, or selectively excluding the other than the identification mark portion After exposure, a developing step is performed to form a second photoresist pattern including a mark pattern that exposes or covers the identification mark corresponding to the step of using the main body pattern and the main body pattern, and ,
A sixth step of determining a step in which the body pattern is used by the second photoresist pattern of the mark pattern;
And a method for manufacturing a semiconductor integrated circuit.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of a method for manufacturing a semiconductor integrated circuit according to the present invention will be described with reference to FIGS.
1A and 1B show a P-well photoresist patterning process, wherein FIG. 1A is a cross-sectional view and FIG. 1B is a plan view of a photomask used at that time. FIG. 2 is a sectional view showing a P-well forming step. 3A and 3B show an N-well photoresist patterning process, wherein FIG. 3A is a cross-sectional view and FIG. 3B is a plan view of a photomask used at that time. FIG. 4 is a cross-sectional view showing an N-well forming step. FIG. 5 is a cross-sectional view showing the step of forming the Si nitride film. FIG. 6 is a sectional view showing an N-channel field transistor threshold voltage adjusting photoresist patterning process. FIG. 7 is a cross-sectional view showing an N-channel field transistor threshold voltage adjusting impurity implantation step. FIG. 8 is a sectional view showing a P-channel field channel field transistor threshold voltage adjusting impurity implantation step. FIG. 9 is a diagram showing a field oxide film forming step. FIG. 10 is a sectional view showing an N-channel transistor threshold voltage adjusting photoresist patterning step. FIG. 11 is a cross-sectional view showing an N-channel transistor threshold voltage adjusting impurity implantation step. FIG. 12 is a cross-sectional view showing a P-channel transistor threshold voltage adjusting impurity implantation step. FIG. 13 is a cross-sectional view showing a step of forming a gate oxide film and a gate electrode. FIG. 14 is a cross-sectional view showing a step of forming an interlayer insulating film and a metal wiring layer.
[0008]
Hereinafter, a method for manufacturing a semiconductor integrated circuit will be described.
(P well photoresist patterning process)
As shown in FIG. 1A, after a photoresist 2 is applied on a Si substrate 1, a photomask 3 for a P-well is placed above the photoresist 2 and the photomask 3 is formed by photolithography. Exposure from above.
[0009]
At this time, as shown in FIG. 1B, a P-well pattern 3a used in the (P-well photoresist patterning step) is provided at a central portion of the photomask 3 and an end portion of the photomask 3 is provided at each end. An identification pattern 3b indicating a process is formed. For example, “PWL” of the identification pattern 3b indicates that it is used in the (P-well photoresist patterning step), and “NWL” of the identification pattern 3b indicates that it is used in the (N-well photoresist patterning step). "NFV" indicates that it is used in the (N-channel field transistor threshold voltage adjustment photoresist patterning step).
[0010]
Then, only the “PWL” and the P-well pattern 3 a in the identification pattern 3 b formed at the end of the photomask 3 are exposed and developed to form a pattern on the photoresist 2 (P-well photoresist patterning step). Is formed simultaneously with the P-well pattern 3a to form a photoresist pattern 4 having an opening 4a together with an identification character indicating a (P-well photoresist patterning step).
In this manner, selectively exposing only the “PWL” of the identification pattern 3b and the P-well pattern 3a can be performed by blind setting of an exposure device (not shown).
[0011]
(P well forming step)
As shown in FIG. 2, B (boron) ions are implanted into the Si substrate 1 exposed from the opening 4a from above the photoresist pattern 4 to form a P well 5.
[0012]
(N-well photoresist patterning process)
As shown in FIG. 3A, after applying a photoresist 6 on the Si substrate 1, a photomask 7 for an N-well is placed above the photoresist 6, and the photomask 7 is formed by photolithography. Exposure from above.
As shown in FIG. 3B, similarly to the above, an N-well pattern 7a is formed at the center of the photomask 7, and an identification pattern 7b indicating each step is formed at an end of the photomask 7. I have.
At this time, as in the (P-well photoresist patterning step), only the “NWL” and the N-well pattern 7a in the identification pattern 7b formed at the end of the photomask 7 are exposed and developed. On the photoresist 6, an "NWL" of the identification pattern 7b indicating the (N-well photoresist patterning step) is formed simultaneously with the N-well pattern 7a, and together with the identification character indicating the (N-well photoresist patterning step), A photoresist pattern 8 having an opening 8a is formed adjacent to the P well 5.
[0013]
(N-well forming step)
As shown in FIG. 4, P (phosphorus) ions are implanted into the Si substrate 1 exposed from the opening 8a from above the photoresist pattern 8 to form an N well 9.
Thereafter, the photoresist pattern 8 is removed.
[0014]
(Si nitride film forming step)
Next, a Si nitride film is formed on the Si substrate 1, and a photoresist (not shown) is applied on the Si nitride film. Next, as shown in FIG. 5, a photomask for a Si nitride film (not shown) was placed above the photoresist, and the photoresist was exposed from above the photomask by a photolithography method to form a photoresist pattern. Thereafter, etching is performed to form a Si nitride film pattern 10.
[0015]
Also in the following steps, a photomask in which an identification pattern indicating each step is formed at an end portion is used, and at the time of exposure, the identification pattern and the main body pattern in each step are exposed and formed in each step. It is the same that the identification pattern indicating each step described above is formed on the photoresist simultaneously with the main body pattern in each step. Here, the body pattern is the P-well pattern 3a in the case of the photomask 3, and is the N-well pattern 7a in the case of the photomask 7.
[0016]
(N-channel field transistor threshold voltage adjustment photoresist patterning step)
As shown in FIG. 6, after a photoresist 11 is applied on a Si substrate 1 on which a Si nitride film pattern 10 is formed, a photomask for adjusting an N-channel field transistor threshold voltage is formed above the photoresist 11. The same photomask 3 as that used in (P-well photoresist patterning step) is placed, and is exposed from above the photomask 3 by photolithography. At this time, only “NFV” in the identification pattern formed at the end of the photomask 3 and the N-channel field transistor threshold voltage adjustment pattern (not shown) are exposed and developed, and An identification pattern "NFV" indicating the N-channel field transistor threshold voltage adjustment photoresist patterning step) is formed simultaneously with the N-channel field transistor threshold voltage adjustment pattern, thereby forming the (N-channel field transistor threshold voltage adjustment). A photoresist pattern 12 having an opening 12a on the P-well 5 is obtained together with an identification character indicating a (photoresist patterning step).
[0017]
(N-channel field transistor threshold voltage adjusting impurity implantation step)
Next, as shown in FIG. 7, P ions are implanted from above the photoresist pattern 12 into the P well 5 other than those covered with the photoresist pattern 12 and the Si nitride film pattern 10 to form the N channel field 13. Form.
[0018]
(P-channel field transistor threshold voltage adjustment impurity implantation step)
Next, as shown in FIG. 8, the same steps as the (N-channel field transistor threshold voltage adjusting photoresist patterning step) and the (N-channel field transistor threshold voltage adjusting impurity implanting step) are performed. Instead of implanting ions, B ions are implanted into N wells 9 other than those covered with the photoresist pattern 12 and the Si nitride film pattern 10 to form a P channel field 14.
Thereafter, the photoresist pattern 12 is removed.
[0019]
(Field oxide film forming step)
Next, as shown in FIG. 9, after oxidizing the Si substrate 1 into which P and B have been implanted at a temperature of about 1000 ° C., the Si nitride film pattern 10 is removed to form a field oxide film 15. .
[0020]
(N-channel transistor threshold voltage adjustment photoresist patterning step)
Next, as shown in FIG. 10, after applying a photoresist 16 on the field oxide film 15 and the Si substrate 1, the same photomask 3 as used in the (P-well photoresist patterning step) is placed. Then, a photoresist pattern 17 having an opening 17a together with an identification character indicating (N-channel transistor threshold voltage adjustment photoresist patterning step) is obtained by photolithography.
[0021]
(N-channel transistor threshold voltage adjustment impurity implantation step)
Next, as shown in FIG. 11, P ions are implanted into the P well 5 exposed from the opening 17a from above the photoresist pattern 17 in the same manner as in the (P well forming step). To form
After that, the photoresist pattern 17 is removed.
[0022]
(P-channel transistor threshold voltage adjustment impurity implantation step)
Next, as shown in FIG. 12, a photoresist pattern 17 having an opening 17a on the N well 9 is formed in the same manner as in the (P-channel transistor threshold voltage adjustment photoresist patterning step).
Then, B ions are implanted into the N well 9 exposed from the opening 17a to form a P channel 19.
After that, the photoresist pattern 17 is removed.
[0023]
(Step of forming gate oxide film and gate electrode)
Next, as shown in FIG. 13, a gate oxide film 20 is formed on the P and N wells 5 and 9 of the Si substrate 1, and a gate electrode 21 is formed on the gate oxide film 20. Further, using the gate electrode 21 as a mask, As ions are implanted into the P well 5 and B ions are implanted into the N well 9 to form drains 22 and 23 and sources 24 and 25, thereby forming MOS transistors 26 and 27. Form.
[0024]
(Interlayer insulating film and metal wiring layer forming step)
Next, as shown in FIG. 14, after an interlayer insulating film is formed on the MOS transistors 26 and 27 and the field oxide film 15, the interlayer insulating film is formed on the gate oxide films 20 of the MOS transistors 26 and 27 by photolithography and etching. An interlayer insulating film pattern having an opening a is formed. Then, after a metal wiring layer is formed on the interlayer insulating layer pattern 28, the metal connecting to the MOS transistors 26 and 27 is formed in the opening 28a of the interlayer insulating film pattern 28 by photolithography and etching in the same manner as described above. A wiring layer pattern 29 is formed.
Thus, a semiconductor integrated circuit is manufactured.
[0025]
As described above, according to the embodiment of the present invention, which one of the steps is being performed only by looking at the identification patterns 3b and 7b in each of the photoresist patterns 4 and 8 formed on the Si substrate 1. Therefore, even an unskilled worker can easily grasp the current process easily and can know which process to proceed to next.
For this reason, process errors are reduced. If this identification pattern is performed by an automatic reading device using a pattern recognition device, it can be performed more quickly.
[0026]
Further, instead of the embodiment of the present invention, after forming an identification mark for identifying each step in advance on a substrate, a photoresist is applied on this substrate, and a main body used in a predetermined step is formed by photolithography. The step in which the body pattern is used can be determined from a photoresist pattern composed of a pattern and a mark pattern that exposes or covers an identification mark corresponding to the step in which the body pattern is used.
[0027]
This will be described with reference to FIGS. 15 and 16 as a modification of the embodiment of the present invention.
FIG. 15 is a cross-sectional view showing a step of forming a mark on a substrate according to a modification of the embodiment of the present invention. FIG. 16 is a cross-sectional view illustrating an identification mark forming step according to a modification of the embodiment of the present invention.
The same components as those of the embodiment of the present invention are denoted by the same reference numerals, and description thereof will be omitted.
In a modification of the embodiment of the present invention, when performing the above-described (P-well photoresist patterning step) to (interlayer insulating film and metal wiring layer forming step), the photomasks 3 and 7 described above are used as photomasks. A process in which an identification pattern is not formed at the end is used, and two processes (a process for forming a mark on a substrate) and a process for forming an identification mark are added before the process for patterning a P-well photoresist. The rest is the same as the embodiment of the present invention.
[0028]
(Step of forming mark on substrate)
First, as shown in FIG. 15A, after a photoresist 30 is applied on the Si substrate 1, a photomask 31 is placed above the photoresist 30, and the photomask 31 is placed above the photomask 31 by photolithography. Exposure from
[0029]
At this time, the photomask 31 has no pattern formed at the center, and has an identification pattern formed only at the end to identify all the steps used in the method of manufacturing a semiconductor integrated circuit. Here, as an example, as shown in FIG. 15B, a case where an identification pattern 31b for identifying some steps used in a method of manufacturing a semiconductor integrated circuit is formed at an end of a photomask 31 is shown. Is shown.
As described with reference to FIG. 1B, in FIG. 15B, “PWL” of the identification pattern 31b indicates that it is used in the (P-well photoresist patterning step), and “NWL” indicates (N "NFV" indicates that it is used in the (N-channel field transistor threshold voltage adjustment photoresist patterning step).
[0030]
Then, by setting an exposure device (not shown) in a blind setting, the entirety of the identification pattern 31b formed at the end of the photomask 31 is exposed and developed to form a photoresist pattern 32 of the identification pattern 31b on the photoresist 30. I do.
[0031]
(Identification mark forming step)
Next, as shown in FIG. 16, the portions other than those covered with the photoresist pattern 32 are etched to form identification marks 33 on the Si substrate 1 corresponding to the identification patterns 31b. Thereafter, the photoresist pattern 32 is removed.
[0032]
Next, an identification pattern is formed at the end of the photomasks 3 and 7 used in each of the steps of (P-well photoresist patterning step) to (interlayer insulating film and metal wiring layer forming step) in the above-described semiconductor integrated circuit manufacturing method. This is performed using a photomask in which only the main body pattern used in each step is formed in the center without forming 3b and 7b.
Then, the exposure apparatus (not shown) is blind-set to selectively expose the main body pattern used in each step and the identification mark 33 corresponding to the step in which the main pattern is used, or a step in which the main pattern is not formed. After selectively exposing the portions other than the identification mark 33 corresponding to the pattern, development is performed to expose the photoresist pattern of the body pattern and the identification mark 33 corresponding to the step in which the body pattern is used on the Si substrate 1. Or a photoresist pattern of a mark pattern to be covered or covered. Then, a process in which the main pattern is used is determined based on the photoresist pattern of the mark pattern. Hereinafter, a semiconductor integrated circuit is manufactured through the same steps as described above.
In the modification of the embodiment of the present invention, the same effect as that of the embodiment of the present invention can be obtained.
Note that the main body patterns used in the above description are specifically the P-well pattern 3a and the N-well pattern 7a.
[0033]
【The invention's effect】
As has been described in detail above, according to the present invention, it is possible to know which step in the process is being carried out only by looking at the identification pattern of the photoresist pattern, and to determine which step to proceed to next can do. For this reason, process errors by unskilled workers are reduced.
[Brief description of the drawings]
FIG. 1 shows a P-well photoresist patterning step according to a method for manufacturing a semiconductor integrated circuit of the present invention, wherein (A) is a cross-sectional view and (B) is a plan view of a photomask used at that time. .
FIG. 2 is a cross-sectional view showing a P-well forming step.
3A and 3B show an N-well photoresist patterning step, in which FIG. 3A is a cross-sectional view and FIG. 3B is a plan view of a photomask used at that time.
FIG. 4 is a sectional view showing an N-well forming step.
FIG. 5 is a sectional view showing a step of forming a Si nitride film.
FIG. 6 is a sectional view showing an N-channel field transistor threshold voltage adjusting photoresist patterning step.
FIG. 7 is a cross-sectional view showing an N-channel field transistor threshold voltage adjusting impurity implantation step.
FIG. 8 is a cross-sectional view showing a P-channel field transistor threshold voltage adjusting impurity implantation step.
FIG. 9 is a view showing a field oxide film forming step.
FIG. 10 is a cross-sectional view showing an N-channel transistor threshold voltage adjusting photoresist patterning forming step.
FIG. 11 is a cross-sectional view showing an N-channel transistor threshold voltage adjusting impurity implantation step.
FIG. 12 is a cross-sectional view showing a P-channel transistor threshold voltage adjusting impurity implantation step.
FIG. 13 is a sectional view showing a step of forming a gate oxide film and a gate electrode.
FIG. 14 is a cross-sectional view showing a step of forming an interlayer insulating film and a metal wiring layer.
FIG. 15 is a sectional view showing a mark forming step.
FIG. 16 is a sectional view illustrating an identification mark forming step.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Si substrate, 2, 6, 11, 16, 30 ... Photoresist, 3a ... P-well pattern (body pattern), 4a, 8a, 12a, 17a, 19a ... Opening, 3b, 7b ... Identification pattern 3, 7, 13, 31 photomask, 4, 8, 12, 17, 32 ... photoresist pattern, 5 ... P well, 7a ... N well pattern (body pattern), 9 ... N well, 10 ... Si nitride film pattern, 13 ... N channel field, 14 ... P channel field, 15 ... field oxide film, 18 ... N channel, 19 ... P channel, 20 ... gate oxide film, 21 ... gate electrode, 22, 23 ... drain, 24, 25 ... source , 26, 27: MOS transistor, 28: interlayer insulating film pattern, 29: metal wiring layer pattern, 33: identification mark

Claims (2)

By using a photolithography method, in a method of manufacturing a semiconductor integrated circuit manufactured through a plurality of steps of repeating impurity diffusion to the substrate,
A first step of applying a photoresist to the substrate or a layer laminated on the substrate,
Using a photomask in which a plurality of identification patterns corresponding to the plurality of steps are formed in a portion other than the main body pattern and the main body pattern, the photomask is arranged above the photoresist, and from above the photomask. After selectively exposing the body pattern and the identification pattern in a process corresponding to the body pattern, development is performed to form a photoresist pattern of the body pattern and a photoresist pattern of the identification pattern on the photoresist. A second step;
A third step of determining the second step from the photoresist pattern of the identification pattern;
A method for manufacturing a semiconductor integrated circuit, comprising: By using a photolithography method, in a method of manufacturing a semiconductor integrated circuit manufactured through a plurality of steps of repeating impurity diffusion to the substrate,
A first step of applying a first photoresist to the substrate or a layer laminated on the substrate,
Using a photomask in which only a plurality of identification patterns corresponding to the plurality of processes are formed at an end, the photomask is disposed above the first photoresist, and the plurality of identification patterns are arranged on the photomask. After exposing the pattern, performing development, a second step of forming a first photoresist pattern of the plurality of identification patterns on the substrate or a layer laminated on the substrate,
Etching the substrate exposed from the first photoresist pattern to form a plurality of identification marks corresponding to the plurality of identification patterns on the substrate, and then removing the first photoresist pattern; Three steps,
A fourth step of forming a second photoresist on the substrate on which the plurality of identification marks are formed;
Using a photomask in which only the main body pattern is formed, after selectively exposing the main body pattern and the identification mark portion corresponding to the step in which the main body pattern is used, or selectively excluding the other than the identification mark portion After exposure, a developing step is performed to form a second photoresist pattern including a mark pattern that exposes or covers the identification mark corresponding to the step of using the main body pattern and the main body pattern, and ,
A sixth step of determining a step in which the body pattern is used by the second photoresist pattern of the mark pattern;
A method for manufacturing a semiconductor integrated circuit, comprising:

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